Method, device and equipment for fragment recombination based on DPU low-delay protocol stack and medium

Abstract

The invention relates to a DPU-based low-delay protocol stack fragment recombination method, apparatus and device, and a medium. The DPU-based low-delay protocol stack fragment recombination method comprises the following steps: receiving a network data stream, the network data stream comprising a fragment data packet; carrying out attribute identification judgment on the fragmented data packet through a hardware layer; when the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, fragmenting and recombining the fragmented data packet through the hardware layer; and when the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, fragmenting and recombining the fragmented data packet through a software layer. According to the embodiment of the invention, the fragmentation data packet discarding can be reduced, the fragmentation recombination efficiency is improved, and the packet loss condition is reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of low-latency network protocol stack software, and in particular to a DPU-based low-latency protocol stack sharding reorganization method, device, equipment and medium. Background Art

[0002] The existing Internet Protocol (IP) layer fragmentation and reassembly technology is used to divide a data packet into smaller fragments (fragments) according to the Maximum Transmission Unit (MTU), and reassemble them to form the original data packet according to an identifier, such as a quintuple, after reaching the target address.

[0003] In the related technology, the logic of fragmentation and reassembly of the low-latency protocol stack is all done by the hardware layer. However, when the network traffic is too large, the fragmentation and reassembly logic of the hardware layer cannot support such a large-scale fragmentation and reassembly. That is, when there are too many fragmented messages, the hardware layer will discard the excess fragmented messages, resulting in serious packet loss during data transmission. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a DPU-based low-latency protocol stack fragmentation reorganization method, device, equipment and medium.

[0005] In a first aspect, the present disclosure provides a method for reorganizing fragments based on a DPU low-latency protocol stack, comprising:

[0006] Receiving a network data stream, wherein the network data stream includes fragmented data packets;

[0007] Performing attribute identification judgment on the fragmented data packets through the hardware layer;

[0008] When the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, performing fragment reassembly processing on the fragmented data packet through the hardware layer;

[0009] When the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the fragmented data packet is reassembled through the software layer.

[0010] In a second aspect, the present disclosure provides a fragmentation reorganization device based on a DPU low-latency protocol stack, comprising:

[0011] A data receiving module, used for receiving a network data stream, wherein the network data stream includes fragmented data packets;

[0012] An identification judgment module, used for performing attribute identification judgment on the fragmented data packet through a hardware layer;

[0013] A first processing module, configured to perform fragment reassembly processing on the fragment data packet through the hardware layer when the attribute identifier of the fragment data packet is the identifier required by the hardware layer;

[0014] The second processing module is used to perform fragment reassembly processing on the fragment data packet through the software layer when the attribute identifier of the fragment data packet is not the identifier required by the hardware layer.

[0015] In a third aspect, the present disclosure provides a fragmentation and reorganization device based on a DPU low-latency protocol stack, including:

[0016] processor;

[0017] A memory for storing executable instructions;

[0018] The processor is used to read executable instructions from the memory and execute the executable instructions to implement the DPU low-latency protocol stack sharding reorganization method based on the first aspect.

[0019] In a fourth aspect, the present disclosure provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the DPU low-latency protocol stack sharding reorganization method based on the first aspect.

[0020] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0021] The fragmentation reassembly method, apparatus, device and medium based on the DPU low-latency protocol stack of the embodiments of the present disclosure can receive a network data stream, wherein the network data stream includes fragmented data packets, and then perform attribute identification judgment on the fragmented data packets through the hardware layer, and then when the attribute identification of the fragmented data packets is the identification required by the hardware layer, perform fragmentation reassembly processing on the fragmented data packets through the hardware layer, and finally when the attribute identification of the fragmented data packets is not the identification required by the hardware layer, perform fragmentation reassembly processing on the fragmented data packets through the software layer. Thus, when a network data stream containing fragmented data packets is received, fragmented data packets that are not processed by the hardware layer are reassembled through the software layer according to the attribute identification of the fragmented data packets, thereby reducing the discard of fragmented data packets, improving the efficiency of fragmentation reassembly, and reducing packet loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0023] Figure 1A flowchart of a DPU low-latency protocol stack sharding reorganization method provided in an embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of another process of a DPU low-latency protocol stack fragmentation reorganization method provided in an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of the structure of a DPU low-latency protocol stack fragmentation and reorganization device provided in an embodiment of the present disclosure;

[0026] Figure 4 A structural diagram of a DPU low-latency protocol stack sharding and reassembly device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0028] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0029] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0030] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0031] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0032] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0033] In order to solve the above problems, the embodiments of the present disclosure provide a method, device, equipment and medium for reorganizing fragments based on a DPU low-latency protocol stack. Figure 1 to Figure 2 The DPU low-latency protocol stack sharding reorganization method provided in the embodiment of the present disclosure is described in detail.

[0034] Optionally, a data processing unit or dedicated data processor (Data Processing Unit, DPU) is a hardware accelerator for data processing that runs an independent operating system, complex hardware offload modules, and matching network, security, and storage software functions. DPUs are typically used to accelerate throughput-intensive tasks in data centers, cloud computing, and edge computing, such as artificial intelligence reasoning, large-scale data analysis, and network security. DPUs consist of three main elements, including processing cores, network interfaces, and memory interfaces. These components work together to enable the DPU to process data efficiently.

[0035] Figure 1 A flow chart of a DPU-based low-latency protocol stack fragmentation reorganization method provided in an embodiment of the present disclosure is shown.

[0036] In an embodiment of the present disclosure, the DPU low-latency protocol stack slicing reorganization method may be performed by an electronic device, wherein the electronic device may include but is not limited to devices such as computer devices, cloud servers, or cloud server clusters.

[0037] like Figure 1 As shown, the DPU low-latency protocol stack fragmentation reorganization method may include the following steps.

[0038] S110: Receive a network data stream, where the network data stream includes fragmented data packets.

[0039] In an embodiment of the present disclosure, an electronic device may receive a network data stream.

[0040] Optionally, the network data stream is a sequence of data transmitted in the network, which is transmitted and processed according to specific rules and methods. The network data stream includes fragmented data packets.

[0041] Optionally, the fragmented data packet may be a data packet including multiple data fragments.

[0042] Specifically, the electronic device may receive a network data stream containing fragmented data packets.

[0043] S120: Perform attribute identification judgment on the fragmented data packet through the hardware layer.

[0044] In the disclosed embodiment, the electronic device may perform attribute identification judgment on the fragmented data packet through the hardware layer.

[0045] Alternatively, the hardware layer is the most basic level in a computer system, including all physical components.

[0046] Optionally, the attribute identification judgment may be to judge the identification of the basic attribute corresponding to the data packet.

[0047] Specifically, after receiving the network data stream containing the fragmented data packets, the electronic device can perform attribute identification judgment on the fragmented data packets through the hardware layer, that is, judge the identification of the basic attribute corresponding to the fragmented data packets.

[0048] S130: When the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, perform fragment reassembly processing on the fragmented data packet through the hardware layer.

[0049] In the embodiment of the present disclosure, when the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, the electronic device can perform fragment reassembly processing on the fragmented data packet through the hardware layer.

[0050] Optionally, the attribute identifier may be an identifier used to characterize basic attributes of the fragmented data packet, wherein the attribute identifier includes five-tuple information.

[0051] Optionally, the quintuple information may include a source IP address, a destination IP address, a source port number, a destination port number, and a transport protocol.

[0052] Optionally, the identifier required by the hardware layer is an identifier corresponding to a fragmented data packet that needs to be reassembled by the hardware layer.

[0053] Optionally, the fragment reassembly process may be a process of reassembling fragmented data packets.

[0054] Specifically, after the electronic device performs attribute identification judgment on the fragmented data packet, if the attribute identification of the fragmented data packet is the identification required by the hardware layer, that is, when it judges through the quintuple information that the fragmented data packet is a data packet that needs to be processed by the hardware layer, the electronic device can perform fragment reassembly processing on the fragmented data packet through the hardware layer.

[0055] S140: When the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, fragment reassembly processing is performed on the fragmented data packet through the software layer.

[0056] In an embodiment of the present disclosure, when the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the electronic device can perform fragment reassembly processing on the fragmented data packet through the software layer.

[0057] Specifically, after the electronic device performs attribute identification judgment on the fragmented data packet, if the attribute identification of the fragmented data packet is not the identification required by the hardware layer, that is, when it judges through the quintuple information that the fragmented data packet is not a data packet that needs to be processed by the hardware layer, the electronic device can perform fragment reassembly processing on the fragmented data packet through the software layer.

[0058] Therefore, in the embodiment of the present disclosure, it is possible to receive a network data stream, which includes fragmented data packets, and then perform attribute identification judgment on the fragmented data packets through the hardware layer, and then, when the attribute identification of the fragmented data packets is the identification required by the hardware layer, the fragmented data packets are fragmented and reassembled through the hardware layer, and finally, when the attribute identification of the fragmented data packets is not the identification required by the hardware layer, the fragmented data packets are fragmented and reassembled through the software layer. Therefore, when a network data stream containing fragmented data packets is received, the fragmented data packets that are not processed by the hardware layer are fragmented and reassembled through the software layer according to the attribute identification of the fragmented data packets, thereby reducing the discard of fragmented data packets, improving the efficiency of fragment reassembly, and reducing packet loss.

[0059] Optionally, before S110, the DPU low-latency protocol stack-based fragmentation and reassembly method may further include: performing data fragmentation processing on the original data packet through the hardware layer to obtain the fragmented data packet.

[0060] In the disclosed embodiment, the electronic device may perform data fragmentation processing on the original data packet through the hardware layer to obtain the fragmented data packet.

[0061] Optionally, the original data packet may be a data packet that needs to be fragmented and reassembled for transmission.

[0062] Optionally, the data fragmentation process may be a method of fragmenting a data packet into multiple smaller fragments.

[0063] Specifically, the electronic device can perform data fragmentation processing on the original data packet through the hardware layer. For example, after obtaining the original data packet, the electronic device can divide the original data packet into multiple smaller fragments according to the maximum transmission unit (MTU) through the hardware layer to obtain fragmented data packets.

[0064] Optionally, S130 may specifically include: when the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, performing fragment reassembly processing on the fragmented data packet through a reassembly pool of the hardware layer to obtain an original data packet.

[0065] In the embodiment of the present disclosure, when the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, the electronic device can perform fragment reassembly processing on the fragmented data packet through the reassembly pool of the hardware layer to obtain the original data packet.

[0066] Optionally, the reassembly pool of the hardware layer may be a structure that performs shard reassembly processing in the hardware layer.

[0067] Specifically, if the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, the electronic device can obtain the fragmented data packet through the hardware layer and put the fragmented data packet into the reassembly pool of the hardware layer. The reassembly pool of the hardware layer will perform fragment reassembly processing on the fragmented data packet to obtain the original data packet.

[0068] Optionally, after the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the fragment reassembly method based on the DPU low-latency protocol stack may also include: importing the network data stream containing the fragmented data packet into the DMA cache.

[0069] In an embodiment of the present disclosure, the electronic device may import the network data stream including the fragmented data packets into a DMA cache.

[0070] Optionally, a Direct Memory Access (DMA) cache can be used to store the network data stream.

[0071] Specifically, if the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the electronic device may import the network data stream containing the fragmented data packet into the DMA cache.

[0072] Optionally, S140 may specifically include: obtaining the fragmented data packets contained in the network data stream from the DMA cache through the software layer; and performing fragment reassembly processing on the fragmented data packets through the reassembly pool of the software layer to obtain the original data packets.

[0073] In the embodiment of the present disclosure, the electronic device can obtain the fragmented data packets included in the network data stream from the DMA cache through the software layer.

[0074] Specifically, after the electronic device imports the network data stream containing the fragmented data packets into the DMA cache, the fragmented data packets contained in the network data stream can be obtained from the DMA cache through the software layer.

[0075] Furthermore, the electronic device may perform fragment reassembly processing on the fragmented data packet through the reassembly pool of the software layer to obtain the original data packet.

[0076] Optionally, the reassembly pool of the software layer may be a structure in the software layer that performs shard reassembly processing.

[0077] Specifically, if the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the electronic device can obtain the fragmented data packet contained in the network data stream from the DMA cache through the software layer, and put the fragmented data packet into the reassembly pool of the software layer. The reassembly pool of the software layer will perform fragment reassembly processing on the fragmented data packet to obtain the original data packet.

[0078] Optionally, the DPU low-latency protocol stack-based fragmentation reassembly method may further include: sending the original data packet to a transport layer.

[0079] In the embodiment of the present disclosure, the electronic device may send the reassembled original data packet to the transport layer.

[0080] Figure 2 A flow chart of another method for reorganizing DPU low-latency protocol stack fragments provided in an embodiment of the present disclosure is shown.

[0081] like Figure 2 As shown, the electronic device can receive a network data stream containing fragmented data packets, and then perform attribute identification judgment on the fragmented data packets through the hardware layer, that is, judge the identification of the basic attributes corresponding to the fragmented data packets. If the attribute identification of the fragmented data packets is the identification required by the hardware layer, that is, when the fragmented data packets are judged as the data packets that need to be processed by the hardware layer through the five-tuple information, the electronic device can perform fragment reassembly processing on the fragmented data packets through the hardware layer to obtain the original data packets, and send the original data packets to the transport layer; if the attribute identification of the fragmented data packets is not the identification required by the hardware layer, that is, when the fragmented data packets are judged not to be the data packets that need to be processed by the hardware layer through the five-tuple information, the network data stream containing the fragmented data packets can be imported into the DMA cache, and the fragmented data packets contained in the network data stream are obtained from the DMA cache through the software layer, and the fragmented data packets are placed in the reassembly pool of the software layer, and the reassembly pool of the software layer performs fragment reassembly processing on the fragmented data packets to obtain the original data packets, and the original data packets are sent to the transport layer.

[0082] Figure 3 A structural schematic diagram of a DPU-based low-latency protocol stack fragmentation reorganization device provided in an embodiment of the present disclosure is shown.

[0083] like Figure 3 As shown, the DPU low-latency protocol stack based fragmentation reorganization device 300 may include a data receiving module 310, an identification judgment module 320, a first processing module 330 and a second processing module 340.

[0084] The data receiving module 310 may be configured to receive a network data stream, wherein the network data stream includes fragmented data packets.

[0085] The identification determination module 320 may be used to perform attribute identification determination on the fragmented data packet through a hardware layer.

[0086] The first processing module 330 may be configured to perform fragment reassembly processing on the fragment data packet through the hardware layer when the attribute identifier of the fragment data packet is the identifier required by the hardware layer.

[0087] The second processing module 340 may be configured to perform fragment reassembly processing on the fragment data packet through the software layer when the attribute identifier of the fragment data packet is not the identifier required by the hardware layer.

[0088] Therefore, in the embodiment of the present disclosure, it is possible to receive a network data stream, which includes fragmented data packets, and then perform attribute identification judgment on the fragmented data packets through the hardware layer, and then, when the attribute identification of the fragmented data packets is the identification required by the hardware layer, the fragmented data packets are fragmented and reassembled through the hardware layer, and finally, when the attribute identification of the fragmented data packets is not the identification required by the hardware layer, the fragmented data packets are fragmented and reassembled through the software layer. Therefore, when a network data stream containing fragmented data packets is received, the fragmented data packets that are not processed by the hardware layer are fragmented and reassembled through the software layer according to the attribute identification of the fragmented data packets, thereby reducing the discard of fragmented data packets, improving the efficiency of fragment reassembly, and reducing packet loss.

[0089] In some embodiments of the present disclosure, the attribute identifier includes five-tuple information, and the five-tuple information includes a source IP address, a destination IP address, a source port number, a destination port number, and a transmission protocol.

[0090] In some embodiments of the present disclosure, the DPU-based low-latency protocol stack fragmentation reassembly device 300 may further include a third processing module.

[0091] The third processing module may be used to perform data fragmentation processing on the original data packet through the hardware layer before receiving the network data stream to obtain the fragmented data packet.

[0092] In some embodiments of the present disclosure, the first processing module 330 may specifically include a first processing unit.

[0093] The first processing unit may be configured to, when the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, perform fragment reassembly processing on the fragmented data packet through the reassembly pool of the hardware layer to obtain the original data packet.

[0094] In some embodiments of the present disclosure, the DPU low-latency protocol stack based fragmentation reorganization device 300 may also include a data import module.

[0095] The data import module can be used to import the network data stream containing the fragmented data packet into the DMA cache after the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer.

[0096] In some embodiments of the present disclosure, the second processing module 340 may specifically include a data acquisition unit and a second processing unit.

[0097] The data acquisition unit may be configured to acquire the fragmented data packets contained in the network data stream from the DMA buffer through the software layer.

[0098] The second processing unit can be used to perform fragment reassembly processing on the fragmented data packet through the reassembly pool of the software layer to obtain the original data packet.

[0099] In some embodiments of the present disclosure, the DPU low-latency protocol stack based fragmentation reassembly device 300 may also include a data sending module.

[0100] The data sending module can be used to send the original data packet to the transport layer.

[0101] It should be noted that Figure 3 The DPU low-latency protocol stack based fragmentation reassembly device 300 shown can execute Figure 1 to Figure 2 The various steps in the method embodiment shown in the figure are implemented Figure 1 to Figure 2 The various processes and effects in the method embodiment shown are not described in detail here.

[0102] Figure 4 A structural schematic diagram of a DPU low-latency protocol stack fragmentation and reassembly device provided in an embodiment of the present disclosure is shown.

[0103] In some embodiments of the present disclosure, Figure 4 The DPU low-latency protocol stack-based slicing and reassembly device shown may be an electronic device. Specifically, the electronic device may include but is not limited to devices such as computer devices, cloud servers, or cloud server clusters.

[0104] like Figure 4 As shown, the DPU-based low-latency protocol stack fragmentation reassembly device may include a processor 401 and a memory 402 storing computer program instructions.

[0105] Specifically, the processor 401 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0106] The memory 402 may include a large capacity memory for information or instructions. By way of example and not limitation, the memory 402 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a tape, or a universal serial bus (USB) drive or a combination of two or more of these. Where appropriate, the memory 402 may include a removable or non-removable (or fixed) medium. Where appropriate, the memory 402 may be inside or outside the integrated gateway device. In a particular embodiment, the memory 402 is a non-volatile solid-state memory. In a particular embodiment, the memory 402 includes a read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (Electrically Erasable Programmable ROM, EEPROM), an electrically rewritable ROM (EAROM) or a flash memory, or a combination of two or more of these.

[0107] The processor 401 reads and executes the computer program instructions stored in the memory 402 to perform the steps of the DPU low-latency protocol stack fragmentation reorganization method provided in the embodiment of the present disclosure.

[0108] In one example, the DPU low-latency protocol stack based fragmentation and reassembly device may further include a transceiver 403 and a bus 404. Figure 4 As shown, the processor 401, the memory 402 and the transceiver 403 are connected via a bus 404 and communicate with each other.

[0109] The bus 404 includes hardware, software, or both. For example, but not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industrial Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a Memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses or a combination of two or more of these. Where appropriate, the bus 404 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

[0110] The embodiments of the present disclosure also provide a computer-readable storage medium, which may store a computer program. When the computer program is executed by a processor, the processor implements the DPU low-latency protocol stack sharding reorganization method provided by the embodiments of the present disclosure.

[0111] The above-mentioned storage medium may, for example, include a memory 402 of computer program instructions, and the above-mentioned instructions may be executed by a processor 401 based on a DPU low-latency protocol stack sharding and reorganization device to complete the DPU low-latency protocol stack sharding and reorganization method provided in the embodiment of the present disclosure. Optionally, the storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may be a ROM, a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc ROM, CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0112] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0113] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fragmentation and reorganization method based on a DPU low-latency protocol stack, characterized in that: include: Receiving a network data stream, wherein the network data stream includes fragmented data packets; Performing attribute identification judgment on the fragmented data packets through the hardware layer; When the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, performing fragment reassembly processing on the fragmented data packet through the hardware layer; When the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the fragmented data packet is reassembled through the software layer.

2. The method according to claim 1, characterized in that The attribute identifier includes five-tuple information, and the five-tuple information includes a source IP address, a destination IP address, a source port number, a destination port number, and a transmission protocol.

3. The method according to claim 1, characterized in that Before receiving the network data stream, the method further includes: The hardware layer performs data fragmentation processing on the original data packet to obtain the fragmented data packet.

4. The method according to claim 1, characterized in that: When the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, performing fragment reassembly processing on the fragmented data packet through the hardware layer includes: When the attribute identifier of the fragmented data packet is the identifier required by the hardware layer, the fragmented data packet is subjected to fragment reassembly processing by the reassembly pool of the hardware layer to obtain the original data packet.

5. The method according to claim 1, characterized in that After the attribute identifier of the fragmented data packet is not the identifier required by the hardware layer, the method further includes: The network data stream including the fragmented data packets is imported into a DMA buffer.

6. The method according to claim 5, characterized in that The fragmentation and reassembly processing of the fragmented data packet through the software layer includes: Obtaining the fragmented data packets included in the network data stream from the DMA buffer through the software layer; The fragmented data packet is reassembled through the reassembly pool of the software layer to obtain the original data packet.

7. The method according to any one of claims 4 or 6, characterized in that: The method further comprises: The original data packet is sent to the transport layer.

8. A fragmentation and reorganization device based on a DPU low-latency protocol stack, characterized in that: include: A data receiving module, used for receiving a network data stream, wherein the network data stream includes fragmented data packets; An identification judgment module, used for performing attribute identification judgment on the fragmented data packet through a hardware layer; A first processing module, configured to perform fragment reassembly processing on the fragment data packet through the hardware layer when the attribute identifier of the fragment data packet is the identifier required by the hardware layer; The second processing module is used to perform fragment reassembly processing on the fragment data packet through the software layer when the attribute identifier of the fragment data packet is not the identifier required by the hardware layer.

9. A fragmentation and reassembly device based on a DPU low-latency protocol stack, characterized in that: include: processor; A memory for storing executable instructions; The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the DPU low-latency protocol stack sharding reorganization method described in any one of claims 1 to 7.

10. A non-volatile computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the processor implements the DPU low-latency protocol stack sharding reorganization method described in any one of claims 1 to 7.

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