Multi-die panel level high performance computing component

Abstract

Panel-level high performance computing (HPC) computing architectures and methods of making the same are disclosed. Panel architectures with and without glass cores include dielectric layers with interconnect structures (vias, conductive traces) to convert die-level output pins arranged at fine pitches to panel-level output pins arranged at thicker pitches. Local interconnects and local interconnect components provide electrical communication between integrated circuit dies in the panel. The coreless panel architecture may include a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer may have interconnect structures and local interconnect features. Panel embodiments having a glass core or glass reinforcement layer may include waveguides and channels through which liquid coolant passes, and may also include photonic integrated circuits. Panel-level manufacturing techniques may implement panels having dimensions larger (e.g., greater than 300 mm) than components manufactured using wafer-level manufacturing techniques.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application Serial No. 17 / 871,413, filed on July 22, 2022, entitled “MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS”. The disclosure of the prior application is considered part of the disclosure of the present application and is hereby incorporated by reference in its entirety. Background Art

[0003] As the technical challenges of high performance computing (HPC) continue to rise, heterogeneous integration scaling has become an important performance enabler. Heterogeneous integration scaling can include components with increased die volume, increased interconnect density, increased bandwidth, and improved power efficiency. As a result, many different advanced packaging architecture solutions have been adopted. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An exemplary HPC package implementing a panel architecture according to various embodiments is shown.

[0005] Figure 2 is a simplified cross-sectional view of an exemplary multi-die architecture provided for reference in connection with the presented embodiments.

[0006] Figure 3 is a simplified cross-sectional view of an exemplary panel architecture with a glass reinforcement layer according to various embodiments.

[0007] Figure 4A is a simplified cross-sectional view of a first exemplary local interconnect feature.

[0008] Figure 4B is a simplified cross-sectional view of a second exemplary local interconnect feature.

[0009] Figure 4C is a simplified cross-sectional view of a third exemplary local interconnect feature.

[0010] Figure 4D is a simplified cross-sectional view of a third exemplary local interconnect feature.

[0011] Figure 5 is a simplified cross-sectional view of a panel architecture with a photonic integrated circuit implemented in a glass reinforcement layer according to various embodiments.

[0012] Figure 6 is a simplified cross-sectional view of a panel architecture with microchannels implemented in a glass reinforcement layer according to various embodiments.

[0013] Figure 7 is a simplified cross-sectional view of an exemplary conductive contact that may be implemented in various embodiments.

[0014] Figure 8-Figure 9 is a simplified cross-sectional diagram illustrating a process flow for manufacturing a panel-level HPC system using a panel architecture according to various embodiments.

[0015] Fig.10 is a first exemplary method of forming a panel.

[0016] Fig.11 is a second exemplary method of forming a panel.

[0017] Fig.12 is a third exemplary method of forming a panel.

[0018] Fig.13 is a simplified cross-sectional view of a portion of an exemplary panel substrate including a glass core.

[0019] Fig.14 is a simplified cross-sectional view of an exemplary panel assembly including a panel including a glass core and local interconnect components positioned in a set of dielectric layers of the panel.

[0020] Fig.15 is a simplified cross-sectional view of an exemplary panel including a glass core having local interconnect features located in the glass core.

[0021] Fig.16 is a simplified cross-sectional view of an exemplary panel including a glass core and a photonic integrated circuit.

[0022] Fig.17 is a simplified cross-sectional view of an exemplary panel including a glass core, a photonic integrated circuit, and local interconnect features located in a dielectric layer.

[0023] Fig.18 is a simplified cross-sectional view of an exemplary panel including a glass core, a photonic integrated circuit, and local interconnect components located in the glass core.

[0024] Fig.19 is a simplified cross-sectional view of an exemplary panel including a glass core with microchannels and a photonic integrated circuit.

[0025] Fig. 20 is a simplified cross-sectional view of an exemplary panel including a glass core with microchannels, a photonic integrated circuit, and local interconnect features located in a dielectric layer.

[0026] Fig.21 is a simplified cross-sectional view of an exemplary panel including a glass core having microchannels, a photonic integrated circuit, and local interconnect components located in the glass core.

[0027] Fig. 22 is a simplified cross-sectional view of an exemplary coreless panel.

[0028] Fig.23 is a simplified cross-sectional view of an exemplary coreless panel including local interconnect components.

[0029] Fig.24 is a simplified cross-sectional view of an exemplary coreless panel including a photonic integrated circuit.

[0030] Fig.25 is a simplified cross-sectional view of an exemplary coreless panel including a photonic integrated circuit and local interconnect components.

[0031] Fig.26 is a fourth exemplary method of forming a panel.

[0032] Fig. 27 is a top view of a wafer and die that can be included in a microelectronic assembly according to any embodiment disclosed herein.

[0033] Fig.28 is a simplified cross-sectional side view illustrating an implementation of an integrated circuit on a die that may be included in various embodiments according to any of the embodiments disclosed herein.

[0034] Fig.29 is a cross-sectional side view of a microelectronic assembly that can include any of the embodiments disclosed herein.

[0035] Fig.30 is a block diagram of an exemplary electrical device that may include any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0036] As the technical challenges of high-performance computing (HPC) continue to rise, heterogeneous integration scaling has become an important performance driver. Heterogeneous integration scaling can include increased interconnect density, increased number of integrated circuit dies per package, increased bandwidth, and improved power efficiency. Therefore, many different advanced packaging architecture solutions have been adopted to increase planar and three-dimensional (3D) input / output (I / O) wire and area density for higher data bandwidth requirements, and to achieve more efficient die decomposition and heterogeneous integration to shorten time to market. Other technical solutions to meet HPC challenges include 2.5D / 3D advanced packaging technologies, such as die embedding and / or the use of local interconnect components to provide interconnections between dies (e.g., silicon (Si) interposers or bridges) to achieve significantly higher numbers and densities of packaged integrated circuit dies and I / Os, thereby meeting the HPC segment market demand and product performance needs.

[0037] Applications that rely on extremely high performance computing include those that are expected to operate at a zettflops (1021 The invention relates to applications that are executed on the order of 1000 floating point operations (FLOPS). These applications can be referred to as zettascale performance applications. Non-limiting examples of zettascale performance applications include supercomputing, autonomous driving, and machine learning. The implementation platform capable of achieving zettascale performance poses technical challenges, and packaging and system-level architecture innovations are expected to be developed to achieve this performance level. The proposed technical solutions include system-level heterogeneous integration of computing, I / O, memory, power management, and thermal management components. Some available high-performance computing solutions include implementing system-level architecture on wafers (also known as wafer-level system integration, or wafer-level solutions). However, wafer-level system integration poses several technical challenges. As is known, wafer-level system integration has a package whose size is limited by the diameter of the wafer. In addition, wafer-level system integration puts an entire system on one wafer; therefore, solving the yield problem of wafer-level solutions may become very challenging.

[0038] The embodiments disclosed herein propose technical solutions to the above-mentioned technical problems in the form of panel-level components (referred to herein individually as "panels") and systems including panels or panel-level components. Embodiments of the panel may include a plurality of components (e.g., integrated circuit components) assembled using panel-level manufacturing techniques. As used herein, the term "panel-level" manufacturing technology refers to a manufacturing technology in which integrated circuit dies are assembled and the interconnections between the integrated circuit dies are formed on a single substrate and / or carrier to form an integral structure. If the integral structure includes a plurality of panels, the integral structure is singulated into a single panel. The integral structure may be packaged (e.g., by molding) before singulation, or a single panel may be packaged after singulation. In application, as described in more detail below, one or more panels in the panel may be assembled to form a multi-panel structure or panel assembly. A single panel (and a multi-panel structure or component) may have an area less than, equal to, or greater than the area of ​​a wafer on which any single integrated circuit die of the panel may be formed.

[0039] Embodiments include various panel architectures. The panel architecture includes interconnect structures (e.g., conductive traces, vias) for routing die-level signals to package-level signals and local interconnects for routing signals between integrated circuit dies. Some panel architectures include a glass layer (or glass core) having a dielectric layer located on one or both sides of the glass layer. Other panel architectures do not contain a glass layer. The dielectric layer (in some embodiments, together with the glass layer) includes an interconnect structure. Panel architectures containing and not containing a glass layer may be referred to as "core" and "coreless" architectures, respectively, in this article. Some panel architectures (including coreless architectures) are assembled on a glass carrier that provides mechanical rigidity and a flat surface on which a panel can be manufactured. One benefit of the mechanical rigidity that a glass carrier (or glass reinforcement layer) can provide is that the amount of warping that a panel may experience during manufacturing or in the field is limited. Some panel architectures assembled on a glass carrier may include a glass layer (also referred to as a glass reinforcement layer in this article) to provide additional mechanical rigidity for the panel. The thickness of the glass reinforcement layer may be thinner than the glass layer used in the core panel architecture. Thus, a panel manufactured on a glass carrier and having a glass reinforcement layer can be thinner than other panels having a glass layer and manufactured without a glass carrier.

[0040] The provided panel architecture provides several technical and economic advantages, first of all, support for the design of panel-level solutions with larger areas than available wafer-level (300 mm diameter wafer size) solutions; while wafer-level integration may limit packaged HPC solutions to an area of ​​about 215 millimeters (mm) × 215 mm, in some embodiments, a single panel disclosed herein can reach an area in the range of about 250 mm × 250 mm to about 600 mm × 600 mm, and in other embodiments, a single panel can exceed 600 mm × 600 mm in area. In addition, a single panel can provide a panel-level HPC solution; however, in other embodiments, for example Figure 1 As shown, individual panels can be further assembled into larger HPC solutions.

[0041] Other non-limiting examples of the advantages of the provided panel architecture include: support for design redundancy (by assembling smaller known good dies (KGD) to produce multi-die structures), additional mechanical rigidity and capacity for fine pitch geometries supported by glass reinforcement layers, interconnect structures for die-to-die or chip-to-chip communication within the panel, cavities in the glass reinforcement layer for accommodating discrete device integration (e.g., discrete devices such as deep trench capacitors, capacitors, transistors, magnetic inductor arrays (MIA), inductors, etc.), flexible thermal management, and flexibility to vertically integrate integrated circuit dies and other components into the panel. In addition, embodiments may use a glass carrier to provide improved flatness and mechanical rigidity to the panel during manufacturing and assembly. These concepts are described in more detail below.

[0042] Exemplary embodiments will be described below in conjunction with the following figures, wherein the same reference numerals represent the same elements. The drawings are not necessarily drawn to scale, but may depend on the spatial orientation and relative position of the features. As can be appreciated, certain terms, such as "upper limit" and "lower limit", as well as "upper", "uppermost", "lower", "above", "below", "bottom" and "top" refer to the direction of the drawings referenced based on observation. In addition, terms such as "front", "back", "rear", "side", "vertical" and "horizontal" can describe the orientation and / or position of parts of components within a consistent but arbitrary reference system, which becomes clear by citing the text and related drawings of the components described herein. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0043] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other (with no layers or components in between). For example, layer X adjacent to layer Y refers to a layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase "located" (or, "located below," "located above," or "located next to" in the context of a first layer or component located on a second layer or component) includes: (i) configurations in which the first layer or component is directly physically attached to (i.e., adjacent to) the second layer, and (ii) components and configurations in which the first layer or component is attached (e.g., coupled) to the second layer or component via one or more intervening layers or components.

[0044] The term modified by the word "substantially" includes arrangements, orientations, spacings, or positions that are slightly different from the meaning of the unmodified term. For example, a portion of a first layer or feature that is substantially perpendicular to a second layer or feature may include a first layer or feature that is + / -20 degrees to the second layer or feature, and a first surface that is substantially parallel to a second surface may include a first surface that is parallel to the second surface within a certain degree. The variation covered by the term modified by the term "substantially" always indicates a specific arrangement, orientation, spacing, position, etc. Values ​​modified by the word "approximately" include values ​​with + / -10% of the described value and values ​​listed as being within a range of 10% less than the lower limit of the range and 10% greater than the upper limit of the range.

[0045] As used herein, the term "electronic component" may refer to an active electronic circuit (eg, a processing unit, a memory, a storage device, a FET) or a passive electronic circuit (eg, a resistor, an inductor, a capacitor).

[0046] As used herein, the term "integrated circuit component" may refer to an electronic component constructed on a semiconductor material to perform a function. An integrated circuit (IC) component may include any computing system component described or referenced herein or any other computing system component, such as a processor unit (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0047] A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die (referred to herein simply as a "die"); the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may enable the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0048] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are enclosed in a housing material such as metal, plastic, glass, or ceramic. Typically, the housing includes an integrated heat sink (IHS); the packaged integrated circuit component typically has bumps, leads, or pins attached to the package substrate (directly or by wires that attach the bumps, leads, or pins to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or baseboard) or another component.

[0049] The following detailed description is not intended to limit the application and use of the disclosed technology. It is apparent that novel embodiments can be practiced without every detail described herein. For the sake of brevity, well-known structures and devices may be shown in block diagram form to facilitate description thereof.

[0050] Embodiments of the provided panel architecture are intended to address technical issues faced by using panels to provide applications with HPC or other levels of performance. In some embodiments, an HPC solution may include a single panel of the provided architecture. In other examples, such as Figure 1 As shown, a panel assembly 100 including a plurality of panels of the provided panel architecture assembled is employed to implement an HPC solution.

[0051] exist Figure 1 In a non-limiting example, the panel assembly 100 includes four panels (panel 102, panel 104, panel 106, and panel 108) assembled, where four panels are assembled to form the panel assembly 100, a single panel may be referred to as a "sub-panel" or "panel quad" or "quarter panel". However, the panel assembly 100 may include more or less than four panels and panels arranged in any manner (e.g., square (e.g., 2×2, 4×4, 6×6), rectangular (e.g., 2×4, 3×5, 4×7)). The panels of the panel assembly 100 may be attached to a panel-level substrate 112. The panel-level substrate 112 may include a printed circuit board, a film substrate, or another suitable substrate. In various embodiments and HPC solutions, an enclosure 110 may be used to mold a single panel or the entire panel assembly 100. The enclosure 110 may include molded plastic, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof.

[0052] In various embodiments, a single panel of panel assembly 100 may have an area in the range of approximately 250-300 mm x 250-300 mm (e.g., see Figure 1 ). In other embodiments, a single panel of the panel assembly 100 may have an area in the range of about 450-600 mm x 450-600 mm or more. That is, in some embodiments, the lateral dimension of the panel (the dimension of the panel orthogonal to the thickness of the panel) may be 250-300 mm, and in other embodiments may be 450-600 mm. In other embodiments, a single panel may be smaller or larger. For example, in some embodiments, the lateral dimension of the panel is greater than 250 mm.

[0053] The blocks drawn inside each panel represent individual unpackaged integrated circuit dies (e.g., die 114, die 116, die 118, and die 120). Unpackaged integrated circuit dies (die 114, die 116, die 118, and die 120) may also be referred to as chips, corelets, chip complexes, or corelet complexes. Although the terms "die," "chip," and "corelet" may be used interchangeably, the term "corelet" is sometimes used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit component, which is formed using one or more corelets connected by inter-die interconnects (e.g., interposers, bridges, local interconnect components, local silicon interconnects). As feature sizes decrease and demand for high-performance larger integrated circuit components increases, the use of corelets in integrated circuit components has become attractive. Since the overall yield of integrated circuit components assembled from multiple small corelets is better than the overall yield of integrated circuit components where the functions of the corelets are implemented on a single large integrated circuit die, the method of assembling multiple known good dies (corelets) to form larger integrated circuit components achieves improved manufacturing efficiency. Any integrated circuit die, chip, or coreparticle may implement any portion of the functionality of any processor unit described or referenced herein.

[0054] Although the schematics depict the die within and between panels as having uniform size, in practice, the die size (lateral size and thickness) and shape may vary between die within a panel and across the panel; further, the die on a given panel may vary by type / function (e.g., compute, memory, I / O, power management (controlling the delivery of power and / or providing power to components)). In a non-limiting example, each panel includes 12 dies arranged in a 4×3 array, however, other numbers of dies per panel and other arrangements of dies within a panel are supported. In addition, the die area and die height of the integrated circuit components within a given panel may vary. Further, the panels may have any shape, such as a substantially non-circular shape (e.g., a substantially square shape, a substantially rectangular shape (e.g., panels 102, 104, 106, 108)), or a substantially circular shape.

[0055] As described in more detail below, in some embodiments, panel assembly 100 may be co-packaged with other electronic components or optical interconnects or waveguides, and may support a photonic integrated circuit (PIC) of a panel attached or connected thereto. In some embodiments, the other electronic components or PICs may be located external to the panel, such as indicated by position 122. In other embodiments, a panel of the panel assembly may have its substrate etched with a waveguide, and may further include one or more other electronic components or PICs in a keep-out area of ​​the panel, such as indicated by position 124 of panel 108.

[0056] The panel can take the form of a populated or unpopulated panel substrate. Both the populated and unpopulated panel substrates are constructed (e.g., constructed with appropriate output pins) to communicatively couple the associated integrated circuit dies to each other (e.g., via fine pitch redistribution layers, conductive traces, or local interconnect components, such as the bridges shown in FIG. 4 ).

[0057] Cutting line A-A' is the combination Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 13-Figure 25 The cut line BB' provides a reference for intra-panel (i.e., within a panel) architectural discussions. The cut line BB' provides a reference for inter-panel (i.e., between panels) architectural discussions, such as generating panel components, which are Fig. 9 was referenced again.

[0058] Figure 2 A simplified cross-sectional view of a portion of a panel 200 is provided as a reference for discussion of general panel architecture, and Figure 3-Figure 9 and Figure 13-Figure 25 The embodiment shown in FIG. Figure 2 A technical improvement of the general panel architecture in the , with additional and / or alternative features. Figure 2 Many of the components in Figure 3-Figure 9 and Figure 13-Figure 25 This can be observed through comparison of shape, position and context.

[0059] For example, interconnect structures (vias, conductive traces) 228, 328, 428, 528, 628, 728, 828, 1328, 2228, etc. are similar; build-up layers (or, alternatively, redistribution layers (RDL) or dielectric layers) 222, 322, 422, 522, 622, 722, 822, 1322, 2222, etc. are similar; build-up layers, dielectric layers, or redistribution layers 224, 324, 424, 524, 624, 72 4, 824, 1324, 2224, etc. are similar; conductive pads (or contacts) 232, 332, 532, 632, 1332, 2232, etc. are similar; conductive contacts 226, 326, 526, 626, 1326, 2226, etc. are similar; upper surface contact layers 256, 356, 1356, 2256 are similar; lower surface contact layers 260, 360, 1360, 2260 are similar; thermal management solutions 209, 9 60, 962, 1409, 1509, 2309 are similar; glass reinforcement layers 350, 550, 650, etc. are similar; glass cores 1351, 1451, 1551, etc. are similar; interconnect structures in the form of through-glass vias 352, 552, 652, 1352, etc. are similar; solder resists or dielectric materials 212, 312, 512, 612, 1312, 2212, etc. are similar; solder resists or dielectric materials 218, 318, 518, 618, 1318, 2218, etc. are similar; microchannels 668, 1968, 2068, etc. are similar; local interconnect components 234, 334, 434, 534, 634, 1434, 2334, 2434, etc. are similar; waveguides 564, 1664, 2464, etc. are similar, photonic integrated circuits 562, 1662a, 1662b, 1762a, 1762b, 2462, 2562, etc. are similar, FAUs 1621a, 1621b, 1721a, 172b, 2421, 2521, etc. are similar, and so on. In addition, those skilled in the art will understand that although some object numbers are omitted in some figures to reduce clutter, objects that share the same shape, position, and / or context with labeled objects in other figures are similar (e.g., include the same material, have the same size, have the same attributes). Figure 3-Figure 7 and Figure 13-Figure 25 Focus on the (in-panel) panel architecture for unpopulated panels, and Figure 8-Figure 9 Filling and encapsulating the panels is described.

[0060] As used herein, "pitch" refers to the physical distance at which a feature repeats (e.g., the spacing from the center of one instance of a feature to the center of an adjacent instance of the feature). For example, on surface 203, conductive contacts 226 have a spacing 240; and on surface 205, conductive pads 232 have a spacing 242.

[0061] As used herein, "fine pitch" generally refers to the die-level pitch as shown on surface 203, and "coarse pitch" generally refers to the package-level pitch as shown on surface 205. Fine pitch dimensions may include a range of about 0.001 mm to about 0.3 mm. In some embodiments, features with fine pitch have a size of about 1 μm (micrometer) or less. In other embodiments, features with fine pitch may have a size of about 0.5 μm or less. In addition to conductive contacts for attaching an integrated circuit die to a panel, other features in a panel that may have fine pitch include vias in one or more RDLs adjacent to output pins of an integrated circuit die. Fine pitch geometries are smaller than "coarse pitch" geometries.

[0062] As shown on surface 205, "coarse pitch" 242 generally refers to the geometric dimensions associated with package-level conductive pads 332 (or contacts 332); the coarse pitch can be a ball grid array (BGA) pitch or a land grid array (LGA) pitch. In various embodiments, the BGA pitch is in the range of about 0.1 mm to about 1 mm, and the LGA pitch is in the range of about 0.1 mm to about 1 mm. In addition, as generally represented in the figure, the thickness of the conductive traces of the RDL adjacent to the package-level conductive contacts or conductive pads 332 at surface 205 can be thicker than the conductive traces in the RDL adjacent to the output pins of the integrated circuit die at surface 203.

[0063] In some embodiments, the pitch at surface 203 is less than the pitch at surface 205, and in some embodiments, the pitch at surface 203 is the same as the pitch at surface 205. Conductive contacts 226 and conductive pads 232 may include solder, copper, or another suitable metal or other material.

[0064] Build-up layers or redistribution layers (RDLs) (e.g., 222, 322, 422, 522, 622, 722, and 822) are described herein. Although the accompanying drawings show two RDL 222 sublayers and two RDL 224 sublayers, in practice, any number of RDL sublayers may be present. For example, in server applications, the RDL may include up to 10 sublayers. In various embodiments, the RDL includes a dielectric material and may include a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organosilicate glass, which is a material including silicon, oxygen and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material including fluorine, silicon and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, which is a material including silicon, oxygen and hydrogen). In some embodiments, the RDL includes a photoimageable dielectric (PID). In some embodiments, the RDL includes an Ajinomoto Build-up Film (commonly referred to as ABF), which is a material including an organic resin matrix having different types of fillers (e.g., silica fillers of different sizes, or hollow fillers of different sizes) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk) and / or dissipation factor (insertion loss) (Df)) of the RDL.

[0065] In some embodiments, it is advantageous for the RDL to have a CTE that matches the CTE of the integrated circuit die attached to the panel substrate (e.g., matches the CTE of silicon). In some embodiments, the dielectric material of the RDL can have a CTE that is close to (e.g., within 10%) the CTE of silicon. In other embodiments, the dielectric material of the RDL can be any type of epoxy molding compound. The RDL or buildup layer can include a metal layer containing conductive traces (or metal lines), and the metal used for the interconnect metal in the RDL includes copper or other suitable metals.

[0066] Local interconnect components and interconnect structures are introduced herein. As used herein, local interconnect components refer to separately manufactured components for routing signals between dies within a panel. In contrast, external interconnect components can be used to route signals between panels. As used herein, an "interconnect structure" may include one or more conductive traces, one or more vias, or a combination thereof. The term "conductive trace" may refer to a via contact, which may be a metal line connected to a via, and does not include a lateral signal routing portion. The interconnect structure may be present in various RDLs, dielectric layers, buildup layers, or glass layers, and may span multiple such layers. The interconnect structure may collectively provide a conductive path from a feature on the first surface 203 of the panel substrate 201 to a feature on the second surface 205 of the panel substrate. In various embodiments, the interconnect structure in the first dielectric layer is attached to the interconnect structure in the second dielectric layer, thereby providing a conductive path through the substrate.

[0067] Portion 200 relates to cut line A-A' and includes substrate 201. Substrate 201 may have a thickness 210 in the range of about 0.05 mm to about 3 mm, where that corresponds to about + / - 10%, and may include one or more buildup or redistribution layers 214, 216, 218, and 220. Region 202 (column on the left side of the page) provides signal communications and conversion routing (e.g., converting fine pitch die-level signals to coarser pitch panel-level signals) for a die or core 204 attached at an upper surface 203, and on the right, region 206 provides signal communications and conversion routing for a die or core 208 attached at the upper surface 203. For individual die of the one or more die that are part of portion 200, solder resist or other dielectric material 212 on the upper substrate surface may be patterned to have corresponding output pins (physical arrangement of conductive contacts 226 at corresponding spacings). The corresponding output pins may include a single conductive contact 226 arranged as a conductive contact for a single core particle or die (e.g., die 204 and die 208). In some embodiments, the conductive contacts 226 are arranged in the upper surface contact layer 256 as two distinguishable groups with the same spacing (e.g., die pitch or fine pitch), however, in other embodiments, the conductive contacts 226 are arranged as two groups that do not have the same die pitch or fine pitch. In addition, the conductive contacts associated with a die may be arranged with more than one pitch. Some signal routing may be generated from at least one conductive contact in the first group of conductive contacts 226 (e.g., die 204) to at least one conductive contact in the second group of conductive contacts 226 (e.g., die 208) via local interconnect components 234. Some vias 228b may be arranged with a fine pitch to match the spacing of the conductive contacts 226.

[0068] In various embodiments, RDL 222 includes features (e.g., interconnect structures including metal lines and vias) having a finer pitch than the pitch of features in RDL 224. Thus, RDL 222 and RDL 224 can be considered to translate the tighter pitch of the die pads (which matches the pitch of conductive pads 226) to the larger pitch of the panel pads (which matches the pitch of conductive pads 232). Although RDL 222 is depicted as including two layers (RDL 214 and RDL 216), and RDL 224 is depicted as including two layers (RDL 218 and RDL 220), in practice, the number of layers in RDL 222 and RDL 224 may vary. Those skilled in the art will appreciate that in the present discussion, the distinction attributed to RDL 222 and RDL 224 in the various dielectric layers or buildup layers is introduced for illustrative purposes; in a cross-sectional image of substrate 201, for example, by transmission electron microscopy (TEM), layers 212, 214, 216, 218, and 220 may be indistinguishable.

[0069] For illustrative purposes, RDL 222 includes interconnect structure 228, and RDL 224 includes interconnect structure 230. Interconnect structure 228 may be arranged within RDL 214 and RDL 216 to route electrical signals according to a variety of applications; in particular, the arrangement is not limited to Figure 2 . In some embodiments, the interconnect structure 228 may include conductive traces or metal lines (wires) and / or via contacts 228a and vias 228b. The conductive traces, via contacts, and vias may include conductive materials, such as metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof). The wires of the interconnect structure 228a may be arranged to route electrical signals along a surface of a plane substantially parallel to the surface 203 of the substrate 201. For example, the wires of the interconnect structure 228a may route electrical signals in a direction in and out of the page and / or in a direction across the page. The vias 228b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the substrate 201. Similarly, the interconnect structure 230 may include conductive traces or wires and / or via contacts 230a and / or vias 230b (which include conductive materials, such as metals (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or combinations thereof)). The lines of the interconnect structure 230a can be arranged to route electrical signals in a direction substantially parallel to the surface 203 of the substrate 201. For example, the lines 230a can route electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 230b can be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the substrate 201.

[0070] The local interconnect component 234 is used to communicatively couple the core particles 204 and 208. The substrate 201 can be a filled or unfilled portion of the product. In various filled embodiments, there can be components attached to the upper surface 203 of the substrate 201 as indicated in the area 290. For example, the filled panel substrate can be filled with corresponding tube cores or core particles (e.g., 204, 208), which can be connected via conductive tube core bumps 238 or any solder or hybrid bonding (bonding of components through interconnection of components and bonding of dielectric layers (direct attachment)). In some embodiments, polymers can be used to bond copper conductive contacts (e.g., pads) on the tube core to copper conductive contacts (e.g., 226) of the panel substrate. In some embodiments, polymers can also be used to bond solder conductive contacts on the tube core to solder conductive contacts on the panel substrate. In some embodiments, inorganic materials (e.g., silicon dioxide, silicon nitride) can be used to bond the copper conductive contacts of the components together. In some embodiments, the die is attached to substrate 201 by direct attachment of bumps (e.g., microbumps) attached to two surfaces (e.g., die surface, panel surface). In some embodiments, the die also has an underfill (not shown) applied below the die and above the surface of substrate 201. A large form factor thermal management solution 236 including a cooling component (e.g., a vapor chamber, a heat pipe, a heat sink, or a liquid-cooled cold plate) may be implemented. The thermal management solution is a large form factor solution because it may be a panel-level thermal management solution (providing cooling of the integrated circuit die of a panel) or a multi-panel thermal management solution (providing cooling of the integrated circuit die of multiple panels). As part of the thermal management solution, a thermally conductive layer interface material (TIM) may be located above die 204, die 208. The TIM may be any suitable material, such as a silver particle filled thermal compound, thermal grease, phase change material, indium foil, or graphite sheet. The thermal management solution may be a conformal solution that accommodates the height differences of the integrated circuit die to which the thermal management solution provides cooling. For example, the thermal management solution may include a substantially planar cooling component having a TIM with different thicknesses between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar and the profile of the cooling component may vary with the thickness of the integrated circuit die to which the cooling component provides cooling. In such an embodiment, the TIM may have a substantially uniform thickness between the cooling component and the integrated circuit die of different thicknesses. The thermal management solution may also include an integrated heat sink. Fig. 9 An example of a panel with a thermal management solution is provided.

[0071] Now go to Figure 3, embodiments of the provided panel architecture include a glass reinforcement layer located between dielectric layers or RDLs of a substrate. The simplified cross-sectional view of portion 300 relates to cut line A-A' and includes substrate 301. Substrate 301 includes a glass reinforcement layer 350 sandwiched between dielectric layer or RDL 322 and dielectric layer or RDL 324. In various embodiments, the overall height of the substrate is constant (e.g., substantially 210, Figure 2 ), and RDL 322 and RDL 324 are thinned or omitted to accommodate glass reinforcement layer 350, and the height / thickness 380 of glass reinforcement layer 350 is in the range of about 30 microns to 1.5 mm, + / - 10%. Figure 2 , RDL 322 may include multiple buildup layers, dielectric layers, or redistribution layers, and RDL 324 may include multiple buildup layers, dielectric layers, or redistribution layers. Likewise, by analogy, solder resist or other dielectric material 312 may be patterned into output pins of corresponding one or more core particles that may be attached to the substrate of the panel. The output pins may include individual conductive contacts 326 arranged at a fine pitch, and the upper surface contact layer 356 may also take the form of other embodiments (e.g., 726a, 726b), such as in combination with Figure 7 The lower surface contact layer 360 may also take the form of other embodiments (e.g., 760), such as a combination of Figure 7 Also as described above, vias / contacts / traces / pads 328, 330, 360, and 332 are similar to counterparts 228, 230, 260, and 232. Local interconnect component 334 is similar to local interconnect component 234. Region 302 is dedicated to the first die, and region 306 is dedicated to the second die.

[0072] The glass reinforcement layer 350 may include glass, which, as used herein, may be an alkali-free alkaline earth metal boroaluminosilicate glass, such as a glass including aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium, such as a glass including SiO2, Al2O3, B2O3, and MgO), or a photosensitive glass (a photomachinable or photocurable glass). In some embodiments, the photosensitive glass may be a glass belonging to the lithium silicate family (e.g., a glass including lithium, silicon, and oxygen) that includes metal particles, such as gold, silver, or other suitable metal particles. The glass reinforcement layer 350 may include a plurality of glass sheets (in a non-limiting example, three glass sheets 350-1, 350-2, and 350-3 are shown).

[0073] The glass reinforcement layer 350 may contain some or all of the interconnect structures to support signal routing from the contacts 326 at the die surface (303) of the substrate 301 to the conductive pads 332. The interconnect structures may include vias 352 in the glass layer 350, which may be referred to as through-glass vias (TGVs). The interconnect structures collectively provide a conductive path from features on the first surface 303 of the panel substrate 301 to other features on the first surface 303 and / or to the conductive pads 332. The individual glass sheets 350-1, 350-2, and 350-3 may have respective dielectric layers (351-1, 351-2, 351-3) located on their lower surfaces to act as adhesive layers, thereby laminating the glass sheets on / over a layer 354 of solder resist or dielectric having conductive contacts 358 and traces therein. Although it will be appreciated by those skilled in the art that in practice, "layer" and "sheet" may be used interchangeably, these concepts are employed herein to aid in understanding the embodiments.

[0074] In various embodiments, the thickness 362 of the glass sheets 350-1, 350-2, 350-3 can be substantially in the range of 20 microns to 150 microns, where "substantially" means + / - 5%. In some embodiments, the thickness of any glass sheet can be different from the thickness of any other glass sheet in the glass layer. In various embodiments, the dielectric layer 351 can include Ajinomoto built-up film (ABF), epoxy molding compound, any other dielectric layer referenced or described herein, or any other suitable dielectric material. In various embodiments, the dielectric layer 351 can be substantially 10 microns thick.

[0075] The local interconnect component 334 in the glass reinforcement layer 350 facilitates communication between two or more cores in a substrate, panel, and / or a portion of the panel assembly 100. The local interconnect component 334 may include an interposer (or bridge) or one or more redistribution layers (RDL). The local interconnect component 334 may be selectively located in the substrate. That is, in a panel including two dies connected by a local interconnect component (e.g., 334), the panel may also include adjacent dies that are not connected by a local interconnect component.

[0076] Figure 4A A simplified cross-sectional view of a first exemplary local interconnect feature is shown. Figure 4A FIG. 4 is a simplified cross-sectional view of a portion 400 of a panel substrate including an RDL 422 and a first glass sheet 450 that is part of the glass layer of the panel. Figure 13-Figure 21In the embodiment of , glass layer 450 can be a glass reinforcement layer (e.g., 350, 550, 650) or a glass layer that is part of a glass core. RDL 422 includes two component layers (sub-layers) 422a and 422b. Local interconnect component 434 (or bridge) is located in glass sheet 450 and provides interconnection between a first die attached to conductive contact 406 and a second die (not shown) connected to conductive contact 408.

[0077] The bridging conductive contact 476 is located on the surface 474 of the local interconnect component 434. In various embodiments, the bridging conductive contact 476 includes copper. The local interconnect component 434 includes conductive traces 480a, 480b, 480c, and 480d located in the first, second, third, and fourth dielectric layers 492, 494, 496, and 498, respectively. The dielectric layers 492, 494, 496, and 498 also include vias 478 that provide connections between conductive traces in different dielectric layers or between conductive traces and the bridging conductive contact 476.

[0078] The bridging via 478 and the bridging conductive trace 480 may include copper or another suitable conductive material and provide a conductive path between the bridging conductive contacts 476. The dielectric layers 492, 494, 496, 498, and 422 may be a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide, fluorine-doped silicon dioxide, hydrogen-doped silicon dioxide, or silicon nitride.

[0079] The interconnect structures (conductive traces 428a and vias 428b) in RDL 422 are similar to interconnect structures 328a and 328b and provide a conductive path from bridging conductive contact 476 to conductive contacts 406 of the first die or core and conductive contacts 408 of the second die or core. Vias 452 provide a connection from the RDL interconnect structures to bridging conductive pads 476. In embodiments where the top surface 474 of local interconnect feature 434 is flush with the top surface of the top glass sheet within the glass layer (e.g., surface 483), vias 452 may not be present.

[0080] In some embodiments, the area in one or more dielectric layers located above the local interconnect component may include an interconnect structure that provides a conductive path between the tube cores attached to the panel substrate. For example, area 487 in dielectric layer 422 includes conductive traces 428c and vias 428d, which provide a conductive path between one of conductive contacts 406 and one of conductive contacts 408. In other embodiments, the area above the local interconnect component does not contain wiring that provides a conductive path between adjacent tube cores. Conductive contacts and traces / vias 406, 428a, 428b, 428c, 428d, 452, 476, 478, 480a, and 480b together provide a conductive path between the first tube core and the second tube core, and thus allow the tube cores to be communicatively coupled.

[0081] In this example, two of vias 478 connect conductive trace 480b to 480c, and 480c to bridge pad 480d, which in turn connects to via 428e and conductive trace 428f within glass layer 450. Thus, local interconnect component 434 may also provide a conductive path between the first die and the second die to a conductive trace in the glass layer below local interconnect component 434.

[0082] Figure 4B 4 is a simplified cross-sectional view of a second exemplary local interconnect component. The local interconnect component 435 includes a through-silicon via (TSV) 452. The TSV 452 provides a conductive path from an interconnect structure (via 452) positioned adjacent to a top surface 474 of the local interconnect component 435 to an interconnect structure (via 454) positioned adjacent to a bottom surface 484 of the local interconnect component 435. In various embodiments, the TSV may include copper, tungsten, or another metal.

[0083] Figure 4BAlso shown is a trench capacitor 456 located in the local interconnect component 435. The trench capacitor 456 includes a first terminal (one or more first capacitor conductive traces) 458, a second terminal (one or more second capacitor conductive traces) 458, and a capacitor dielectric 459 located between the first terminal 457 and the second terminal 458. The first terminal 457 and the second terminal 458 include one or more conductive traces oriented substantially perpendicular to the top surface (e.g., upper surface 203) of the panel substrate in which the local interconnect component 435 is located. The capacitor dielectric 459 can include any dielectric disclosed herein (e.g., doped or undoped silicon dioxide, silicon nitride) or any other suitable dielectric. The first terminal 457 and the second terminal 458 are further connected to the conductive trace 486 of the local interconnect component, which allows connection to the capacitor 456 through an interconnect structure (e.g., via 452) external to the local interconnect component 435. In addition to trench capacitors, the local interconnect component can also include other types of capacitors, such as planar capacitors.

[0084] Figure 4C and Figure 4D 4 is a cross-sectional view and a top view of a third exemplary local interconnect component. Local interconnect component 437 includes a magnetic inductor array (MIA) 475. MIA 475 includes pads 477, vias 479, and conductive traces 481. Conductive traces 481 act as inductors and are surrounded by ferromagnetic material 491. Conductive traces 481 may include copper or another suitable metal, pads 477 may include nickel, palladium, and gold or another suitable metal or alloy, and ferromagnetic material 491 may include iron or an iron alloy. In some embodiments, ferromagnetic material 491 includes iron or iron alloy particles in an epoxy matrix.

[0085] In addition to TSVs, capacitors, and inductors (eg, MIAs), in other embodiments, local interconnect components 434 may include other passive components, such as resistors, and / or active components (eg, transistors).

[0086] As described above, the local interconnect components located in the panel substrate (e.g., the local interconnect components 434 embedded in the portion 400 of the panel substrate) can be implemented as a silicon interposer (interposer) or a local silicon interconnect (local interconnect). In some embodiments, the local interconnect components can be Embedded Multi-die Interconnect Bridge (EMIB). In some embodiments, the local interconnect component may conform to the Universal Chip Interconnect Express (UCIe) standard.

[0087] The local interconnect components may be fabricated separately from the panel substrate and then located in, integrated into, or embedded within the panel substrate. The separate fabrication of the local interconnect components allows the local interconnect components to be produced using semiconductor fabrication techniques, thereby producing local interconnect components having internal features (e.g., vias, pads, conductive traces) having geometric dimensions (e.g., via width / spacing, conductive trace width / spacing / thickness) that may be smaller than the geometric dimensions of similar features external to the local interconnect components in the panel substrate.

[0088] The local interconnect components can be located in the panel substrate by forming a cavity in the panel substrate during panel manufacturing (e.g., forming a cavity in a glass layer and / or one or more dielectric layers), inserting the local interconnect components within the panel substrate, and forming the remainder of the panel substrate. The local interconnect components can be located in a glass layer or one or more RDLs. The local interconnect components can span more than one RDL. The upper surface of the RDL can be flush with the upper surface on the RDL (including the upper surface of the RDL that is part of the upper surface of the panel surface). Thus, in the context of a local interconnect component located in a glass layer or one or more RDLs, the phrase "located in..." can mean that the local interconnect component is fully embedded (the glass layer or one or more RDLs are placed adjacent to all sides of the local interconnect component), or partially embedded (the glass layer or one or more RDLs are placed adjacent to less than all sides of the local interconnect component).

[0089] In some embodiments, local interconnects that provide conductive paths between adjacent die in a panel may be provided by an interconnect structure that is part of one or more RDL layers that provide routing of die-level signals to package-level signals. That is, adjacent die in a panel may be interconnected without the use of separately fabricated local interconnect components that are placed in the panel substrate during panel fabrication. Figure 4A Area 487, Fig.13 Area 1387, Fig.16 Area 1687, Fig.19 Area in 1987, Fig. 22 Area 2287 and Fig.24 Area 2487 in shows such a local interconnect.

[0090] refer to Figure 5 In various embodiments, the panel assembly 100 may implement waveguide routing and / or silicon photonic components, such as photonic integrated circuits (PICs). The simplified cross-sectional view of the portion 500 relates to the cut line AA′ and includes a substrate 501 . Figure 5A photonic integrated circuit (PIC) 562 is shown implemented in the panel architecture of portion 500 of panel substrate 501 implemented directly in glass reinforcement layer 550. PIC 562 and associated waveguide routing 564 outside substrate 501 may also be implemented directly in glass reinforcement layer 550, directly in substrate 501.

[0091] In these embodiments, the waveguide wiring 564 can be manufactured by laser direct writing in the glass sheet of the glass reinforcement layer 550. In an embodiment, the waveguide wiring 564 is a closed path formed or etched in the glass reinforcement layer 550, which has a first end 565 and a second end 567. The waveguide wiring 564 is constructed to passively allow light of a specific wavelength or wavelength range to travel therethrough. That is, in operation, the waveguide wiring 564 provides operable communication by receiving light from a first light source (e.g., PIC 562) at a first end 565, and passively transmits the light to the second end 567, where it can exit the waveguide wiring 564 (alternatively, the light can travel through the waveguide wiring in the opposite direction). In some embodiments, as shown, the waveguide wiring 564 has a first end 565 in operable communication with the PIC 562 and a second end 567 at the surface of the glass reinforcement layer. In various embodiments, as shown, the second end 567 can be located relative to Figure 5 and in other embodiments, the second end 567 may be located relative to the vertically oriented surface. Figure 5 In various embodiments, there may be an optional optical coupling component 569 added to the surface at the second end 567 for attaching external components to the waveguide wiring 564. Although in Figure 5 564 are shown as straight lines, but in reality, the waveguide wiring 564 can be implemented as a two-dimensional or three-dimensional pattern having a uniform diameter and a total path length that can include curves and / or loops, where the total path length (typically from the first end 565 to the second end 567) reflects the specific application.

[0092] In some embodiments, the waveguide wiring 564 may include a dielectric material having a higher dielectric constant, and therefore a higher refractive index, than the dielectric constant of the material surrounding the waveguide wiring (glass reinforcement layer 550). In some embodiments, the waveguide includes silicon and oxygen. In some embodiments, the waveguide may include a photonic crystal fiber, a hollow tube with a reflective inner surface (e.g., a polished metal or multilayer film that guides light by Bragg reflection), or a small prism surrounding a hollow tube that reflects light via internal reflection.

[0093] Photonic integrated circuits implement one or more photonic functions and include one or more optical components, such as waveguides, lasers, electro-optic modulators, polarizers, photodetectors, etc. PICs are commonly used in data communications (e.g., fiber optic communications) and sensing applications. Examples of PIC usage include wavelength division multiplexing (WDM), interferometers, wave modulators, optical transceivers, light detection and ranging (LiDAR) antennas, etc.

[0094] A non-limiting example of an optical component that may be included in a PIC is a silicon microring resonator (MRR), generally referred to herein as a ring resonator structure. A ring resonator structure is a passive structure that generally includes: (i) a compact circular microring structure that includes an optical silicon waveguide that loops back on itself with a small bending radius to resonate at one or more frequencies referred to as the spectral response or free spectral range (FSR); and (ii) a linear silicon waveguide that is located adjacent to and in communication with the microring structure.

[0095] In various embodiments, the micro-ring structure is substantially circular (i.e., deviates from circular by + / - 10%), and the silicon waveguide is substantially linear (i.e., deviates from linear by + / - 10%). In some embodiments, the micro-ring structure may have an elliptical shape or the shape of a racetrack. In some embodiments, the silicon waveguide may include a curve in the area beside the micro-ring structure to enhance the coupling effect between the silicon waveguide and the micro-ring structure. In some embodiments of the ring resonator structure, the ring resonator structure also includes an optional second silicon waveguide that is also linear.

[0096] In some embodiments, the micro-ring structure may include silicon. In some embodiments, the micro-ring structure may include a lightly doped P region, a lightly doped N region, a highly doped P+ region, a highly doped N+ region, intrinsic silicon, and silicon dioxide (as a separator between different Si doping regions when needed). The optical component (e.g., PIC) may be embedded in the panel substrate by forming a cavity in the panel substrate during panel manufacturing, inserting the optical component into the panel substrate, and forming the rest of the panel substrate.

[0097] When implementing PIC 562, the number of glass sheets (e.g., individual glass sheets 550-1, 550-2, and 550-3) may be informed by the thickness of PIC 562. For example, for PICs with a thickness in the range of 300 microns to 1 millimeter, the glass reinforcement layer 550 should be equal to the thickness of the PIC, and thus the number of associated glass layers may be in the range of three to ten.

[0098] A non-limiting manner for identifying the PIC may include visually inspecting both the material present in the cross-sectional view and the structure and shape of the material to determine that a ring resonator structure has been implemented. Although in various embodiments, the ring resonator structure may include the same material as an electronic integrated circuit (e.g., a CMOS (complementary metal oxide semiconductor) component), the structure of the ring resonator structure and its shape employ a different doping profile than the CMOS component. Various embodiments of the ring resonator structure (in the cross-sectional view) may have a thickness of approximately 220 nanometers.

[0099] like Figure 5 As shown, in various embodiments, an optional local interconnect component 534 may also be present in the glass reinforcement layer 550. The integration of the local interconnect component (e.g., 534) and the PIC (e.g., 562) into the glass reinforcement layer of the panel is independent of each other. That is, the panel may include one or more local interconnect components and / or one or more PICs.

[0100] Waveguide wiring 564 may enable the embedded PIC 562 to communicate with a fiber array unit (FAU) connector located outside the panel. The FAU connector may be a top side connector such as a grating coupler or an edge connector (such as a micro lens or V-groove). Return to Reference Figure 1 In various panel assembly 100 embodiments, the FAU may be within the panel architecture (e.g., within the panel 108 at position 124 (e.g., see Fig. 9 , FAU 910)) or implemented outside the panel but within the panel assembly (e.g., at location 122). Any panel or panel assembly herein may have multiple PICs and multiple FAUs.

[0101] like Figure 6As shown, embodiments of panel architectures may employ cavities and / or microchannels in glass reinforcement layers. The simplified cross-sectional view of portion 600 relates to cutting line A-A' and includes substrate 601. Microchannel 668 may be added to glass reinforcement layer 650 to help remove heat from components of the panel. Microchannel 668 is another example of a closed passage formed in glass reinforcement layer 650. Microchannel 668 may include lateral portions 668-1 and 668-2 and vertical portions 668-3. In some embodiments, a microchannel lateral portion is formed on the surface of a glass layer (or glass sheet) by, for example, etching or laser cutting, and a microchannel vertical portion is formed by, for example, drilling through a glass layer (or glass sheet). In some embodiments, a microchannel vertical portion may include a through-glass via having an appropriate diameter to facilitate the flow of a liquid coolant. In other embodiments, a lateral portion of microchannel 668 may be located inside a glass layer. Microchannel vertical portion 668-3 extends through more than one glass sheet (through 650-1 and 650-2, and into 650-3). In an embodiment, the microchannel lateral portion (e.g., 668-2) can be located near a set of conductive contacts, where "near" refers to the surface of the glass reinforcement layer below the conductive contacts. It is understood that although Figure 6 The schematic diagram of FIG. 668 is two-dimensional, but indicates the three-dimensional nature of the design / configuration of microchannel 668 ; for example, transverse portion 668 - 2 passes in front of two TGVs 652 and behind one TGV 652 .

[0102] Some embodiments add cavities in the glass reinforcement layer 650 to serve as a pool or reservoir for liquid coolant. When there is a cavity 671, the cavity 671 can be located in the glass reinforcement layer, and similar to the microchannel 668, the cavity 671 can be etched or laser cut into the surface of the glass sheet. In other embodiments, the cavity can be formed inside the glass layer. In embodiments implementing the cavity 671 and the microchannel 668, the microchannel 668 can be configured to utilize the flow of the liquid coolant in the cavity to extract heat from the glass reinforcement layer 650. Therefore, the diameter of the microchannel 668 can be a function of the selected liquid coolant (e.g., water, alcohol, ethylene glycol) because the diameter is selected to accommodate the movement of the selected liquid coolant at the expected operating temperature of the tube core located near the microchannel 668. The glass in the glass reinforcement layer 650 can provide an airtight seal around the microchannel 668 for the liquid coolant flowing closest to the corresponding tube core, thereby enhancing the cooling function of the tube core.

[0103] Substrate 601 illustrates optional local interconnect features 634 implemented in glass reinforcement layer 650, as described in connection with other embodiments. However, other embodiments of substrate 601 and / or the resulting panel do not necessarily include optional local interconnect features 634. In other words, the panel may include cavity 671 and / or microchannel 668 without local interconnect features 634.

[0104] The panel may include one or more ports (e.g., at 673) to allow connection to an external liquid-cooled thermal management solution to cool the panel (e.g., by controlling the flow of fluid into / out of microchannels 668). In various embodiments, the liquid-cooled thermal management solution may include: a heat exchanger to remove heat through heated liquid coolant leaving the panel that has absorbed heat generated by the tube core on the panel; a pump to provide circulation of the coolant through the microchannels; and conduits to connect the panel, the heat exchanger, and the pump. The liquid-cooled thermal management solution can cool multiple panels. In addition, the liquid-cooled thermal management solution can be co-located in the same system as the panel cooled by the liquid-cooled thermal management solution, or located external to the system in which the panel is located. For example, in a rack-level solution, the liquid-cooled thermal management solution can cool panel components in multiple systems located within a rack. Panels that employ microchannels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, the panel can remove heat generated by the die within the panel through thermal management solutions located both below the die (cavities and / or microchannels) and above the die (e.g., thermal management solutions such as liquid cooling, vapor chambers, heat sinks).

[0105] During manufacturing, the panel architecture of the embodiments may be filled and packaged using a variety of techniques. Figure 7 , embodiment 700 shows a solder resist or dielectric layer 712 having conductive pads 726 therein, to which solder balls 702 can be attached at a first pitch or fine pitch, thereby allowing a die or core particle to be attached thereto. In embodiment 720, the solder resist or dielectric layer 712 is shown as having a recess 706 etched therein, into which solder balls 708 are placed before attaching the die or core particle. Notably, the recess 706 has tapered walls that are wider at the upper opening and narrower where the recess meets the conductive contact. Similarly, the bottom surface of the panel architecture can have exposed second-level interconnects (SLIs) or conductive contacts 732, which are arranged in the solder resist or dielectric layer 718 at a pitch greater than the pitch of the conductive contacts or the pitch of the BGA or land grid array (LGA). Solder balls 710 can be attached to the SLI or conductive contacts 732. Figure 7 The examples in are non-limiting.

[0106] Go to Figure 8-Figure 9 , an exemplary process flow for panel architecture is provided. Figure 8-Figure 9 The schematic diagram in FIG. 1 relates to the cutting line B-B', because the chips (chips) 1-3 are the first panel ( Fig. 9 1, which is generally similar to panel 106), and chips (chips) 4-5 are a portion of the second panel ( Fig. 9 "Panel 2" in the figure is generally similar to a portion of panel 108). Figure 8-Figure 9 The process flow shown in can be used in conjunction with the above Figure 3 , Figure 5-Figure 6 and Figure 21-25 The described embodiments, therefore, show some intra-panel architectural features (e.g., local interconnect components) for chips 1-3 and separately for chips 4-5, although microchannels and cavities are not depicted to simplify the drawings. The order of operations described in the process flow is non-limiting, the operations may be performed in a different order, and operations may be added or removed without changing the final product. During manufacturing and packaging, panel 1 and panel 2 will be singulated or cut apart (at 859).

[0107] At 800, a glass carrier 806 is employed to build a plurality of panels thereon. The glass carrier 806 is used to provide a mechanically rigid surface for depositing corresponding buildup layers or RDLs and solder resists, performing etching, depositing copper or other conductive trace and pad materials, and stacking a glass reinforcement layer 850, thereby achieving a panel substrate architecture as described herein. The glass carrier 806 may also provide a level of flatness that may not be achievable for other types of substrates (e.g., printed circuit boards comprising organic substrate materials). The flatness provided by the glass carrier may enable the formation of smaller feature sizes (e.g., via width / spacing, conductive contact width / spacing), thereby enabling the formation of conductive contacts, vias, and other features with fine pitches. The glass carrier 806 has an area of ​​at least the same size as the area of ​​a single panel described herein, and may be, for example, 510 mm×515 mm, or larger or smaller as desired. The glass carrier 806 may be an alkali-free alkaline earth boroaluminosilicate glass, such as a glass including aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium), such as a glass including SiO2, Al2O3, B2O3, and MgO, or a photosensitive glass. The glass carrier 806 may have a thickness in the range of 0.5 to 2 mm (+ / - 10%).

[0108] On the upper surface 803 of the panel architecture (similar to the upper surfaces 203, 303, 503 and 603), conductive contacts 808 are arranged to attach corresponding chips or dies at positions 802-1, 802-2, 802-3, 802-4 and 802-5. The conductive contacts 808 are arranged at an appropriate pitch (e.g., a "die pitch") for the attachment of the corresponding dies. Thus, the pitch of the conductive contacts at position 802-1 may be different from the pitch of the conductive contacts 808 at position 802-2, and so on. In various embodiments, the conductive contacts 808 are attached to the corresponding dies at a fine pitch for first level interconnect (FLI).

[0109] Optional embedded structures, such as local interconnect components 804-1, 804-2, and 804-3, may be formed at this packaging stage. Optional cavities 671 and microchannels 668 may be etched at this stage. Additionally, optional waveguides may be etched, and photonic integrated circuits (e.g., Fig. 9 , PIC 906, waveguide 908). Although not shown for clarity of illustration, the RDL interconnect structure can be implemented directly above the local interconnect component.

[0110] At 835, as illustrated, the corresponding integrated circuit dies or chips can be attached (i.e., assembled) to the panel substrate. As described above, the chips (chip 1, chip 2, chip 3, chip 4, and chip 5) can implement different functions, have different heights, have different pin (output pin) arrangements, have different lateral dimensions, and / or can occupy different amounts of cross-sectional area within the panel. Different panels can have the same or different numbers of chips. The assembly at 835 can be referred to as performing fine pitch assembly. At 835, any welding technology or hybrid bonding technology can be used. The various chips can be assembled to the panel substrate using bottom filler 812; and although the bottom filler 812 is depicted as being uniform, in reality, the bottom filler of each chip can be different (for example, the bottom filler under chip 1 can be different from the bottom filler of chip 2, etc.). The embodiment at 835 can be referred to as a filled panel substrate.

[0111] At 855, the glass carrier 806 can be debonded or removed from the populated panel substrate, and the panel substrate can be cut into corresponding panels (e.g., the four panel squares initially described, as indicated by dashed lines 859). At 855, solder balls 857 can be attached via second level interconnects or conductive contacts 832 at the lower surface, and mechanical contact such as for LGA attachment can be performed. Optionally, the solder balls 857 can be added before the populated panel substrate is cut into corresponding panels.

[0112] As depicted at 900, respective large form factor thermal solutions 960 and 962 may be added to the single populated panel substrates (Panel 1 and Panel 2), and in various embodiments, underfills 964 and 966 may be added respectively under the large form factor thermal solutions 960 and 962. Co-packaged integrated circuit components, such as FAU 910, may be added at 930.

[0113] According to an embodiment, encapsulant 972 may be applied / molded over the panel, as shown at 930 for panel 1. At 930, in a non-limiting example, FAU 910 may be attached to PIC 906 via waveguide 908 as part of panel 2. In other embodiments, the co-packaged integrated circuit components may be located outside the panel, above the panel, or stacked vertically with the panel.

[0114] In some embodiments, at 930, a single packaged multi-die panel (e.g., Panel 1) having the panel architecture provided herein is a complete HPC solution for an application. In other embodiments, multiple panels are assembled into a panel assembly, e.g. Figure 1 . Embodiment 950 generally reflects cut line B-B', showing panel 1 and panel 2 assembled onto a panel-level substrate 970. Panel-level substrate 970 may include one or more layers, each of which includes an inorganic or organic dielectric material (e.g., any dielectric material disclosed or referenced herein), one or more conductive traces, and one or more vias. Substrate 970 may provide a conductive path between panels. For example, substrate 970 includes two substrate layers of conductive traces 973 and vias 974 that provide a conductive path connection between conductive contacts 976 of panel 1 and conductive contacts 978 of panel 2. The resulting panel assembly at 950 may provide a complete HPC solution for an application, or the panel assembly from 950 may be further assembled with other components to provide a complete HPC solution.

[0115] Fig.10is an exemplary first method of forming a panel. At 1004 in method 1000, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first pitch. At 1008, a glass layer is formed on the first dielectric layer, the glass layer including a local interconnect component. At 1012, a second dielectric layer is located on the glass layer, the second dielectric layer including conductive contacts arranged at a second pitch, the conductive contacts are also arranged in a first group and a second group, and the local interconnect component is used to provide electrical communication between the first group of first conductive contacts and the second group of first conductive contacts. At 106, an interconnect structure is located in the glass layer, the interconnect structure is used to provide electrical communication between the first group of second conductive contacts and one of the conductive pads.

[0116] Fig.11 is an exemplary second method of forming a panel. At 1104, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first spacing. At 1108, a glass layer is formed on the first dielectric layer, the glass layer including a photonic integrated circuit (PIC). At 1112, a second dielectric layer is located on the glass layer, the second dielectric layer including conductive contacts arranged at a second spacing, and the conductive contacts are also arranged in a first group and a second group. The PIC is configured to electrically communicate with the first group of first conductive contacts or the second group of first conductive contacts. At 1116, an interconnect structure is located in the glass layer, the interconnect structure is used to provide electrical communication between the first group of second conductive contacts and one of the conductive pads.

[0117] Fig.12 is an exemplary third method of forming a panel. At 1204, a first dielectric layer is formed on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm×250 mm, the first dielectric layer including conductive pads arranged at a first spacing. At 1208, a glass layer is formed on the first dielectric layer, the glass layer including microchannels. At 1212, a second dielectric layer is located on the glass layer, the second dielectric layer including conductive contacts arranged at a second spacing, the conductive contacts also being arranged in a first group and a second group. The microchannel is constructed to have a portion proximate to the first group. At 1216, an interconnect structure is located in the glass layer, the interconnect structure being used to provide electrical communication between the first group of conductive contacts and one of the conductive pads.

[0118] The order of the elements in methods 1000, 1100, and 1200 is non-limiting. The operations of the methods may be performed in a different order, and operations may be added or removed without changing the final product. For example, any of methods 1000, 1100, and 1200 may further include: attaching a first die to the first group; and attaching a second die to the second group, thereby producing a filled substrate. In a second example, any of methods 1000, 1100, and 1200 may further include debonding the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0119] Figure 13-Figure 21 Simplified cross-sectional views of various "core" panel embodiments are shown, wherein the panel substrate comprises a glass core. Figure 1 The dielectric layer is located on the upper surface of the glass core (between the integrated circuit die and the glass core), or on the upper and bottom surfaces of the glass core. The glass core provides similar functions (signal routing, mechanical stability during manufacturing, a flat surface on which the dielectric layer can be formed) and has similar Figure 3 , Figure 5-Figure 6 The glass reinforcement layer in the panel has similar properties (it can be composed of the same material and have a similar expansion coefficient as the material of the integrated circuit die attached to the panel), but due to Figure 13-Figure 21 The panel embodiment shown is not assembled on a glass carrier, so Figure 13-Figure 21 The glass core can be compared Figure 3 , Figure 5-Figure 6 Thickness of glass reinforcement layer.

[0120] Fig.13 13 is a simplified cross-sectional view of an exemplary panel substrate portion including a glass core. Panel portion 1300 includes a glass core 1351 located between a first set of dielectric layers (RDL, buildup layers) 1322 (1322a, 1322b, 1322c, 1322d) and a second set of dielectric layers 1324 (1324a, 1324b). The first set of dielectric layers 1322 are stacked vertically, and the second set of dielectric layers 1324 are stacked vertically. That is, a single first dielectric layer 1322 (e.g., 1322a) is placed adjacent to another first dielectric layer 1322 (e.g., 1322b), and a single second dielectric layer 1324 (e.g., 1324a) is placed adjacent to another second dielectric layer 1324 (e.g., 1324b). Glass core 1351 includes glass layer 1354, encapsulation layers 1370 and 1372, and through glass vias (TGVs) 1352 located in layer 1354. Glass core 1351 has a thickness 1380. Encapsulation layers 1370 and 1372 include dielectric layer 1374 in which TGV contacts 1376 are located.

[0121] The upper surface contact layer 1356 includes solder resist or other suitable dielectric material 1312 and conductive contacts 1326, which are arranged to correspond to the output pins of the core particle to be attached to the panel portion 1300. The upper surface contact layer 1356 (and therefore, the conductive contacts 1326) is located on the top dielectric layer (e.g., 1322a) in the first dielectric layer 1322. A group of conductive contacts 1326 is arranged with a fine pitch. The lower surface contact layer 1360 includes solder resist or other suitable dielectric material 1318 and conductive contacts 1332, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1360 (and therefore, the conductive contacts 1332) is located on the bottom dielectric layer (e.g., 1324b) in the second dielectric layer 1324. A group of conductive contacts 1332 is arranged with a pitch greater than the fine pitch at which a group of conductive contacts 1326 are arranged.

[0122] The dielectric layer 1322 includes conductive traces 1328a and vias 1328b, and the dielectric layer 1324 includes conductive traces 1330a and vias 1330b. The local interconnects including vias 1328b and conductive traces 1328a included in the region 1387 provide a conductive path between conductive contacts 1326 belonging to a first set of conductive contacts 1364 to be attached to a first integrated circuit die and conductive contacts 1326 belonging to a second set of conductive contacts 1366 to be attached to a second integrated circuit die.

[0123] Vias 1328b and 1330b are shown as tapered, with the narrower end of the via being closer to the glass core 1351 than the wider end of the via. These tapers reflect that dielectric layers 1322 and 1324 are built up from glass core 1351, and when individual dielectric layers 1322 and 1324 are etched to form vias, they are etched toward glass core 1351. Vias in dielectric layers of other panel embodiments that include glass cores (e.g., vias 1428b, 1430b, 1528b, 1530b, 1628b, 1630b) are similarly tapered.

[0124] Fig.1414 is a simplified cross-sectional view of an exemplary panel assembly including a panel including a glass core and local interconnect components located in a set of dielectric layers of the panel. Panel assembly 1400 includes panel 1403, integrated circuit components 1405 and 1407 attached to panel 1403, and thermal management solution 1409. Panel 1403 includes a glass core 1451 located between a first set of dielectric layers 1422 (1422a, 1422b, 1422c, 1422d) and a second set of dielectric layers 1424 (1424a, 1424b). The first set of dielectric layers 1422 and the second set of dielectric layers 1424 are stacked vertically. Glass core 1451 includes glass layer 1454, encapsulation layers 1470 and 1472, and through glass vias (TGVs) 1452 located in glass layer 1454. Glass core 1451 has a thickness 1480. Encapsulation layers 1470 and 1472 include a dielectric layer 1474 in which TGV contacts 1476 are located.

[0125] The upper surface contact layer 1456 includes solder resist or other suitable dielectric material 1412 and conductive contacts 1426, which are arranged to correspond to the output pins of the tube core 1404 and 1408 directly attached to the panel 1403. The upper surface contact layer 1456 (and therefore, the conductive contacts 1426) is located on the top dielectric layer (e.g., 1422a) in the first dielectric layer 1422. A set of conductive contacts 1426 is arranged with a fine pitch. The lower surface contact layer 1460 includes solder resist or other suitable dielectric material 1418 and conductive contacts 1432, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1460 (and therefore, the conductive contacts 1432) is located on the bottom dielectric layer (e.g., 1424b) in the second dielectric layer 1424. The set of conductive contacts 1432 are arranged at a pitch that is greater than the fine pitch at which the set of conductive contacts 1426 are arranged.

[0126] The dielectric layer 1422 includes conductive traces 1428a and vias 1428b, and the dielectric layer 1424 includes conductive traces 1430a and vias 1430b. The local interconnect component 1434 provides a conductive path between the conductive contacts 1426 connected to the die 1404 and the first packaged integrated circuit component 1492 and the conductive contacts 1426 connected to the die 1408 and the second packaged integrated circuit component 1407.

[0127] Integrated circuit die 1404 and 1408 are attached to panel substrate 1401 at conductive contacts 1426 via solder balls 1438. In other embodiments, die 1404 and 1408 can be attached to panel substrate 1401 by other methods (e.g., hybrid bonding). Panel 1403 also includes solder balls 1410 attached to panel substrate 1401 at conductive contacts 1432. In other embodiments, panel 1403 does not include solder balls 1410, and the package can be attached to other components, such as a printed circuit board, via conductive contacts 1432 as pads. Package panel 1403 also includes an encapsulation 1498 that surrounds die 1404 and 1408 and panel substrate 1401.

[0128] Integrated circuit components 1405 and 1407 are attached to panel 1403 by a package-on-package assembly technique, wherein solder balls 1411 of integrated circuit components 1405 and 1407 are attached to through-package vias 1415 that extend through encapsulation 1498 and are attached to conductive contacts 1426. Panel assembly 1400 illustrates only one example of how a package may be attached to a package panel. In other embodiments, integrated circuit components may be attached to a package panel by different methods.

[0129] Fig.15 1 is a simplified cross-sectional view of an exemplary panel including a glass core with local interconnect components located in the glass core. Panel 1500 includes integrated circuit dies 1504a, 1504b, 1504c, 1504d, and 1508 and a thermal management solution 1509 attached directly or indirectly to the panel. Panel 1500 includes a glass core 1551 located between a first set of vertically stacked dielectric layers 1522 (1522a, 1522b, 1522c, 1522d) and a second set of vertically stacked dielectric layers 1524 (1524a, 1524b). Glass core 1551 includes glass layer 1554, encapsulation layers 1570 and 1572, and through glass vias (TGVs) 1552 located in glass layer 1554. Glass core 1551 has a thickness 1580. Encapsulation layers 1570 and 1572 include a dielectric layer 1574 in which TGV contacts 1576 are located.

[0130] The upper surface contact layer 1556 includes solder resist or other suitable dielectric material 1512 and conductive contacts 1526, which are arranged to correspond to the output pins of the tube core 1504a and 1508 directly attached to the panel substrate 1501. The upper surface contact layer 1556 (and therefore, the conductive contacts 1526) is located on the top dielectric layer (e.g., 1522a) in the first dielectric layer 1522. A set of conductive contacts 1526 is arranged with a fine pitch. The lower surface contact layer 1560 includes solder resist or other suitable dielectric material 1518 and conductive contacts 1532, which are arranged to correspond to the desired panel level output pins. The lower surface contact layer 1560 (and therefore, the conductive contacts 1532) is located on the bottom dielectric layer (e.g., 1524b) in the second dielectric layer 1524. A set of conductive contacts 1532 are arranged at a pitch that is greater than the fine pitch at which a set of conductive contacts 1526 are arranged.

[0131] The dielectric layer 1522 includes conductive traces 1528a and vias 1528b, and the dielectric layer 1524 includes conductive traces 1530a and vias 1530b. Local interconnect features 1534 located in the glass layer 1554 of the glass core 1551 provide a conductive path between one of the conductive contacts 1526 connected to the die 1504a and one of the conductive contacts connected to the die 1508.

[0132] Integrated circuit dies 1504a and 1508 are attached to panel substrate 1501 at conductive contacts 1526 via solder balls 1538. In other embodiments, dies 1504a and 1508 may be attached to the panel substrate by other methods, such as hybrid bonding. Panel 1500 also includes solder balls 1510 attached to panel substrate 1501 at conductive contacts 1532. In other embodiments, panel 1500 does not include solder balls 1510, and the panel may be attached to other components, such as a printed circuit board, via conductive contacts 1532 as pads.

[0133] Integrated circuit die 1504a, 1504b, 1504c and 1504d are vertically stacked and connected by solder bumps (or microbumps) 1519, which are connected to through-silicon vias (TSVs) 1517 extending through die 1504c and 1504d. TSVs may include copper, carbon nanotubes, graphene nanotubes or other suitable materials. Stacked die 1504a-d can implement various functions, and in one embodiment, die 1504a can be a high bandwidth memory (HBM) controller die that controls HBM die 1504b-d. In other embodiments, die 1504a may include TSVs 1517 connected to conductive contacts 1526. Panel 1500 shows an example of how a panel can accommodate vertically stacked integrated circuit die. In other embodiments, integrated circuit components may be attached to the panel by different methods.

[0134] Fig.16 1 is a simplified cross-sectional view of an exemplary panel including a glass core and a photonic integrated circuit. Panel 1600 includes integrated circuit dies 1604 and 1608, a glass core 1651 located between a first set of vertically stacked dielectric layers 1622 (1622a, 1622b, 1622c, 1622d) and a second set of vertically stacked dielectric layers 1624 (1624a, 1624b), photonic integrated chips 1622a and 1622b, and a thermal management solution 1609. Glass core 1651 includes glass layer 1654, encapsulation layers 1670 and 1673, and through glass vias (TGVs) 1652 located in glass layer 1654. Glass core 1651 has a thickness 1680. Encapsulation layers 1670 and 1672 include dielectric layer 1674, and TGV contacts 1676 are located in dielectric layer 1374.

[0135] The upper surface contact layer 1656 includes solder resist or other suitable dielectric material 1612 and conductive contacts 1626, which are arranged to correspond to the output pins of the tube core 1604 and 1608 directly attached to the panel 1600. The upper surface contact layer 1656 (and therefore, the conductive contacts 1626) is located on the top dielectric layer (e.g., 1622a) in the first dielectric layer 1622. A group of conductive contacts 1626 is arranged with a fine pitch. The lower surface contact layer 1660 includes solder resist or other suitable dielectric material 1618 and conductive contacts 1632, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1660 (and therefore, the conductive contacts 1632) is located on the bottom dielectric layer (e.g., 1624b) in the second dielectric layer 1624. A set of conductive contacts 1632 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 1626 are arranged.

[0136] Dielectric layer 1622 includes conductive traces 1628a and vias 1628b, and dielectric layer 1624 includes conductive traces 1630a and vias 1630b. Local interconnects including vias 1628b and conductive traces 1628a included in region 1687 provide a conductive path between conductive contacts 1626 attached to die 1604 and conductive contacts 1626 attached to die 1608.

[0137] Integrated circuit dies 1604 and 1608 are attached to conductive contacts 1626 via solder balls 1638. In other embodiments, dies 1604 and 1608 may be attached to conductive contacts 1626 by other methods, such as hybrid bonding. Panel 1600 also includes solder balls 1610 attached to conductive contacts 1632. In other embodiments, panel 1600 does not include solder balls 1610, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1632 as pads.

[0138] Panel 1600 includes photonic integrated circuits (PICs) 1662a and 1662b. PICs 1662a and 1662b are located on glass layer 1654. PICs 1662a and 1662b are attached to conductive contacts 1626 associated with dies 1604 and 1608, respectively. The PICs are integrated into panel 1600 during panel manufacturing and are therefore considered part of panel 1600. Waveguides 1664a and 1664b are located in glass layer 1654 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1600. Fiber array units 1621a and 1621b are attached to panel 1600, wherein waveguide 1664a provides an optical communication path for optical signals to be generated or received by PIC 1662a or FAU 1621a, and waveguide 1664b provides an optical communication path for optical signals to be generated or received by PIC 1662b or FAU 1621b.

[0139] Fig.17 17 is a simplified cross-sectional view of an exemplary panel including a glass core, a photonic integrated circuit, and local interconnect components. Panel 1700 includes integrated circuit dies 1704 and 1708, a glass core 1751 located between a first set of vertically stacked dielectric layers 1722 (1722a, 1722b, 1722c, 1722d) and a second set of vertically stacked dielectric layers 1724 (1724a, 1724b), and a thermal management solution 1709. Glass core 1751 includes glass layer 1754, encapsulation layers 1770 and 1772, and through glass vias (TGVs) 1752 located in glass layer 1754. Glass core 1751 has a thickness 1780.

[0140] The upper surface contact layer 1756 includes solder resist or other suitable dielectric material 1712 and conductive contacts 1726, which are arranged to correspond to the output pins of the tube core 1704 and 1708 directly attached to the panel 1700. The upper surface contact layer 1756 (and therefore, the conductive contacts 1726) is located on the top dielectric layer (e.g., 1722a) in the first dielectric layer 1722. A set of conductive contacts 1726 is arranged with a fine pitch. The lower surface contact layer 1760 includes solder resist or other suitable dielectric material 1718 and conductive contacts 1732, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1760 (and therefore, the conductive contacts 1732) is located on the bottom dielectric layer (e.g., 1724b) in the second dielectric layer 1724. A set of conductive contacts 1732 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 1726 are arranged.

[0141] The dielectric layer 1722 includes conductive traces 1728a and vias 1728b, and the dielectric layer 1724 includes conductive traces 1730a and vias 1730b. The local interconnect features 1734 provide conductive paths between the conductive contacts 1726 attached to the die 1704 and the conductive contacts attached to the die 1708.

[0142] Integrated circuit dies 1704 and 1708 are attached to conductive contacts 1726 via solder balls 1738. In other embodiments, dies 1704 and 1708 may be attached to conductive contacts 1726 by other methods, such as hybrid bonding. Panel 1700 also includes solder balls 1710 attached to conductive contacts 1732. In other embodiments, panel 1700 does not include solder balls 1710, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1732 as pads.

[0143] Panel 1700 includes photonic integrated circuits (PICs) 1762a and 1762b. PICs 1762a and 1762b are located on glass layer 1754. PICs 1762a and 1762b are attached to conductive contacts 1726 associated with dies 1704 and 1708, respectively. PICs 1762a and 1762b are integrated into panel 1700 during panel manufacturing and are therefore considered part of panel 1700. Waveguides 1764a and 1764b are located in glass layer 1754 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1700. Fiber array units 1721a and 1721b are attached to panel 1700, wherein waveguide 1764a provides an optical communication path for optical signals to be generated or received by PIC 1762a or FAU 1721a, and waveguide 1764b provides an optical communication path for optical signals to be generated or received by PIC 1762b or FAU 1721b.

[0144] Fig.18 1 is a simplified cross-sectional view of an exemplary panel including a glass core, a photonic integrated circuit, and a local interconnect component located in the glass core. Panel 1800 includes integrated circuit dies 1804 and 1808, a glass core 1851 located between a first set of vertically stacked dielectric layers 1822 (1822a, 1822b, 1822c, 1822d) and a second set of vertically stacked dielectric layers 1824 (1824a, 1824b), and a thermal management solution 1809. Glass core 1851 includes glass layer 1854, encapsulation layers 1870 and 1872, and through glass vias (TGVs) 1852 located in glass layer 1854. Glass core 1851 has a thickness 1880.

[0145] The upper surface contact layer 1856 includes solder resist or other suitable dielectric material 1812 and conductive contacts 1826, which are arranged to correspond to the output pins of the tube core 1804 and 1808 directly attached to the panel 1800. The upper surface contact layer 1856 (and therefore, the conductive contacts 1826) is located on the top dielectric layer (e.g., 1822a) in the first dielectric layer 1822. A set of conductive contacts 1826 is arranged with a fine pitch. The lower surface contact layer 1860 includes solder resist or other suitable dielectric material 1818 and conductive contacts 1832, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1860 (and therefore, the conductive contacts 1832) is located on the bottom dielectric layer (e.g., 1824b) in the second dielectric layer 1824. A set of conductive contacts 1832 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 1826 are arranged.

[0146] Dielectric layer 1822 includes conductive traces 1828a and vias 1828b, and dielectric layer 1824 includes conductive traces 1830a and vias 1830b. Local interconnect features 1834 located in glass core 1851 provide conductive paths between conductive contacts 1826 connected to die 1804 and conductive contacts connected to die 1808.

[0147] Integrated circuit dies 1804 and 1808 are attached to conductive contacts 1826 via solder balls 1838. In other embodiments, dies 1804 and 1808 may be attached to conductive contacts 1826 by other methods, such as hybrid bonding, and panel 1800 further includes solder balls 1810 attached to conductive contacts 1832. In other embodiments, panel 1800 does not include solder balls 1810, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1832 as pads.

[0148] Panel 1800 includes photonic integrated circuits (PICs) 1862a and 1862b. PICs 1862a and PICs 1862b are located on glass layer 1854. PICs 1862a and PICs 1862b are attached to conductive contacts 1826 associated with dies 1804 and 1808, respectively. The PICs are integrated into panel 1800 during panel manufacturing and are therefore considered part of panel 1800. Waveguides 1864a and 1864b are located in glass layer 1854 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1800. Fiber array units 1821a and 1821b are attached to panel 1800, wherein waveguide 1864a provides an optical communication path for optical signals to be generated or received by PIC 1862a or FAU 1821a, and waveguide 1864b provides an optical communication path for optical signals to be generated or received by PIC 1862b or FAU 1821b.

[0149] Fig.19 1 is a simplified cross-sectional view of an exemplary panel including a glass core with microchannels and a photonic integrated circuit. Panel portion 1900 includes a glass core 1951 located between a first set of dielectric layers (RDL, buildup layers) 1922 (1922a, 1922b, 1922c, 1922d) and a second set of dielectric layers 1924 (1924a, 1924b). The first set of dielectric layers 1922 are stacked vertically, and the second set of dielectric layers 1924 are stacked vertically. Glass core 1951 includes glass layer 1954, encapsulation layers 1970 and 1972, and through glass vias (TGVs) 1952 located in layer 1954. Glass core 1951 has a thickness 1980. Encapsulation layers 1970 and 1972 include dielectric layer 1974, and TGV contacts 1976 are located in dielectric layer 1374.

[0150] The upper surface contact layer 1956 includes solder resist or other suitable dielectric material 1912 and conductive contacts 1926, which are arranged to correspond to the output pins of the tube core 1904 and 1908 directly attached to the conductive contacts 1926. The upper surface contact layer 1956 (and therefore, the conductive contacts 1926) is located on the top dielectric layer (e.g., 1922a) in the first dielectric layer 1922. A set of conductive contacts 1926 is arranged with a fine pitch. The lower surface contact layer 1960 includes solder resist or other suitable dielectric material 1918 and conductive contacts 1932, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 1960 (and therefore, the conductive contacts 1932) is located on the bottom dielectric layer (e.g., 1924b) in the second dielectric layer 1924. A set of conductive contacts 1932 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 1926 are arranged.

[0151] Dielectric layer 1922 includes conductive traces 1928a and vias 1928b, and dielectric layer 1924 includes conductive traces 1930a and vias 1930b. Local interconnects including vias 1928b and conductive traces 1928a included in region 1987 provide a conductive path between conductive contacts 1926 attached to die 1904 and conductive contacts 1926 attached to die 1908.

[0152] Integrated circuit dies 1904 and 1908 are attached to conductive contacts 1926 via solder balls 1938. In other embodiments, dies 1904 and 1908 may be attached to conductive contacts 1926 by other methods, such as hybrid bonding. Panel 1900 also includes solder balls 1910 attached to conductive contacts 1932. In other embodiments, panel 1900 does not include solder balls 1910, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 1932 as pads.

[0153] Panel 1900 includes photonic integrated circuits (PICs) 1962a and 1962b. PICs 1962a and PICs 1962b are located on glass layer 1954. PICs 1962a and PICs 1962b are attached to conductive contacts 1926 associated with dies 1904 and 1908, respectively. The PICs are integrated into panel 1900 during panel manufacturing and are therefore considered part of panel 1900. Waveguides 1964a and 1964b are located in glass layer 1954 and are also manufactured during panel manufacturing and are therefore also considered part of panel 1900. Fiber array units 1921a and 1921b are attached to panel 1900, wherein waveguide 1964a provides an optical communication path for optical signals to be generated or received by PIC 1962a or FAU 1921a, and waveguide 1964b provides an optical communication path for optical signals to be generated or received by PIC 1962b or FAU 1921b.

[0154] like Fig.19 As shown, in some embodiments, the panel can include cavities and / or microchannels in the glass core. Generally, including microchannels in the glass core of the panel helps remove heat generated by the integrated circuit die attached to the panel or any heat-generating components located in the panel (such as active components located in the local interconnect components). Microchannels 1968 are located in the glass layer 1954 and can be formed on the surface of the glass layer 1954 by, for example, etching or laser cutting. In other embodiments, microchannels 1968 can be located inside the glass layer 1954. It will be appreciated that although Fig.19 The schematic diagram of is two-dimensional, but by showing the microchannel 1968 as passing in front of some TGVs 1952 and behind other TGVs 1952, this indicates the three-dimensional nature of the design / construction of the microchannel 1968.

[0155] Some panel embodiments with microchannels may further include a cavity in the glass core to act as a pool or reservoir for a liquid coolant. The microchannels may be configured to draw heat from the glass core using the flow of liquid coolant in the cavity. In panel 1900, glass core 1951 includes cavity 1971. Cavity 1971 may be etched or laser cut into the surface of glass layer 1954. In other embodiments, the cavity may be formed inside the glass layer. Port 1973 provides a connection to an external liquid-cooled thermal management solution for cooling panel 1900 (e.g., by controlling the flow of fluid into / out of microchannel 1968).

[0156] Fig. 202000 is a simplified cross-sectional view of an exemplary panel including a glass core with microchannels, a photonic integrated circuit, and local interconnect components located in a dielectric layer. Panel 2000 includes integrated circuit dies 2004 and 2008, a glass core 2051 located between a first set of vertically stacked dielectric layers 2022 (2022a, 2022b, 2022c, 2022d) and a second set of vertically stacked dielectric layers 2024 (2024a, 2024b), and a thermal management solution 2009. Glass core 2051 includes glass layer 2054, encapsulation layers 2070 and 2072, and through glass vias (TGVs) 2052 located in glass layer 2054. Glass core 2051 has a thickness 2080.

[0157] The upper surface contact layer 2056 includes solder resist or other suitable dielectric material 2012 and conductive contacts 2026, which are arranged to correspond to the output pins of the tube core 2004 and 2008 directly attached to the panel 2000. The upper surface contact layer 2056 (and therefore, the conductive contacts 2026) is located on the top dielectric layer (e.g., 2022a) in the first dielectric layer 2022. A group of conductive contacts 2026 is arranged with a fine pitch. The lower surface contact layer 2060 includes solder resist or other suitable dielectric material 2018 and conductive contacts 2032, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2060 (and therefore, the conductive contacts 2032) is located on the bottom dielectric layer (e.g., 2024b) in the second dielectric layer 2024. A set of conductive contacts 2032 are arranged at a pitch that is greater than the fine pitch at which a set of conductive contacts 2026 are arranged.

[0158] The dielectric layer 2022 includes conductive traces 2028a and vias 2028b, and the dielectric layer 2024 includes conductive traces 2030a and vias 2030b. The local interconnect features 2034 provide conductive paths between the conductive contacts 2026 attached to the die 2004 and the conductive contacts attached to the die 2008.

[0159] Integrated circuit dies 2004 and 2008 are attached to conductive contacts 2026 via solder balls 2038. In other embodiments, dies 2004 and 2008 may be attached to conductive contacts 2026 by other methods, such as hybrid bonding. Panel 2000 also includes solder balls 2010 attached to conductive contacts 2032. In other embodiments, panel 2000 does not include solder balls 2010, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2032 as pads.

[0160] Panel 2000 includes photonic integrated circuits (PICs) 2022a and 2022b. PICs 2022a and 2022b are located on glass layer 2054. PICs 2062a and 2062b are attached to conductive contacts 2026 associated with dies 2004 and 2008, respectively. PICs 2062a and 2062b are integrated into panel 2000 during panel manufacturing and are therefore considered part of panel 2000. Waveguides 2064a and 2064b are located in glass layer 2054 and are also manufactured during panel manufacturing and are therefore also considered part of panel 2000. Fiber array units 2021a and 2021b are attached to panel 2000, wherein waveguide 2064a provides an optical communication path for optical signals to be generated or received by PIC 2062a or FAU 2021a, and waveguide 2064b provides an optical communication path for optical signals to be generated or received by PIC 2062b or FAU 2021b.

[0161] Glass core 2051 includes microchannels 2068 located in glass layer 2054. Microchannels 2068 can be formed on the surface of glass layer 2054 by, for example, etching or laser cutting. In other embodiments, microchannels 2068 can be located inside glass layer 2054. It is understood that although Fig. 20 The schematic diagram of is two-dimensional, but by showing the microchannel 2068 as passing in front of some TGVs 2052 and behind other TGVs 2052, this indicates the three-dimensional nature of the design / configuration of the microchannel 2068.

[0162] The glass core 2051 also includes a cavity 2071 connected to the microchannel 2068. The cavity 2071 can be etched or laser cut into the surface of the glass layer 2054. In other embodiments, the cavity can be formed inside the glass layer. Port 2073 provides a connection to an external liquid cooling thermal management solution for cooling the panel 2000 (e.g., by controlling the flow of fluid into / out of the microchannel 2068).

[0163] Fig.2121 is a simplified cross-sectional view of an exemplary panel including a glass core with microchannels, a photonic integrated circuit, and local interconnect components located in the glass core. Panel 2100 includes integrated circuit dies 2104 and 2108, a glass core 2151 located between a first set of vertically stacked dielectric layers 2122 (2122a, 2122b, 2122c, 2122d) and a second set of vertically stacked dielectric layers 2124 (2124a, 2124b), and a thermal management solution 2109. Glass core 2151 includes glass layer 2154, encapsulation layers 2170 and 2172, and through glass vias (TGVs) 2152 located in glass layer 2154. Glass core 2151 has a thickness 2180.

[0164] The upper surface contact layer 2156 includes solder resist or other suitable dielectric material 2112 and conductive contacts 2126, which are arranged to correspond to the output pins of the tube core 2104 and 2108 directly attached to the panel 2100. The upper surface contact layer 2156 (and therefore, the conductive contacts 2126) is located on the top dielectric layer (e.g., 2122a) in the first dielectric layer 2122. A group of conductive contacts 2126 is arranged with a fine pitch. The lower surface contact layer 2160 includes solder resist or other suitable dielectric material 2118 and conductive contacts 2132, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2160 (and therefore, the conductive contacts 2132) is located on the bottom dielectric layer (e.g., 2124b) in the second dielectric layer 2124. A set of conductive contacts 2132 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 2126 are arranged.

[0165] Dielectric layer 2122 includes conductive traces 2128a and vias 2128b, and dielectric layer 2124 includes conductive traces 2130a and vias 2130b. Local interconnect features 2134 located in glass core 2151 provide conductive paths between conductive contacts 2126 connected to die 2104 and conductive contacts connected to die 2108.

[0166] Integrated circuit dies 2104 and 2108 are attached to conductive contacts 2126 via solder balls 2138. In other embodiments, dies 2104 and 2108 may be attached to conductive contacts 2126 by other methods, such as hybrid bonding. Panel 2100 also includes solder balls 2110 attached to conductive contacts 2132. In other embodiments, panel 2100 does not include solder balls 2110, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2132 as pads.

[0167] Panel 2100 includes photonic integrated circuits (PICs) 2162a and 2162b. PICs 2162a and PICs 2162b are located on glass layer 2154. PICs 2162a and PICs 2162b are attached to conductive contacts 2126 associated with dies 2104 and 2108, respectively. The PICs are integrated into panel 2100 during panel manufacturing and are therefore considered part of panel 2100. Waveguides 2164a and 2164b are located in glass layer 2154 and are also manufactured during panel manufacturing and are therefore also considered part of panel 2100. Fiber array units 2121a and 2121b are attached to panel 2100, wherein waveguide 2164a provides a path for optical communication between PIC 2162a and FAU 2121a, and waveguide 2164b provides a path for optical communication between PIC 2162b and FAU 2121b.

[0168] Panel 2100 includes photonic integrated circuits (PICs) 2122a and 2122b. PICs 2122a and PICs 2122b are located on a glass core 2151. PICs 2162a and PICs 2162b are attached to conductive contacts 2126 associated with dies 2104 and 2108, respectively. The PICs are integrated into panel 2100 during panel manufacturing and are therefore considered part of panel 2100. Waveguides 2164a and 2164b are located in glass layer 2154 and are also manufactured during panel manufacturing and are therefore considered part of panel 2100. Fiber array units 2121a and 2121b are attached to panel 2100, wherein waveguide 2164a provides an optical communication path for optical signals to be generated or received by PIC2162a or FAU 2121a, and waveguide 2164b provides an optical communication path for optical signals to be generated or received by PIC2162b or FAU 2121b.

[0169] Glass core 2151 includes microchannels 2168 located in glass layer 2154. Microchannels 2168 can be formed on the surface of glass layer 2154 by, for example, etching or laser cutting. In other embodiments, microchannels 2168 can be located inside glass layer 2154. It is understood that although Fig.21 The schematic diagram of is two-dimensional, but by showing the microchannel 2168 as passing in front of some TGVs 2152 and behind other TGVs 2152, this indicates the three-dimensional nature of the design / configuration of the microchannel 2168.

[0170] The glass core 2151 also includes a cavity 2171 connected to the microchannel 2168. The cavity 2171 can be etched or laser cut into the surface of the glass layer 2154. In other embodiments, the cavity can be formed inside the glass layer. Port 2173 provides a connection to an external liquid cooling thermal management solution for cooling the panel 2100 (e.g., by controlling the flow of fluid into / out of the microchannel 2168).

[0171] Figure 13-Figure 21 The "core" panel and panel assembly shown in FIG. 1, wherein the integrated circuit die is attached to the panel substrate or panel, is merely illustrative. As described above, the Figure 13-Figure 21 More integrated circuit dies are shown attached to or incorporated into a panel or panel assembly, and the die attached to the panel may have a different lateral size, area, height, shape, and / or implement a different function than another die attached to or incorporated into the panel.

[0172] Figure 13-Figure 21 The glass cores of the illustrated embodiments (eg, glass cores 1351, 1451, 1551) may include any glass described or referenced herein, or include any glass layer described or referenced herein (eg, Figure 3 , Figure 5-Figure 6 The glass reinforcement layer in the embodiment may include materials. Figure 13-Figure 21 The dielectric layers of the encapsulation layers in the glass core in the illustrated embodiment (eg, dielectric layer 1374 , dielectric layer 1474 , dielectric layer 1574 ) may include any dielectric material described or referenced herein. Figure 13-Figure 21 The TGVs (e.g., TGVs 1352, 1452, 1552) in the glass core in the illustrated embodiment may include copper or any other suitable metal. In alternative embodiments, the glass core may not include TGV contacts (e.g., 1376, 1476, 1576), and vias (e.g., vias 1328b, 1330b, 1428b, 1430b, 1528b, 1530b) in the dielectric layers on either side of the glass core may be directly attached to the TGVs.

[0173] Figure 13-Figure 21 The upper surface contact layer (e.g., 1326, 1426, 1526) shown can take the form of other upper surface contact layer embodiments, such as in combination with Figure 7 (e.g., 726a, 726b) described embodiments. Figure 13-Figure 21 The lower surface contact layer (e.g., 1360, 1460, 1560) shown in the figure can take the form of other lower surface contact layer embodiments, such as in combination with Figure 7 Described embodiments (eg, lower surface contact layer embodiment 760).

[0174] Figure 14-Figure 21 The illustrated thermal management solutions (eg, 1409 , 1509 , 1609 ) may include any cooling components described or referenced herein and attached to an integrated circuit component or integrated circuit die via a thermal interface material.

[0175] Figure 16-Figure 21 The fiber array units shown (e.g., 1621a, 1621b, 1721a, 1721b, 1821a, 1821b) can be attached to the panel during panel manufacturing and can be part of the end panel product or attached to the panel after panel manufacturing. Any FAU described or referenced herein can include optical fibers (e.g., 1625, 1725, 1825) as part of the optical connection between panels in a system or between panels on different systems.

[0176] Figure 19-21 The microchannels shown in (e.g., microchannel 1968, microchannel 2068, microchannel 2168) are located in the glass core layer, and the diameter of the microchannel can be a function of the selected liquid coolant (e.g., water, alcohol, ethylene glycol) because the diameter is selected to accommodate the movement of the selected liquid coolant at the expected operating temperature of the tube core located near the microchannel. The glass core can provide an airtight seal around the microchannel for the liquid coolant flowing closest to the corresponding tube core, thereby enhancing the cooling function of the tube core. The microchannel ports (e.g., 1973, 2073, 2173) allow the microchannel to be connected to an external liquid-cooled thermal management solution for cooling the panel (e.g., by controlling the flow of fluid into / out of the microchannel). In various embodiments, the liquid-cooled thermal management solution may include: a heat exchanger to remove heat through the heated liquid coolant leaving the panel, which has absorbed the heat generated by the tube core on the panel; a pump for providing circulation of the coolant through the microchannel; and a conduit for connecting the panel, the heat exchanger and the pump. Liquid-cooled thermal management solutions can cool multiple panels.

[0177] In addition, a liquid-cooled thermal management solution (which includes microchannels in a glass core and / or cooling components attached to one or more integrated circuit components and / or a die attached to a panel or panel assembly) can be co-located in the same system as the panel or panel assembly cooled by the liquid-cooled thermal management solution. In some embodiments, the thermal management solution is located outside the system. For example, in a rack-level solution, a liquid-cooled thermal management solution can cool panels in multiple systems located within a rack. Panels that employ microchannels and cavities may or may not have a large form factor thermal management solution attached to the top of the panel. That is, the panel can remove heat generated by the die within the panel through thermal management solutions located both below the die (cavity and / or microchannels) and above the die (e.g., thermal management solutions such as liquid cooling, vapor chambers, heat sinks).

[0178] Figure 13-Figure 21 The "core" panel embodiment shown includes various panel features that can be independently integrated into the panel. That is, these panel features are independent of each other and can be mixed and matched to produce Figure 13-Figure 21 The panel features shown in the figure include: local interconnects that are integrally formed with the dielectric layers of the panel and provide electrical communication between the die in the panel; local interconnect components that are separately manufactured during panel manufacturing and placed within the panel (in one or more dielectric layers or glass core) and provide electrical communication between the die in the panel, PICs, waveguides, vertically stacked packaged or unpackaged die, and microchannels (and reservoirs) in the glass core.

[0179] Figure 22-Figure 25 Simplified cross-sectional views of various "coreless" panel embodiments are shown, wherein the panel includes a set of dielectric layers to which integrated circuit dies are attached, but does not include a core (e.g., a glass core for a "core" panel embodiment). Figure 1 The dielectric layers in a coreless panel are not formed on a core that becomes part of the panel, but are formed on a glass carrier that provides mechanical stability during panel manufacturing and provides a flat surface on which panel features with fine pitch can be formed. Figure 22-Figure 25 The glass carrier used during manufacturing is not shown in FIG. Since the coreless panel embodiments do not have a glass core or glass reinforcement layer, the coreless panel embodiments can be thinner than any of these types of panel embodiments.

[0180] Fig. 222200 includes integrated circuit dies 2204 and 2208 attached to a set of vertically stacked dielectric layers 2222, and a thermal management solution 2209. The upper surface contact layer 2256 includes solder resist or other suitable dielectric material 2212 and conductive contacts 2226, which are arranged to correspond to the output pins of the dies 2204 and 2208 directly attached to the panel 2200. The upper surface contact layer 2256 (and therefore, the conductive contacts 2226) is located on the top dielectric layer (e.g., 2222a) in the dielectric layer 2222. A set of conductive contacts 2226 is arranged with a fine pitch. The lower surface contact layer 2260 includes solder resist or other suitable dielectric material 2218 and conductive contacts 2232, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2260 (and therefore, the conductive contacts 2232) is located on a bottom dielectric layer (eg, 2222d) in the dielectric layers 2222. A set of conductive contacts 2232 is arranged at a pitch greater than the fine pitch at which a set of conductive contacts 2226 are arranged.

[0181] The dielectric layer 2222 includes conductive traces 2228a and vias 2228b. The local interconnects included in the region 2287, including the vias 2228b and conductive traces 2228a, provide a conductive path between the conductive contacts 2226 attached to the integrated circuit die 2204 and the conductive contacts 2226 attached to the second integrated circuit die 2208.

[0182] Integrated circuit dies 2204 and 2208 are attached to conductive contacts 2226 via solder balls 2238. In other embodiments, dies 2204 and 2208 may be attached to conductive contacts 2226 by other methods, such as hybrid bonding. Panel 2200 also includes solder balls 2210 attached to conductive contacts 2232. In other embodiments, panel 2200 does not include solder balls 2210, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2232 as pads.

[0183] Fig.2323 is a simplified cross-sectional view of an exemplary coreless panel including local interconnect components. Panel 2300 includes integrated circuit dies 2304 and 2308 attached to a set of vertically stacked dielectric layers 2322, and a thermal management solution 2309. Upper surface contact layer 2356 includes solder resist or other suitable dielectric material 2312 and conductive contacts 2326, which are arranged to correspond to the output pins of dies 2304 and 2308 directly attached to conductive contacts 2326. Upper surface contact layer 2356 (and therefore, conductive contacts 2326) is located on the top dielectric layer (e.g., 2322a) in the first dielectric layer 2322. A set of conductive contacts 2326 is arranged with a fine pitch. Lower surface contact layer 2360 includes solder resist or other suitable dielectric material 2318 and conductive contacts 2332, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2360 (and therefore, the conductive contacts 2332) is located on a bottom dielectric layer (eg, 2322b) in the dielectric layers 2322. A set of conductive contacts 2332 is arranged at a pitch greater than the fine pitch at which a set of conductive contacts 2326 are arranged.

[0184] The dielectric layer 2322 includes conductive traces 2328a and vias 2328b. The local interconnect features 2334 provide a conductive path between the conductive contacts 2326 attached to the die 2304 and the conductive contacts attached to the die 2308.

[0185] Integrated circuit dies 2304 and 2308 are attached to conductive contacts 2326 via solder balls 2338. In other embodiments, dies 2304 and 2308 may be attached to conductive contacts 2326 by other methods, such as hybrid bonding. Panel 2300 also includes solder balls 2310 attached to conductive contacts 2332. In other embodiments, panel 2300 does not include solder balls 2310, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2332 as pads.

[0186] Fig.24 2400 includes integrated circuit dies 2404 and 2408 attached to a set of vertically stacked dielectric layers 2422 (1622a, 2422b, 2422c, 2422d), a photonic integrated circuit 2462, a waveguide interposer 2427, and a thermal management solution 2409.

[0187] The upper surface contact layer 2456 includes solder resist or other suitable dielectric material 2412 and conductive contacts 2426, which are arranged to correspond to the output pins of the tube core 2404 and 2408 directly attached to the conductive contacts 2526. The upper surface contact layer 2456 (and therefore, the conductive contacts 2426) is located on the top dielectric layer (e.g., 2422a) in the dielectric layer 2422. A group of conductive contacts 2426 is arranged with a fine pitch. The lower surface contact layer 2460 includes solder resist or other suitable dielectric material 2418 and conductive contacts 2432, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2460 (and therefore, the conductive contacts 2432) is located on the bottom dielectric layer (e.g., 2422d) in the dielectric layer 2422. A set of conductive contacts 2432 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 2426 are arranged.

[0188] The dielectric layer 2422 includes a conductive trace 2428a and a via 2428b. The local interconnects included in the region 2487, including the via 2428b and the conductive trace 2428a, provide a conductive path between the conductive contacts 2426 attached to the die 2404 and the conductive contacts 2426 attached to the die 2408.

[0189] Dies 2404 and 2408 are attached to conductive contacts 2426 via solder balls 2438. In other embodiments, dies 2404 and 2408 may be attached to conductive contacts 2426 by other methods, such as hybrid bonding. Panel 2400 also includes solder balls 2410 attached to conductive contacts 2432. In other embodiments, panel 2400 does not include solder balls 2410, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2432 as pads.

[0190] The die 2404 is attached to the PIC 2462 via solder balls 2419, which are attached to pads 2431 and 2433 belonging to the die 2404 and the PIC 2462, respectively. The die 2404 can implement one or more functions, including analog functions implemented using electronic components (e.g., transistors). In some embodiments, the die 2404 can control the behavior of the PIC and / or act as an interface between the PIC 2462 and other panel components (e.g., the die 2408). In the case of communicating with the PIC, the die 2404 can be referred to as an electronic integrated chip (EIC), and the PIC 2462 and the die 2404 can be collectively referred to as a PIC-EIC pair.

[0191] The waveguide interposer 2427 includes a waveguide 2464 that provides a path for optical communication for an optical signal to be generated or received by the PIC 2462 or the FAU 2421. The waveguide interposer 2427 may be formed as part of the panel 2400 during assembly of the panel.

[0192] Fig.25 25 is a simplified cross-sectional view of an exemplary coreless panel including a photonic integrated circuit and local interconnect components. Panel 2500 includes integrated circuit dies 2504 and 2508 attached to a set of vertically stacked dielectric layers 2522 (2522a, 2522b, 2522c, 2522d), a photonic integrated circuit 2562, a waveguide interposer 2527, and a thermal management solution 2509.

[0193] The upper surface contact layer 2556 includes solder resist or other suitable dielectric material 2512 and conductive contacts 2526, which are arranged to correspond to the output pins of the tube core 2504 and 2508 directly attached to the conductive contacts 2526. The upper surface contact layer 2556 (and therefore, the conductive contacts 2526) is located on the top dielectric layer (e.g., 2522a) in the dielectric layer 2522. A group of conductive contacts 2526 is arranged with a fine pitch. The lower surface contact layer 2560 includes solder resist or other suitable dielectric material 2518 and conductive contacts 2532, which are arranged to correspond to the desired panel-level output pins. The lower surface contact layer 2560 (and therefore, the conductive contacts 2532) is located on the bottom dielectric layer (e.g., 2522d) in the dielectric layer 2522. A set of conductive contacts 2532 are arranged at a pitch greater than the fine pitch at which a set of conductive contacts 2526 are arranged.

[0194] The dielectric layer 2522 includes conductive traces 2528a and vias 2528b. The local interconnect features included in the region 2562, including the vias 2528b and conductive traces 2528a, provide a conductive path between the conductive contacts 2526 attached to the die 2504 and the conductive contacts 2526 attached to the die 2508.

[0195] Dies 2504 and 2508 are attached to conductive contacts 2526 via solder balls 2538. In other embodiments, dies 2504 and 2508 may be attached to conductive contacts 2526 by other methods, such as hybrid bonding. Panel 2500 also includes solder balls 2510 attached to conductive contacts 2532. In other embodiments, panel 2500 does not include solder balls 2510, and the package may be attached to other components, such as a printed circuit board, via conductive contacts 2532 as pads.

[0196] The die 2504 is attached to the PIC 2562 via solder balls 2519, which are attached to pads 2531 and 2533 belonging to the die 2504 and PIC 2562, respectively. The die 2504 can implement one or more functions, including analog functions implemented using electronic components (e.g., transistors). In some embodiments, the die 2504 can control the behavior of the PIC and / or act as an interface between the PIC 2562 and other panel components (e.g., die 2508). In the case of communicating with the PIC, 2504 can be referred to as an electronic integrated chip (EIC), and the PIC 2562 and the die 2504 can be collectively referred to as a PIC-EIC pair.

[0197] The waveguide interposer 2527 includes a waveguide 2564 that provides a path for optical communication for an optical signal to be generated or received by the PIC 2462 or the FAU 2421. The waveguide interposer 2527 may be formed as part of the panel 2500 during assembly of the panel.

[0198] Figure 22-Figure 25 The "coreless" panels and panel sections shown in are illustrative only. In addition, as previously mentioned, the Figure 22-Figure 25 More integrated circuit dies are shown attached to the panel, and a die attached to or incorporated into the panel may have a different lateral size, area, shape, height, and / or implement a different function than another die attached to or incorporated into the panel.

[0199] Figure 22-Figure 25 The upper surface contact layer (e.g., 2226, 2326, 2426, 2526) shown in the figure can take the form of other upper surface contact layer embodiments, such as in combination with Figure 7 (e.g., 726a, 726b) described embodiments. Figure 22-Figure 25 The lower surface contact layer (e.g., 2260, 2360, 2460) shown in the figure can take the form of other lower surface contact layer embodiments, such as in combination with Figure 7 Described embodiments (eg, lower surface contact layer embodiment 760).

[0200] Figure 22-Figure 25 The thermal management solutions shown in (eg, 2209, 2309, 2409, 2509) may include any cooling components described or referenced herein and attached to an integrated circuit component or integrated circuit die via a thermal interface material.

[0201] Figure 24-25The fiber array units (e.g., 2421, 2521) shown in the figure can be attached to the panel during panel manufacturing and can be part of the terminal panel product or attached to the panel after panel manufacturing. Any FAU described or referenced herein may include optical fibers (e.g., 2425, 2525) as part of the optical connection between panels in a system or between panels on different systems.

[0202] Figure 24-25 The waveguide interposer shown in FIG. 24 (e.g., 2427, 2527) may include any glass described or referenced herein, or include any glass layer described or referenced herein (e.g., Figure 3 , Figure 5-Figure 6 The glass reinforcement layer in the embodiment may include materials.

[0203] Figure 22-Figure 25 The coreless panel embodiment shown includes various panel features that can be independently integrated into the panel. Figure 22-Figure 25 The panel features shown and various other panel features described herein are independent of each other and can be mixed and matched to produce Figure 22-Figure 25 Coreless panel arrangement in addition to the panel features shown. These panel features include: local interconnects that are integrally formed with the dielectric layer of the panel and provide electrical communication between the die in the panel; local interconnect components that are separately manufactured and placed within the panel during panel manufacturing and provide electrical communication between the die in the panel, the PIC and waveguide interposer, and the vertically stacked packaged or unpackaged die.

[0204] Fig.26 is a fourth exemplary method of forming a panel. At 2604 in method 2600, the following are formed on a glass carrier: a plurality of dielectric layers, a single dielectric layer of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts on a bottom dielectric layer of the dielectric layers, the first conductive contacts being arranged at a first pitch less than 100 nm and the second conductive contacts being arranged at a second pitch greater than the first pitch. At 2608, one or more integrated circuit dies are attached to the first conductive contacts. At 2612, the glass carrier is removed from the dielectric layers.

[0205] The order of the elements in method 2600 is non-limiting. The operations of method 2600 can be performed in a different order, and operations can be added or subtracted without changing the final product. For example, method 2600 can also include etching one or more of the dielectric layers to create a cavity; and placing a bridge in the cavity, the bridge including one or more conductive traces and one or more vias.

[0206] Various non-limiting embodiments of panel architectures and methods of manufacturing the same have been described. The disclosed panel embodiments can enable high performance computing (e.g., Zeta-class computing) applications using panels having dimensions that exceed what is possible with wafer-level integration. The provided embodiments enable system-level heterogeneous integration of computing, I / O, memory, power management integrated circuit components and dies (which can include vertical stacking of integrated circuit components and dies), and thermal cooling solutions.

[0207] Fig. 27 2702 may be included in any of the embodiments disclosed herein. Wafer 2700 may be composed of semiconductor material and may include one or more die 2702 formed on a surface of wafer 2700. After completing the fabrication of integrated circuit components on wafer 2700, wafer 2700 may undergo a singulation process in which die 2702 are separated from one another to provide discrete "chips" or packaged integrated circuit components. Individual dies 2702 including integrated circuit components may include one or more transistors (e.g., transistors discussed below). Fig.28 Some of the transistors in transistors 2840), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 2700 or die 2702 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. In addition, multiple devices may be combined on a single die 2702. For example, a memory array formed by multiple memory devices may be coupled to a processor unit (e.g., Fig.30 The processor unit 3002 in the chip or other logic units configured to store information in a memory device or execute instructions stored in a memory array are formed on the same die 2702. In some embodiments, the die 2702 can be attached to a wafer 2700 including other dies, and the wafer 2700 is then singulated, which is a manufacturing process called die-to-wafer assembly technology.

[0208] Fig.28 2702 ( FIG. 2703 ) is a cross-sectional side view of an integrated circuit 2800 that may be included in any of the embodiments disclosed herein. One or more integrated circuits in the integrated circuit 2800 may be included in one or more dies 2702 ( Fig. 27 ). The integrated circuit 2800 may be formed on a die substrate 2802 (eg, Fig. 272700) and may be included in a die (e.g., Fig. 27 In the tube core 2702).

[0209] The die substrate 2802 can be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 2802 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials that may or may not be combined with silicon can be used to form the die substrate 2802, and the alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Groups II-VI, III-V, or IV can also be used to form the die substrate 2802. Although several examples of materials that can form the die substrate 2802 are described herein, any material that can serve as the basis for the integrated circuit 2800 can be used. The die substrate 2802 can be a singulated die (e.g., Fig. 27 2702) or a wafer (e.g., Fig. 27 portion of wafer 2700).

[0210] The integrated circuit 2800 may include one or more device layers 2804 disposed on a die substrate 2802. The device layer 2804 may include features of one or more transistors 2840 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 2802. The transistor 2840 may include, for example, one or more source and / or drain (S / D) regions 2820, a gate 2822 for controlling current flow between the S / D regions 2820, and one or more S / D contacts 2824 for routing electrical signals to / from the S / D regions 2820.

[0211] The gate 2822 may be formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include a layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0212] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2840 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0213] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0214] In some embodiments, when viewed from a cross section of transistor 2840 along the source-channel-drain direction, the gate electrode may include a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 2802 and two sidewall portions substantially perpendicular to the top surface of die substrate 2802. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 2802 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 2802. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0215] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0216] The S / D region 2820 may be formed within the die substrate 2802 adjacent to the gate 2822 of the single transistor 2840. For example, the S / D region 2820 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 2802 to form the S / D region 2820. An annealing process may follow the ion implantation process, which activates the dopant and diffuses it further into the die substrate 2802. In the latter process, the die substrate 2802 may first be etched to form a recess at the location of the S / D region 2820. An epitaxial deposition process may then be performed to fill the recess with the material used to fabricate the S / D region 2820. In some embodiments, the S / D region 2820 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) may be used to form S / D region 2820. In further embodiments, S / D region 2820 may be formed using one or more layers of metals and / or metal alloys.

[0217] The device layer 2804 may be provided with one or more interconnect layers (in Fig.28 2806-2810) to route electrical signals (e.g., power and / or input / output (I / O) signals) to and / or from devices (e.g., transistors 2840) of device layer 2804. For example, conductive features (e.g., gates 2822 and S / D contacts 2824) of device layer 2804 can be electrically coupled to interconnect structures 2828 of interconnect layers 2806-2810. One or more interconnect layers 2806-2810 can form a metallization stack (also referred to as an "ILD stack") 2819 of integrated circuit 2800.

[0218] Interconnect structure 2828 may be arranged within interconnect layers 2806-2810 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig.28 The specific configuration of interconnect structure 2828 depicted in FIG. Fig.28 A particular number of interconnect layers 2806 - 2810 are depicted in FIG. 2 , but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

[0219] In some embodiments, the interconnect structure 2828 may include a line 2828a and / or a via 2828b filled with a conductive material (e.g., metal). The line 2828a may be arranged to route electrical signals in a direction of a plane substantially parallel to the surface of the die substrate 2802 on which the device layer 2804 is formed. For example, the line 2828a may route electrical signals in a direction in and out of the page and / or in a direction across the page. The via 2828b may be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 2802 on which the device layer 2804 is formed. In some embodiments, the via 2828b may electrically couple the lines 2828a of different interconnect layers 2806-2810 together.

[0220] like Fig.28 As shown, interconnect layers 2806-2810 may include dielectric material 2826 disposed between interconnect structures 2828. In some embodiments, dielectric material 2826 disposed between interconnect structures 2828 in different ones of interconnect layers 2806-2810 may have different compositions; in other embodiments, the composition of dielectric material 2826 between different interconnect layers 2806-2810 may be the same. Device layer 2804 may also include dielectric material 2826 disposed between transistor 2840 and the bottom layer of the metallization stack. Dielectric material 2826 included in device layer 2804 may have a different composition than dielectric material 2826 included in interconnect layers 2806-2810; in other embodiments, the composition of dielectric material 2826 in device layer 2804 may be the same as dielectric material 2826 included in any one of interconnect layers 2806.

[0221] A first interconnect layer 2806 (referred to as metal 1 or "M1") can be formed directly on the device layer 2804. In some embodiments, as shown, the first interconnect layer 2806 can include lines 2828a and / or vias 2828b. The lines 2828a of the first interconnect layer 2806 can be coupled to contacts (e.g., S / D contacts 2824) of the device layer 2804. The vias 2828b of the first interconnect layer 2806 can be coupled to the lines 2828a of the second interconnect layer 2808.

[0222] A second interconnect layer 2808 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 2806. In some embodiments, the second interconnect layer 2808 may include vias 2828b to couple the wires 2828 of the second interconnect layer 2808 with the wires 2828a of the third interconnect layer 2810. Although the wires 2828a and the vias 2828b are structurally drawn with lines within a single interconnect layer for clarity, in some embodiments, the wires 2828a and the vias 2828b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0223] A third interconnect layer 2810 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) can be formed successively on the second interconnect layer 2808 according to similar techniques and constructions described in conjunction with the second interconnect layer 2808 or the first interconnect layer 2806. In some embodiments, interconnect layers that are "higher up" (i.e., farther from the device layer 2804) in the metallization stack 2819 in the integrated circuit 2800 can be thicker than interconnect layers lower in the metallization stack 2819, with lines 2828a and vias 2828b in higher interconnect layers being thicker than lines and vias in lower interconnect layers.

[0224] The integrated circuit 2800 may include a solder resist material 2834 (eg, polyimide or a similar material) and one or more conductive contacts 2836 formed on the interconnect layer 2806. Fig.28 , the conductive contacts 2836 are shown as taking the form of bonding pads. The conductive contacts 2836 can be electrically coupled to the interconnect structure 2828 and configured to route electrical signals of the transistor(s) 2840 to an external device. For example, a solder joint can be formed on one or more of the conductive contacts 2836 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit 2800 to another component (e.g., a printed circuit board). The integrated circuit 2800 may include additional or alternative structures to route electrical signals from the interconnect layers 2806-2810; for example, the conductive contacts 2836 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0225] In some embodiments where the integrated circuit 2800 is a double-sided die, the integrated circuit 2800 may include another metallization stack (not shown) on the opposite side of the device layer(s) 2804. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 2806-2810 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 2804 and additional conductive contacts (not shown) on the side of the integrated circuit 2800 opposite the conductive contacts 2836.

[0226] In other embodiments where the integrated circuit 2800 is a double-sided die, the integrated circuit 2800 may include one or more through-silicon vias (TSVs) through the die substrate 2802; these TSVs may contact the device layer(s) 2804 and may provide a conductive path between the device layer(s) 2804 and additional conductive contacts (not shown) located on the side of the integrated circuit 2800 opposite the conductive contacts 2836. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit 2800 from the conductive contacts 2836 to the transistors 2840 and any other components integrated into the die 2800, and the metallization stack 2819 may be used to route I / O signals from the conductive contacts 2836 to the transistors 2840 and any other components integrated into the die 2800.

[0227] Multiple integrated circuits 2800 can be stacked, wherein one or more TSVs in a single stacked device provide a connection between one device in the device and any device in the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between a single HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0228] Fig.29 2900, which may include any of the embodiments disclosed herein. The microelectronic assembly 2900 includes a plurality of integrated circuit components disposed on a circuit board 2902 (which may be a motherboard, a system board, a mainboard, etc.). The microelectronic assembly 2900 may include components disposed on a first side 2940 of the circuit board 2902 and an opposing second side 2942 of the circuit board 2902; typically, the components may be disposed on one or both of the sides 2940 and 2942.

[0229] In some embodiments, circuit board 2902 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. A single metal layer includes conductive traces. Any one or more of the metal layers may be formed in accordance with a desired circuit pattern to route electrical signals between components coupled to circuit board 2902 (optionally, in conjunction with other metal layers). In other embodiments, circuit board 2902 may be a non-PCB substrate. Fig.29The illustrated microelectronic assembly 2900 includes a package-on-interposer structure 2936 coupled to a first side 2940 of a circuit board 2902 via a coupling feature 2916. The coupling feature 2916 can electrically and mechanically couple the package-on-interposer structure 2936 to the circuit board 2902 and can include solder balls (e.g., Fig.29 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0230] Package-on-interposer structure 2936 may include integrated circuit component 2920 coupled to interposer 2904 via coupling component 2918. Coupling component 2918 may take any appropriate form for the application, such as the forms discussed above with reference to coupling component 2916. Fig.29 A single integrated circuit component 2920 is shown in FIG. 29 , but multiple integrated circuit components may be coupled to interposer 2904 ; indeed, additional interposers may be coupled to interposer 2904 . Interposer 2904 may provide an intermediate substrate for bridging circuit board 2902 and integrated circuit components 2920 .

[0231] Integrated circuit component 2920 may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (eg, Fig. 27 The tube core 2702, Fig.28 integrated circuit 2800) and / or one or more other suitable components.

[0232] The unpackaged integrated circuit component 2920 includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 2904. In embodiments where the integrated circuit component 2920 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types of dies (a heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, the integrated circuit component 2920 may also include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, an input / output (I / O) controller, or a memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These individual integrated circuit dies may be referred to as "chips." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., A packaged multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0233] Interposer 2904 can extend the connection to a wider pitch or reroute the connection to a different connection. For example, interposer 2904 can couple integrated circuit component 2920 to a set of ball grid array (BGA) conductive contacts of coupling component 2916 to couple to circuit board 2902. Fig.29 In the illustrated embodiment, integrated circuit component 2920 and circuit board 2902 are attached to opposite sides of interposer 2904; in other embodiments, integrated circuit component 2920 and circuit board 2902 may be attached to the same side of interposer 2904. In some embodiments, three or more components may be interconnected through interposer 2904.

[0234] In some embodiments, the interposer 2904 may be formed as a PCB including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 2904 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, the interposer 2904 may be formed of alternative rigid or flexible materials, which may include the same materials as those described above for semiconductor substrates (e.g., silicon, germanium, and other III-V and IV materials). The interposer 2904 may include metal interconnects 2908 and vias 2910, including but not limited to through-hole vias 2910-1 (which extend from the first side 2950 of the interposer 2904 to the second side 2954 of the interposer 2904), blind vias 2910-2 (which extend from the first side 2950 or the second side 2954 of the interposer 2904 to the internal metal layer), and buried vias 2910-3 (which connect the internal metal layer).

[0235] In some embodiments, interposer 2904 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect connectors on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 2904 including a silicon interposer may further include one or more routing layers to route connectors on a first side of interposer 2904 to an opposite second side of interposer 2904.

[0236] Interposer 2904 may also include embedded devices 2914, including both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on interposer 2904. Interposer-on-package structure 2936 may take the form of any interposer-on-package structure known in the art. In embodiments where the interposer is a non-printed circuit board.

[0237] Integrated circuit component 2900 may include integrated circuit component 2924 coupled to first side 2940 of circuit board 2902 via coupling component 2922. Coupling component 2922 may take the form of any of the embodiments discussed above with reference to coupling component 2916, and integrated circuit component 2924 may take the form of any of the embodiments discussed above with reference to integrated circuit component 2920.

[0238] Fig.29 The illustrated integrated circuit assembly 2900 includes a package-on-package structure 2934 coupled to the second side 2942 of the circuit board 2902 via a coupling component 2928. The package-on-package structure 2934 may include an integrated circuit component 2926 and an integrated circuit component 2932 coupled together via a coupling component 2930, such that the integrated circuit component 2926 is disposed between the circuit board 2902 and the integrated circuit component 2932. The coupling components 2928 and 2930 may take the form of any embodiment of the coupling component 2916 discussed above, and the integrated circuit components 2926 and 2932 may take the form of any embodiment of the integrated circuit component 2920 discussed above. The package-on-package structure 2934 may be constructed according to any package-on-package structure known in the art.

[0239] Fig.30 2 is a block diagram of an exemplary electrical device 3000 that may include one or more embodiments disclosed herein. For example, any suitable component of the components of the electrical device 3000 may include one or more of the microelectronic assembly 2900, the integrated circuit component 2920, the integrated circuit 2800, the integrated circuit die 2702, or the structures disclosed herein. Fig.303000, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 3000 may be attached to one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-chip (SoC) die. In various embodiments, the electrical device 3000 is enclosed by a housing, or is integrated with the housing.

[0240] In addition, in various embodiments, the electrical device 3000 may not include Fig.30 , but the electrical device 3000 may include interface circuitry for coupling to one or more components. For example, the electrical device 3000 may not include the display device 3006, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 3006 may be coupled. In another set of examples, the electrical device 3000 may not include the audio input device 3024 or the audio output device 3008, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 3024 or the audio output device 3008 may be coupled.

[0241] The electrical device 3000 may include one or more processor units 3002 (e.g., one or more processor units). As used herein, the term "processor unit", "processing unit" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 3002 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0242] The electrical device 3000 may include a memory 3004, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 3004 may include memory located on the same integrated circuit die as the processor unit 3002. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0243] In some embodiments, the electrical device 3000 may include one or more processor units 3002 that are heterogeneous or asymmetric with another processor unit 3002 in the electrical device 3000. There may be a variety of differences between the processor units 3002 in the system in terms of a range of quality criteria including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 3002 in the electrical device 3000.

[0244] In some embodiments, the electrical device 3000 may include a communication component 3012 (e.g., one or more communication components). For example, the communication component 3012 may manage wireless communications for transmitting data to and from the electrical device 3000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain wires.

[0245] The communication component 3012 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. The communication component 3012 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 3012 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 3012 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 3012 can operate according to other wireless protocols. The electrical device 3000 may include an antenna 3022 to facilitate wireless communications and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0246] In some embodiments, the communication component 3012 can manage wired communications, such as electrical, optical or any other appropriate communication protocol (e.g., IEEE802.3 Ethernet standard). As described above, the communication component 3012 can include multiple communication components. For example, the first communication component 3012 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 3012 can be dedicated to longer-range wireless communications, such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other. In some embodiments, the first communication component 3012 can be dedicated to wireless communications, and the second communication component 3012 can be dedicated to wired communications.

[0247] The electrical device 3000 may include a battery / electrical power circuit 3014. The battery / power circuit 3014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 3000 to an energy source separate from the electrical device 3000 (e.g., AC line power).

[0248] The electrical device 3000 may include a display device 3006 (or corresponding interface circuitry, as described above). The display device 3006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0249] The electrical device 3000 may include an audio output device 3008 (or corresponding interface circuitry, as described above). The audio output device 3008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0250] The electrical device 3000 may include an audio input device 3024 (or corresponding interface circuitry, as described above). The audio input device 3024 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 3000 may include a global navigation satellite system (GNSS) device 3018 (or corresponding interface circuitry, as described above), such as a global positioning system (GPS) device. As is known in the art, the GNSS device 3018 may communicate with a satellite-based system and may determine the geographic location of the electrical device 3000 based on information received from one or more GNSS satellites.

[0251] The electrical device 3000 may include another output device 3010 (or corresponding interface circuitry, as described above). Examples of other output devices 3010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0252] The electrical device 3000 may include another input device 3020 (or corresponding interface circuitry, as described above). Examples of other input devices 3020 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (e.g., a mouse), a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0253] The electrical device 3000 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 transformable computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 3000 may be any other electronic device that processes data. In some embodiments, the electrical device 3000 may include a plurality of discrete physical components. Considering the range of devices that the electrical device 3000 may appear in various embodiments, in some embodiments, the electrical device 3000 may be referred to as a computing device or a computing system.

[0254] Thus, embodiments of improved via structures for use with embedded components have been provided. The provided embodiments advantageously enable the use of finer pitch architectures and high density input / output (I / O) designs in multi-chip packages.

[0255] Although at least one embodiment has been presented in the foregoing detailed description, it will be appreciated that there are numerous variations. It will also be understood that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing the disclosed embodiments to those skilled in the art. Various changes may be made to the function and arrangement of the elements without departing from the scope of the present disclosure as set forth in the appended claims and their legal equivalents.

[0256] As used herein, phrases such as "an embodiment," "various embodiments," "some embodiments," and the like indicate that some embodiments may have some, all, or none of the features described for other embodiments. Unless explicitly stated, "first," "second," "third," and the like describe a common object and indicate different instances of similar objects; unless explicitly stated, they do not imply a given order in time or space, in order, or in any other manner. According to patent application terminology, "connected" indicates elements that are in direct physical or electrical contact with each other, and "coupled" indicates elements that cooperate or interact with each other, and the coupled elements may or may not be in direct physical or electrical contact. In addition, the terms "include," "comprise," "have," and the like are used synonymously to indicate non-exclusive inclusions.

[0257] As used in the present application and claims, a list of items connected by the term "at least one" or the term "one or more" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0258] As used in this application and claims, a recited or stated list of items having a feature, characteristic, etc. followed by the phrase "individually" or "respectively" means that all of the listed items have the recited or stated feature, characteristic, etc.

[0259] The theories of operation, scientific principles or other theoretical descriptions presented herein with reference to the devices or methods disclosed herein have been provided for the purpose of better understanding and are not intended to limit the scope. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such theories of operation.

[0260] The following examples pertain to additional embodiments of the technology disclosed herein.

[0261] Example Al includes: a first dielectric layer, which includes conductive pads arranged at a first spacing; a second dielectric layer, which is located above the first dielectric layer, the second dielectric layer includes conductive contacts arranged into a first group and a second group, and the first group of conductive contacts is further arranged at a second spacing; a glass layer, which is located between the first dielectric layer and the second dielectric layer; a local interconnect component, which is located in the glass layer, and the local interconnect component is used to provide electrical communication between the first group of first conductive contacts and the second group of first conductive contacts; and a conductive path, which is between the first group of second conductive contacts and one of the conductive pads, and the conductive path includes an interconnect structure.

[0262] Example A2 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or the second dielectric layer, and wherein the conductive path further includes a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

[0263] Example A3 includes the subject matter of Example A1, wherein the interconnect structure is a first interconnect structure located in a first dielectric layer, wherein the conductive path further includes a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is constructed to couple the first interconnect structure to the third interconnect structure.

[0264] Example A4 includes the subject matter of any of Examples A1-A3, wherein the interconnect structure includes conductive traces and vias.

[0265] Example A5 includes the subject matter of Example A1, wherein the first dielectric layer includes more than one sub-layer, the individual sub-layers including the respective conductive traces and vias.

[0266] Example A6 includes the subject matter of Example A1, wherein the second dielectric layer includes more than one sub-layer, and the individual sub-layers include the respective conductive traces and vias.

[0267] Example A7 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet.

[0268] Example A8 includes the subject matter of Example A1, wherein the glass layer includes more than one glass sheet.

[0269] Example A9 includes the subject matter of Example A1, wherein the glass layer includes more than one glass sheet, and the respective glass sheets have a thickness in a range of 100-150 microns.

[0270] Example A10 includes the subject matter of Example A1, wherein the glass layer has a thickness substantially in the range of 300 micrometers to 1 millimeter.

[0271] Example A11 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer positioned adjacent thereto.

[0272] Example A12 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0273] Example A13 includes the subject matter of Example A1, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0274] Example A14 includes the subject matter of Example A1, wherein the glass layer includes silicon and oxygen.

[0275] Example A15 includes the subject matter of Example A14, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0276] Example A16 includes the subject matter of Example A1, wherein the local interconnect component comprises silicon.

[0277] Example A17 includes the subject matter of Example A1, wherein the local interconnect component is a redistribution layer.

[0278] Example A18 includes the subject matter of any of Examples A1-A17, further comprising: a first die attached to the first set of conductive contacts; and a second die attached to the second set of conductive contacts.

[0279] Example A19 includes the subject matter of any of Examples A1-A17, and further includes: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first function and the second die has a second function, the second function being different from the first function.

[0280] Example A20 includes the subject matter of any of Examples A1-A17, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0281] Example A21 includes the subject matter of any of Examples A18-A20, further comprising: an encapsulant over the first die and the second die.

[0282] Example A22 includes the subject matter of Example A21, wherein the device is a panel and further includes a cooling component located on the panel.

[0283] Example A23 includes the subject matter of Example A22, wherein the cooling component includes a heat exchanger.

[0284] Example A24 includes the subject matter of Example A21 or Example A22, wherein the apparatus is a first panel and further includes a second panel in electrical communication with the first panel.

[0285] Example A25 includes the subject matter of Example A24, further comprising: a substrate; and the first panel and the second panel attached to the substrate.

[0286] Example A26 includes the subject matter of Example A25, further comprising: an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0287] Example A27 includes the subject matter of Example A26, and further includes: a housing enclosing the panel; and a heat pump connected via a conduit to a heat exchanger located on the panel.

[0288] Example A28 includes the subject matter of any of Examples A25-A29, further comprising a power management system electrically coupled to the panel.

[0289] Example A29 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having an area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first spacing, the first spacing being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising local interconnect components; placing a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second spacing, the conductive contacts being further arranged into a first group and a second group; the local interconnect components being used to provide electrical communication between the first group of first conductive contacts and the second group of first conductive contacts; and placing an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between the first group of second conductive contacts and one of the conductive pads.

[0290] Example A30 includes the subject matter of Example A29, further comprising: attaching a first die to the first group; and attaching a second die to the second group, thereby producing a filled substrate.

[0291] Example A31 includes the subject matter of Example A30, further comprising: debonding the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0292] Example A32 includes the subject matter of Example A31, further comprising singulating the populated substrate to thereby produce a first panel and a second panel.

[0293] Example A33 includes the subject matter of Example A32, further comprising: attaching the thermal solution to the first panel or the second panel.

[0294] Example A34 is a device comprising: a first dielectric layer comprising conductive pads arranged at a first spacing; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged into a first group and a second group, the first group of conductive contacts being arranged at a second spacing less than the first spacing; a glass layer located between the first dielectric layer and the second dielectric layer, the glass layer comprising through-glass vias; a photonic integrated circuit (PIC) located in the glass layer and electrically communicating with the first group of first conductive contacts; and a conductive path between the first group of second conductive contacts and one of the conductive pads, the conductive path comprising an interconnect structure located in the first dielectric layer or the second dielectric layer.

[0295] Example A35 includes the subject matter of Example A34, wherein the PIC comprises a silicon microring resonator.

[0296] Example A36 includes the subject matter of Example A34, further comprising: a waveguide associated with the PIC located in the glass layer.

[0297] Example A37 includes the subject matter of any of Examples A34-A36, wherein the interconnect structure includes conductive traces and vias.

[0298] Example A38 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or the second dielectric layer, and wherein the conductive path further includes a second interconnect structure located in the glass layer and coupled to the first interconnect structure.

[0299] Example A39 includes the subject matter of Example A34, wherein the interconnect structure is a first interconnect structure located in a first dielectric layer, wherein the conductive path also includes a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is constructed to couple the first interconnect structure to the third interconnect structure.

[0300] Example A40 includes the subject matter of any of Examples A38-A39, wherein the first dielectric layer includes more than one sublayer, and a single sublayer includes corresponding conductive traces and vias.

[0301] Example A41 includes the subject matter of any of Examples A38-A40, wherein the second dielectric layer includes more than one sublayer, and a single sublayer includes corresponding conductive traces and vias.

[0302] Example A42 includes the subject matter of any of Examples A34-A41, wherein the glass layer comprises a glass sheet.

[0303] Example A43 includes the subject matter of any of Examples A34-A41, wherein the glass layer includes more than one glass sheet.

[0304] Example A44 includes the subject matter of any of Examples A34-A41, wherein the glass layer includes more than one glass sheet, and the respective glass sheets have a thickness in a range of 100-150 microns.

[0305] Example A45 includes the subject matter of any of Examples A34-A41, wherein the glass layer has a thickness substantially in the range of 300 micrometers to 1 millimeter.

[0306] Example A46 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer positioned adjacent thereto.

[0307] Example A47 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0308] Example A48 includes the subject matter of Example A34, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0309] Example A49 includes the subject matter of Example A34, wherein the glass layer includes silicon and oxygen.

[0310] Example A50 includes the subject matter of Example A34, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0311] Example A51 includes the subject matter of any of Examples A34-A50, further comprising: a local interconnect component located in the glass layer, the local interconnect component being used to provide electrical communication between the first set of third conductive contacts and the second set of fourth conductive contacts.

[0312] Example A52 includes the subject matter of any of Examples A34-A51, further comprising: a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

[0313] Example A53 includes the subject matter of any of Examples A34-A51, and further includes: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first function and the second die has a second function, the second function being different from the first function.

[0314] Example A54 includes the subject matter of any of Examples A34-A51, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0315] Example A55 includes the subject matter of any of Examples A52-A54, further comprising: an encapsulation over the first die and the second die.

[0316] Example A56 includes the subject matter of Example A55, wherein the device is a panel and further includes a cooling component located on the panel.

[0317] Example A57 includes the subject matter of Example A56, wherein the cooling component includes a heat exchanger.

[0318] Example A58 includes the subject matter of any of Examples A56-A57, wherein the apparatus is a first panel and further includes a second panel in electrical communication with the first panel.

[0319] Example A59 includes the subject matter of Example A58, further comprising: a substrate; and the first panel and the second panel attached to the substrate.

[0320] Example A60 includes the subject matter of Example A59, further comprising: an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0321] Example A61 includes the subject matter of Example A58, and further includes: a housing enclosing the first panel; and a heat pump connected via a conduit to a heat exchanger located on the panel.

[0322] Example A62 includes the subject matter of Example A58, further comprising: a power management system electrically coupled to the panel.

[0323] Example A63 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first pitch, the first pitch being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising a photonic integrated circuit (PIC); placing a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second pitch, the conductive contacts being further arranged into a first group and a second group; the PIC being constructed to electrically communicate with the first group of first conductive contacts or the second group of first conductive contacts; and placing an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between the first group of second conductive contacts and one of the conductive pads.

[0324] Example A64 includes the subject matter of Example A63, further comprising: attaching a first die to the first group; and attaching a second die to the second group, thereby producing a filled substrate.

[0325] Example A65 includes the subject matter of Example A64, further comprising: debonding the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0326] Example A66 includes the subject matter of Example A65, further comprising singulating the populated substrate to thereby produce a first panel and a second panel.

[0327] Example A67 includes the subject matter of Example A66, further comprising: attaching the thermal solution to the first panel or the second panel.

[0328] Example A68 is a device comprising: a first dielectric layer comprising conductive pads arranged at a first spacing; a second dielectric layer located above the first dielectric layer, the second dielectric layer comprising conductive contacts arranged at a second spacing, the conductive contacts also being arranged into a first group and a second group; a glass layer located between the first dielectric layer and the second dielectric layer; a microchannel located in the glass layer, the microchannel being configured to accommodate the flow of a liquid coolant; and a conductive path located between the first group of second conductive contacts or the second group of second conductive contacts and one of the conductive pads, the conductive path comprising an interconnect structure located in the first dielectric layer, the second dielectric layer or the glass layer.

[0329] Example A69 includes the subject matter of Example A68, wherein the microchannel has a lateral portion proximate to the first set of conductive contacts.

[0330] Example A70 includes the subject matter of Example A68, further comprising a cavity in the glass layer.

[0331] Example A71 includes the subject matter of Example A68, wherein the interconnect structure includes conductive traces and vias.

[0332] Example A72 includes the subject matter of Example A71, wherein the interconnect structure is located in the first dielectric layer.

[0333] Example A73 includes the subject matter of Example A72, wherein the interconnect structure is a first interconnect structure and further includes a second interconnect structure located in the second dielectric layer, the second interconnect structure coupled to the first interconnect structure via a through-glass via in the glass layer.

[0334] Example A74 includes the subject matter of Example A68, wherein the first dielectric layer includes more than one sublayer, the individual sublayers including the respective conductive traces and vias.

[0335] Example A75 includes the subject matter of Example A68, wherein the second dielectric layer includes more than one sublayer, the individual sublayers including the respective conductive traces and vias.

[0336] Example A76 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet.

[0337] Example A77 includes the subject matter of Example A68, wherein the glass layer includes more than one glass sheet.

[0338] Example A78 includes the subject matter of Example A68, wherein the glass layer includes more than one glass sheet, and the respective glass sheets have a thickness in a range of 100-150 microns.

[0339] Example A79 includes the subject matter of Example A68, wherein the glass layer has a thickness substantially in the range of 300 micrometers to 1 millimeter.

[0340] Example A80 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet, and the glass sheet has a dielectric layer positioned adjacent thereto.

[0341] Example A81 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer comprises an Ajinomoto built-up film (ABF).

[0342] Example A82 includes the subject matter of Example A68, wherein the glass layer comprises a glass sheet having a dielectric layer positioned adjacent thereto, and the dielectric layer is substantially 10 microns thick.

[0343] Example A83 includes the subject matter of Example A68, wherein the glass layer includes silicon and oxygen.

[0344] Example A84 includes the subject matter of Example A83, wherein the glass layer further includes aluminum, boron, or an alkaline earth metal.

[0345] Example A85 includes the subject matter of any of Examples A68-A84, further comprising: a first die attached to the first set of conductive contacts and a second die attached to the second set of conductive contacts.

[0346] Example A86 includes the subject matter of any of Examples A68-A84, further comprising: a first die attached to a first set of conductive contacts; a second die attached to a second set of conductive contacts; and wherein the first die has a first function and the second die has a second function that is different from the first function.

[0347] Example A87 includes the subject matter of any of Examples A68-A84, further comprising: a first die attached to the first set of conductive contacts; a second die attached to the second set of conductive contacts; and wherein the first die has a different thickness than the second die.

[0348] Example A88 includes the subject matter of any of Examples A65-A87, further comprising: an encapsulation over the first die and the second die.

[0349] Example A89 includes the subject matter of Example A88, wherein the device is a panel and further includes a cooling component located on the panel.

[0350] Example A90 includes the subject matter of Example A89, wherein the cooling component includes a heat exchanger.

[0351] Example A91 includes the subject matter of any of Examples A89-A90, wherein the apparatus is a first panel and further includes a second panel in electrical communication with the first panel.

[0352] Example A92 includes the subject matter of Example A91, further comprising: a substrate; and the first panel and the second panel attached to the substrate.

[0353] Example A93 includes the subject matter of Example A92, further comprising: an electronic component attached to the substrate, the electronic component being located outside of the first panel and the second panel.

[0354] Example A94 includes the subject matter of Example A93, and further includes: a housing enclosing the panel; and a heat pump connected via a conduit to a heat exchanger located on the panel.

[0355] Example A95 includes the subject matter of Example A94, further comprising: a power management system electrically coupled to the panel.

[0356] Example A96 is a method comprising: forming a first dielectric layer on a glass carrier, the glass carrier having a cross-sectional area of ​​at least 250 mm × 250 mm, the first dielectric layer comprising conductive pads arranged at a first spacing, the first spacing being 100 microns or less; forming a glass layer on the first dielectric layer, the glass layer comprising microchannels; placing a second dielectric layer on the glass layer, the second dielectric layer comprising conductive contacts arranged at a second spacing, the conductive contacts also being arranged into a first group and a second group; the microchannel being constructed to have a portion proximate to the first group; and placing an interconnect structure in the glass layer, the interconnect structure being used to provide electrical communication between the first group of conductive contacts and one of the conductive pads.

[0357] Example A97 includes the subject matter of Example A96, further comprising: attaching a first die to the first group; and attaching a second die to the second group, thereby producing a filled substrate.

[0358] Example A98 includes the subject matter of Example A97, further comprising: debonding the glass carrier from the filled substrate; and forming solder bumps on the conductive pads.

[0359] Example A99 includes the subject matter of Example A98, further comprising singulating the populated substrate to thereby produce a first panel and a second panel.

[0360] Example A100 includes the subject matter of Example A99, further comprising: attaching the thermal solution to the first panel or the second panel.

[0361] Example Bl is a device comprising: one or more first dielectric layers, a single first dielectric layer among the first dielectric layers being placed adjacent to another first dielectric layer; a plurality of first conductive contacts, which are located on a top dielectric layer among the first dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; one or more second dielectric layers, a single second dielectric layer being placed adjacent to another second dielectric layer, a single first dielectric layer among the first dielectric layers and a single second dielectric layer among the second dielectric layers comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts, which are located on a bottom dielectric layer among the second dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; and a glass core comprising a glass layer, the glass core being placed between the one or more first dielectric layers and the one or more second dielectric layers, the glass core comprising through-glass vias.

[0362] Example B2 includes the subject matter of Example Bl, further including: a conductive path from a first set of conductive contacts of the first conductive contacts to a second set of conductive contacts of the first conductive contacts, the conductive path comprising a conductive trace of a first dielectric layer in the first dielectric layer and a via of a first dielectric layer in the first dielectric layer.

[0363] Example B3 includes the subject matter of Example Bl, and further includes: a conductive path from one of the first conductive contacts to one of the second conductive contacts, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one via of one of the first dielectric layers, a through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers.

[0364] Example B4 is a device comprising: one or more first dielectric layers, a single first dielectric layer being placed adjacent to another first dielectric layer; a plurality of first conductive contacts being located on a top dielectric layer among the first dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; one or more second dielectric layers, a single second dielectric layer being placed adjacent to another second dielectric layer, the single first dielectric layer and the single second dielectric layer comprising one or more conductive traces and one or more vias; a plurality of second conductive contacts being located on a bottom dielectric layer among the second dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; a glass core comprising a glass layer, the glass core being located between the first dielectric layer and the second dielectric layer, the glass core comprising through-glass vias; and a bridge being located in the first dielectric layer or the glass core, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

[0365] Example B5 includes the subject matter of Example B4, further comprising: a conductive path from the first set of conductive contacts of the first conductive contacts to the second set of conductive contacts of the first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

[0366] Example B6 includes the subject matter of Example B4, and further includes: a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising at least one conductive trace of one of the first dielectric layers, at least one via of one of the first dielectric layers, a through-glass via of the glass core, at least one conductive trace of one of the second dielectric layers, and at least one via of one of the second dielectric layers in the second dielectric layer.

[0367] Example B7 includes the subject matter of Examples B4-B6, wherein the bridge spans two or more first dielectric layers.

[0368] Example B8 includes the subject matter of Examples B4-B7, wherein the bridge further includes one or more through-silicon vias.

[0369] Example B9 includes the device of any of Examples B4-B6, wherein the bridge is located in the glass core.

[0370] Example B10 includes the subject matter of Examples B4-B9, wherein the bridge includes a trench capacitor, the trench capacitor including a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric placed between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second capacitor conductive trace being oriented substantially perpendicular to a surface of a top dielectric layer in the first dielectric layer.

[0371] Example B11 includes the subject matter of Examples B4-B10, wherein the bridge further comprises a plurality of conductive traces, a single conductive trace of the conductive traces of the bridge being surrounded by a ferromagnetic material comprising iron.

[0372] Example B12 includes the subject matter of Examples B4-B11, wherein the bridge further includes a transistor.

[0373] Example B13 includes the subject matter of the example apparatus of any of Examples B1-B12, wherein the first pitch is less than about 1 micron.

[0374] Example B14 includes the subject matter of the example apparatus of any of Examples B1-B12, wherein the first pitch is less than about 0.5 microns.

[0375] Example B15 includes the subject matter of the example apparatus of any of Examples B1-B14, wherein the glass core further includes a waveguide.

[0376] Example B16 includes the subject matter of Example B15, wherein the waveguide is located in the glass layer, and the waveguide includes a dielectric material having a dielectric constant greater than a dielectric constant of the glass.

[0377] Example B17 includes the subject matter of Example B15, wherein the waveguide comprises silicon and oxygen.

[0378] Example B18 includes the subject matter of Example B15, wherein the apparatus further comprises a photonic integrated circuit, and the waveguide provides a path for optical communication for an optical signal to be generated or received by the photonic integrated circuit.

[0379] Example B19 includes the subject matter of Example B15, wherein the apparatus further comprises an optical fiber array unit, and the waveguide provides a path for optical communication for an optical signal to be generated or received by the optical fiber array unit.

[0380] Example B20 includes the subject matter of any of Examples B1-B19, wherein a single one of the vias is tapered, the single one of the vias comprising a narrower end and a wider end, the narrower end being positioned closer to the glass core than the wider end.

[0381] Example B21 includes the subject matter of Examples B1-B20, wherein the glass includes aluminum, oxygen, boron, silicon, and an alkaline earth metal.

[0382] Example B22 includes the subject matter of Examples B1-B20, wherein the glass includes silicon, lithium, oxygen, and a metal.

[0383] Example B23 includes the subject matter of the exemplary apparatus of any of Example B22, wherein the metal is gold or silver.

[0384] Example B24 includes the subject matter of Examples B1-B23, wherein the glass core includes one or more microchannels.

[0385] Example B25 includes the subject matter of Example B24, wherein the one or more microchannels include one or more lateral portions and one or more vertical portions.

[0386] Example B26 includes the subject matter of Example B25, wherein the through-glass via is a first through-glass via and the one or more vertical portions of the microchannel include a second through-glass via.

[0387] Example B27 includes the subject matter of Example B25, wherein the glass core further includes a reservoir connected to at least one of the microchannels.

[0388] Example B28 includes the subject matter of Examples B24-B27, wherein the apparatus further includes a heat exchanger, a pump, and one or more conduits connecting one of the microchannels to the heat exchanger and / or the pump.

[0389] Example B29 includes the subject matter of Examples B1-B28, further comprising: a plurality of integrated circuit dies, a single one of the integrated circuit dies attached to one or more of the first conductive contacts.

[0390] Example B30 includes the subject matter of Example B29, wherein a lateral dimension of a first one of the integrated circuit dies is different than a lateral dimension of a second one of the integrated circuit dies.

[0391] Example B31 includes the subject matter of Example B29, wherein a thickness of a first integrated circuit die in the integrated circuit dies is different than a thickness of a second integrated circuit die in the integrated circuit dies.

[0392] Example B32 includes the subject matter of Example B29, wherein functionality implemented by a first one of the integrated circuit dies is different than functionality implemented by a second one of the integrated circuit dies.

[0393] Example B33 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a plurality of third conductive contacts attached to the first set of first conductive contacts via solder balls.

[0394] Example B34 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

[0395] Example B35 includes the subject matter of Example B34, wherein the third conductive contact and the first set of first conductive contacts comprise copper.

[0396] Example B36 includes the subject matter of Example B29, wherein one of the integrated circuit dies includes a bottom dielectric layer directly attached to a top dielectric layer in the first dielectric layer.

[0397] Example B37 includes the subject matter of Example B29, wherein a first integrated circuit die of the integrated circuit die includes a first surface and a second surface opposite to the first surface, the first integrated circuit die is attached to a first conductive contact at the first surface of the first integrated circuit die, and the device further includes an additional integrated circuit die, the additional integrated circuit die being attached to the second surface of the first integrated circuit die.

[0398] Example B38 includes the subject matter of Example B29, and further includes: an encapsulation body encapsulating an integrated circuit die, the encapsulation body including a through-package via; and a packaged integrated circuit component, which includes an integrated circuit component attached to the through-package via, the through-package via being attached to one of the first conductive contacts.

[0399] Example B39 includes the subject matter of Examples B1-B38, wherein the glass core has a lateral dimension of at least 250 mm.

[0400] Example B40 includes the subject matter of Examples B1-B38, wherein the glass core has a lateral dimension of at least 400 mm.

[0401] Example B41 includes the subject matter of Examples B1-B40, wherein the glass core has a rectangular shape.

[0402] Example B42 includes the subject matter of Examples B1-B40, wherein the glass core has a non-circular shape.

[0403] Example B43 includes the subject matter of Examples B29-B42, further comprising: a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0404] Example B44 includes the subject matter of Examples B1-B43, further including a housing that houses the first dielectric layer and the second dielectric layer.

[0405] Example B45 includes the subject matter of Examples B1-B44, and further includes a power management component.

[0406] Example B46 is a device comprising: a plurality of first dielectric layers, a single first dielectric layer being placed adjacent to another first dielectric layer; a plurality of first conductive contacts being located on a top dielectric layer among the first dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; a plurality of second dielectric layers, a single second dielectric layer being placed adjacent to another second dielectric layer, the single first dielectric layer of the first dielectric layer and the single second dielectric layer of the second dielectric layer comprising one or more first conductive traces and one or more first vias; a plurality of second conductive contacts being located on a bottom dielectric layer among the second dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; a first glass core comprising a glass layer, the first glass core being placed between one or more first dielectric layers and one or more second dielectric layers, the first glass core comprising a first through-glass via; a plurality of first integrated circuit dies, a single first integrated circuit die among the first integrated circuit dies being attached to one or more first conductive contacts among the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts, which are located on a top dielectric layer in the third dielectric layers; a plurality of third conductive contacts including a first group of third conductive contacts and a second group of third conductive contacts; a plurality of fourth dielectric layers, a single third dielectric layer of the third dielectric layers and a single fourth dielectric layer of the fourth dielectric layers including one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts, which are located on a surface of a bottom dielectric layer in the fourth dielectric layers; a second glass core, which includes glass layers, a second glass core is located between the third dielectric layer and the fourth dielectric layer, and the second glass core includes second through-glass vias; a plurality of second integrated circuit dies, a single second integrated circuit die in the second integrated circuit dies is attached to one or more third conductive contacts in the third conductive contacts; and a substrate, the substrate including one or more fifth dielectric layers, a single fifth dielectric layer in the fifth dielectric layers including one or more conductive traces and one or more vias, and a conductive path from one of the second conductive contacts to one of the fourth conductive contacts includes a conductive trace of one of the fifth dielectric layers in the fifth dielectric layers and a via of one of the fifth dielectric layers in the fifth dielectric layers.

[0407] Example B47 includes the subject matter of Example B46, wherein the conductive path is a first conductive path and further includes: a second conductive path from one of the conductive contacts in the first group of first conductive contacts to one of the conductive contacts in the second group of first conductive contacts, the second conductive path including a conductive trace of one of the first dielectric layers in the first dielectric layer and a via of one of the first dielectric layer in the first dielectric layer.

[0408] Example B48 includes the subject matter of Example B46, wherein the conductive path is a first conductive path, the device also includes a second conductive path from the first conductive contact to the second conductive contact, the second conductive path including at least one conductive trace of the first dielectric layer, at least one via of the first dielectric layer, a first through-glass via of the first glass core, a conductive trace of a second dielectric layer in the second dielectric layer, and at least one via of the second dielectric layer in the second dielectric layer.

[0409] Example B49 is a device comprising: a plurality of first dielectric layers, a single first dielectric layer is placed adjacent to another first dielectric layer; a plurality of first conductive contacts, which are located on a top dielectric layer in the first dielectric layers, the plurality of first conductive contacts include a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts are arranged at a first spacing; a plurality of second dielectric layers, a single second dielectric layer of the second dielectric layer is placed adjacent to another second dielectric layer, the single first dielectric layer and the single second dielectric layer include one or more first conductive traces and one or more first vias; a plurality of second conductive contacts, which are located on the second dielectric a first glass core including a glass layer, the first glass core being disposed between the first dielectric layer and the second dielectric layer, the first glass core including a first through-glass via; a first bridge located in the first dielectric layer or the first glass core, the first bridge including one or more conductive traces and one or more vias, the first bridge including silicon; a plurality of first integrated circuit dies, a single first integrated circuit die in the first integrated circuit dies being attached to one or more first conductive contacts in the first conductive contacts; a plurality of third dielectric layers; a plurality of third conductive contacts , which is located on the top dielectric layer in the third dielectric layer; a plurality of third conductive contacts including a first group of third conductive contacts and a second group of third conductive contacts; a plurality of fourth dielectric layers, a single third dielectric layer of the third dielectric layer and a single fourth dielectric layer of the fourth dielectric layer including one or more second conductive traces and one or more second vias; a plurality of fourth conductive contacts, which is located on the bottom dielectric layer in the fourth dielectric layer; a second glass core, which includes a glass layer, the second glass core is located between the third dielectric layer and the fourth dielectric layer, the second glass core including a second through-glass via; and a second bridge, which is located in the third dielectric layer or the second glass layer The core comprises a second bridge including one or more conductive traces and one or more vias, the second bridge comprising silicon; a plurality of second integrated circuit dies, a single second integrated circuit die among the second integrated circuit dies being attached to one or more third conductive contacts among the third conductive contacts; and a substrate comprising one or more fifth dielectric layers, a single fifth dielectric layer among the fifth dielectric layers comprising one or more conductive traces and one or more vias, a conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the vias of the substrate.

[0410] Example B50 includes the subject matter of Example B49, wherein the conductive path is a first conductive path, and the device further includes: a second conductive path from one of the conductive contacts in the first group of first conductive contacts to one of the conductive contacts in the second group of first conductive contacts, the second conductive path including a conductive trace of the first bridge and a via of the first bridge.

[0411] Example B51 includes the subject matter of Example B49, wherein the conductive path is a first conductive path, the device also includes a second conductive path from the first conductive contact to the second conductive contact, the second conductive path including at least one conductive trace of the first dielectric layer, at least one via of the first dielectric layer, a first through-glass via of the first glass core, a conductive trace of a second dielectric layer in the second dielectric layer, and at least one via of the second dielectric layer in the second dielectric layer.

[0412] Example B52 includes the subject matter of Examples B46-B51, wherein the number of first integrated circuit dies is different than the number of second integrated circuit dies.

[0413] Example B53 includes the subject matter of Examples B46-B51, wherein functionality implemented by the first plurality of integrated circuit dies is different than functionality implemented by the second plurality of integrated circuit dies.

[0414] Example B54 includes the subject matter of Examples B46-B51, and further includes: a cooling component located on one or more first integrated circuit dies in the first integrated circuit die and one or more second integrated circuit dies in the second integrated circuit die, the cooling component comprising a liquid-cooled cooling plate, a vapor chamber, or a heat sink.

[0415] Example B55 includes the subject matter of Example B54, wherein the cooling component includes a liquid-cooled cold plate, and the apparatus further includes a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0416] Example B56 includes the subject matter of Examples B46-B55, further comprising a housing that houses the first dielectric layer, the second dielectric layer, and the first integrated circuit die.

[0417] Example B57 includes the subject matter of Examples B46-B56, and further includes a power management component.

[0418] Example C1 is a device comprising: a plurality of dielectric layers stacked vertically, a single dielectric layer in the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer in the dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; and a plurality of second conductive contacts located on a bottom dielectric layer in the dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing, wherein the first spacing is less than approximately 1 micron, and a single dielectric layer in the dielectric layers has a lateral dimension greater than approximately 250 mm.

[0419] Example C2 includes the subject matter of Example C1, further comprising: a conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the dielectric layer and a via of the dielectric layer.

[0420] Example C3 includes the subject matter of Example C1, further comprising: a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising a conductive trace of the dielectric layer and a via of the dielectric layer.

[0421] Example C4 is a device comprising: a plurality of dielectric layers stacked vertically, a single dielectric layer in the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer in the dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; a plurality of second conductive contacts arranged on a bottom dielectric layer in the dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; and a bridge located in one or more dielectric layers, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

[0422] Example C5 includes the subject matter of Example C4, further comprising: a conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

[0423] Example C6 includes the subject matter of Example C4, further comprising: a conductive path from the first conductive contact to the second conductive contact, the conductive path comprising a conductive trace of the dielectric layer and a via of one of the dielectric layers.

[0424] Example C7 includes the subject matter of any of Examples C4-C6, wherein the bridge spans two or more dielectric layers.

[0425] Example C8 includes the subject matter of any of Examples C4-C7, wherein the bridge comprises one or more through-silicon vias.

[0426] Example C9 includes the subject matter of any of Examples C4-C8, wherein the bridge includes a trench capacitor, the trench capacitor including a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric placed between the first capacitor conductive trace and the second capacitor conductive trace, the first capacitor conductive trace and the second conductive trace being oriented substantially perpendicular to a surface of a top dielectric layer in the dielectric layer.

[0427] Example C10 includes the subject matter of any of Examples C4-C9, wherein the bridge further comprises a plurality of conductive traces, a single one of the conductive traces being surrounded by a ferromagnetic layer comprising iron.

[0428] Example C1 includes the subject matter of any of Examples C4-C10, wherein the bridge comprises a field effect transistor.

[0429] Example C12 includes the subject matter of any of Examples C1-C10, wherein the dielectric layer has a thickness in a range of 0.5-200 microns.

[0430] Example C13 includes the subject matter of any of Examples C1-C12, wherein the first pitch is less than about 1 micron.

[0431] Example C14 includes the subject matter of any of Examples C1-C12, wherein the first pitch is less than about 0.5 microns.

[0432] Example C15 includes the subject matter of any of Examples C1-C14, further comprising: a photonic integrated circuit; and an interposer comprising glass and a waveguide to provide a communication path for optical signals to be generated or received by the photonic integrated circuit.

[0433] Example C16 includes the subject matter of Example C15, wherein the waveguide is located in the glass, and the waveguide includes a dielectric material having a dielectric constant greater than a dielectric constant of the glass.

[0434] Example C17 includes the subject matter of Example C15, wherein the waveguide comprises silicon and oxygen.

[0435] Example C18 includes the subject matter of Example C15, further including: an electronic integrated circuit, the electronic integrated circuit comprising a first set of electronic integrated circuit conductive contacts located on a first surface of the electronic integrated circuit and a second set of electronic integrated circuit conductive contacts located on a second surface of the electronic integrated circuit opposite to the first surface, the first set of electronic integrated circuit conductive contacts attached to one or more of the first conductive contacts, and a photonic integrated circuit comprising one or more photonic integrated circuit conductive contacts, the photonic integrated circuit conductive contacts attached to the second set of electronic integrated circuit conductive contacts.

[0436] Example C19 includes the subject matter of Example C15, wherein the photonic integrated circuit includes one or more photonic integrated circuit conductive contacts attached to one or more of the first conductive contacts.

[0437] Example C20 includes the subject matter of any of Examples C15-C19, wherein the apparatus further comprises an optical fiber array unit, and the waveguide further provides a communication path for optical signals to be generated or received by the optical fiber array unit.

[0438] Example C21 includes the subject matter of any of Examples C15-C20, wherein the glass includes aluminum, oxygen, boron, silicon, and an alkaline earth metal.

[0439] Example C22 includes the subject matter of any of Examples C1-C21, wherein the glass includes silicon, lithium, oxygen, and a metal.

[0440] Example C23 includes the subject matter of any of Examples C22, wherein the metal is gold or silver.

[0441] Example C24 includes the subject matter of any of Examples C1-C23, further comprising: a plurality of integrated circuit dies, individual ones of the dies attached to one or more of the first conductive contacts.

[0442] Example C25 includes the subject matter of Example C24, wherein a lateral dimension of a first one of the integrated circuit dies is different than a lateral dimension of a second one of the integrated circuit dies.

[0443] Example C26 includes the subject matter of Example C24, wherein a thickness of a first integrated circuit die in the integrated circuit dies is different than a thickness of a second integrated circuit die in the integrated circuit dies.

[0444] Example C27 includes the subject matter of Example C24, wherein the functionality implemented by a first one of the integrated circuit dies is different than the functionality implemented by a second one of the integrated circuit dies.

[0445] Example C28 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a plurality of third integrated circuit die conductive contacts attached to the first set of conductive contacts via solder balls.

[0446] Example C29 includes the subject matter of Example C23, wherein one of the integrated circuit dies includes a plurality of third conductive contacts directly attached to the first set of first conductive contacts.

[0447] Example C30 includes the subject matter of Example C29, wherein the third plurality of integrated circuit die conductive contacts and the first set of conductive contacts comprise copper.

[0448] Example C31 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a bottom dielectric layer directly attached to a surface of a top dielectric layer.

[0449] Example C32 includes the subject matter of Example C24, wherein one of the integrated circuit dies includes a first surface and a second surface opposite to the first surface, one of the integrated circuit dies is attached to a first conductive contact at the first surface of the one of the integrated circuit dies, and the device further includes an additional integrated circuit die, the additional integrated circuit die being attached to the second surface of the integrated circuit die.

[0450] Example C33 includes the subject matter of Example C24, and further includes: an encapsulation body that encapsulates an integrated circuit die, the encapsulation body including a through-package via; and a packaged integrated circuit component, which includes an integrated circuit component conductive contact attached to the through-package via, the through-package via being attached to a first conductive contact of the first conductive contacts.

[0451] Example C34 includes the subject matter of any of Examples C1-C33, wherein a single one of the dielectric layers has a lateral dimension of at least 250 mm.

[0452] Example C35 includes the subject matter of any of Examples C1-C33, wherein a single one of the dielectric layers has a lateral dimension of at least 400 mm.

[0453] Example C36 includes the subject matter of any of Examples C1-C35, wherein a single one of the dielectric layers has a rectangular shape.

[0454] Example C37 includes the subject matter of any of Examples C1-C35, wherein a single one of the dielectric layers has a non-circular shape.

[0455] Example C38 includes the subject matter of any of Examples C24-C37, further comprising: a cooling component located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

[0456] Example C39 includes the subject matter of Example C38, wherein the cooling component includes a liquid-cooled cold plate, and the device further includes a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0457] Example C40 includes the subject matter of any of Examples C1-C39, further comprising: a housing that houses the dielectric layer.

[0458] Example C41 includes the subject matter of any of Examples C1-40, further including a power distribution component.

[0459] Example C42 is a device comprising: a plurality of first dielectric layers arranged as a stack, a single first dielectric layer in the first dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of first conductive contacts located on a surface of a top dielectric layer in the first dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; a plurality of second conductive contacts arranged on a surface of a bottom dielectric layer in the first dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; a plurality of first integrated circuit dies, a single first integrated circuit die in the first integrated circuit dies being attached to one or more first conductive contacts in the first conductive contacts; a plurality of second dielectric layers arranged as a stack, a single first integrated circuit die in the second dielectric layer The second dielectric layer includes one or more second conductive traces and one or more second vias; a plurality of third conductive contacts, which are located on the surface of the top dielectric layer in the second dielectric layer, the plurality of third conductive contacts include a first group of third conductive contacts and a second group of third conductive contacts; a plurality of fourth conductive contacts, which are located on the surface of the bottom dielectric layer in the second dielectric layer; a plurality of second integrated circuit dies, a single second integrated circuit die in the second integrated circuit dies is attached to one or more third conductive contacts in the third conductive contacts; and a substrate, the substrate includes one or more third dielectric layers, a single third dielectric layer in the third dielectric layer includes one or more conductive traces and one or more vias, and the conductive path from one of the second conductive contacts to one of the fourth conductive contacts in the fourth conductive contacts includes the conductive trace of the substrate and the via of the substrate.

[0460] Example C43 includes the subject matter of Example C42, wherein the conductive path is a first conductive path and further includes: a second conductive path from one of the conductive contacts in the first group of first conductive contacts to one of the conductive contacts in the second group of first conductive contacts, the second conductive path including a conductive trace of the first dielectric layer and a via of the first dielectric layer.

[0461] Example C44 includes the subject matter of Example C42, wherein the conductive path is a first conductive path, the apparatus further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising a conductive trace of the first dielectric layer and a via of the first dielectric layer.

[0462] Example C45 includes the subject matter of a device, including: one or more first dielectric layers stacked vertically, a single first dielectric layer in the first dielectric layers including one or more first conductive traces and one or more first vias; a plurality of first conductive contacts located on a top dielectric layer in the first dielectric layers, the plurality of first conductive contacts including a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first spacing; a plurality of second conductive contacts arranged on a bottom dielectric layer in the first dielectric layers, the second conductive contacts being arranged at a second spacing, the second spacing being greater than the first spacing; a first bridge located in the one or more first dielectric layers, the first bridge including one or more conductive traces and one or more vias, the bridge including silicon; a plurality of first integrated circuit dies, a single first integrated circuit die in the first integrated circuit dies being attached to the one or more first conductive contacts in the first conductive contacts; one or more second dielectric layers stacked vertically, a single second dielectric die in the second dielectric layer The layer includes one or more second conductive traces and one or more second vias; a plurality of third conductive contacts, which are located on a top dielectric layer in the second dielectric layer, the plurality of third conductive contacts include a first group of third conductive contacts and a second group of third conductive contacts; a plurality of fourth conductive contacts, which are arranged on a bottom dielectric layer in the second dielectric layer; a second bridge, which is located in the second dielectric layer, the second bridge includes one or more conductive traces and one or more vias, the bridge includes silicon; and a plurality of second integrated circuit dies, a single second integrated circuit die in the second integrated circuit dies being attached to one or more third conductive contacts in the third conductive contacts; and a substrate, the substrate includes one or more third dielectric layers, a single third dielectric layer in the third dielectric layer includes one or more conductive traces and one or more vias, and a substrate conductive path from one of the second conductive contacts to one of the fourth conductive contacts in the fourth conductive contacts includes one of the conductive traces of the substrate and one of the vias of the substrate.

[0463] Example C46 includes the subject matter of Example C45, wherein the conductive path is a first conductive path, and the device further includes: a second conductive path from one of the conductive contacts in the first group of first conductive contacts to one of the conductive contacts in the second group of first conductive contacts, the second conductive path including a conductive trace of a bridge and a via of the bridge.

[0464] Example C47 includes the subject matter of Example C45, wherein the conductive path is a first conductive path, the apparatus further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising a conductive trace of the first dielectric layer and a via of the first dielectric layer.

[0465] Example C48 includes the subject matter of any of Examples C42-C47, wherein the number of first integrated circuit dies is different than the number of second integrated circuit dies.

[0466] Example C49 includes the subject matter of any of Examples C42-C47, wherein functionality implemented by the first plurality of integrated circuit dies is different than functionality implemented by the second plurality of integrated circuit dies.

[0467] Example C50 includes the subject matter of any of Examples C42-C49, further including: a cooling component located on one or more first integrated circuit dies in the first integrated circuit die and one or more second integrated circuit dies in the second integrated circuit die, the cooling component comprising a liquid-cooled cooling plate, a vapor chamber, or a heat sink.

[0468] Example C51 includes the subject matter of Example C50, wherein the cooling component includes a liquid-cooled cold plate, and the apparatus further includes a heat exchanger, a pump, and one or more conduits connecting the cooling component to the heat exchanger and / or the pump.

[0469] Example C52 includes the subject matter of any of Examples C42-C51, further comprising: a housing housing the first dielectric layer, the second dielectric layer, and the first integrated circuit die.

[0470] Example C53 includes the subject matter of any of Examples C42-C52, further including a power distribution component.

[0471] Example C54 includes the subject matter of a method comprising: forming on a glass carrier: a plurality of dielectric layers, a single dielectric layer of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts on a top dielectric layer of the dielectric layers; and a plurality of second conductive contacts on a bottom dielectric layer of the dielectric layers, the first conductive contacts being arranged at a first pitch less than 1 micron and the second conductive contacts being arranged at a second pitch greater than the first pitch; attaching one or more integrated circuit dies to the first conductive contacts; and removing the glass carrier from the dielectric layers.

[0472] Example C55 includes the subject matter of Example C54, further comprising: etching one or more of the dielectric layers to create a cavity; and placing a bridge in the cavity, the bridge comprising one or more conductive traces and one or more vias.

[0473] Example C56 includes the subject matter of Example C55, wherein the first conductive contacts include a first group of first conductive contacts and a second group of first conductive contacts, and the conductive path from the conductive contacts in the first group of first conductive contacts to the conductive contacts in the second group of first conductive contacts includes a conductive trace of a bridge and a via of the bridge.

[0474] Example C57 includes the subject matter of Example C54, wherein the glass carrier and a single one of the dielectric layers have a lateral dimension of at least 250 mm.

[0475] Example C58 includes the subject matter of Example C54, wherein the glass carrier and a single one of the dielectric layers have a lateral dimension of at least 400 mm.

Claims

1. A device comprising: a plurality of dielectric layers stacked vertically, a single dielectric layer of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer among the dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first pitch; as well as A plurality of second conductive contacts are located on a bottom dielectric layer in the dielectric layers, the second conductive contacts are arranged at a second spacing, the second spacing is greater than the first spacing, wherein the first spacing is less than about 1 micron and a single dielectric layer in the dielectric layers has a lateral dimension greater than about 250 mm.

2. The apparatus according to claim 1, further comprising: A conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the dielectric layer and a via of the dielectric layer.

3. The apparatus according to claim 1, further comprising: A conductive path from the first conductive contact to the second conductive contact includes a conductive trace of the dielectric layer and a via of the dielectric layer.

4. A device comprising: a plurality of dielectric layers stacked vertically, a single dielectric layer of the dielectric layers comprising one or more conductive traces and one or more vias; a plurality of first conductive contacts located on a top dielectric layer among the dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first pitch; a plurality of second conductive contacts arranged on a bottom dielectric layer among the dielectric layers, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; as well as A bridge is located in one or more of the dielectric layers, the bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon.

5. The apparatus according to claim 4, further comprising: A conductive path from one of the conductive contacts in the first set of first conductive contacts to one of the conductive contacts in the second set of first conductive contacts, the conductive path comprising a conductive trace of the bridge and a via of the bridge.

6. The apparatus according to claim 4, further comprising: A conductive path from a first conductive contact to a second conductive contact, the conductive path comprising a conductive trace of the dielectric layers and a via of one of the dielectric layers.

7. The device according to any one of claims 4 to 6, wherein: The bridge spans two or more dielectric layers.

8. The device according to any one of claims 4 to 7, wherein: The bridge includes one or more through-silicon vias.

9. The device according to any one of claims 4 to 8, wherein: The bridge includes a trench capacitor, which includes a first capacitor conductive trace, a second capacitor conductive trace, and a capacitor dielectric placed between the first capacitor conductive trace and the second capacitor conductive trace, wherein the first capacitor conductive trace and the second conductive trace are oriented substantially perpendicular to a surface of the top dielectric layer in the dielectric layers.

10. The device according to any one of claims 4 to 9, wherein: The bridge includes a field effect transistor.

11. The device according to any one of claims 1 to 10, wherein: The first spacing is less than about 0.5 microns.

12. The device according to any one of claims 1 to 11, further comprising: Photonic integrated circuits; as well as An interposer includes glass and waveguides to provide a communication path for optical signals to be generated or received by the photonic integrated circuit.

13. The device of claim 12, further comprising an electronic integrated circuit, the electronic integrated circuit comprising a first set of electronic integrated circuit conductive contacts on a first surface of the electronic integrated circuit and a second set of electronic integrated circuit conductive contacts on a second surface of the electronic integrated circuit opposite to the first surface, the first set of electronic integrated circuit conductive contacts being attached to one or more of the first conductive contacts, the photonic integrated circuit comprising one or more photonic integrated circuit conductive contacts being attached to the second set of electronic integrated circuit conductive contacts.

14. The device according to claim 12, wherein: The photonic integrated circuit includes one or more photonic integrated circuit conductive contacts attached to one or more first ones of the first conductive contacts.

15. The device according to any one of claims 12 to 14, wherein: The device further comprises an optical fiber array unit, and the waveguide further provides a communication path for an optical signal to be generated or received by the optical fiber array unit.

16. The device according to any one of claims 12 to 15, wherein: The glass includes aluminum, oxygen, boron, silicon and alkaline earth metals.

17. The device according to any one of claims 12 to 16, wherein: The glass includes silicon, lithium, oxygen and metal.

18. The apparatus according to any one of claims 1 to 17, further comprising: A plurality of integrated circuit dies, individual ones of the dies being attached to one or more of the first conductive contacts.

19. The apparatus according to claim 18, further comprising: an encapsulation body encapsulating the integrated circuit die, the encapsulation body including through-package vias; as well as A packaged integrated circuit component includes an integrated circuit component conductive contact attached to the through-package via, the through-package via being attached to a first one of the first conductive contacts.

20. The device according to any one of claims 1 to 19, wherein: A single one of the dielectric layers has a lateral dimension of at least 400 mm.

21. The apparatus according to any one of claims 18 to 20, further comprising: A cooling component is located on one or more of the integrated circuit dies, the cooling component comprising a liquid-cooled cold plate, a vapor chamber, or a heat sink.

22. The apparatus according to any one of claims 1 to 21, further comprising: A housing houses the dielectric layer.

23. An apparatus comprising: one or more first dielectric layers stacked vertically, a single one of the first dielectric layers comprising one or more first conductive traces and one or more first vias; a plurality of first conductive contacts located on a top dielectric layer in the first dielectric layers, the plurality of first conductive contacts comprising a first group of first conductive contacts and a second group of first conductive contacts, the first group of first conductive contacts being arranged at a first pitch; a plurality of second conductive contacts arranged on a bottom dielectric layer in the first dielectric layer, the second conductive contacts being arranged at a second pitch, the second pitch being greater than the first pitch; a first bridge located in the one or more first dielectric layers, the first bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon; a plurality of first integrated circuit dies, a single first integrated circuit die of the first integrated circuit dies being attached to one or more first conductive contacts of the first conductive contacts; one or more second dielectric layers stacked vertically, a single one of the second dielectric layers comprising one or more second conductive traces and one or more second vias; a plurality of third conductive contacts located on a top dielectric layer in the second dielectric layer, the plurality of third conductive contacts comprising a first set of third conductive contacts and a second set of third conductive contacts; a plurality of fourth conductive contacts disposed on a bottom dielectric layer in the second dielectric layer; a second bridge located in the second dielectric layer, the second bridge comprising one or more conductive traces and one or more vias, the bridge comprising silicon; and a plurality of second integrated circuit dies, a single one of the second integrated circuit dies being attached to one or more of the third conductive contacts; as well as A substrate comprising one or more third dielectric layers, a single one of the third dielectric layers comprising one or more conductive traces and one or more vias, a substrate conductive path from one of the second conductive contacts to one of the fourth conductive contacts comprising one of the conductive traces of the substrate and one of the vias of the substrate.

24. The device according to claim 23, wherein: The conductive path is a first conductive path, and the device also includes a second conductive path from one of the conductive contacts in the first group of first conductive contacts to one of the conductive contacts in the second group of first conductive contacts, and the second conductive path includes a conductive trace of the bridge and a via of the bridge.

25. The device according to claim 23, wherein: The conductive path is a first conductive path, the device further comprising a second conductive path from the first conductive contact to the second conductive contact, the second conductive path comprising a conductive trace of the first dielectric layer and a via of the first dielectric layer.

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