A timing control circuit, a display device and a display driving method

Abstract

The application provides a timing control circuit, a display device and a display driving method, and relates to the technical field of display. The timing control circuit comprises a first detection module, a first identification module and a compensation output module. The first detection module is electrically connected with the first identification module, is used for receiving a display signal of a frame of picture and determining a corresponding pixel clock frequency, and sending the pixel clock frequency to the first identification module. The first identification module is electrically connected with the compensation output module, is used for determining a target frequency partition corresponding to the pixel clock frequency from a plurality of preset frequency partitions, and sending a first compensation list corresponding to the target frequency partition to the compensation output module. The first compensation list comprises a compensation relationship between the gray scale values of the pixels in adjacent pixel rows. The compensation output module is used for compensating the gray scale values of the pixels in at least one pixel row in the display signal according to the first compensation list, and outputting the compensated display signal. The pixel brightness difference can be reduced, and the picture quality can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a timing control circuit, a display device, and a display driving method. Background Technology

[0002] With advancements in display technology and increasing user demands, display devices are achieving higher refresh rates, such as the MNT display. In some applications employing dual-gate driving (DGD) or triple-gate driving (TGD) technologies, pixel charging times are becoming increasingly shorter.

[0003] For special pixel architectures such as Zigzag, there are differences in pre-charge voltage between pixels, resulting in charging differences between rows of pixels. As pixel charging times become shorter, these charging differences lead to more pronounced brightness differences between rows of pixels, easily causing issues such as fine lines in the image display. Summary of the Invention

[0004] This application provides a timing control circuit, a display device, and a display driving method, which can solve the technical problem that brightness differences between different rows of pixels can easily cause fine lines in the display.

[0005] In a first aspect, this application provides a timing control circuit, the timing control circuit comprising: a first detection module, a first identification module, and a compensation output module;

[0006] The first detection module is electrically connected to the first recognition module and is used to receive a display signal of a frame, determine the pixel clock frequency corresponding to the display signal, and send the pixel clock frequency to the first recognition module.

[0007] The first identification module is electrically connected to the compensation output module and is used to determine the target frequency partition corresponding to the pixel clock frequency from a plurality of preset frequency partitions, and send the first compensation list corresponding to the target frequency partition to the compensation output module; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows;

[0008] The compensation output module is used to compensate the grayscale value of pixels in at least one pixel row of the display signal according to the first compensation list, and output the compensated display signal.

[0009] Optionally, the first identification module includes a first partitioning unit and a first enabling unit;

[0010] The first partitioning unit is electrically connected to the first detection module and the first enabling unit, respectively, and is used to determine the target frequency partition corresponding to the pixel clock frequency from the preset plurality of frequency partitions, and send the first enabling signal corresponding to the target frequency partition to the first enabling unit.

[0011] The first enabling unit is also electrically connected to the compensation output module, and is used to send the first compensation list corresponding to the first enabling signal to the compensation output module.

[0012] Optionally, the first enabling unit includes a plurality of first controllers;

[0013] The enable terminal of the first controller is electrically connected to the first partition unit, and the output terminal of the first controller is electrically connected to the compensation output module.

[0014] The first controller is configured to send the first compensation list input at the input terminal to the compensation output module through the output terminal when the first enable signal sent by the first partition unit is received at the enable terminal.

[0015] Optionally, the compensation output module includes a first input terminal, which is electrically connected to the output terminals of a plurality of first controllers respectively;

[0016] The compensation output module is used to receive the first compensation list through the first input terminal, and to look up the table according to the first compensation list to determine the adjusted grayscale value of the pixels in the at least one pixel row after compensation, so as to compensate the grayscale value of the pixels in the at least one pixel row in the display signal.

[0017] Optionally, the timing control circuit further includes a second detection module and a second identification module;

[0018] The second detection module is electrically connected to the second recognition module and is used to receive the display signal of the frame, determine the first blanking duration corresponding to the display signal, and send the first blanking duration to the second recognition module; wherein, the first blanking duration is the duration of the vertical scan blanking region corresponding to the display signal;

[0019] The second identification module is electrically connected to the compensation output module and is used to send the second compensation list corresponding to the first blanking time to the compensation output module; wherein, the second compensation list includes a plurality of preset grayscale values ​​and a compensation coefficient corresponding to each grayscale value;

[0020] The compensation output module is also used to compensate the grayscale value of each pixel in the display signal according to the second compensation list.

[0021] Optionally, the second identification module includes a second partitioning unit and a second enabling unit;

[0022] The second partitioning unit is electrically connected to the second detection module and the second enabling unit, respectively, and is used to compare the first blanking duration with the multiple time-duration partitions in ascending order according to a preset multiple time-duration partitions, and send the second enabling signal corresponding to the time-duration partition to the second enabling unit each time the first blanking duration is greater than the minimum length of a time-duration partition; wherein the durations of the vertical scan blanking regions corresponding to the multiple time-duration partitions do not overlap;

[0023] The second enabling unit is also electrically connected to the compensation output module and is used to send the second compensation list corresponding to the second enabling signal to the compensation output module.

[0024] Optionally, the second enabling unit includes a plurality of second controllers;

[0025] The enable terminal of the second controller is electrically connected to the second partition unit, and the output terminal of the second controller is electrically connected to the compensation output module.

[0026] The second controller is used to send the second compensation list input at the input terminal to the compensation output module through the output terminal when the second enable signal sent by the second partition unit is received at the enable terminal.

[0027] Optionally, the compensation output module includes multiple second input terminals, which are connected one-to-one with the output terminals of multiple second controllers;

[0028] The compensation output module is used to receive at least one second compensation list through the plurality of second input terminals, and to determine the compensation coefficient corresponding to the grayscale value of each pixel in the display signal by looking up the table according to the last second compensation list received, and to determine the output grayscale value of each pixel in the display signal according to the compensation coefficient, so as to compensate the grayscale value of each pixel in the display signal.

[0029] In a second aspect, this application provides a display device, the display device including a display panel and a timing control circuit as described in the first aspect;

[0030] The timing control circuit is electrically connected to the display panel and is used to output a compensated display signal to the display panel to drive the display panel to perform display.

[0031] Secondly, this application provides a display driving method, the display driving method comprising:

[0032] Receive a display signal for a frame and determine the pixel clock frequency corresponding to the display signal;

[0033] The target frequency partition corresponding to the pixel clock frequency is determined from a plurality of preset frequency partitions, and a corresponding first compensation list is determined based on the target frequency partition; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows;

[0034] The grayscale values ​​of pixels in at least one pixel row of the display signal are compensated according to the first compensation list, and the compensated display signal is output to the display panel to drive the display panel to display.

[0035] Optionally, the step of compensating the grayscale values ​​of pixels in at least one pixel row of the display signal according to the first compensation list includes:

[0036] For the grayscale value of the first pixel in the first pixel row of the display signal, determine the grayscale value of the second pixel in the second pixel row adjacent to the first pixel row; wherein the first pixel and the second pixel are connected to the same data line, and the first pixel receives the driving signal transmitted by the data line later than the second pixel;

[0037] Based on the grayscale value of the first pixel and the grayscale value of the second pixel, the adjusted grayscale value of the first pixel after compensation is determined by looking up the first compensation list, so as to compensate the grayscale value of each first pixel in the first pixel row in the display signal; wherein, the at least one pixel row includes the first pixel row.

[0038] Optionally, determining the adjusted grayscale value of the first pixel after compensation by looking up a table based on the grayscale value of the first pixel and the grayscale value of the second pixel includes:

[0039] A preset grayscale value that is the same as the grayscale value of the first pixel is determined according to the first set of grayscale values ​​in the first compensation list, and a preset grayscale value that is the same as the grayscale value of the second pixel is determined according to the second set of grayscale values ​​in the first compensation list.

[0040] Based on the correspondence between the two preset grayscale values, the corresponding adjusted grayscale value is obtained from the first compensation list and used as the adjusted grayscale value of the first pixel after compensation.

[0041] The first compensation list includes the first group of grayscale values, the second group of grayscale values, and multiple adjustable grayscale values ​​corresponding to multiple sets of correspondences; the first group of grayscale values ​​and the second group of grayscale values ​​each include multiple preset grayscale values; the multiple sets of correspondences include the correspondence between each preset grayscale value in the first group of grayscale values ​​and different preset grayscale values ​​in the second group of grayscale values.

[0042] Optionally, before the compensated display signal is output to the display panel, the display driving method further includes:

[0043] Determine the first blanking duration corresponding to the display signal; wherein, the first blanking duration is the duration of the vertical scan blanking region corresponding to the display signal;

[0044] Determine a second compensation list corresponding to the first blanking duration; wherein the second compensation list includes a plurality of preset grayscale values ​​and a compensation coefficient corresponding to each grayscale value;

[0045] The grayscale values ​​of each pixel in the display signal are compensated according to the second compensation list.

[0046] Optionally, determining the second compensation list corresponding to the first blanking duration includes:

[0047] According to the preset multiple duration partitions in ascending order, the first blanking duration is compared with the multiple duration partitions in turn, and the second compensation list corresponding to the duration partition is triggered each time the first blanking duration is greater than the minimum length of a duration partition; wherein the durations of the vertical scan blanking regions corresponding to the multiple duration partitions do not overlap.

[0048] The last triggered second compensation list is determined as the second compensation list corresponding to the first blanking duration.

[0049] Optionally, the step of compensating the grayscale values ​​of each pixel in the display signal according to the second compensation list includes:

[0050] For a target pixel with an adjustable grayscale value, the output grayscale value of the target pixel is determined based on the adjusted grayscale value and the compensation coefficient corresponding to the target pixel; wherein, the compensation coefficient corresponding to the target pixel is the compensation coefficient corresponding to the grayscale value of the target pixel before compensation;

[0051] For pixels other than the target pixel, the output grayscale value of the other pixels is determined based on the original grayscale value of the other pixels and the corresponding compensation coefficient;

[0052] Before the compensated display signal is output to the display panel, the display driving method further includes:

[0053] The compensated display signal is obtained based on the output grayscale value of the target pixel and the output grayscale values ​​of the other pixels.

[0054] This application provides a timing control circuit, display device, and display driving method, which have at least the following advantages: The timing control circuit uses a first detection module to detect the pixel clock frequency corresponding to the display signal, enabling a first identification module to identify the correspondence between the pixel clock frequency and multiple preset frequency partitions. The first identification module outputs a first compensation list corresponding to the target frequency partition to a compensation output module based on the target frequency partition corresponding to the pixel clock frequency. Since the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows, the compensation output module can compensate the grayscale values ​​of pixels in at least one pixel row of the display signal according to the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows in the first compensation list, and output the compensated display signal. In this way, the compensated display signal drives the display screen, reducing the charging difference between pixels in at least one pixel row and pixels in adjacent rows, thereby improving problems such as fine lines in the display caused by brightness differences between pixels in different rows, and improving the display screen quality. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of a pixel architecture in related technologies;

[0057] Figure 2 This is a schematic diagram of the structure of a timing control circuit provided in an embodiment of this application;

[0058] Figure 3 This is a schematic diagram of another timing control circuit provided in an embodiment of this application;

[0059] Figure 4 This is a schematic diagram of pixel leakage current under variable refresh rate in related technologies;

[0060] Figure 5 This is a schematic diagram of another timing control circuit provided in the embodiments of this application.

[0061] Figure 6This is a schematic diagram of a time-based partitioning method provided in an embodiment of this application;

[0062] Figure 7 This is a schematic diagram of another timing control circuit provided in the embodiments of this application;

[0063] Figure 8 This is a schematic diagram illustrating the steps of a display driving method provided in an embodiment of this application. Detailed Implementation

[0064] The technical solutions in some embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0065] Figure 1 This is a schematic diagram of a pixel architecture in related technologies, such as... Figure 1 As shown, if a mixed-color image of R127 / G127 needs to be displayed, R127 represents the red grayscale value and G127 represents the green grayscale value. Comparing the R1 / G1 sub-pixels and the R2 / G2 sub-pixels, since the charging pixel before sub-pixel R1 is sub-pixel G1, sub-pixel G1 has a grayscale pre-charge voltage of G1(127), so sub-pixel R1 is charged well. However, the charging pixel before sub-pixel R2 is sub-pixel B1, and the grayscale pre-charge voltage of sub-pixel B1 is B1(0), so sub-pixel R2 is relatively undercharged. Therefore, there is a pre-charge voltage difference between sub-pixels R1 and R2. Similarly, there will also be a pre-charge voltage difference between sub-pixels G1 and G2, resulting in charging differences between pixels in different rows.

[0066] In the Zigzag pixel architecture of related technologies, the nth sub-pixel of each row is driven by the same source line, but the spatial arrangement of the sub-pixels is staggered. The advantage is that the power consumption of column flipping can achieve the display effect of point flipping. For special pixel architectures such as Zigzag, as pixel charging time becomes shorter and shorter, the difference in charging leads to more obvious differences in brightness between pixels in different rows, which can easily cause problems such as fine lines in the image display.

[0067] Figure 2 This is a schematic diagram of the structure of a timing control circuit 10 provided in an embodiment of this application. The timing control circuit 10 includes: a first detection module 101, a first identification module 102, and a compensation output module 103.

[0068] The first detection module 101 is electrically connected to the first recognition module 102, and is used to receive the display signal of a frame, determine the pixel clock frequency corresponding to the display signal, and send the pixel clock frequency to the first recognition module 102.

[0069] The first identification module 102 is electrically connected to the compensation output module 103 and is used to determine the target frequency partition corresponding to the pixel clock frequency from a plurality of preset frequency partitions, and send the first compensation list corresponding to the target frequency partition to the compensation output module 103; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows.

[0070] The compensation output module 103 is used to compensate the grayscale values ​​of pixels in at least one pixel row of the display signal according to the first compensation list, and output the compensated display signal.

[0071] In some embodiments, the timing control circuit 10 in the display device may include a detection sub-circuit composed of a first detection module 101, a first identification module 102, and a compensation output module 103. The detection sub-circuit compensates the grayscale value of the pixels in the display signal by detecting the pixel clock frequency corresponding to the display signal, so that the timing control circuit 10 drives the display panel through the compensated display signal. This can reduce the brightness difference caused by insufficient charging of pixels in different rows, avoid problems such as fine lines in the display, and improve the display quality.

[0072] For example, the timing control circuit 10 can be a timing controller (TCON), which can be electrically connected to the motherboard of the display device and receive display signals sent by the motherboard.

[0073] In some embodiments, the first detection module 101 receives a display signal of a frame, such as a Low-Voltage Differential Signaling (LVDS) signal, an Embedded DisplayPort (eDP) signal, or a V-by-One (VBO) signal. This is merely an example, and the embodiments of this application do not impose limitations.

[0074] The first detection module 101 can detect the pixel clock frequency of the display signal. The pixel clock frequency refers to the frequency of the pixel clock signal (DCLK) corresponding to the display signal. The pixel clock frequency is related to the total number of horizontal pixels, the total number of vertical pixels in the pixel array of the display panel, and the refresh rate corresponding to the display signal. It can be calculated by the following formula (1).

[0075] DCLKFreq=H-Total×V-Total×FRS(1)

[0076] Where DCLKFreq represents the pixel clock frequency, H-Total represents the total number of horizontal pixels, V-Total represents the total number of vertical pixels, and FRS represents the refresh rate corresponding to the display signal.

[0077] In some embodiments, the first detection module 101 may include digital circuit units such as a control unit, an arithmetic unit, and a storage unit. The first detection module 101 can communicate with the motherboard of the display device, receive display signals sent by the motherboard, and obtain the total horizontal and vertical pixel counts of the display panel of the display device from the motherboard. Then, the first detection module 101 obtains the pixel clock frequency of the display signal through internal calculation. For example, the first detection module 101 may be a detector (DCLKDetector). The DCLKDetector can calculate the size of DCLKFreq according to formula (1) using the H-Total information, V-Total information, and FRS information provided by the motherboard.

[0078] In some embodiments, the first identification module 102 may pre-store multiple different frequency partitions, each frequency partition being a certain range of frequency intervals, and the frequency ranges of different frequency partitions do not overlap. For example, as shown in Table 1, the maximum value of the pixel clock frequency is 1000 MHz, and 1000 MHz can be divided into 4 frequency partitions by partitioning nodes 400 MHz, 600 MHz, and 800 MHz, namely (0, 400], (400, 600], (600, 800], and (800, 1000].

[0079] In some embodiments, as shown in Table 1, one frequency partition corresponds to one first compensation list. Different frequency partitions correspond to different first compensation lists. In Table 1, LOD_1 to LOD_4 represent the first compensation lists corresponding to the frequency partitions (0, 400], (400, 600], (600, 800], and (800, 1000], respectively. Multiple frequency partitions and their multiple first compensation lists can be pre-stored in the first identification module 102, or multiple frequency partitions can be pre-stored in the first identification module 102 while the multiple first compensation lists can be stored in the external storage unit of the first identification module 102. This application embodiment does not limit this.

[0080] Table 1 Frequency Zoning

[0081] Partition Node 400 600 800 1000 LOD List LOD_1 LOD_2 LOD_3 LOD_4

[0082] In some embodiments, to address the brightness differences between different rows of pixels caused by charging differences, this embodiment compensates for the brightness differences between different rows of pixels by using a pre-defined compensation relationship between grayscale values ​​of pixels in adjacent rows in a first compensation list. For adjacent rows of pixels, the grayscale values ​​of pixels in one row can be adjusted based on the grayscale values ​​of pixels in another row, so that the adjusted grayscale values ​​of pixels in that row can reduce the brightness difference between adjacent rows of pixels.

[0083] The first compensation list may include two sets of preset grayscale values, as well as adjusted grayscale values ​​after compensation for the preset grayscale values. The compensation relationship is specifically the correspondence between the preset grayscale values ​​and the adjusted grayscale values.

[0084] In some embodiments, the first detection module 101 sends the detected pixel clock frequency to the first identification module 102. The first identification module 102 compares the pixel clock frequency with a plurality of preset frequency partitions to determine which frequency partition the pixel clock frequency belongs to, and that frequency partition is the target frequency partition. Then, the first identification module 102 sends the first compensation list corresponding to the target frequency partition to the compensation output module 103, so that the compensation output module 103 can compensate the display signal according to the first compensation list.

[0085] In some embodiments, for the grayscale value of a pixel in the display signal, the compensation output module 103 can determine a preset grayscale value that is the same as the grayscale value of the pixel based on the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows in the first compensation list, and a preset grayscale value that is the same as the grayscale value of pixels connected to the same data line in the pixel row adjacent to the pixel's row. The module then looks up the table to determine the adjustment grayscale value corresponding to this set of preset grayscale values ​​and compensates the grayscale value of the pixel in the display signal to the adjustment grayscale value.

[0086] To address issues such as fine lines in the display image caused by brightness differences between pixels in different rows, the compensation output module 103 can compensate for the grayscale values ​​of pixels in at least one pixel row of the display signal by adjusting the grayscale values, thereby reducing the brightness differences between pixels in different rows. For example, in a 90 grayscale image, pixels in different rows can be assigned grayscale values ​​of 90 or 90.5 respectively to compensate for the charging differences between pixels in different rows.

[0087] In this embodiment, the first detection module 101 in the timing control circuit 10 detects the pixel clock frequency corresponding to the display signal, enabling the first identification module 102 to identify the correspondence between the pixel clock frequency and multiple preset frequency partitions. The first identification module 102 outputs a first compensation list corresponding to the target frequency partition to the compensation output module 103 based on the target frequency partition corresponding to the pixel clock frequency. Since the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows, the compensation output module 103 can compensate the grayscale values ​​of pixels in at least one pixel row in the display signal according to the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows in the first compensation list, and output the compensated display signal. Thus, by driving the display screen with the compensated display signal, the charging difference between pixels in at least one pixel row and pixels in adjacent rows can be reduced, thereby improving problems such as fine lines in the screen display caused by brightness differences between pixels in different rows, and improving the display screen quality.

[0088] Optionally, the first identification module 102 includes a first partitioning unit 1021 and a first enabling unit 1022;

[0089] The first partitioning unit 1021 is electrically connected to the first detection module 101 and the first enabling unit 1022 respectively, and is used to determine the target frequency partition corresponding to the pixel clock frequency from a plurality of preset frequency partitions, and send the first enabling signal corresponding to the target frequency partition to the first enabling unit 1022.

[0090] The first enabling unit 1022 is also electrically connected to the compensation output module 103, and is used to send the first compensation list corresponding to the first enabling signal to the compensation output module 103.

[0091] In some embodiments, the first partitioning unit 1021 may preset multiple frequency partitions. The first partitioning unit 1021 receives the pixel clock frequency sent by the first detection module 101, compares the pixel clock frequency with the preset multiple frequency partitions, determines which frequency partition the pixel clock frequency belongs to, and determines the frequency partition as the target frequency partition.

[0092] For example, the first partitioning unit 1021 can be a digital signal processor (DSP), which can pre-store multiple frequency partitions. A signal processing algorithm can be written into the DSP to determine the target frequency partition corresponding to the pixel clock frequency from the preset multiple frequency partitions. After receiving the pixel clock frequency, the DSP executes the signal processing algorithm and outputs a first enable signal corresponding to the target frequency partition to the first enable unit 1022. This is merely an example, and the embodiments of this application do not impose limitations.

[0093] In some embodiments, the first enable signal is used to indicate which of the preset multiple frequency partitions the target frequency partition is, so that the first enable unit 1022 sends the first compensation list corresponding to the target frequency partition to the compensation output module 103.

[0094] Optionally, the first enabling unit 1022 includes a plurality of first controllers;

[0095] The enable terminal of the first controller is electrically connected to the first partition unit 1021, and the output terminal of the first controller is electrically connected to the compensation output module 103.

[0096] When the first controller receives a first enable signal from the first partition unit 1021 at the enable terminal, it sends the first compensation list input at the input terminal to the compensation output module 103 through the output terminal.

[0097] In some embodiments, the first partitioning unit 1021 may include multiple output terminals, which are connected one-to-one with the enable terminals of multiple first controllers. Each output terminal of the first partitioning unit 1021 is used to output a first enable signal for the corresponding frequency partition. Each first controller corresponds to a preset frequency partition and is used to enable the output of the first compensation list corresponding to that frequency partition to the compensation output module 103. The input terminal of the first controller may be electrically connected to a storage unit in the timing control circuit 10 or an external storage module of the timing control circuit 10 to receive the first compensation list corresponding to that first controller.

[0098] In some embodiments, after the first partitioning unit 1021 determines the target frequency partition corresponding to the pixel clock frequency, it sends a corresponding first enable signal to the enable terminal of the first controller corresponding to the target frequency partition through the output terminal of the multiple output terminals. In response to the first enable signal received by the enable terminal, the first controller outputs the first compensation list input by the input terminal to the compensation output module 103.

[0099] For example, the first controller can be an enable controller. When the enable terminal of the first controller detects the first enable signal input, it can output the first compensation list at the input terminal to the compensation output module 103 through the output terminal.

[0100] Optionally, the compensation output module 103 includes a first input terminal, which is electrically connected to the output terminals of a plurality of first controllers respectively;

[0101] The compensation output module 103 is used to receive a first compensation list through a first input terminal, and to look up the table according to the first compensation list to determine the adjusted grayscale value of the pixels in at least one pixel row after compensation, so as to compensate the grayscale value of the pixels in at least one pixel row in the display signal.

[0102] In some embodiments, the outputs of multiple first controllers in the first enabling unit 1022 are connected to the same first input of the compensation output module 103. The first partitioning unit 1021 identifies a frequency partition from a plurality of preset frequency partitions based on the pixel clock frequency and determines it as the target frequency partition. Then, the first partitioning unit 1021 outputs a first enable signal corresponding to the target frequency partition to the corresponding first controller through an output terminal, causing the first controller to enable the output of the first compensation list corresponding to the target frequency partition. That is, the first enabling unit 1022 outputs only one first compensation list to the compensation output module 103 for the display signal of one frame.

[0103] In some embodiments, the compensation output module 103 receives a first compensation list output by the first enable unit 1022 through a first input terminal, and then compensates the display signal according to the first compensation list. Specifically, for pixels in a pixel row to be compensated, the compensation output module 103 can look up a table to determine the adjustment grayscale value corresponding to this set of preset grayscale values ​​based on the preset grayscale value corresponding to the grayscale value of the pixels in that row, and the preset grayscale value corresponding to the grayscale value of the pixels in the adjacent pixel row, so as to compensate the grayscale value of the pixels in the pixel row to be compensated.

[0104] Figure 3 This is a schematic diagram of another timing control circuit 10 provided in an embodiment of this application, as shown below. Figure 3 As shown, the timing control circuit 10 includes a first detection module 101 (DCLK Detector), a first partitioning unit 1021 (DSP1), the first partitioning unit 1021 including M first controllers (EnableControllers), and a compensation output module 103 (Synthesizer). DSP1 includes M output terminals (O_M), where M is a positive integer. The enable terminal (EN) of each first controller is electrically connected to the corresponding output terminal O_M in DSP1, the input terminal of each first controller receives the corresponding first compensation list (LOD_M), and the output terminal of each first controller is electrically connected to one first input terminal (LOD) of the compensation output module 103.

[0105] like Figure 3As shown, the first detection module 101 receives and detects the display signal of a frame, and sends the pixel clock frequency corresponding to the display signal to the DSP1. The DSP1 determines the target frequency partition corresponding to the pixel clock frequency, and sends a first enable signal to the corresponding first controller through the output terminal O_M of the target frequency partition. This enables the first controller to output the first compensation list LOD_M corresponding to the target frequency partition to the first input terminal LOD of the compensation output module 103.

[0106] Figure 4 This is a schematic diagram of pixel leakage current under variable refresh rate in related technologies, such as... Figure 4 As shown, after a pixel completes its charging within one frame, if the vertical scan blanking region (V-Blank) takes a long time, the charge of the pixels in the V-Blank region will leak out. Figure 4 The horizontal axis represents time, and the vertical axis represents voltage. Under variable refresh rate (VRR) conditions, the V-Blank duration in the display signal of different frames may be different. Different V-Blank durations lead to differences in the leakage time of pixels in different frames, resulting in differences in the amount of charge within the pixels, and ultimately causing differences in pixel brightness.

[0107] Optionally, such as Figure 5 As shown, the timing control circuit 10 also includes a second detection module 104 and a second identification module 105;

[0108] The second detection module 104 is electrically connected to the second recognition module 105 and is used to receive the display signal of a frame, determine the first blanking duration corresponding to the display signal, and send the first blanking duration to the second recognition module 105; wherein, the first blanking duration is the duration of the vertical scan blanking area corresponding to the display signal.

[0109] The second identification module 105 is electrically connected to the compensation output module 103 and is used to send the second compensation list corresponding to the first blanking time to the compensation output module 103; wherein, the second compensation list includes a plurality of preset grayscale values ​​and a compensation coefficient corresponding to each grayscale value.

[0110] The compensation output module 103 is also used to compensate the grayscale values ​​of each pixel in the display signal according to the second compensation list.

[0111] In some embodiments, the detection sub-circuit of the timing control circuit 10, which consists of the first detection module 101, the first identification module 102, and the compensation output module 103, may further include a second detection module 104 and a second identification module 105. The detection sub-circuit can compensate for the grayscale value of each pixel in the display signal by detecting the V-Blank duration corresponding to the display signal, thereby compensating for the grayscale value of a frame. This allows the timing control circuit 10 to drive the display panel with the compensated display signal, reducing the leakage time difference caused by the V-Blank duration difference between different frames, improving the pixel brightness difference caused by the leakage time difference, and enhancing the display quality.

[0112] In some embodiments, the second detection module 104 receives a display signal of a frame, such as LVDS, eDP, and VBO. The second detection module 104 can detect the V-Blank duration of the display signal; in this embodiment, the V-Blank duration is referred to as the first blanking duration. The time of a frame may include a display phase (V-active) and a vertical scan blanking region (V-Blank). The second detection module 104 can subtract the display phase duration from the total time corresponding to the display signal of a frame to obtain the V-Blank duration, which is also the first blanking duration. This is merely an example, and the embodiments of this application do not impose limitations.

[0113] In some embodiments, the second detection module 104 may include digital circuit units such as a control unit, an arithmetic unit, and a storage unit. The second detection module 104 can communicate with the motherboard of the display device and receive display signals sent by the motherboard. For example, the second detection module 104 may be a detector (V-BlankDetector).

[0114] In some embodiments, the second identification module 105 may pre-store multiple time-duration partitions, each of which is a certain range of time intervals, and the duration ranges of different time-duration partitions do not overlap. Each time-duration partition corresponds to a second compensation list, and different time-duration partitions correspond to different second compensation lists. Multiple time-duration partitions and their multiple second compensation lists may be pre-stored in the second identification module 105, or multiple time-duration partitions may be pre-stored in the second identification module 105 while the multiple second compensation lists may be stored in the external storage unit of the second identification module 105. This application embodiment does not impose any limitations on this.

[0115] In some embodiments, given the different V-Blank durations corresponding to the display signals of different frames, this embodiment compensates for the overall display signal of a frame by using multiple preset grayscale values ​​in the second compensation list and the compensation coefficient corresponding to each grayscale value. This means compensating for the grayscale values ​​of each pixel in the display signal, thereby reducing the pixel brightness differences caused by the different V-Blank durations in different frames. For example, to display a 90 grayscale image, grayscale values ​​such as 90.1 and 90.2 can be actually displayed to compensate for the brightness differences caused by different V-Blank durations.

[0116] The second compensation list includes multiple preset grayscale values, which can include several grayscale values ​​from Gray0 to Gray255 in the image. A corresponding compensation coefficient can be set for each preset grayscale value, and the compensation coefficient is the compensation multiplier corresponding to the grayscale value. For example, Gray63 grayscale can be increased to Gray63.1 grayscale through the compensation coefficient.

[0117] In some embodiments, the second detection module 104 sends the detected first blanking duration to the second identification module 105. The second identification module 105 compares the first blanking duration with a plurality of preset duration partitions and sends the second compensation list corresponding to the first blanking duration to the compensation output module 103, so that the compensation output module 103 can compensate the grayscale value of each pixel in the display signal according to the second compensation list.

[0118] Optionally, the second identification module 105 includes a second partitioning unit 1051 and a second enabling unit 1052;

[0119] The second partitioning unit 1051 is electrically connected to the second detection module 104 and the second enabling unit 1052, respectively. It is used to compare the first blanking duration with the multiple time-duration partitions in ascending order according to the preset multiple time-duration partitions, and send the second enabling signal corresponding to the time-duration partition to the second enabling unit 1052 each time the first blanking duration is greater than the minimum length of a time-duration partition; wherein the durations of the vertical scanning blanking regions corresponding to the multiple time-duration partitions do not overlap.

[0120] The second enabling unit 1052 is also electrically connected to the compensation output module 103, and is used to send the second compensation list corresponding to the second enabling signal to the compensation output module 103.

[0121] In some embodiments, the second partitioning unit 1051 receives the first blanking duration sent by the second detection module 104, and compares the first blanking duration with the preset multiple duration partitions in ascending order. When the first blanking duration is greater than the minimum length of a duration partition, a second enable signal is triggered, that is, the second enable signal corresponding to that duration partition is sent to the second enable unit 1052. The number of times the second enable signal is triggered during the comparison of the first blanking duration with the preset multiple duration partitions corresponds to the number of times the second enable signal is sent from the second partitioning unit 1051 to the second enable unit 1052. Thus, the duration partition corresponding to the last second enable signal sent by the second partitioning unit 1051 to the second enable unit 1052 is the duration range to which the first blanking duration belongs.

[0122] For example, the second partitioning unit 1051 can be a digital signal processor (DSP), which can pre-store multiple duration partitions. A signal processing algorithm can be written into the DSP to compare the first blanking duration with the multiple duration partitions in ascending order, determining whether the first blanking duration is greater than the minimum length of a duration partition at each comparison. After receiving the first blanking duration, the DSP executes the signal processing algorithm and outputs a second enable signal triggered by each comparison to the second enable unit 1052. This is merely an example, and the embodiments of this application do not impose limitations.

[0123] Figure 6 This is a schematic diagram of a time-based partitioning method provided in an embodiment of this application, such as... Figure 6 As shown, the duration of the V-active region is 1440 microseconds (μs), the V-Blank region is (1440, 7200], and the duration of the V-Blank region is 5760 μs. The V-Blank region (1440, 7200] can be divided into 6 duration partitions using partition nodes 2400 μs, 3360 μs, 4320 μs, 5280 μs, 6240 μs, and 7200 μs, respectively: [1440, 2400], (2400, 3360], (3360, ..., 7200 μs).

[4320] , (4320, 5280], (5280, 6240], and (6240, 7200]. Each duration partition corresponds to a second compensation list. Different duration partitions correspond to different second compensation lists. The six duration partitions correspond to GLC_1, GLC_2, GLC_3, GLC_4, GLC_5, and GLC_6, respectively. This is only an example. In actual applications, the number of partitions and the duration range of each duration partition can be set as needed. This application embodiment does not limit this.

[0124] Table 2 shows multiple second compensation lists GLC_N provided in the embodiments of this application. Each second compensation list in Table 2 corresponds to a time partition. For example, GLC_1, GLC_2, GLC_3, GLC_4, GLC_5, and GLC_6 correspond to time partitions [1440, 2400], (2400, 3360], (3360, 4320], (4320, 5280], (5280, 6240], and (6240, 7200], respectively. For gray levels Gray 0 to 255, each second compensation list sets three gray level values ​​Gray 63, Gray 127, and Gray 191 and their compensation coefficients. For example, the compensation coefficients 1-1, 1-2, and 1-3 corresponding to the GLC_1 list in Table 2 are shown.

[0125] Table 2 GLC_N List

[0126] GLC_1 - 63*coefficient 1-1 127 * coefficient 1-2 191*coefficient 1-3 - GLC_2 - 63*coefficient2-1 127 * coefficient 2-2 191*coefficient 2-3 - GLC_3 - 63*coefficient 3-1 127 * coefficient 3 - 2 191*coefficient 3-3 - GLC_4 - 63*coefficient 4-1 127 * coefficient 4 - 2 191*coefficient 4-3 - GLC_5 - 63 * coefficient 5-1 127 * coefficient 5 - 2 191*coefficient 5-3 - GLC_6 - 63 * coefficient 6-1 127 * coefficient 6 - 2 191*coefficient 6-3 -

[0127] In some embodiments, the compensation coefficients for each grayscale value between Gray0 and Gray63, Gray63 and Gray127, Gray127 and Gray191, and Gray191 and Gray255 can be obtained through interpolation. For example, linear interpolation compensation can be performed internally by the GLC digital module to avoid excessive computational load. In practical applications, to improve compensation accuracy, the preset grayscale values ​​in the second compensation list can be subdivided to achieve higher precision compensation. For example, the grayscale values ​​can be subdivided into Gray31, Gray63, Gray95, Gray127, Gray159, Gray191, and Gray223, while Gray0 and Gray255 grayscale values ​​generally do not require compensation.

[0128] Optionally, the second enabling unit 1052 includes a plurality of second controllers;

[0129] The enable terminal of the second controller is electrically connected to the second partition unit 1051, and the output terminal of the second controller is electrically connected to the compensation output module 103.

[0130] When the second controller receives the second enable signal sent by the second partition unit 1051 at the enable terminal, it sends the second compensation list input at the input terminal to the compensation output module 103 through the output terminal.

[0131] In some embodiments, the second partitioning unit 1051 may include multiple output terminals, each of which is connected to an enable terminal of a plurality of second controllers. Each output terminal of the second partitioning unit 1051 is used to output a second enable signal for the corresponding duration partition. Each second controller corresponds to a preset duration partition and is used to enable the output of the second compensation list corresponding to that duration partition to the compensation output module 103. The input terminal of the second controller may be electrically connected to a storage unit in the timing control circuit 10 or an external storage module of the timing control circuit 10 to receive the second compensation list corresponding to that second controller.

[0132] In some embodiments, after the second partitioning unit 1051 triggers a second enable signal corresponding to a duration partition, it sends a corresponding second enable signal to the enable terminal of the second controller corresponding to that duration partition through one of the multiple output terminals. In response to the second enable signal received by the enable terminal, the second controller outputs the second compensation list input at the input terminal to the compensation output module 103.

[0133] For example, the second controller can be an enable controller. When the enable terminal of the second controller detects the second enable signal input, it can output the second compensation list at the input terminal to the compensation output module 103 through the output terminal.

[0134] Optionally, the compensation output module 103 includes a plurality of second input terminals, which are connected one-to-one with the output terminals of a plurality of second controllers;

[0135] The compensation output module 103 is used to receive at least one second compensation list through multiple second input terminals, and to determine the compensation coefficient corresponding to the gray level value of each pixel in the display signal by looking up the table according to the last received second compensation list, and to determine the output gray level value of each pixel in the display signal according to the compensation coefficient, so as to compensate the gray level value of each pixel in the display signal.

[0136] In some embodiments, each second input terminal of the compensation output module 103 corresponds to a preset duration partition, and the duration partition corresponding to each second input terminal is the same as that of the second controller connected to it. The second partitioning unit 1051 compares the first blanking duration with the preset multiple duration partitions and triggers a second enable signal at least once. Then, at least one second controller in the second enable unit 1052 sends a corresponding second compensation list to the compensation output module 103, so that the compensation output module 103 receives at least one second compensation list through the multiple second input terminals.

[0137] The order in which the compensation output module 103 receives the second compensation list is independent of the order of the multiple second input terminals themselves, but only depends on the order in which the multiple second controllers send the second compensation list to the compensation output module 103.

[0138] In some embodiments, the second enable signal sent by the second partitioning unit 1051 to the second enable unit 1052 for the last time is the duration partition corresponding to the last triggered second enable signal, which is the final determined duration range of the first blanking duration. Therefore, the compensation output module 103 compensates the grayscale values ​​of each pixel in the display signal according to the received last second compensation list. Specifically, it looks up the compensation coefficient corresponding to the grayscale value of each pixel in the second compensation list, and then multiplies the grayscale value with the compensation coefficient. The product is the grayscale value of the pixel after compensation. The grayscale value of each pixel after compensation is used as the output grayscale value, thereby compensating the grayscale values ​​of each pixel in the display signal.

[0139] Figure 7 This is a schematic diagram of another timing control circuit 10 provided in the embodiments of this application, as shown below. Figure 7 As shown, the timing control circuit 10 also includes a second detection module 104 (V-Blank Detector), a second partitioning unit 1051 (DSP2), and a second enable unit 1052 comprising N second controllers (EnableControllers). DSP2 includes M output terminals (G_N), where N is a positive integer. The enable terminal (EN) of each second controller is electrically connected to the corresponding output terminal G_N in DSP2. The input terminal of each second controller receives the corresponding second compensation list (GLC_N). The output terminals of the multiple second controllers are connected one-to-one with the multiple second input terminals (GLCN) of the compensation output module 103.

[0140] like Figure 7 As shown, the second detection module 104 receives the display signal of a frame and detects the display signal, sending the first blanking duration corresponding to the display signal to the DSP2. The DSP2 compares the first blanking duration with multiple preset duration partitions in sequence, triggers a second enable signal, and sends the second enable signal to the corresponding second controller through the corresponding output terminal G_N. This enables the second controller to output the corresponding second compensation list GLC_N to the second input terminal GLCN of the compensation output module 103.

[0141] This application provides a display device, which includes a display panel and a timing control circuit 10 as described in the foregoing embodiments;

[0142] The timing control circuit 10 is electrically connected to the display panel and is used to output the compensated display signal to the display panel to drive the display panel to display.

[0143] In some embodiments, the timing control circuit 10 can drive the display panel through the gate driving circuit and the source driving circuit. The timing control circuit 10 controls the gate driving circuit and the source driving circuit to output driving signals respectively according to the compensated display signal, thereby driving the display panel to display a frame corresponding to the compensated display signal. For example, the display device can be a liquid crystal display (LCD), and the display panel can be an LCD panel.

[0144] The display device provided in this application embodiment can achieve the same or similar technical effects as the timing control circuit 10 in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0145] Figure 8 This is a schematic diagram illustrating the steps of a display driving method provided in an embodiment of this application, as shown below. Figure 8 As shown, the display driving method includes:

[0146] Step S1: Receive the display signal of a frame and determine the pixel clock frequency corresponding to the display signal;

[0147] Step S2: Determine the target frequency partition corresponding to the pixel clock frequency from a preset plurality of frequency partitions, and determine the corresponding first compensation list according to the target frequency partition; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows;

[0148] Step S3: Compensate the grayscale value of the pixels in at least one pixel row of the display signal according to the first compensation list, and output the compensated display signal to the display panel to drive the display panel to display.

[0149] Optionally, step S3 may include the following sub-steps:

[0150] Sub-step A1: For the grayscale value of the first pixel in the first pixel row of the display signal, determine the grayscale value of the second pixel in the second pixel row adjacent to the first pixel row; wherein the first pixel and the second pixel are connected to the same data line, and the first pixel receives the driving signal transmitted by the data line later than the second pixel;

[0151] Sub-step A2: Based on the grayscale value of the first pixel and the grayscale value of the second pixel, the adjusted grayscale value of the first pixel after compensation is determined by looking up a table based on the first compensation list, so as to compensate the grayscale value of each first pixel in the first pixel row in the display signal; wherein, at least one pixel row includes the first pixel row.

[0152] In some embodiments, the first pixel row is a certain pixel row to be compensated. The compensation output module 103 can compare the grayscale values ​​of pixels in different pixel rows in the display signal of a frame, and take the pixel row with a larger difference in grayscale value from the adjacent pixel row as the pixel row to be compensated, i.e., the first pixel row. Alternatively, the compensation output module 103 can directly start from the second row of pixels on the display panel and sequentially take each row of pixels as the first pixel row for grayscale value compensation. This application embodiment does not limit this.

[0153] In some embodiments, the second pixel row is a pixel row adjacent to the first pixel row, and the second pixel row is the row preceding the first pixel row. That is, the first pixel in the first pixel row receives the drive signal transmitted via the data line later than the second pixel in the second pixel row. Thus, for first and second pixels connected to the same data line, the first pixel has the grayscale pre-charge voltage corresponding to the second pixel. If the grayscale values ​​of the second pixels in the second pixel row are different, then the pre-charge grayscale voltages of the first pixels in the first pixel row will differ.

[0154] In some embodiments, for any first pixel in a first pixel row, a second pixel in a second pixel row adjacent to the first pixel row that is connected to the same data line as the first pixel is determined. Then, based on the grayscale values ​​of this set of first pixels and the grayscale values ​​of the second pixel, a lookup table is performed based on a first compensation list to obtain the adjusted grayscale value corresponding to this set of grayscale values, which is used as the adjusted grayscale value of the first pixel after compensation.

[0155] In this way, by compensating the original grayscale value of each first pixel in the first pixel row of the display signal to an adjusted grayscale value, the grayscale value of each first pixel in the first pixel row of the display signal can be compensated, thereby reducing the charging difference caused by the difference in pre-charge voltage among the first pixels in the first pixel row and improving the pixel brightness difference caused by the charging difference between the two adjacent pixel rows, the first pixel row and the second pixel row.

[0156] Optionally, sub-step A2 may include the following sub-steps:

[0157] A preset grayscale value that is the same as the grayscale value of the first pixel is determined according to the first set of grayscale values ​​in the first compensation list, and a preset grayscale value that is the same as the grayscale value of the second pixel is determined according to the second set of grayscale values ​​in the first compensation list.

[0158] Based on the correspondence between two preset grayscale values, the corresponding adjusted grayscale value is obtained from the first compensation list and used as the adjusted grayscale value of the first pixel after compensation.

[0159] The first compensation list includes a first group of grayscale values, a second group of grayscale values, and multiple adjustable grayscale values ​​corresponding to multiple sets of correspondences; the first group of grayscale values ​​and the second group of grayscale values ​​each include multiple preset grayscale values; the multiple sets of correspondences include the correspondence between each preset grayscale value in the first group of grayscale values ​​and different preset grayscale values ​​in the second group of grayscale values.

[0160] In some embodiments, a first set of grayscale values ​​in the first compensation list is used to look up the grayscale value of the first pixel in the first pixel row, and a second set of grayscale values ​​in the first compensation list is used to look up the grayscale value of the second pixel in the second pixel row. Multiple preset grayscale values ​​in the first set are paired with multiple preset grayscale values ​​in the second set to obtain multiple sets of correspondences between the preset grayscale values. Each set of correspondences is assigned an adjustment grayscale value, resulting in multiple adjustment grayscale values. These adjustment grayscale values ​​are used to compensate for the grayscale value of the first pixel in the first pixel row.

[0161] In some embodiments, when performing a lookup table based on the grayscale values ​​of the first pixel and the second pixel, a preset grayscale value that is the same as or similar to the grayscale value of the first pixel is determined from a plurality of preset grayscale values ​​in the first group of grayscale values, and a preset grayscale value that is the same as or similar to the grayscale value of the second pixel is determined from a plurality of preset grayscale values ​​in the second group of grayscale values. If a matching preset grayscale value cannot be directly found from the first and second groups of grayscale values, a temporary grayscale value is determined by interpolation of similar preset grayscale values. This temporary grayscale value is then interpolated during subsequent lookups of the adjustment grayscale value to determine the corresponding adjustment grayscale value.

[0162] In some embodiments, two preset grayscale values ​​are obtained by looking up the grayscale values ​​of the first pixel and the second pixel in a table. Next, based on the correspondence between the two preset grayscale values, a common correspondence is determined from multiple sets of correspondences in the first compensation list. Then, the adjusted grayscale value corresponding to this correspondence is used as the compensated adjusted grayscale value of the first pixel. If there is a temporary grayscale value determined by interpolation among the two obtained preset grayscale values, a similar correspondence is determined from multiple sets of correspondences, and its adjusted grayscale value is interpolated. The interpolation result is used as the compensated adjusted grayscale value of the first pixel.

[0163] Table 3 shows a first compensation list, namely the LOD_M list, provided in an embodiment of this application. As shown in Table 3, the first row of the table contains the first set of preset grayscale values, and the first column contains the second set of preset grayscale values. Table 3 also shows the adjusted grayscale values ​​corresponding to multiple sets of correspondences between the preset grayscale values. For example, if the grayscale value of a first pixel is 127, and the grayscale value of the corresponding second pixel is 63, based on the correspondence between the preset grayscale value 127 in the first set of grayscale values ​​and the preset grayscale value 63 in the second set of grayscale values, the adjusted grayscale value is determined to be 130 by looking up the table. The grayscale value corresponding to the first pixel is adjusted to 130 to compensate for the grayscale value of the first pixel.

[0164] Table 3 LOD _ M list

[0165]

[0166] Optionally, before outputting the compensated display signal to the display panel, the display driving method further includes:

[0167] Step S4: Determine the first blanking duration corresponding to the display signal; wherein, the first blanking duration is the time length of the vertical scan blanking region corresponding to the display signal;

[0168] Step S5: Determine the second compensation list corresponding to the first blanking duration; wherein, the second compensation list includes multiple preset grayscale values ​​and the compensation coefficient corresponding to each grayscale value;

[0169] Step S6: Compensate the grayscale values ​​of each pixel in the display signal according to the second compensation list.

[0170] Optionally, step S5 may include the following sub-steps:

[0171] Sub-step B1: According to the preset multiple duration partitions in ascending order, the first blanking duration is compared with the multiple duration partitions in turn, and the second compensation list corresponding to the duration partition is triggered each time the first blanking duration is greater than the minimum length of a duration partition; wherein, the duration of the vertical scan blanking area corresponding to the multiple duration partitions does not overlap.

[0172] Sub-step B2: Determine the last triggered second compensation list as the second compensation list corresponding to the first blanking duration.

[0173] Optionally, step S6 may include the following sub-steps:

[0174] Sub-step C1: For a target pixel with an adjustable grayscale value, determine the output grayscale value of the target pixel based on the adjusted grayscale value and the compensation coefficient corresponding to the target pixel; wherein, the compensation coefficient corresponding to the target pixel is the compensation coefficient corresponding to the grayscale value of the target pixel before compensation.

[0175] Sub-step C2: For pixels other than the target pixel, determine the output grayscale value of the other pixels based on their original grayscale values ​​and corresponding compensation coefficients.

[0176] Before outputting the compensated display signal to the display panel, the display driving method also includes:

[0177] Step S7: Obtain the compensated display signal based on the output grayscale value of the target pixel and the output grayscale values ​​of other pixels.

[0178] In some embodiments, for a single frame of the display signal, the pixel clock frequency is detected by the first detection module 101 and the first recognition module 102, and the compensation output module 103 receives a first compensation list corresponding to the target frequency partition to which the pixel clock frequency belongs. Furthermore, the first blanking duration is detected by the second detection module 104 and the second recognition module 105, and the compensation output module 103 receives at least one second compensation list. The compensation output module 103 performs grayscale value compensation on the display signal based on the first compensation list and the last received second compensation list.

[0179] Specifically, when the compensation output module 103 compensates the grayscale values ​​of each pixel in the display signal according to the second compensation list, if a pixel has already had its grayscale value adjusted, then that pixel is the target pixel. The compensation output module 103 can multiply the adjusted grayscale value by a compensation coefficient to obtain the final output grayscale value of the target pixel. If the pixel has not had its grayscale value adjusted, then it is another pixel, and the output grayscale value of the other pixels is the original grayscale value multiplied by the compensation coefficient. In this way, the signal of each pixel in the display signal is compensated according to the second compensation list.

[0180] In some embodiments, to improve processing efficiency, the supplementary output module can simultaneously compensate the grayscale values ​​of each pixel in the display signal according to a first compensation list and a second compensation list. Specifically, the compensation output module 103 can determine the adjusted grayscale value of a pixel after compensation based on the original grayscale value of the pixel by looking up a table in the first compensation list, and determine the compensation coefficient corresponding to the grayscale value of the pixel by looking up a table in the second compensation list. Then, it multiplies the adjusted grayscale value by the compensation coefficient to obtain the output grayscale value of the pixel. Here, the pixel is the target pixel, and the compensation coefficient corresponding to the target pixel is the compensation coefficient corresponding to the grayscale value of the target pixel before compensation.

[0181] In some embodiments, for a single frame of the display signal, the compensation output module 103 compensates the grayscale value of the target pixel to the corresponding output grayscale value, and compensates the grayscale values ​​of other pixels to the corresponding output grayscale values, thereby compensating the grayscale values ​​of each pixel in the display signal to obtain a compensated display signal. In practical applications, adjustments can be made based on the display effect. The compensation output module 103 can perform digital signal processing, such as gain coefficient or attenuation coefficient, when calculating the output grayscale value. Then, the compensation output module 103 sends the compensated display signal to the display panel to drive the display panel to display the image, which can avoid problems such as fine lines in the image and improve the display quality.

[0182] The display driving method provided in this application embodiment can achieve the same or similar technical effects as the timing control circuit 10 in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0183] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0184] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0185] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0186] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0187] The timing control circuit, display device, and display driving method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A timing control circuit, characterized in that, The timing control circuit includes: a first detection module, a first identification module, and a compensation output module; The first detection module is electrically connected to the first recognition module and is used to receive a display signal of a frame, determine the pixel clock frequency corresponding to the display signal, and send the pixel clock frequency to the first recognition module. The first identification module is electrically connected to the compensation output module and is used to determine the target frequency partition corresponding to the pixel clock frequency from a plurality of preset frequency partitions, and send the first compensation list corresponding to the target frequency partition to the compensation output module; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows; The compensation output module is used to compensate the grayscale value of pixels in at least one pixel row of the display signal according to the first compensation list, and output the compensated display signal. One frequency partition corresponds to one first compensation list, and different frequency partitions correspond to different first compensation lists; The first compensation list includes two sets of preset grayscale values ​​and an adjusted grayscale value after compensation for the preset grayscale values. The compensation relationship is the correspondence between the preset grayscale values ​​and the adjusted grayscale values.

2. The timing control circuit according to claim 1, characterized in that, The first identification module includes a first partitioning unit and a first enabling unit; The first partitioning unit is electrically connected to the first detection module and the first enabling unit, respectively, and is used to determine the target frequency partition corresponding to the pixel clock frequency from the preset plurality of frequency partitions, and send the first enabling signal corresponding to the target frequency partition to the first enabling unit. The first enabling unit is also electrically connected to the compensation output module and is used to send the first compensation list corresponding to the first enabling signal to the compensation output module.

3. The timing control circuit according to claim 2, characterized in that, The first enabling unit includes a plurality of first controllers; The enable terminal of the first controller is electrically connected to the first partition unit, and the output terminal of the first controller is electrically connected to the compensation output module. The first controller is configured to send the first compensation list input at the input terminal to the compensation output module through the output terminal when the first enable signal sent by the first partition unit is received at the enable terminal.

4. The timing control circuit according to claim 1, characterized in that, The compensation output module includes a first input terminal, which is electrically connected to the output terminals of a plurality of first controllers respectively. The compensation output module is used to receive the first compensation list through the first input terminal, and to look up the table according to the first compensation list to determine the adjusted grayscale value of the pixels in the at least one pixel row after compensation, so as to compensate the grayscale value of the pixels in the at least one pixel row in the display signal.

5. The timing control circuit according to any one of claims 1-4, characterized in that, The timing control circuit also includes a second detection module and a second identification module; The second detection module is electrically connected to the second recognition module and is used to receive the display signal of the frame, determine the first blanking duration corresponding to the display signal, and send the first blanking duration to the second recognition module; wherein, the first blanking duration is the duration of the vertical scan blanking region corresponding to the display signal; The second identification module is electrically connected to the compensation output module and is used to send the second compensation list corresponding to the first blanking time to the compensation output module; wherein, the second compensation list includes a plurality of preset grayscale values ​​and a compensation coefficient corresponding to each grayscale value; The compensation output module is also used to compensate the grayscale value of each pixel in the display signal according to the second compensation list.

6. The timing control circuit according to claim 5, characterized in that, The second identification module includes a second partitioning unit and a second enabling unit; The second partitioning unit is electrically connected to the second detection module and the second enabling unit, respectively, and is used to compare the first blanking duration with the multiple time-duration partitions in ascending order according to a preset multiple time-duration partitions, and send the second enabling signal corresponding to the time-duration partition to the second enabling unit each time the first blanking duration is greater than the minimum length of a time-duration partition; wherein the durations of the vertical scan blanking regions corresponding to the multiple time-duration partitions do not overlap; The second enabling unit is also electrically connected to the compensation output module and is used to send the second compensation list corresponding to the second enabling signal to the compensation output module.

7. The timing control circuit according to claim 6, characterized in that, The second enabling unit includes a plurality of second controllers; The enable terminal of the second controller is electrically connected to the second partition unit, and the output terminal of the second controller is electrically connected to the compensation output module. The second controller is used to send the second compensation list input at the input terminal to the compensation output module through the output terminal when the second enable signal sent by the second partition unit is received at the enable terminal.

8. The timing control circuit according to claim 5, characterized in that, The compensation output module includes multiple second input terminals, and the multiple second input terminals are connected one-to-one with the output terminals of multiple second controllers; The compensation output module is used to receive at least one second compensation list through the plurality of second input terminals, and to determine the compensation coefficient corresponding to the grayscale value of each pixel in the display signal by looking up the table according to the last second compensation list received, and to determine the output grayscale value of each pixel in the display signal according to the compensation coefficient, so as to compensate the grayscale value of each pixel in the display signal.

9. A display device, characterized in that, The display device includes a display panel and a timing control circuit as described in any one of claims 1-8; The timing control circuit is electrically connected to the display panel and is used to output a compensated display signal to the display panel to drive the display panel to perform display.

10. A display driving method, characterized in that, The display driving method includes: Receive a display signal for a frame and determine the pixel clock frequency corresponding to the display signal; The target frequency partition corresponding to the pixel clock frequency is determined from a plurality of preset frequency partitions, and a corresponding first compensation list is determined based on the target frequency partition; wherein, the first compensation list includes the compensation relationship between the grayscale values ​​of pixels in adjacent pixel rows; The grayscale values ​​of pixels in at least one pixel row of the display signal are compensated according to the first compensation list, and the compensated display signal is output to the display panel to drive the display panel to display. One frequency partition corresponds to one first compensation list, and different frequency partitions correspond to different first compensation lists; The first compensation list includes two sets of preset grayscale values ​​and an adjusted grayscale value after compensation for the preset grayscale values. The compensation relationship is the correspondence between the preset grayscale values ​​and the adjusted grayscale values.

11. The display driving method according to claim 10, characterized in that, The step of compensating the grayscale values ​​of pixels in at least one pixel row of the display signal according to the first compensation list includes: For the grayscale value of the first pixel in the first pixel row of the display signal, determine the grayscale value of the second pixel in the second pixel row adjacent to the first pixel row; wherein the first pixel and the second pixel are connected to the same data line, and the first pixel receives the driving signal transmitted by the data line later than the second pixel; Based on the grayscale value of the first pixel and the grayscale value of the second pixel, the adjusted grayscale value of the first pixel after compensation is determined by looking up the first compensation list, so as to compensate the grayscale value of each first pixel in the first pixel row in the display signal; wherein, the at least one pixel row includes the first pixel row.

12. The display driving method according to claim 11, characterized in that, The step of determining the adjusted grayscale value of the first pixel after compensation by looking up a table based on the grayscale value of the first pixel and the grayscale value of the second pixel includes: A preset grayscale value that is the same as the grayscale value of the first pixel is determined according to the first set of grayscale values ​​in the first compensation list, and a preset grayscale value that is the same as the grayscale value of the second pixel is determined according to the second set of grayscale values ​​in the first compensation list. Based on the correspondence between the two preset grayscale values, the corresponding adjusted grayscale value is obtained from the first compensation list and used as the adjusted grayscale value of the first pixel after compensation. The first compensation list includes the first group of grayscale values, the second group of grayscale values, and multiple adjustable grayscale values ​​corresponding to multiple sets of correspondences; the first group of grayscale values ​​and the second group of grayscale values ​​each include multiple preset grayscale values; the multiple sets of correspondences include the correspondence between each preset grayscale value in the first group of grayscale values ​​and different preset grayscale values ​​in the second group of grayscale values.

13. The display driving method according to claim 10, characterized in that, Before the compensated display signal is output to the display panel, the display driving method further includes: Determine the first blanking duration corresponding to the display signal; wherein, the first blanking duration is the duration of the vertical scan blanking region corresponding to the display signal; Determine a second compensation list corresponding to the first blanking duration; wherein the second compensation list includes a plurality of preset grayscale values ​​and a compensation coefficient corresponding to each grayscale value; The grayscale values ​​of each pixel in the display signal are compensated according to the second compensation list.

14. The display driving method according to claim 13, characterized in that, The determination of the second compensation list corresponding to the first blanking duration includes: According to the preset multiple duration partitions in ascending order, the first blanking duration is compared with the multiple duration partitions in turn, and the second compensation list corresponding to the duration partition is triggered each time the first blanking duration is greater than the minimum length of a duration partition; wherein the durations of the vertical scan blanking regions corresponding to the multiple duration partitions do not overlap. The last triggered second compensation list is determined as the second compensation list corresponding to the first blanking duration.

15. The display driving method according to claim 13, characterized in that, The step of compensating the grayscale values ​​of each pixel in the display signal according to the second compensation list includes: For a target pixel with an adjustable grayscale value, the output grayscale value of the target pixel is determined based on the adjusted grayscale value and the compensation coefficient corresponding to the target pixel; wherein, the compensation coefficient corresponding to the target pixel is the compensation coefficient corresponding to the grayscale value of the target pixel before compensation; For pixels other than the target pixel, the output grayscale value of the other pixels is determined based on the original grayscale value of the other pixels and the corresponding compensation coefficient; Before the compensated display signal is output to the display panel, the display driving method further includes: The compensated display signal is obtained based on the output grayscale value of the target pixel and the output grayscale values ​​of the other pixels.

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