Diode preparation process based on wafer level packaging

Abstract

The invention relates to the technical field of packaged diodes, and in particular to a diode preparation process based on wafer-level packaging. The preparation process comprises: based on forming an initial bump on a target wafer, performing a formation quality inspection, determining whether to start a reflow soldering mode according to a deposition inspection result, and based on starting the reflow soldering mode, determining actual reflow parameters according to a deposition inspection result; heating the target wafer according to the actual reflow parameters to form a target bump; during the reflow heating process, real-time monitoring is performed on the target wafer, and time nodes of each stage of the reflow heating process are determined according to a reflow monitoring parameter set; based on the end of the reflow heating process, the target wafer is packaged and cut, and during the cutting process, electrical tests are performed on each diode wafer grain obtained, and diode wafer grains that fail the electrical test are marked to obtain electrical marking results, and actual abnormal causes are determined according to the electrical marking results.

Description

Technical Field

[0001] The invention relates to the technical field of packaged diodes, and in particular to a diode preparation process based on wafer-level packaging. Background Art

[0002] With the growing demand for miniaturization and high performance of electronic products, wafer-level packaging technology has become one of the key technologies for the preparation of semiconductor devices. The traditional wafer-level packaging diode preparation process has certain limitations in accuracy and efficiency, especially in the parameter control during the packaging process. Therefore, it is necessary to develop a new preparation process.

[0003] Chinese Patent Publication No.: CN111128982A discloses a fan-out type wafer-level light-emitting diode packaging method and structure thereof. The packaging method is used to package a plurality of light-emitting diode chips on a wafer protective film. The method mainly forms a packaging surface layer on the first electrodes of the light-emitting diode chips, and then forms a lead-out electrode electrically connected to the first electrode on the packaging surface layer. Then, the light-emitting diode chips are cut and sorted for testing, and the light-emitting diode chips are reassembled. The sides of the light-emitting diode chips are covered by a packaging layer, and then holes are drilled and filled with conductive materials on the packaging layer to form a plurality of common electrodes. Then, a plurality of common electrical circuits are printed, and each of the common electrical circuits is electrically connected to one of the common electrodes and a plurality of the lead-out electrodes. Finally, the circuit protection layer is covered to complete the process.

[0004] This shows that the packaging accuracy and quality cannot be guaranteed during the current diode packaging process. Summary of the invention

[0005] To this end, an object of the present invention is to provide a diode preparation process based on wafer-level packaging, so as to overcome the problem that packaging accuracy and packaging quality cannot be guaranteed in the current diode packaging process.

[0006] To achieve the above object, the present invention provides a diode preparation process based on wafer-level packaging, comprising:

[0007] A plurality of target diodes are arranged on the target wafer, and initial bumps are formed by deposition on pads corresponding to the target diodes;

[0008] Based on forming the initial bump on the target wafer, performing a formation quality inspection on the target wafer to obtain a deposition inspection result, determining whether to start a reflow mode according to the deposition inspection result, and based on starting the reflow mode, determining actual reflow parameters according to the deposition inspection result;

[0009] heating the target wafer according to the actual reflow parameters to melt and flow the initial bumps to form target bumps;

[0010] During the reflow heating process, the target wafer is monitored in real time to obtain a reflow monitoring parameter set, and the time nodes of each stage of the reflow heating process are determined according to the reflow monitoring parameter set;

[0011] Based on the completion of the reflow heating process, the target wafer is packaged and cut, and during the cutting process, each diode wafer grain obtained is electrically tested, and the diode wafer grains that fail the electrical test are marked to obtain an electrical marking result, and the actual cause of the abnormality is determined based on the electrical marking result.

[0012] Further, the process of depositing and forming initial bumps on pads corresponding to each target diode includes:

[0013] Clean the target wafer and determine the target solder;

[0014] depositing the target solder on the target wafer with initial deposition parameters;

[0015] The initial deposition parameters include: initial solder amount, initial deposition temperature and initial deposition time.

[0016] Further, the process of performing a formation quality inspection on the target wafer to obtain a deposition inspection result includes:

[0017] Based on the target wafer returning to room temperature after the initial bumps are deposited;

[0018] Performing image detection on the target wafer to obtain the number of depositions, the size of each single deposition, and the position of each deposition;

[0019] The detection result of a deposition includes: the number of depositions, the size of each single deposition and the position of each deposition.

[0020] Further, the process of determining whether to start the reflow mode according to the first deposition detection result includes:

[0021] Determine whether to start the reflow mode according to the one-time deposition quantity combined with the target quantity of target diodes on the target wafer;

[0022] Based on the matching of the one-time deposition quantity and the target quantity, determining to start the reflow mode;

[0023] Based on the mismatch between the one-time deposition quantity and the target quantity, it is determined to perform compensatory deposition.

[0024] Furthermore, the process of determining the actual reflow parameters based on the result of a deposition detection after the reflow mode is turned on includes:

[0025] Determining an actual reflow peak temperature according to the thermal characteristics of the target solder, and determining an initial reflow time according to the fluidity of the target solder and the thermal characteristics of the target wafer;

[0026] Based on the initial reflow time, the initial reflow time is corrected according to each single deposition size and each deposition position to obtain an actual reflow time;

[0027] Wherein, the actual reflow parameters include: the actual reflow peak temperature and the actual reflow time.

[0028] Furthermore, the process of correcting the initial reflow time according to each single deposition size and each deposition position to obtain the actual reflow time includes:

[0029] Determine the number of abnormal sizes in each primary deposition size and the number of abnormal positions in each primary deposition position;

[0030] The initial reflow time is corrected according to the number of the abnormal sizes and the number of the abnormal positions to obtain the actual reflow time.

[0031] Furthermore, the process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set includes:

[0032] Based on the reflow mode being turned on, preheating the target wafer at a preset initial heating temperature;

[0033] During the preheating process, the edge temperature and the center temperature of the target wafer are monitored in real time, an actual temperature gradient is calculated according to the edge temperature and the center temperature, and the initial heating temperature is adjusted in real time according to the actual temperature gradient;

[0034] When the actual temperature gradient is qualified and the average temperature of the target wafer reaches the preheating standard temperature, it is determined that the preheating stage is ended and the reflow stage is started;

[0035] Wherein, when the actual temperature gradient is less than or equal to a preset standard temperature gradient, the actual temperature gradient is determined to be qualified; and the average temperature is the average temperature of the edge temperature and the center temperature.

[0036] Furthermore, the process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set also includes:

[0037] Based on starting the reflow stage, reflow heating the target wafer at the actual reflow peak temperature;

[0038] During the reflow heating process, the average temperature of the target wafer is monitored in real time, and whether to end the reflow stage is determined based on a comparison result between the average temperature and the actual reflow peak temperature.

[0039] Furthermore, the process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set also includes:

[0040] Based on the end of the reflow stage, the cooling stage is started, and a target monitoring image of the target wafer is acquired. If the target monitoring image shows a solidified state, the cooling stage is ended.

[0041] Furthermore, the process of determining the actual abnormal cause according to the electrical marking result includes:

[0042] Based on the electrical marking result that abnormal diode grains are concentrated in the same area of ​​the target wafer, it is determined that the actual abnormal cause is a material defect of the target wafer;

[0043] Based on the electrical marking result that abnormal diode grains are dispersed in various areas of the target wafer, it is determined that the actual abnormal cause is a quality defect of the oxide layer of the target wafer;

[0044] Based on the electrical marking result that abnormal diode grains are distributed on a cutting path for cutting the target wafer, it is determined that the actual abnormal cause is a cutting speed defect.

[0045] Compared with the prior art, the beneficial effect of the present invention is that, by accurately controlling the heating parameters during the reflow soldering process, it is ensured that the solder can be fully melted and flowed, thereby forming a uniform and reliable solder joint, which is helpful to improve the electrical and mechanical connection quality of the diode wafer grains. By real-time monitoring and adjusting the temperature gradient during the reflow soldering process, it is possible to avoid uneven melting of the solder due to uneven temperature, reduce rework and scrap rates due to solder joint quality problems, and thus improve production efficiency. By preheating and slowly heating up, the thermal stress that may be generated by rapid heating of the wafer is reduced, and potential thermal damage to the wafer and the diode is avoided. By conducting electrical testing on the cut diode wafer grains and marking unqualified wafer grains, the good quality wafer grains can be accurately classified. The causes of precipitation defects, such as material defects, oxide layer quality defects or cutting speed defects, are identified, so that the production process can be improved in a targeted manner. This is achieved through automated equipment, which reduces manual intervention, improves the intelligence level of the production process, and reduces human errors. By detecting the formation quality of the initial bumps and adjusting the reflow parameters accordingly, the consistency of each solder joint can be ensured, thereby improving the overall performance and consistency of the final product. It can be adjusted according to different solder properties and wafer thermal properties, adapt to a variety of materials and process conditions, and has good flexibility. By reducing the scrap rate and improving production efficiency, through precise process control and quality inspection, not only the production quality and efficiency of wafer-level packaged diodes are improved, but also the production cost is reduced.

[0046] By cleaning the target wafer and selecting the appropriate target solder, good wetting between the solder and the pad can be ensured, thereby forming a stable and reliable solder joint, which helps to improve the electrical and mechanical connection quality of the diode wafer grains. By setting the initial deposition parameters, the deposition process of the solder can be accurately controlled to ensure that the size and position of the initial bumps formed on each pad meet the design requirements. By deciding whether to turn on the reflow mode after a quality inspection, it is possible to avoid wasting time and resources on unqualified solder joints, thereby optimizing the production process and improving production efficiency. By obtaining the number of depositions, the size of each single deposition, and the position of each deposition through image detection, defects in the deposition process, such as insufficient solder, position offset, etc., can be discovered in time, so that measures can be taken to compensate for the deposition and reduce the defect rate of the final product. Through automated image detection and analysis, manual intervention is reduced, the automation level of the production process is improved, and human errors are reduced. By accurately controlling the deposition process and timely detecting defects, raw material waste and rework costs are reduced, and cost-effectiveness is improved. By ensuring the deposition quality of each solder joint, the consistency of wafer-level packaged diodes is improved, which can effectively improve the production quality and efficiency of wafer-level packaged diodes while reducing production costs.

[0047] By precisely adjusting the reflow time of each solder joint, it is possible to ensure that the solder can fully melt and flow on each solder joint, thereby forming a uniform and reliable solder joint and improving the electrical and mechanical connection performance of the solder joint. By correcting the reflow time according to the actual deposition size and position, the reflow process can be optimized to avoid problems such as incomplete melting or overheating of the solder caused by improper reflow time. By identifying and counting solder joints with abnormal deposition size and position, the reflow time can be adjusted in a targeted manner to reduce solder joint defects caused by uneven solder deposition or position offset. Through automated image detection and reflow time adjustment, manual intervention and rework are reduced, the efficiency of the production line is improved, and it can adapt to different solder characteristics and wafer thermal characteristics, as well as The changes in different deposition sizes and positions have strong flexibility. By ensuring that the reflow time of each solder joint is properly adjusted, the consistency of all solder joints on the wafer is improved, thereby improving the packaging quality of the entire wafer. By reducing the defect rate and improving production efficiency, the production cost is reduced. The reflow time of each solder joint can be accurately controlled to ensure that the solder can fully flow and wet the pad after melting to form an ideal solder joint shape and size. During the reflow process, the reflow time can be dynamically adjusted according to the real-time monitoring of the solder flow and wetting conditions to adapt to the actual production conditions. The reflow time under different deposition sizes and positions can be verified by experiments, and a correction curve or model can be established to provide a scientific basis for the adjustment of the reflow time.

[0048] By real-time monitoring and adjustment of the edge and center temperatures of the wafer, the temperature uniformity of the wafer during the entire heating process can be ensured, reducing the impact of thermal stress on the wafer and solder joints. Uniform temperature distribution helps the solder to melt evenly, thereby improving the quality and reliability of the solder joints and reducing solder joint defects caused by uneven melting of the solder. Through the slow preheating process, the potential thermal damage to the wafer and diode caused by rapid heating can be avoided, protecting the performance of the device. The initial heating temperature can be adjusted in real time according to the actual temperature gradient to optimize the heating process and ensure that each solder joint can complete reflow soldering under the best conditions. By accurately controlling the time nodes of the preheating stage, the entire reflow soldering cycle can be shortened, the efficiency of the production line can be improved, and the reflow soldering process can be more finely controlled. The uniform control makes the production process more stable and predictable. The uniform heating and reflow process helps to improve the consistency of all solder joints on the wafer, thereby improving the overall quality of the product. By controlling the actual temperature gradient to be less than or equal to the preset standard temperature gradient, thermal stress can be minimized, wafer warping or device damage can be prevented, and the wafer can be ensured to reach the appropriate preheating standard temperature before entering the reflow stage, creating good conditions for the melting and flow of the solder. Using a non-contact infrared thermometer or thermal imager for real-time monitoring can quickly respond to temperature changes, adjust the heating strategy in time, and maintain the stability of the temperature gradient. By dynamically controlling the power output of the heating equipment or changing the heating strategy, it can adapt to the thermal characteristics of different wafers and solders and improve the flexibility of the process.

[0049] By heating the wafer at the actual reflow peak temperature, it is possible to ensure that the solder is fully melted and flows at the appropriate temperature, thereby forming high-quality solder joints. Real-time monitoring of the average temperature of the wafer and comparing it with the actual reflow peak temperature helps to accurately control the melting process of the solder to avoid overheating or insufficient melting. When the average temperature reaches or exceeds the actual reflow peak temperature, it indicates that the solder has melted and flowed to a sufficient extent. Ending the reflow stage at this time can prevent overheating and improve the reliability of the solder joints. By accurately controlling the end of the reflow stage, thermal damage caused by overheating can be reduced and sensitive electronic components on the wafer can be protected. In the cooling stage, image detection and analysis of the solidification state of the solder joint can ensure that the solder has cooled and solidified to form Stable solder joints. The high degree of automation of the entire reflow heating and cooling process reduces human intervention, improves production efficiency and consistency, monitors the average temperature of the wafer in real time, and adjusts the reflow time according to the monitoring results, provides instant feedback and adjustment, and enhances the flexibility of the process. Image detection technology is used to monitor the solidification state of the solder joints, providing intuitive evidence for the quality of the solder joints and facilitating quality control. By controlling the reflow peak temperature and monitoring the average temperature, uniform melting and flow of solder on the entire wafer are ensured, reducing solder joint defects caused by uneven temperature. By precisely controlling the reflow and cooling stages, the quality of the solder joints and the reliability of the package are ensured, the overall quality of the final product is improved, and the production quality and efficiency of wafer-level packaged diodes can be effectively improved.

[0050] Through electrical testing and analysis of the distribution of abnormal diode grains, it is possible to accurately identify whether it is a material defect, an oxide layer quality defect or a cutting speed defect, so that targeted measures can be taken. Rapidly locating the cause of the defect can reduce rework and troubleshooting time and improve the efficiency of the production line. By accurately judging and handling the cause of the defect, the product quality of wafer-level packaged diodes can be significantly improved. Timely detection of problems and taking measures can reduce the scrap rate caused by defects and reduce production costs. Through electrical testing of diode grains, early diagnosis of potential preparation defects can be achieved to avoid defect amplification in subsequent processes. The location and test results of each unqualified diode grain are recorded, providing valuable data support for subsequent analysis and processing, ensuring the performance and reliability of each diode grain, thereby ensuring the quality control of the final product, saving raw materials and human resources by reducing scrap and rework, and reducing overall production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a flow chart of a diode preparation process based on wafer-level packaging according to an embodiment of the present invention;

[0052] Figure 2This is a flow chart of determining to start the reflow soldering mode in a diode manufacturing process based on wafer-level packaging according to an embodiment of the present invention;

[0053] Figure 3 This is a flow chart of initial reflow time correction in a diode manufacturing process based on wafer-level packaging according to an embodiment of the present invention;

[0054] Figure 4 The present invention provides a flowchart for determining the time nodes at each stage in the diode preparation process based on wafer-level packaging according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0056] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0057] It should be noted that, in the description of the present invention, terms such as "up", "down", "left", "right", "inside" and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the drawings. This is merely for the convenience of description and does not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention.

[0058] See also Figure 1 As shown, it is a flow chart of a diode preparation process based on wafer-level packaging;

[0059] The present invention provides a diode preparation process based on wafer-level packaging, comprising:

[0060] Step S100, a plurality of target diodes are arranged on a target wafer, and initial bumps are formed by deposition on pads corresponding to the target diodes;

[0061] Step S200, based on forming the initial bump on the target wafer, performing a formation quality inspection on the target wafer to obtain a deposition inspection result, determining whether to turn on the reflow mode according to the deposition inspection result, and based on turning on the reflow mode, determining actual reflow parameters according to the deposition inspection result;

[0062] Step S300, heating the target wafer according to the actual reflow parameters to melt and flow the initial bumps to form target bumps;

[0063] Step S400, during the reflow heating process, real-time monitoring is performed on the target wafer to obtain a reflow monitoring parameter set, and time nodes of each stage of the reflow heating process are determined according to the reflow monitoring parameter set;

[0064] Step S500, based on the end of the reflow heating process, the target wafer is packaged and cut, and during the cutting process, each diode wafer grain obtained is electrically tested, and the diode wafer grains that fail the electrical test are marked to obtain an electrical marking result, and the actual abnormality cause is determined based on the electrical marking result.

[0065] In this embodiment, the target wafer is a wafer that has completed the front-end process, that is, before packaging, the wafer is oxidized so that an insulating silicon dioxide layer grows on the surface of the wafer, and then a photoresist is coated on the wafer. A circuit pattern is transferred to the wafer using a photolithography machine, and the exposed wafer portion is removed to form a circuit pattern. Dopants are injected into the wafer, insulating or conductive materials are deposited on the wafer, and metal is deposited to form an interconnection structure. Small grooves are cut on the wafer, but it is not completely cut off to obtain the target wafer.

[0066] Specifically, the embodiments of the present invention ensure that the solder can fully melt and flow, thereby forming uniform and reliable solder joints, by accurately controlling the heating parameters during the reflow soldering process, which helps to improve the electrical and mechanical connection quality of the diode wafer particles. By real-time monitoring and adjusting the temperature gradient during the reflow soldering process, uneven melting of the solder caused by uneven temperature can be avoided, and rework and scrap rates caused by solder joint quality problems can be reduced, thereby improving production efficiency. By preheating and slowly heating up, thermal stress that may be generated by rapid heating of the wafer is reduced, and potential thermal damage to the wafer and the diode is avoided. By conducting electrical tests on the cut diode wafer particles and marking unqualified wafer particles, defects can be accurately analyzed. The reasons for the defects, such as material defects, oxide layer quality defects or cutting speed defects, can be found, so as to improve the production process in a targeted manner. It can be achieved through automated equipment, which reduces manual intervention, improves the intelligence level of the production process, and reduces human errors. By detecting the formation quality of the initial bumps and adjusting the reflow parameters accordingly, the consistency of each solder joint can be ensured, thereby improving the overall performance and consistency of the final product. It can be adjusted according to different solder properties and wafer thermal characteristics, adapt to a variety of materials and process conditions, and has good flexibility. By reducing the scrap rate and improving production efficiency, through precise process control and quality inspection, it not only improves the production quality and efficiency of wafer-level packaged diodes, but also reduces production costs.

[0067] Specifically, in this embodiment, the process of depositing and forming initial bumps on the pads corresponding to each target diode includes:

[0068] Step S110, cleaning the target wafer and determining the target solder;

[0069] Step S120, depositing the target solder on the target wafer with initial deposition parameters;

[0070] The initial deposition parameters include: initial solder amount, initial deposition temperature and initial deposition time.

[0071] In the process of wafer-level packaging diodes, heat treatment is crucial to maintaining the stability of the package. The target wafer is cleaned before heat treatment to ensure that the surface of the target wafer is dust-free and pollution-free. In the specific implementation process, it is completed by ultrasonic cleaning and the use of chemical solvents. The cleaned target wafer is loaded onto the heat treatment equipment. In the specific implementation process, the heat treatment equipment can use a reflow oven or a hot plate. In wafer-level packaging, the wetting force refers to the interaction force between the solder and the diode pad after melting. This force determines whether the solder can wet the pad surface well. The composition of the solder has a great influence on the wetting force. Different solder alloys have different wetting characteristics. Therefore, choosing the right solder is the first step to ensure the deposition quality.

[0072] Specifically, in this embodiment, the process of performing a formation quality inspection on the target wafer to obtain a deposition inspection result includes:

[0073] Step S211, based on the target wafer being restored to room temperature after the initial bumps are deposited;

[0074] Step S212, performing image detection on the target wafer to obtain the number of depositions per time, the size of each single deposition, and the position of each deposition;

[0075] The detection result of a deposition includes: the number of depositions, the size of each single deposition and the position of each deposition.

[0076] In the specific implementation process, the initial bump refers to the solder joint, which is a small metal protrusion located on the diode pad, which is used to connect with other electronic components or circuit boards during the packaging process. The bump can be gold, silver or other conductive materials; the process of depositing solder to form the bump can be through evaporation, that is, under vacuum conditions, the solder material is heated to evaporate and then deposited on the diode pad, or through sputtering, that is, high-energy particles are used to hit the solder target material to sputter the material onto the diode pad, or through chemical vapor deposition (CVD), that is, the solder material is deposited on the pad through a chemical reaction, or through electroplating, that is, an electric current is applied to the pad to deposit solder ions on the pad to form a bump. This is not specifically limited in this embodiment and will not be repeated here.

[0077] See also Figure 2As shown, it is a flow chart of determining whether to start the reflow mode in the diode preparation process based on wafer-level packaging, wherein the process of determining whether to start the reflow mode according to the one-time deposition detection result includes:

[0078] Step S221, determining whether to start the reflow mode according to the one-time deposition quantity combined with the target quantity of target diodes on the target wafer;

[0079] Step S222, based on the matching of the one-time deposition quantity and the target quantity, determining to start the reflow mode;

[0080] Step S223 , based on the mismatch between the one-time deposition quantity and the target quantity, it is determined to perform compensation deposition.

[0081] Specifically, the embodiment of the present invention can ensure good wetting between the solder and the pad by cleaning the target wafer and selecting a suitable target solder, thereby forming a stable and reliable solder joint, which is helpful to improve the electrical and mechanical connection quality of the diode wafer grain. By setting the initial deposition parameters, the deposition process of the solder can be accurately controlled to ensure that the size and position of the initial bump formed on each pad meet the design requirements. By deciding whether to start the reflow mode after a quality inspection, it is possible to avoid wasting time and resources on unqualified solder joints, thereby optimizing the production process and improving production efficiency. By obtaining the number of depositions, the size of each single deposition, and the position of each deposition through image detection, defects in the deposition process, such as insufficient solder, position offset, etc., can be discovered in time, so that measures can be taken to compensate for the deposition and reduce the defect rate of the final product. Through automated image detection and analysis, manual intervention is reduced, the automation level of the production process is improved, and human errors are reduced. By accurately controlling the deposition process and timely detecting defects, the waste of raw materials and rework costs are reduced, and cost-effectiveness is improved. By ensuring the deposition quality of each solder joint, the consistency of the wafer-level packaged diode is improved, and the production quality and efficiency of the wafer-level packaged diode can be effectively improved, while reducing production costs.

[0082] Specifically, in this embodiment, the process of determining the actual reflow parameters based on the result of a deposition detection based on starting the reflow mode includes:

[0083] Step S231, determining an actual reflow peak temperature according to the thermal characteristics of the target solder, and determining an initial reflow time according to the fluidity of the target solder and the thermal characteristics of the target wafer;

[0084] Step S232, based on the initial reflow time, correct the initial reflow time according to each single deposition size and each deposition position to obtain an actual reflow time;

[0085] Wherein, the actual reflow parameters include: the actual reflow peak temperature and the actual reflow time.

[0086] In this embodiment, the thermal properties of the target solder refer to the behavioral properties of the solder in melting, flowing and solidifying during the heating process, including melting point, solidification point, thermal conductivity, specific heat capacity and thermal expansion coefficient. These properties determine the performance of the solder during the reflow process, such as melting rate, wettability and cooling rate. According to the thermal properties of the target solder, especially the melting point, the peak temperature during the reflow process can be determined to ensure that the solder can fully melt and flow, thereby forming a good solder joint. According to the thermal properties of the target solder, the material data sheet of the solder is consulted to determine its reflow peak temperature. In the specific implementation process, the reflow peak temperature The temperature will be set 20-30°C above the melting point of the solder to ensure that the solder is completely melted, but not too high to avoid damaging the wafer and diode. The fluidity of the target solder refers to the flow ability of the solder in a molten state, which affects the distribution of the solder on the pad and the formation of the solder joint. The thermal properties of the target wafer include thermal conductivity, thermal expansion coefficient, and specific heat capacity. These properties determine the thermal response of the wafer during heating and cooling. The fluidity of the solder and the thermal properties of the wafer jointly determine the time window in which the solder can be evenly distributed on the wafer after melting. The initial reflow time is the basic time required to ensure the solder flows and wets the pad;

[0087] The specific process of determining the initial reflow time includes: determining a preliminary reflow time through experiments or simulations based on the fluidity of the solder and the thermal characteristics of the wafer, and adjusting the reflow time according to the actual size and position of the deposition. For example, if the deposited solder is large or the position is offset, a longer reflow time may be required to ensure solder flow and wetting. Since different deposition sizes and positions may lead to differences in solder melting speed and flow behavior, the reflow time needs to be fine-tuned according to actual conditions to ensure that all solder joints can achieve the best soldering effect. In the specific implementation process, larger depositions may require longer reflow times to ensure complete melting. If the deposition position is offset, the reflow time may need to be adjusted to promote the flow of solder so that it covers the entire pad. The reflow time under different deposition sizes and positions is verified through experiments, and a correction curve or model is established. During the reflow process, visual monitoring or other sensors are used to detect the flow and wetting of the solder in real time, and the reflow time is dynamically adjusted to ensure the efficiency of the reflow process and the quality of the solder joints, thereby improving the reliability and production efficiency of the entire wafer-level packaging.

[0088] See also Figure 3 As shown, it is a flowchart of the initial reflow time correction in the diode preparation process based on wafer-level packaging, wherein the process of correcting the initial reflow time according to each single deposition size and each deposition position to obtain the actual reflow time includes:

[0089] Step S2321, determining the number of abnormal sizes in each primary deposition size and the number of abnormal positions in each primary deposition position;

[0090] Step S2322, correcting the initial reflow time according to the number of the abnormal sizes and the number of the abnormal positions to obtain the actual reflow time.

[0091] In this embodiment, a high-resolution camera or scanning device is used to perform image detection on the solder joints on the wafer, and the deposition size and position of each solder joint are analyzed by image processing software. According to the design specifications of the solder joints, a standard range of normal deposition size and position is pre-set, and this range is determined based on the electrical and mechanical connection performance that the solder joints should have. The actual deposition size and position of each solder joint are compared with the standard range, abnormal solder joints that exceed the range are identified, and the identified abnormal solder joints are counted, and the number of abnormal sizes and the number of abnormal positions are counted respectively. In the specific implementation process, the abnormal deposition size and position affect the melting and flow behavior of the solder, so it is necessary to adjust the reflow time to ensure that all solder joints can achieve the best welding effect, analyze the degree of influence of the abnormal size and position on the melting and flow of the solder, and adjust the initial reflow time to increase or decrease according to the severity of the influence. The influence of different adjustment schemes on the quality of the solder joints is verified by experiments, and the optimal reflow time is found. For example, for each additional solder joint of abnormal size, the reflow time is increased by X seconds; for each additional solder joint of abnormal position, the reflow time is increased by Y seconds.

[0092] Specifically, the embodiments of the present invention can ensure that the solder can fully melt and flow on each solder joint by accurately adjusting the reflow time of each solder joint, thereby forming a uniform and reliable solder joint, improving the electrical and mechanical connection performance of the solder joint, and correcting the reflow time according to the actual deposition size and position, so as to optimize the reflow soldering process and avoid the problem of incomplete melting or overheating of the solder caused by improper reflow time. By identifying and counting solder joints with abnormal deposition size and position, the reflow time can be adjusted in a targeted manner to reduce solder joint defects caused by uneven solder deposition or position offset. Through automated image detection and reflow time adjustment, manual intervention and rework are reduced, the efficiency of the production line is improved, and it can adapt to different solder characteristics and wafer thermal conductivity. Characteristics, as well as changes in different deposition sizes and positions, have strong flexibility. By ensuring that the reflow time of each solder joint is properly adjusted, the consistency of all solder joints on the wafer is improved, thereby improving the packaging quality of the entire wafer. By reducing the defect rate and improving production efficiency, the production cost is reduced. The reflow time of each solder joint can be accurately controlled to ensure that the solder can fully flow and wet the pad after melting to form an ideal solder joint shape and size. During the reflow process, the reflow time can be dynamically adjusted according to the real-time monitoring of the solder flow and wetting conditions to adapt to the actual production conditions. The reflow time under different deposition sizes and positions can be verified by experiments, and a correction curve or model can be established to provide a scientific basis for the adjustment of the reflow time.

[0093] See also Figure 4 As shown, it is a flow chart for determining the time nodes of each stage in the diode preparation process based on wafer-level packaging, wherein the process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set includes:

[0094] Step S410, based on the reflow mode being turned on, preheating the target wafer at a preset initial heating temperature;

[0095] Step S420, during the preheating process, monitoring the edge temperature and the center temperature of the target wafer in real time, calculating the actual temperature gradient according to the edge temperature and the center temperature, and adjusting the initial heating temperature in real time according to the actual temperature gradient;

[0096] Step S430, when the actual temperature gradient is qualified and the average temperature of the target wafer reaches the preheating standard temperature, it is determined that the preheating stage is ended and the reflow stage is started;

[0097] Wherein, when the actual temperature gradient is less than or equal to a preset standard temperature gradient, the actual temperature gradient is determined to be qualified; and the average temperature is the average temperature of the edge temperature and the center temperature.

[0098] In the specific implementation process, the preset initial heating temperature is generally set to about 50-100°C below the melting point of the solder to ensure that the wafer is heated slowly at the initial stage of heating to avoid thermal stress damage caused by rapid heating and to prepare for the melting of the solder. The setting of the initial heating temperature can ensure that the temperature is high enough to promote the flow of the solder, but not too high to avoid damaging the components;

[0099] In this embodiment, a non-contact infrared thermometer or thermal imager is used to monitor the edge and center areas of the wafer in real time. The actual temperature gradient = (edge ​​temperature - center temperature) / wafer radius. The actual temperature gradient is calculated to ensure that the overall temperature of the wafer is uniform, and thermal stress or uneven melting of solder caused by excessive temperature gradient is avoided. If the actual temperature gradient is greater than the preset standard temperature gradient, the heating rate is reduced or the distribution of the heating source is adjusted to reduce the temperature difference between the edge and the center. If the actual temperature gradient is less than the standard temperature gradient, the heating rate can be appropriately increased. In the specific implementation process, the temperature is adjusted by controlling the power output of the heating device or changing the heating strategy (such as changing the distribution of the heating area); the standard temperature gradient is used to measure the uniformity of the temperature distribution on the wafer, and the specific setting is affected by the soldering. The preheating standard temperature is used to measure whether the wafer has reached the initial temperature for reflow soldering. It is specifically set to about 50-100°C below the melting point of the solder to ensure that the solder does not melt prematurely before entering the reflow stage. The qualified actual temperature gradient indicates that the temperature distribution on the wafer is uniform, reducing the risk of thermal stress and uneven melting of the solder. The average temperature reaches the preheating standard temperature, indicating that the wafer is ready to enter the reflow stage and the solder is about to begin to melt, which can ensure that the preheating stage of the reflow process proceeds smoothly and create good conditions for the reflow stage, thereby improving the quality of the solder joints and the reliability of the package.

[0100] Specifically, the embodiments of the present invention can ensure the temperature uniformity of the wafer during the entire heating process by real-time monitoring and adjusting the edge temperature and center temperature of the wafer, reduce the impact of thermal stress on the wafer and solder joints, and the uniform temperature distribution helps the solder to melt evenly, thereby improving the quality and reliability of the solder joints and reducing solder joint defects caused by uneven melting of the solder. The slow preheating process can avoid potential thermal damage to the wafer and diode caused by rapid heating, thereby protecting the performance of the device. The initial heating temperature can be adjusted in real time according to the actual temperature gradient to optimize the heating process, ensuring that each solder joint can complete reflow soldering under optimal conditions. By accurately controlling the time nodes of the preheating stage, the entire reflow soldering cycle can be shortened, the efficiency of the production line can be improved, and the reflow More detailed control of the soldering process makes the production process more stable and predictable. Uniform heating and reflow processes help improve the consistency of all solder joints on the wafer, thereby improving the overall quality of the product. By controlling the actual temperature gradient to be less than or equal to the preset standard temperature gradient, thermal stress can be minimized, wafer warping or device damage can be prevented, and the wafer can be ensured to reach a suitable preheating standard temperature before entering the reflow stage, creating good conditions for the melting and flow of the solder. Using a non-contact infrared thermometer or thermal imager for real-time monitoring can quickly respond to temperature changes, adjust the heating strategy in time, and maintain the stability of the temperature gradient. By dynamically controlling the power output of the heating equipment or changing the heating strategy, it can adapt to the thermal characteristics of different wafers and solders and improve process flexibility.

[0101] Specifically, in this embodiment, the process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set also includes:

[0102] Step S440, based on starting the reflow phase, reflow heating the target wafer at the actual reflow peak temperature;

[0103] Step S450, during the reflow heating process, real-time monitoring of the average temperature of the target wafer, and determining whether to end the reflow stage according to a comparison result between the average temperature and the actual reflow peak temperature;

[0104] Step S460, based on the end of the reflow stage, starting the cooling stage, acquiring the target monitoring image of the target wafer, and ending the cooling stage if the target monitoring image shows a solidified state.

[0105] In this embodiment, the purpose of reflow soldering is to melt and flow the solder to fill the groove on the pad and wet its surface to form a reliable solder joint. The actual reflow peak temperature is determined based on the thermal characteristics of the target solder and the thermal characteristics of the wafer to ensure that the solder can fully melt and flow. Based on the determined actual reflow peak temperature, the target wafer is heated. The average temperature reflects the melting and flow state of the solder on the wafer. By comparing the average temperature with the actual reflow peak temperature, it can be determined whether the solder has melted and flowed to a sufficient degree. The average temperature of the wafer is monitored in real time and compared with the actual reflow peak temperature. When the average temperature reaches or exceeds the actual reflow peak temperature, it indicates that the solder has melted and flowed to a sufficient degree and the reflow stage can be ended.

[0106] During the cooling stage, a camera or scanning device is used to perform image inspection of the solder joints on the wafer, and image processing software is used to analyze the status of each solder joint, including whether it has solidified. The solidified state indicates that the solder has cooled and solidified to form a stable solder joint, ensuring that each stage of the reflow process is precisely controlled, thereby improving the quality of the solder joints and the reliability of the package.

[0107] Specifically, the embodiments of the present invention heat the wafer at the actual reflow peak temperature to ensure that the solder is fully melted and flows at an appropriate temperature, thereby forming a high-quality solder joint. Real-time monitoring of the average temperature of the wafer and comparison with the actual reflow peak temperature helps to accurately control the melting process of the solder to avoid overheating or insufficient melting. When the average temperature reaches or exceeds the actual reflow peak temperature, it indicates that the solder has melted and flowed to a sufficient extent. Ending the reflow stage at this time can prevent overheating and improve the reliability of the solder joint. By accurately controlling the end of the reflow stage, thermal damage caused by excessive heating can be reduced and sensitive electronic components on the wafer can be protected. In the cooling stage, the solidification state of the solder joint can be detected and analyzed by image to ensure that the solder has cooled. The high degree of automation of the entire reflow heating and cooling process reduces human intervention, improves production efficiency and consistency, monitors the average temperature of the wafer in real time, and adjusts the reflow time according to the monitoring results, provides instant feedback and adjustment, and enhances the flexibility of the process. Image detection technology is used to monitor the solidification state of the solder joint, which provides intuitive evidence for the quality of the solder joint and facilitates quality control. By controlling the reflow peak temperature and monitoring the average temperature, uniform melting and flow of solder on the entire wafer are ensured, reducing solder joint defects caused by uneven temperature. By precisely controlling the reflow and cooling stages, the quality of the solder joints and the reliability of the package are ensured, the overall quality of the final product is improved, and the production quality and efficiency of wafer-level packaged diodes can be effectively improved.

[0108] Specifically, in this embodiment, the process of determining the actual abnormal cause according to the electrical marking result includes:

[0109] Step S510, based on the electrical marking result that the abnormal diode grains are concentrated in the same area of ​​the target wafer, it is determined that the actual abnormal cause is a material defect of the target wafer;

[0110] Step S520, based on the electrical marking result that the abnormal diode grains are dispersed in various areas of the target wafer, it is determined that the actual abnormal cause is a quality defect of the oxide layer of the target wafer;

[0111] Step S530 , based on the electrical marking result that the abnormal diode grains are distributed on a cutting path for cutting the target wafer, it is determined that the actual abnormal cause is a cutting speed defect.

[0112] In this embodiment, electrical testing equipment, such as a multimeter or semiconductor testing equipment, is used to perform electrical testing on each diode wafer. The test includes measuring parameters such as the forward voltage, reverse voltage, forward current, and reverse current of the diode. Electrical testing is a key step in evaluating the performance and function of the diode, and can detect potential manufacturing defects. If the test result shows that a certain parameter exceeds the qualified range, it is judged to be unqualified in the electrical test. Each diode wafer that fails the test is marked, and its corresponding position and test results when it is not cut on the target wafer are recorded. Abnormal diode grains concentrated in the same area indicate that there are defects in the wafer material itself, such as uneven distribution of dopants, oxide layer defects, etc. , then the target wafer material needs to be inspected and processed to avoid affecting the quality of the entire wafer. Abnormal diode grains scattered in various areas indicate that there are quality problems with the oxide layer on the surface of the wafer, such as uneven thickness, contamination, etc. The oxide layer needs to be repaired or replaced to ensure the performance and reliability of the diode. Abnormal diode grains on the cutting path indicate that there are problems in the cutting process, such as uneven cutting speed, cutting equipment failure, etc. The cutting equipment and cutting process need to be inspected and adjusted to ensure the cutting quality. Electrical tests are performed on each diode wafer grain obtained, and the actual cause of the abnormality is determined based on the test results, so that corresponding measures can be taken to deal with it and ensure the quality and reliability of wafer-level packaging.

[0113] Specifically, the embodiment of the present invention can accurately identify whether it is a material defect, an oxide layer quality defect or a cutting speed defect through electrical testing and analysis of the distribution of abnormal diode grains, so as to take targeted measures. Rapidly locating the cause of the defect can reduce rework and troubleshooting time, improve the efficiency of the production line, and significantly improve the product quality of wafer-level packaged diodes by accurately judging and processing the cause of the defect. Timely detection of problems and taking measures can reduce the scrap rate caused by defects and reduce production costs. Through electrical testing of diode grains, early diagnosis of potential preparation defects can be achieved to avoid defect amplification in subsequent processes. The location and test results of each unqualified diode grain are recorded, providing valuable data support for subsequent analysis and processing, ensuring the performance and reliability of each diode grain, thereby ensuring the quality control of the final product, saving raw materials and human resources by reducing scrap and rework, and reducing overall production costs.

[0114] The calculation compensation parameters and the calculation adjustment parameters described in the present invention have two functions: one is to balance the left and right dimensions of the formula, and the other is to adjust the numerical results. No specific assignment is performed in this embodiment. In addition, the calculation formulas in this embodiment are used to intuitively reflect the adjustment relationship between the numerical values, such as positive correlation and negative correlation. Unless otherwise specified, the parameter values ​​that are not specifically limited to numerical values ​​are all positive.

[0115] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

[0116] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. Diode preparation process based on wafer-level packaging, including: A plurality of target diodes are arranged on the target wafer, and initial bumps are formed by deposition on pads corresponding to the target diodes; Based on forming the initial bump on the target wafer, performing a formation quality inspection on the target wafer to obtain a deposition inspection result, determining whether to start a reflow mode according to the deposition inspection result, and based on starting the reflow mode, determining actual reflow parameters according to the deposition inspection result; heating the target wafer according to the actual reflow parameters to melt and flow the initial bumps to form target bumps; During the reflow heating process, the target wafer is monitored in real time to obtain a reflow monitoring parameter set, and the time nodes of each stage of the reflow heating process are determined according to the reflow monitoring parameter set; Based on the completion of the reflow heating process, the target wafer is packaged and cut, and during the cutting process, each diode wafer grain obtained is electrically tested, and the diode wafer grains that fail the electrical test are marked to obtain an electrical marking result, and the actual cause of the abnormality is determined based on the electrical marking result.

2. The diode preparation process based on wafer level packaging according to claim 1, characterized in that: The process of depositing and forming initial bumps on pads corresponding to each target diode comprises: Clean the target wafer and determine the target solder; depositing the target solder on the target wafer with initial deposition parameters; The initial deposition parameters include: initial solder amount, initial deposition temperature and initial deposition time.

3. The diode preparation process based on wafer level packaging according to claim 2, characterized in that: The process of performing a formation quality inspection on the target wafer to obtain a deposition inspection result includes: Based on the target wafer returning to room temperature after the initial bumps are deposited; Performing image detection on the target wafer to obtain the number of depositions, the size of each single deposition, and the position of each deposition; The detection result of a deposition includes: the number of depositions, the size of each single deposition and the position of each deposition.

4. The diode preparation process based on wafer level packaging according to claim 3, characterized in that: The process of determining whether to start the reflow mode according to the first deposition detection result includes: Determine whether to start the reflow mode according to the one-time deposition quantity combined with the target quantity of target diodes on the target wafer; Based on the matching of the one-time deposition quantity and the target quantity, determining to start the reflow mode; Based on the mismatch between the one-time deposition quantity and the target quantity, it is determined to perform compensatory deposition.

5. The diode preparation process based on wafer level packaging according to claim 4, characterized in that: The process of determining the actual reflow parameters according to a deposition detection result based on starting the reflow mode includes: Determining an actual reflow peak temperature according to the thermal characteristics of the target solder, and determining an initial reflow time according to the fluidity of the target solder and the thermal characteristics of the target wafer; Based on the initial reflow time, the initial reflow time is corrected according to each single deposition size and each deposition position to obtain an actual reflow time; Wherein, the actual reflow parameters include: the actual reflow peak temperature and the actual reflow time.

6. The diode preparation process based on wafer level packaging according to claim 5, characterized in that: The process of correcting the initial reflow time according to each single deposition size and each deposition position to obtain the actual reflow time includes: Determine the number of abnormal sizes in each primary deposition size and the number of abnormal positions in each primary deposition position; The initial reflow time is corrected according to the number of the abnormal sizes and the number of the abnormal positions to obtain the actual reflow time.

7. The diode preparation process based on wafer level packaging according to claim 6, characterized in that: The process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set includes: Based on the reflow mode being turned on, preheating the target wafer at a preset initial heating temperature; During the preheating process, the edge temperature and the center temperature of the target wafer are monitored in real time, an actual temperature gradient is calculated according to the edge temperature and the center temperature, and the initial heating temperature is adjusted in real time according to the actual temperature gradient; When the actual temperature gradient is qualified and the average temperature of the target wafer reaches the preheating standard temperature, it is determined that the preheating stage is ended and the reflow stage is started; Wherein, when the actual temperature gradient is less than or equal to a preset standard temperature gradient, the actual temperature gradient is determined to be qualified; and the average temperature is the average temperature of the edge temperature and the center temperature.

8. The diode preparation process based on wafer level packaging according to claim 7, characterized in that: The process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set also includes: Based on starting the reflow stage, reflow heating the target wafer at the actual reflow peak temperature; During the reflow heating process, the average temperature of the target wafer is monitored in real time, and whether to end the reflow stage is determined based on a comparison result between the average temperature and the actual reflow peak temperature.

9. The diode preparation process based on wafer level packaging according to claim 8, characterized in that: The process of determining the time nodes of each stage of the reflow heating process according to the reflow monitoring parameter set also includes: Based on the end of the reflow stage, the cooling stage is started, and a target monitoring image of the target wafer is acquired. If the target monitoring image shows a solidified state, the cooling stage is ended.

10. The diode preparation process based on wafer level packaging according to claim 9, characterized in that: The process of determining the actual abnormal cause according to the electrical marking result includes: Based on the electrical marking result that abnormal diode grains are concentrated in the same area of ​​the target wafer, it is determined that the actual abnormal cause is a material defect of the target wafer; Based on the electrical marking result that abnormal diode grains are dispersed in various areas of the target wafer, it is determined that the actual abnormal cause is a quality defect of the oxide layer of the target wafer; Based on the electrical marking result that abnormal diode grains are distributed on a cutting path for cutting the target wafer, it is determined that the actual abnormal cause is a cutting speed defect.

Images