Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a substrate, the substrate comprising a plurality of semiconductor pillars extending along a thickness direction of the substrate; forming a bit line, the bit line extending along a first direction, located at a bottom surface of the semiconductor pillar and in contact with an initial first doped region; forming a word line, the word line extending along a second direction, the word line covering at least an initial channel region of the semiconductor pillar on two opposite sides in a direction perpendicular to the second direction; and forming a ground line, the ground line extending along the second direction, the ground line passing through the initial channel region of the semiconductor pillar, the ground line separating the semiconductor pillar into a first sub-semiconductor pillar and a second sub-semiconductor pillar, and the ground line separating the word line into a first sub-word line and a second sub-word line. The semiconductor structure and the manufacturing method thereof provided by the embodiment of the present disclosure are at least beneficial to improving the stability of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. One of the source and drain or the drain of the transistor is connected to a bit line structure, and the other of the source and drain or the drain is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. A word line structure of the memory cell can control the opening or closing of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line structure or writing data information into the capacitor through the bit line structure for storage. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least facilitate to improve the stability of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on one hand, a method for manufacturing a semiconductor structure is provided, comprising: providing a substrate, the substrate comprising a plurality of semiconductor pillars extending along a thickness direction of the substrate, the semiconductor pillars comprising an initial first doping region, an initial channel region, and an initial second doping region sequentially arranged along the thickness direction of the substrate; forming a bit line, the bit line extending along a first direction, being located on a bottom surface of the semiconductor pillar and contacting the initial first doping region, wherein the same bit line connects the plurality of semiconductor pillars along the first direction; forming a word line, the word line extending along a second direction, the word line covering at least two opposite side surfaces of the initial channel region of the semiconductor pillar along a direction perpendicular to the second direction, Along the second direction, the same word line connects multiple semiconductor pillars; a ground line is formed, which extends along the second direction and passes through the initial channel region of the semiconductor pillar. The ground line separates the semiconductor pillar into a first sub-semiconductor pillar and a second sub-semiconductor pillar. The first sub-semiconductor pillar and the second sub-semiconductor pillar both include a first doping region, a channel region and a second doping region arranged in sequence along the thickness direction of the substrate, and the ground line separates the word line into a first sub-word line and a second sub-word line. The first sub-word line at least covers a side surface of the channel region of the first sub-semiconductor pillar away from the ground line, and the second sub-word line at least covers a side surface of the channel region of the second sub-semiconductor pillar away from the ground line.

[0006] In some embodiments, a substrate is provided, including: providing an initial substrate; forming a first trench in the initial substrate, the first trench extending along a first direction; forming an insulating layer, the insulating layer filling the first trench; forming a second trench, the second trench extending along a second direction and located within the initial substrate and the insulating layer, the depth of the second trench in the initial substrate being less than the depth of the first trench in the initial substrate, the remaining initial substrate serving as a substrate, and the substrate located between the second trenches serving as a semiconductor pillar.

[0007] In some embodiments, forming a bit line includes: performing a doping process on the substrate at the bottom of the second trench to form a plurality of bit line doping regions, wherein the bottom surface of the bit line doping regions is higher than the bottom surface of the first trench; performing an annealing process to interconnect the plurality of bit line doping regions along the first direction to form bit lines, wherein the plurality of bit lines are arranged at intervals along the second direction; or, forming a metal layer, wherein the metal layer covers the surface of the substrate at the bottom of the second trench; performing an annealing process to form a plurality of metal silicide layers, wherein the bottom surface of the metal silicide layers is higher than the bottom surface of the first trench, wherein the plurality of metal silicide layers along the first direction are interconnected to form bit lines, wherein the plurality of bit lines are arranged at intervals along the second direction.

[0008] In some embodiments, before performing the annealing process, the method further includes performing a doping process on at least one of the initial first doping region, the initial channel region, or the initial second doping region of the semiconductor column.

[0009] In some embodiments, forming a word line includes: forming a first filling layer, the first filling layer filling the gap between the semiconductor pillars; patterning the first filling layer to expose the surface of the initial channel region and the initial second doping region of the semiconductor pillar; forming a gate dielectric layer, the gate dielectric layer at least covering the exposed surface of the initial channel region of the semiconductor pillar; forming a gate conductive layer, the gate conductive layer covering the surface of the gate dielectric layer away from the semiconductor pillar and filling the gap between the semiconductor pillars; patterning the gate conductive layer to form a third trench extending along the second direction, and the remaining gate conductive layer serves as the word line; forming a second filling layer, the second filling layer filling the gap between the word lines and the gap between the initial second doping regions of the semiconductor pillars.

[0010] In some embodiments, forming a ground line includes: forming a fourth trench, the fourth trench extending along the second direction, the fourth trench dividing the semiconductor pillar into a first sub-semiconductor pillar and a second sub-semiconductor pillar, and dividing the word line into a first sub-word line and a second sub-word line; laterally etching a portion of the fourth trench to remove a portion of the first sub-word line and the second sub-word line; forming an isolation layer, the isolation layer covering the surface of the first sub-word line and the second sub-word line exposed by the fourth trench; and filling the fourth trench to form a ground line.

[0011] In some embodiments, along the direction perpendicular to the second direction, a ratio of a width of the fourth trench to a width of the semiconductor pillar ranges from 1:2 to 1:5.

[0012] In some embodiments, a bottom surface of the fourth trench is lower than a top surface of the initial channel region and higher than a top surface of the initial first doping region.

[0013] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate, the substrate including multiple semiconductor pillars extending along the thickness direction of the substrate, the semiconductor pillars including adjacent first sub-semiconductor pillars and second sub-semiconductor pillars, the first sub-semiconductor pillars and the second sub-semiconductor pillars both including a first doping region, a channel region and a second doping region arranged in sequence along the thickness direction of the substrate; a bit line, the bit line extends along the first direction, is located on the bottom surface of the semiconductor pillar and contacts the first doping region, and along the first direction, the same bit line connects multiple semiconductor pillars; a word line, the word line extends along the second direction, the word line includes a first sub-word line and a second sub-word line, the first sub-word line at least covers a side surface of the channel region of the first sub-semiconductor pillar away from the second sub-semiconductor pillar, and the second sub-word line at least covers a side surface of the channel region of the second sub-semiconductor pillar away from the first sub-semiconductor pillar; a ground line, the ground line extends along the second direction, the ground line passes between the channel region of the first sub-semiconductor pillar and the channel region of the second sub-semiconductor pillar, and the first sub-word line and the second sub-word line are respectively located on both sides of the ground line.

[0014] In some embodiments, a top surface of the grounding line is not higher than a top surface of the channel region, and a bottom surface of the grounding line is not lower than a bottom surface of the channel region.

[0015] In some embodiments, along the first direction, a width of the ground line is smaller than a distance between adjacent semiconductor pillars.

[0016] In some embodiments, along the first direction, the width of the ground line ranges from 6 nm to 8 nm.

[0017] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0018] In the semiconductor structure and manufacturing method provided by the embodiments of the present disclosure, a substrate includes multiple semiconductor pillars extending along the thickness direction of the substrate. The formed bit lines extend along a first direction, and the same bit line connects the initial first doped regions of the multiple semiconductor pillars. Therefore, multiple transistor structures arranged along the first direction can share the same bit line, thereby improving the controllability of the bit lines. The formed word lines extend along a second direction, and the same word line connects the initial channel regions of the multiple semiconductor pillars. Therefore, multiple transistor structures arranged along the second direction can share the same word line, thereby improving the controllability of the word lines. In addition, a ground line passes through the initial channel region of the semiconductor pillar and separates the semiconductor pillar into a first sub-semiconductor pillar and a second sub-semiconductor pillar. The first sub-semiconductor pillar and the second sub-semiconductor pillar each include a first doped region, a channel region, and a second doped region arranged along the thickness direction of the substrate. The ground line also separates the word line into a first sub-word line and a second sub-word line. In this way, the first sub-semiconductor pillar and the second sub-semiconductor pillar can each constitute two transistor structures, and the ground line between the two transistor structures can be connected to the ground potential to avoid the first sub-semiconductor pillar and the second sub-semiconductor pillar from generating a floating body effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figures 1 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure to improve the stability of the semiconductor structure.

[0022] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0023] Figures 1 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figures 4 to 14 for Figure 1 Schematic diagram of the cross-section structure along the AA1 and BB1 directions, Figure 15 and Figure 16 for Figure 1 The cross-sectional structure diagram along the AA1 direction and the CC1 direction is shown. The manufacturing method of the semiconductor structure provided by this embodiment will be described in detail with reference to the accompanying drawings, as follows:

[0024] A method for manufacturing a semiconductor structure, comprising:

[0025] refer to Figure 1 , providing a substrate 100, the substrate 100 includes a plurality of semiconductor pillars 101 extending along the thickness direction of the substrate 100 (i.e., the third direction Z), and the semiconductor pillars 101 include an initial first doping region I, an initial channel region III and an initial second doping region II arranged in sequence along the thickness direction of the substrate 100.

[0026] The material of substrate 100 includes a semiconductor material, such as, but not limited to, silicon. In some embodiments, substrate 100 may include a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, a base semiconductor includes germanium; a compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and an alloy semiconductor includes silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide.

[0027] In some embodiments, the substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0028] The material of the semiconductor pillar 101 includes semiconductor materials, such as but not limited to silicon. In some embodiments, the material of the semiconductor pillar 101 may also include indium gallium zinc oxide, tungsten-doped indium oxide, or indium tin oxide.

[0029] In some embodiments, a substrate 100 is provided, comprising: Figure 2, providing an initial substrate 200; forming a plurality of first grooves 201 in the initial substrate 200, wherein the first grooves 201 extend along a first direction X. Figure 3 , forming an insulating layer 210, the insulating layer 210 completely filling the first trench 201; forming a plurality of second trenches 202, the second trenches 202 extending along the second direction Y and located within the initial substrate 200 and the insulating layer 210, the depth of the second trenches 202 within the initial substrate 200 being less than the depth of the first trenches 201 within the initial substrate 200. Figure 1 , the insulating layer 210 is removed, and the remaining initial substrate 200 serves as the substrate 100 , and the substrate 100 located between the second trenches 202 serves as the semiconductor pillars 101 . Thus, the material of the initial substrate 200 is the same as that of the semiconductor pillars 101 .

[0030] In some embodiments, a semiconductor layer may be formed on the initial substrate, and the semiconductor pillars may be formed by patterning the semiconductor layer.

[0031] The material of the initial substrate 200 includes a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the basic semiconductor includes germanium; the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or Group III-V semiconductor materials; and the alloy semiconductor includes silicon germanium, silicon germanium carbide, germanium-tin, silicon-germanium-tin, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide.

[0032] The material of the insulating layer 210 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0033] It should be noted that, in this embodiment, the angle between the first direction X and the second direction Y is 90°, which does not constitute a limitation on the angle between the first direction X and the second direction Y. In some embodiments, the angle between the first direction and the second direction may also be 30°, 45°, or 60°.

[0034] refer to Figure 4 , forming a bit line 102, the bit line 102 extends along the first direction X, the bit line 102 is located on the bottom surface of the semiconductor column 101 and contacts the initial first doped region I, along the first direction X, the same bit line 102 connects the initial first doped regions I of multiple semiconductor columns 101.

[0035] In some embodiments, forming the bit line 102 includes: referring to Figure 5 , a doping process is performed on the substrate 100 at the bottom of the second trench 202 to form a plurality of bit line doping regions 212 , wherein the bottom surface of the bit line doping region 212 is higher than the bottom surface of the first trench 201 . Figure 4An annealing process is then performed to interconnect the plurality of bitline doping regions 212 along the first direction X to form the bitlines 102. The plurality of bitlines 102 are then arranged at intervals along the second direction Y. Specifically, a high-concentration bitline doping region 212 is first formed at the bottom of the second trench 202 using a doping process. The bitline doping region 212 is then diffused in all directions by an annealing process, thereby interconnecting the plurality of bitline doping regions 212 along the first direction X to form the bitlines 102. Because the bottom surface of the bitline doping region 212 is higher than the bottom surface of the first trench 201, the bitline doping regions 212 can only be connected to each other through the substrate 100 at the bottom surface of the second trench 202. The bitlines 102 thus formed are arranged at intervals along the second direction Y.

[0036] In some embodiments, phosphorus ions, arsenic ions, antimony ions, boron ions, gallium ions, indium ions, etc. may be doped into the bit line doping region 212 .

[0037] In some embodiments, forming the bit line 102 includes: referring to Figure 6 , forming a metal layer 222, the metal layer 222 covers the surface of the substrate 100 at the bottom of the second trench 202. Figure 7 , an annealing process is performed to form a plurality of metal silicide layers 232. The bottom surfaces of the metal silicide layers 232 are higher than the bottom surfaces of the first trenches 201. The plurality of metal silicide layers 232 along the first direction X are interconnected to form the bit lines 102. The plurality of bit lines 102 are arranged at intervals along the second direction Y. In other words, after a deposition process is first used to form the metal layer 222 at the bottom of the second trenches 202, an annealing process is then performed to diffuse the metal ions within the metal layer 222 to the surrounding areas. The plurality of metal silicide layers 232 formed in the first direction X are interconnected to form the bit lines 102. Because the bottom surfaces of the metal silicide layers 232 are higher than the bottom surfaces of the first trenches 201, the metal silicide layers 232 can only be connected to each other through the substrate 100 at the bottom surfaces of the second trenches 202. The bit lines 102 formed in this manner are arranged at intervals along the second direction Y.

[0038] The material of the metal layer 222 includes a single metal, a metal compound, or an alloy. The single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum; the metal compound may be tungsten nitride, tantalum nitride, or titanium nitride; and the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0039] In some embodiments, before the annealing process, a doping process can also be performed on at least one of the initial first doped region I, the initial channel region III, or the initial second doped region II of the semiconductor pillar 101. In this way, the doping ions in the initial first doped region I, the initial channel region III, or the initial second doped region II can be activated by the subsequent annealing process in forming the bit line 102, and the annealing process can also repair the damage caused to the initial first doped region I, the initial channel region III, or the initial second doped region II during ion implantation.

[0040] In some embodiments, the ions doped into the initial first doped region I, the initial second doped region II, or the initial channel region III can include P-type or N-type doping ions. For example, P-type doping ions can include boron ions, indium ions, or gallium ions; and N-type doping ions can include phosphorus ions, arsenic ions, or antimony ions.

[0041] In some embodiments, referring to Figure 2 After the second trench 202 is formed, the insulating layer 210 can not be removed, and a doping process can be directly performed on the substrate 100 at the bottom of the second trench 202, or a metal layer 222 can be directly formed on the substrate 100 at the bottom of the second trench 202 to form the bit line 102. The insulating layer 210 can act as a protective layer for the substrate 100 at the bottom of the first trench 201, thereby avoiding contamination of the substrate 100 at the bottom of the first trench 201 during the process of forming the bit line 102.

[0042] Referring to Figure 8 The word line 103 is formed, which extends along the second direction Y, and the word line 103 covers at least two opposite sides of the initial channel region III of the semiconductor pillar 101 along a direction perpendicular to the second direction Y. Along the second direction Y, the same word line 103 connects multiple semiconductor pillars 101.

[0043] In some embodiments, the word line 103 can only cover two opposite sides of the initial channel region III of the semiconductor pillar 101 along a direction perpendicular to the second direction Y, so as to avoid leakage between the word line and a ground line formed through the initial channel region of the semiconductor pillar in the subsequent process.

[0044] In some embodiments, the word line 103 can also surround the surface of the initial channel region III of the semiconductor pillar 101 along the second direction Y to form a full-surrounding gate structure, so as to increase the contact area between the word line 103 and the initial channel region III, thereby improving the gate control capability.

[0045] In some embodiments, forming the word line 103 can include: referring to Figure 9, a first filling layer 301 is formed to fill the gaps between the semiconductor pillars 101; the first filling layer 301 is patterned to expose the surfaces of the initial channel regions III and the initial second doped regions II of the semiconductor pillars 101. Referring to Figure 10 , a gate dielectric layer 113 is formed to cover at least the surfaces of the initial channel regions III of the exposed semiconductor pillars 101; a gate conductive layer 123 is formed to cover the surfaces of the gate dielectric layer 113 away from the semiconductor pillars 101 and to fill the gaps between the semiconductor pillars 101. Referring to Figure 11 , the gate conductive layer 123 is patterned to form third trenches 203 extending along the second direction Y, and the remaining gate conductive layer 123 serves as word lines 103. Referring to Figure 8 , a second filling layer 302 is formed to fill the gaps between the word lines 103 and the gaps between the initial second doped regions II of the semiconductor pillars 101.

[0046] The material of the gate dielectric layer 113 can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material, or a combination thereof.

[0047] The material of the gate conductive layer 123 can include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0048] The material of the first filling layer 301 and the material of the second filling layer 302 can include silicon oxide, silicon nitride, or silicon oxynitride, etc. In some embodiments, the material of the first filling layer 301 and the material of the second filling layer 302 can also employ fluorinated polymers, low dielectric constant glass fibers, microporous mass polymers, fluorinated polyurethane, porous low dielectric constant fatty acid methyl ester, etc., such as silicon oxynitride compounds, silicon carbonitride compounds, silicon oxycarbide compounds, or silicon oxycarbonitride compounds, etc.

[0049] In some embodiments, forming the word lines 103 can include: referring to Figure 12 , a first filling layer 301 is formed to fill the gaps between the semiconductor pillars 101; the first filling layer 301 is patterned to form word line trenches 310 extending along the second direction Y, and the word line trenches 310 expose the initial channel regions III of the plurality of semiconductor pillars 101 along the second direction Y. Referring to Figure 13, forming a gate dielectric layer 113, the gate dielectric layer 113 covers the surface of the initial channel region III of the semiconductor pillar 101; forming a word line 103, the word line 103 covers the surface of the gate dielectric layer 113 away from the semiconductor pillar 101 and fills the word line groove 310; forming a second filling layer 302, the second filling layer 302 at least covers the top surface of the word line 103 and fills the gap between the initial second doping region II of the semiconductor pillar 101.

[0050] The material of the word line 103 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0051] refer to Figure 14 , forming a grounding line 104, the grounding line 104 extends along the second direction Y, the grounding line 104 passes through the initial channel region III of the semiconductor column 101, the grounding line 104 separates the semiconductor column 101 into a first sub-semiconductor column 111 and a second sub-semiconductor column 121, the first sub-semiconductor column 111 and the second sub-semiconductor column 121 include a first doped region 211, a channel region 231 and a second doped region 221 arranged in sequence along the thickness direction of the substrate 100, and the grounding line 104 separates the word line 103 into a first sub-word line 213 and a second sub-word line 223, the first sub-word line 213 at least covers a side surface of the channel region 231 of the first sub-semiconductor column 111 away from the grounding line 104, and the second sub-word line 223 at least covers a side surface of the channel region 231 of the second sub-semiconductor column 121 away from the grounding line 104. The grounding line 104 can ground the channel regions 231 of the first and second semiconductor sub-pillars 111 and 121 , thereby preventing the transistors formed by the first and second semiconductor sub-pillars 111 and 121 from generating a floating body effect, thereby improving the stability of the semiconductor structure.

[0052] In some embodiments, forming the ground line 104 includes: referring to Figure 15 , forming a fourth trench 204, the fourth trench 204 extending along the second direction Y, the fourth trench 204 dividing the semiconductor pillar 101 into a first sub-semiconductor pillar 111 and a second sub-semiconductor pillar 121, and dividing the word line 103 into a first sub-word line 213 and a second sub-word line 223; a portion of the fourth trench 204 is laterally etched to remove a portion of the first sub-word line 213 and the second sub-word line 223. Figure 16, forming an isolation layer 305 that covers the surfaces of the first sub-wordline 213 and the second sub-wordline 223 exposed by the fourth trench 204; forming a ground line 104 that partially fills the fourth trench 204; and forming a top-fill layer 304 that covers the top surface of the ground line 104 and completely fills the fourth trench 204. The isolation layer 305 insulates the first and second sub-wordlines 213 and 223 from the ground line 104, preventing leakage caused by a connection between the first and second sub-wordlines 213 and 223. Furthermore, the top-fill layer 304 insulates the ground line 104 from other structures, preventing leakage between the ground line 104 and other structures.

[0053] The materials of the isolation layer 305 and the top filling layer 304 include silicon oxide, silicon nitride or silicon oxynitride.

[0054] It should be noted that in Figure 15 and Figure 16 In the example, the bottom surface of the fourth trench 204 is flush with the top surface of the first doped region 211, which does not constitute a limitation on the depth of the fourth trench 204. In some embodiments, the bottom surface of the fourth trench 204 is lower than the top surface of the initial channel region III and higher than the top surface of the initial first doped region I. In other words, the fourth trench 204 at least separates the initial second doped region II of the semiconductor pillar 101 into the second doped region 221 of the first sub-semiconductor pillar 111 and the second doped region 221 of the second sub-semiconductor pillar 121, and separates at least part of the initial channel region III of the semiconductor pillar 101 into the channel region 231 of the first sub-semiconductor pillar 111 and the channel region 231 of the second sub-semiconductor pillar 121, which are independent of each other. In which, the fourth trench 204 may not separate the initial first doping region I of the semiconductor column 101, so that the transistor structure formed by the first sub-semiconductor column 111 and the second sub-semiconductor column 121 shares the same first doping region 211 as one of the source or drain of the transistor structure, and respectively uses their respective second doping regions 221 as the other of the source or drain of the transistor.

[0055] In some embodiments, the bottom surface of the fourth trench can be lower than the top surface of the initial first doped region. That is, the fourth trench can also divide at least part of the second doped region of the semiconductor pillar into two halves, thereby separating the semiconductor pillar into completely independent first and second sub-semiconductor pillars. In this way, filling the fourth trench includes: forming a bottom fill layer to fill a portion of the fourth trench, the top surface of the bottom fill layer not lower than the top surface of the first doped region; forming a ground line, the ground line covering the top surface of the bottom fill layer and filling a portion of the fourth trench; forming a top fill layer, the top fill layer covering the top surface of the ground line and completely filling the fourth trench.

[0056] In some embodiments, the ratio of the width of the fourth trench 204 to the width of the semiconductor pillar 101 along the direction perpendicular to the second direction Y is in the range of 1:2 to 1:5, such as 1:2, 1:2.3, 1:3, 1:3.6, 1:4, 1:4.5, or 1:5, etc. It can be understood that the fourth trench 204 needs to have a sufficient width to separate the semiconductor pillar 101 into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, but the width of the fourth trench 204 being too wide will result in the size of the remaining first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 being too small, which is not conducive to the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 forming a transistor structure. Therefore, the ratio of the width of the fourth trench 204 to the width of the semiconductor pillar 101 needs to be in an appropriate range.

[0057] In the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, the substrate 100 includes a plurality of semiconductor pillars 101 extending along the thickness direction of the substrate 100. The bit line 102 is formed to extend along the first direction X, and the same bit line 102 connects the initial first doped region I of the plurality of semiconductor pillars 101. Then, the plurality of transistor structures arranged along the first direction X are formed subsequently, and the plurality of transistor structures can share the same bit line 102, so as to improve the control ability of the bit line 102. The word line 103 is formed to extend along the second direction Y, and the same word line 103 connects the initial channel region III of the plurality of semiconductor pillars 101. Then, the plurality of transistor structures arranged along the second direction Y are formed subsequently, and the plurality of transistor structures can share the same word line 103, so as to improve the control ability of the word line 103. In addition, the ground line 104 is formed to pass through the initial channel region III of the semiconductor pillar 101, and the semiconductor pillar 101 is separated into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121. The first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 both include the first doped region 211, the channel region 231, and the second doped region 221 arranged along the thickness direction of the substrate 100. The ground line 104 also separates the word line 103 into the first sub-word line 213 and the second sub-word line 223. In this way, the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can form two transistor structures respectively, and the ground line 104 between the two transistor structures can be connected to the ground potential, so as to avoid the floating body effect of the transistor structures formed by the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121.

[0058] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a semiconductor structure, which can be formed by using the method for manufacturing the semiconductor structure provided by the above-mentioned embodiments, so as to improve the stability of the semiconductor structure. It should be noted that the same or corresponding parts of the above-mentioned embodiments can refer to the corresponding descriptions of the foregoing embodiments, which will not be described in detail below.

[0059] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0060] refer to Figure 14 The semiconductor structure includes: a substrate 100, the substrate 100 includes a plurality of semiconductor pillars 101 extending along the thickness direction of the substrate 100, the semiconductor pillar 101 includes a first sub-semiconductor pillar 111 and a second sub-semiconductor pillar 121 adjacent to each other along a first direction X, the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 each including a first doped region 211, a channel region 231 and a second doped region 221 sequentially arranged along the thickness direction of the substrate 100; a bit line 102, the bit line 102 extends along the first direction X, the bit line 102 is located on the bottom surface of the semiconductor pillar 101 and contacts the first doped region 211, and along the first direction X, the same bit line 102 connects the plurality of semiconductor pillars 101; a word line 103, The word line 103 extends along the second direction Y, and the word line 103 includes a first sub-word line 213 and a second sub-word line 223. The first sub-word line 213 at least covers the side surface of the channel region 231 of the first sub-semiconductor column 111 away from the second sub-semiconductor column 121, and the second sub-word line 223 at least covers the side surface of the channel region 231 of the second sub-semiconductor column 121 away from the first sub-semiconductor column 121; the ground line 104, the ground line 104 extends along the second direction Y, the ground line 104 passes between the channel region 231 of the first sub-semiconductor column 111 and the second sub-semiconductor column 121, and the first sub-word line 213 and the second sub-word line 223 are respectively located on both sides of the ground line 104 along the first direction X.

[0061] In some embodiments, the top surface of the grounding line 104 is no higher than the top surface of the channel region 231, and the bottom surface of the grounding line 104 is no lower than the bottom surface of the channel region 231. In other words, when the grounding line 104 is located in the region directly opposite the channel region 231 of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121, the floating body effect of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can be reduced.

[0062] exist Figure 14 In the third direction Z, taking the case where the width of the ground line 104 is equal to the width of the channel region 231 as an example, it does not constitute a ground line 104. In some embodiments, the width of the ground line 104 can be smaller than the width of the channel region 231.

[0063] In some embodiments, the width of the channel region 231 along the third direction Z may be 45 to 80 nm, for example, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, or 80 nm. It is understood that the width of the channel region 231 corresponds to the thickness of the word line 103 along the third direction Z.

[0064] In some embodiments, the semiconductor pillar 101 has a width along the first direction X that is greater than a width along the second direction Y. In this way, after the semiconductor pillar 101 is divided into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 by the ground line 104 along the second direction Y, the remaining first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can have a uniform size.

[0065] In some embodiments, along the first direction X, the ground line 104 has a width that is less than a spacing between adjacent semiconductor pillars 101. That is, after the semiconductor pillar 101 is divided into the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 by the ground line 104, the distance between the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 corresponding to the same semiconductor pillar 101 is less than the distance between the first sub-semiconductor pillar 111 and another second sub-semiconductor pillar 121. In this way, the arrangement of the first sub-semiconductor pillar 111 and the second sub-semiconductor pillar 121 can have a greater arrangement density than a square arrangement structure, and the increased density can also reduce the coupling effect between the word lines 103 corresponding to adjacent semiconductor pillars 101.

[0066] In some embodiments, along the first direction X, the ground line 104 has a width in a range of 6-8 nm, such as 6 nm, 6.5 nm, 7 nm, 7.5 nm, or 8 nm.

[0067] In some embodiments, the first sub-word line 213 also covers a portion of the surface of the channel region 231 of the first sub-semiconductor pillar 111 on two opposite sides along the first direction X; and the second sub-word line 223 also covers a portion of the surface of the channel region 231 of the second sub-semiconductor pillar 121 on two opposite sides along the first direction X. That is, the first sub-word line 213 and the first sub-semiconductor pillar 111 form a three-side gate-all-around structure, and the second sub-word line 223 and the second sub-semiconductor pillar 121 form a three-side gate-all-around structure, which can improve the gate control ability of the first sub-word line 213 and the second sub-word line 223.

[0068] The semiconductor structure provided by the embodiments of the present disclosure includes a substrate 100 and a plurality of semiconductor pillars 101 extending along the thickness direction of the substrate 100. A bit line 102 is formed to extend along a first direction X, and the same bit line 102 is connected to initial first doped regions I of the plurality of semiconductor pillars 101. Therefore, a plurality of transistor structures arranged along the first direction X can share the same bit line 102, so as to improve the control ability of the bit line 102. A word line 103 is formed to extend along a second direction Y, and the same word line 103 is connected to initial channel regions III of the plurality of semiconductor pillars 101. Therefore, a plurality of transistor structures arranged along the second direction Y can share the same word line 103, so as to improve the control ability of the word line 103. In addition, a ground line 104 passes through the initial channel regions III of the semiconductor pillars 101, and separates the semiconductor pillars 101 into first sub-semiconductor pillars 111 and second sub-semiconductor pillars 121. The first sub-semiconductor pillars 111 and the second sub-semiconductor pillars 121 each include a first doped region 211, a channel region 231 and a second doped region 221 arranged along the thickness direction of the substrate 100. The ground line 104 also separates the word line 103 into a first sub-word line 213 and a second sub-word line 223. Therefore, the first sub-semiconductor pillars 111 and the second sub-semiconductor pillars 121 can respectively constitute two transistor structures, and the ground line 104 between the two transistor structures can be connected to a ground potential, so as to avoid the first sub-semiconductor pillars 111 and the second sub-semiconductor pillars 121 from generating floating body effects.

[0069] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of semiconductor pillars extending along a thickness direction of the substrate, the semiconductor pillars comprising an initial first doping region, an initial channel region, and an initial second doping region sequentially arranged along the thickness direction of the substrate; forming a bit line, wherein the bit line extends along a first direction, is located on a bottom surface of the semiconductor pillar and contacts the initial first doped region, and the same bit line connects a plurality of the semiconductor pillars along the first direction; forming a word line, the word line extending along a second direction, the word line at least covering two opposite side surfaces of the initial channel region of the semiconductor pillar along a direction perpendicular to the second direction, and the same word line connecting a plurality of the semiconductor pillars along the second direction; A grounding line is formed, the grounding line extending along the second direction, the grounding line passing through the initial channel region of the semiconductor column, the grounding line separating the semiconductor column into a first sub-semiconductor column and a second sub-semiconductor column, the first sub-semiconductor column and the second sub-semiconductor column both comprising a first doping region, a channel region and a second doping region sequentially arranged along the thickness direction of the substrate, and the grounding line separating the word line into a first sub-word line and a second sub-word line, the first sub-word line at least covering a side surface of the channel region of the first sub-semiconductor column away from the grounding line, and the second sub-word line at least covering a side surface of the channel region of the second sub-semiconductor column away from the grounding line.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The providing of a substrate comprises: providing an initial substrate; forming a first groove in the initial substrate, wherein the first groove extends along the first direction; forming an insulating layer, wherein the insulating layer completely fills the first trench; A second trench is formed, extending along the second direction and located within the initial substrate and the insulating layer, wherein the depth of the second trench within the initial substrate is less than the depth of the first trench within the initial substrate, the remaining initial substrate serves as the substrate, and the substrate located between the second trenches serves as the semiconductor pillar.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: forming the bit line, comprising: performing a doping process on the substrate at the bottom of the second trench to form a plurality of bit line doping regions, wherein the bottom surfaces of the bit line doping regions are higher than the bottom surface of the first trench; performing an annealing process to interconnect the plurality of bit line doping regions along the first direction to form the bit lines, wherein the plurality of bit lines are arranged at intervals along the second direction; Alternatively, a metal layer is formed, which covers the surface of the substrate at the bottom of the second trench; an annealing process is performed to form a plurality of metal silicide layers, wherein the bottom surface of the metal silicide layer is higher than the bottom surface of the first trench, and the plurality of metal silicide layers along the first direction are interconnected to form the bit lines, and the plurality of bit lines are arranged at intervals along the second direction.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: Before performing the annealing process, the method further includes: A doping process is performed on at least one of the initial first doping region, the initial channel region, or the initial second doping region of the semiconductor column.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Forming the word line includes: forming a first filling layer, wherein the first filling layer fills the gaps between the semiconductor pillars; Patterning the first filling layer to expose surfaces of the initial channel region and the initial second doping region of the semiconductor pillar; forming a gate dielectric layer, wherein the gate dielectric layer at least covers the exposed surface of the initial channel region of the semiconductor pillar; forming a gate conductive layer, wherein the gate conductive layer covers a surface of the gate dielectric layer away from the semiconductor pillars and fills gaps between the semiconductor pillars; patterning the gate conductive layer to form a third trench extending along the second direction, with the remaining gate conductive layer serving as the word line; A second filling layer is formed, where the second filling layer fills the gaps between the word lines and the gaps between the initial second doping regions of the semiconductor pillars.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The forming of the ground line includes: forming a fourth trench extending along the second direction, wherein the fourth trench divides the semiconductor pillar into the first sub-semiconductor pillar and the second sub-semiconductor pillar, and divides the word line into the first sub-word line and the second sub-word line; Laterally etching a portion of the fourth trench to remove a portion of the first sub-word line and the second sub-word line; forming an isolation layer, wherein the isolation layer covers surfaces of the first sub-word line and the second sub-word line exposed by the fourth trench; The fourth trench is filled to form the ground line.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: In a direction perpendicular to the second direction, a ratio of a width of the fourth trench to a width of the semiconductor pillar ranges from 1:2 to 1:

5.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: A bottom surface of the fourth trench is lower than a top surface of the initial channel region and higher than a top surface of the initial first doping region.

9. A semiconductor structure, characterized in that include: A substrate, the substrate comprising a plurality of semiconductor pillars extending along a thickness direction of the substrate, the semiconductor pillars comprising adjacent first and second sub-semiconductor pillars, the first and second sub-semiconductor pillars each comprising a first doped region, a channel region, and a second doped region sequentially arranged along the thickness direction of the substrate; a bit line extending along a first direction, located on a bottom surface of the semiconductor pillar and in contact with the first doped region, wherein the same bit line connects a plurality of semiconductor pillars along the first direction; a word line extending along a second direction, the word line comprising a first sub-word line and a second sub-word line, the first sub-word line at least covering a side surface of the channel region of the first sub-semiconductor pillar away from the second sub-semiconductor pillar, and the second sub-word line at least covering a side surface of the channel region of the second sub-semiconductor pillar away from the first sub-semiconductor pillar; A grounding line extends along the second direction, passes between the channel region of the first sub-semiconductor column and the channel region of the second sub-semiconductor column, and the first sub-word line and the second sub-word line are respectively located on both sides of the grounding line.

10. The semiconductor structure according to claim 9, wherein: The top surface of the grounding line is not higher than the top surface of the channel region, and the bottom surface of the grounding line is not lower than the bottom surface of the channel region.

11. The semiconductor structure according to claim 9, wherein: Along the first direction, the width of the grounding line is smaller than the interval between adjacent semiconductor pillars.

12. The semiconductor structure according to claim 11, wherein: Along the first direction, the width of the ground line ranges from 6 nm to 8 nm.

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