Arbitration strategy verification method and system and related equipment

Abstract

The embodiment of the invention provides an arbitration strategy verification method and system and related equipment, and the method comprises the steps: obtaining a continuous memory access request transaction of a to-be-tested design carrying a request mark used for indicating a special arbitration strategy verification scene corresponding to a continuous memory access request, and recording the continuous memory access request transaction into an atomic transaction queue based on the request mark; the continuous memory access request at least comprises a floating point atomic request and a read request corresponding to the same address, and the read request is a 64B read request and / or a 128B read request; obtaining a request response transaction including response data of the to-be-tested design, wherein the response data is data in a cache before the floating point atomic request is executed; if the operation type of the request response transaction obtained through execution is floating point atomic operation, reference data of the continuous memory access request is obtained through calculation based on the continuous memory access request transaction recorded in the atomic transaction queue; and comparing whether the reference data is the same as the response data, if so, passing the arbitration strategy verification, thereby ensuring the data operation accuracy of the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an arbitration strategy verification method, system, and related equipment. Background Art

[0002] With the rapid development of artificial intelligence, people have higher and higher requirements for computer computing power. Among them, since the operation of floating-point atomic operations requires a long operation time, it is difficult to realize mutual function calls when the floating-point atomic requests and other requests corresponding to the same cache address are continuously executed in the cache. For example, the continuous execution of floating-point atomic requests and other requests corresponds to the same cache line. Since the floating-point atomic request execution takes a long time, when it is not completed, the adjacent request has been completed, making the data obtained by the adjacent request execution uncertain, resulting in data operation errors. Among them, the floating-point atomic requests and other requests corresponding to the same cache address that are continuously executed can be collectively referred to as continuous memory access requests.

[0003] Therefore, in order to avoid data calculation errors in the designed chip, continuous memory access requests can be handled by limiting the interval between two floating-point atomic operation requests to 2 clocks when executing in the cache, and other requests can be executed at any position before or after the floating-point atomic operation request.

[0004] However, this processing method will cause major changes to the arbitration pipeline of continuous memory access requests, so it is necessary to effectively verify the arbitration strategy of the continuous memory access requests in the chip design to ensure the accuracy of the chip's data operations. Summary of the invention

[0005] In view of this, the embodiments of the present application provide an arbitration strategy verification method, system and related devices to effectively verify the arbitration strategy of continuous memory access requests in chip design and ensure the accuracy of chip data operations.

[0006] In a first aspect, an embodiment of the present application provides an arbitration policy verification method, including:

[0007] Obtain a continuous memory access request transaction of the design to be tested, wherein the continuous memory access request transaction is generated according to a continuous memory access request, wherein the continuous memory access request at least includes a floating-point atomic request and a read request corresponding to the same address, wherein the read request is a 64B read request and / or a 128B read request; the continuous memory access request transaction carries a request tag, wherein the request tag is used to indicate a special arbitration strategy verification scenario corresponding to the continuous memory access request, and based on the request tag, the continuous memory access request transaction is recorded in an atomic transaction queue; wherein different atomic transaction queues have different request tags corresponding to them;

[0008] Obtaining a request response transaction of the design to be tested, wherein the request response transaction includes response data, and the response data is data in the cache before the floating-point atomic request is executed;

[0009] If the operation type of the request response transaction obtained by execution is a floating-point atomic operation, based on the continuous memory access request transaction recorded in the atomic transaction queue, the reference data of the corresponding continuous memory access request is calculated;

[0010] The reference data is compared with the response data to see if they are the same. If so, the arbitration strategy verification is passed.

[0011] Optionally, the request response transaction further includes a request response function, and the request response function includes an operation code indicating an operation type of executing a continuous memory access request;

[0012] After obtaining the request response transaction of the design to be tested, the method further includes:

[0013] Based on the operation code of the request response function, it is determined whether the operation executed to obtain the request response transaction is a floating-point atomic operation.

[0014] Optionally, if yes, the calculating and obtaining reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue includes:

[0015] Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue;

[0016] If so, a continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and reference data of the continuous memory access request is calculated.

[0017] Optionally, the continuous memory access request transaction at least includes a memory access address tag; the request response transaction also includes a response address tag and a response address corresponding to the response data;

[0018] The determining, based on the continuous memory access request transactions recorded in the atomic transaction queue, whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue comprises:

[0019] Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the response address tag is the same as the memory access address tag in the first continuous memory access request transaction recorded in the atomic transaction queue;

[0020] If so, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request;

[0021] If yes, determine whether the response address is the same as the lower 64B memory access address in the 128B request;

[0022] If so, the floating-point atomic operation address is the same as the lower 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0023] Optionally, the continuous memory access request transaction further includes a request flag and a memory access address;

[0024] The determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request is specifically, according to the request flag bit, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request;

[0025] The determining whether the response address is the same as the lower 64B memory access address in the 128B request is specifically, according to the memory access address, determining whether the response address is the same as the lower 64B memory access address in the 128B request.

[0026] Optionally, when determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, if the continuous memory access request corresponding to the first continuous memory access request transaction is a non-128B request, the floating-point atomic operation address is the same as the read request address in the first continuous memory access request transaction recorded in the atomic transaction queue;

[0027] When determining whether the response address is the same as the low address bit of the continuous memory access request, if the response address is different from the low 64B memory access address of the 128B request, then the floating-point atomic operation address is the same as the high 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0028] Optionally, if the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue, before obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating the reference data of the continuous memory access request, the method further includes:

[0029] According to the operation code, an operation type of the floating-point atomic operation is determined; wherein the operation type of the floating-point atomic operation includes an operation with a return and an operation without a return.

[0030] Optionally, if the operation type of the floating-point atomic operation is a return operation, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request includes:

[0031] A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and first reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return data function of the floating-point atomic operation.

[0032] Optionally, if the operation type of the floating-point atomic operation is a non-return operation, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request includes:

[0033] A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and second reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return response function of the floating-point atomic operation.

[0034] Optionally, after obtaining the reference data of the continuous memory access request by calculation, the method further includes:

[0035] The reference data is recorded into the corresponding atomic transaction queue.

[0036] Optionally, the special arbitration policy verification scenarios include the first scenario, the second scenario, the third scenario, the fourth scenario, and the fifth scenario:

[0037] The first scenario corresponds to floating point atomic requests and read requests sent continuously;

[0038] The second scenario corresponds to a floating-point atomic request and a read request that are sent continuously, wherein the floating-point atomic request and the read request are separated by a clock cycle;

[0039] The third scenario corresponds to a floating point atomic request and two read requests sent continuously;

[0040] The fourth scenario corresponds to a floating-point atomic request, an integer atomic request, and a read request that are sent continuously, wherein an address of the integer atomic request is different from an address of the floating-point atomic request and the read request;

[0041] The fifth scenario corresponds to floating point atomic requests, write requests and read requests that are sent continuously.

[0042] Optionally, recording the reference data into a corresponding atomic transaction queue includes:

[0043] If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, the first reference data is recorded in the corresponding atomic transaction queue;

[0044] If the special arbitration strategy verification scenario is the fifth scenario, an OR operation is performed on the response data and the second reference data to obtain third reference data; and the third reference data is recorded in the corresponding atomic transaction queue.

[0045] Optionally, comparing whether the reference data is the same as the response data includes:

[0046] If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, comparing whether the first reference data is the same as the response data;

[0047] If the special arbitration strategy verification scenario is the fifth scenario, the third reference data is compared with the response data to see whether they are the same.

[0048] Optionally, if not, the operation type of executing the request response transaction to obtain the request response transaction is a read operation;

[0049] The step of calculating reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue is specifically, based on the continuous memory access request transaction recorded in the atomic transaction queue, obtaining a read operation request corresponding to the response data, and calculating read reference data according to a calling function of the read operation request;

[0050] The comparing whether the reference data is the same as the response data is specifically comparing whether the read reference data is the same as the response data.

[0051] In a second aspect, an embodiment of the present application provides an arbitration strategy verification system, including: a design to be tested, a floating-point atomic operation verification component, and a data comparison module;

[0052] The design to be tested is used to execute a continuous memory access request, wherein the continuous memory access request corresponds to a special arbitration strategy verification scenario, the continuous memory access request at least includes a floating point atomic request and a read request, and the read request is a 64B read request and / or a 128B read request;

[0053] The floating-point atomic operation verification component is used to obtain a continuous memory access request of the design to be tested; generate a continuous memory access request transaction according to the continuous memory access request, wherein the continuous memory access request transaction carries a request tag, the request tag is calculated according to the continuous memory access request, and is used to indicate a special arbitration strategy verification scenario corresponding to the continuous memory access request; and obtain request response information of the design to be tested; generate a request response transaction according to the request response information, the request response transaction includes a request response function and response data; send the continuous memory access request transaction and the request response transaction to the data comparison module;

[0054] The data comparison module is used to obtain continuous memory access request transactions and request response transactions of the design to be tested, and perform arbitration strategy verification according to the continuous memory access request transactions and the request response transactions.

[0055] Optionally, after the data comparison module obtains the continuous memory access request transaction of the design to be tested, based on the request tag carried by the continuous memory access request transaction, the continuous memory access request transaction is recorded in an atomic transaction queue; wherein different atomic transaction queues correspond to different request tags;

[0056] The step of the data comparison module performing arbitration strategy verification according to the continuous memory access request transaction and the request response transaction includes:

[0057] If the operation type of the request response transaction obtained by execution is a floating-point atomic operation, based on the continuous memory access request transaction recorded in the atomic transaction queue, the reference data of the corresponding continuous memory access request is calculated;

[0058] The reference data is compared with the response data to see if they are the same. If so, the arbitration strategy verification is passed.

[0059] In a third aspect, an embodiment of the present application provides a verification platform, which includes the arbitration strategy verification system as described in the second aspect above.

[0060] In a fourth aspect, an embodiment of the present application provides a computing device, including a processor and a memory, wherein the hardware logic design of the memory is verified by the arbitration strategy verification method described in the first aspect above.

[0061] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising one or more computer executable instructions, which, when executed, implement the arbitration policy verification method as described in the first aspect above.

[0062] It can be seen that the embodiment of the present application records the continuous memory access request transaction carrying the request tag into the atomic transaction queue corresponding to the request tag. When the operation type of the request response transaction is a floating-point atomic operation, the reference data of the continuous memory access request is calculated based on the continuous memory access request transaction recorded in the atomic transaction queue, and then the reference data is compared with the response data to see if they are the same. When the two are the same, the arbitration strategy verification is passed, thereby achieving effective verification of the arbitration strategy of the continuously executed memory access request and ensuring the data calculation accuracy of the chip. Moreover, in the special arbitration strategy verification scenario where the request tag indicates the continuous memory access request, the arbitration mechanism of the continuous memory access request is reflected through the request tag, ensuring the arbitration strategy verification in the special arbitration strategy verification scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0064] Figure 1 is an optional structural diagram of the arbitration strategy verification system provided in an embodiment of the present application;

[0065] Figure 2 It is an optional flow chart of the arbitration strategy verification method provided in the embodiment of the present application;

[0066] Figure 3 This is another optional flow chart of the arbitration strategy verification method provided in the embodiment of the present application;

[0067] Figure 4 It is an optional flow chart of step S41 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] Since the cache has a processing method that only limits the interval between two floating-point atomic operation requests to 2 clocks when executing continuous memory access requests, and other requests can be executed at any position before or after the floating-point atomic operation request, the arbitration pipeline corresponding to the continuous memory access requests of the same cache address is greatly changed. Therefore, it is necessary to effectively verify the arbitration strategy of the continuous memory access requests corresponding to the same cache address to ensure the data calculation accuracy of the chip. Among them, the continuous memory access requests corresponding to the same cache address can include continuously executed floating-point atomic requests (fpatomic) and other requests (for example: read request read, write request write, integer atomic request intatomic).

[0069] In view of this, the embodiment of the present application provides an improved arbitration strategy verification scheme, by recording the continuous memory access request transaction carrying the request tag into the atomic transaction queue corresponding to the request tag, when the operation type of the request response transaction is a floating-point atomic operation, the reference data of the continuous memory access request is calculated based on the continuous memory access request transaction recorded in the atomic transaction queue, and then the reference data is compared with the response data to see if they are the same, so that when the two are the same, the arbitration strategy verification is passed, thereby achieving effective verification of the arbitration strategy of the continuously executed memory access request and ensuring the data calculation accuracy of the chip. Moreover, in the special arbitration strategy verification scenario where the request tag indicates the corresponding continuous memory access request, the arbitration mechanism of the continuous memory access request is reflected through the request tag, ensuring the arbitration strategy verification in the special arbitration strategy verification scenario.

[0070] Based on the above-mentioned inventive concept, the embodiments of the present application provide an arbitration strategy verification method, system and related equipment. The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0071] Adopting verification methodology is one of the trends of chip verification, and Universal Verification Methodology (UVM) is a typical representative. UVM is a universal verification methodology based on SystemVerilog class. Its Universal Verification Component (UVC) can be used to build a functional verification environment. Among them, the Universal Verification Component (UVC) is an important component of the universal verification platform, which can be used to verify the relevant functions of the design under test. It can include designing a universal verification component (design uvc) to realize the data processing of the design under test (DUT); wherein, the design under test can be a chip that executes continuous memory access requests, for example, including a router, an arbitration module, a cache, and a system memory model (Sysmem).

[0072] The embodiment of the present application is to realize the arbitration strategy verification of the continuous access request containing at least floating-point atomic request and read request, and a floating-point atomic operation verification component (fpatomic_uvc) is provided for the floating-point atomic request, which may include an interface component (interface) used to connect with the design to be tested to obtain the relevant information of the continuous access request executed in the design to be tested; a monitor component (Monitor) used to collect the interface information of the design to be tested, the monitor may include a calculation unit (calculate), to perform corresponding calculations according to the interface information of the design to be tested, such as calculation flag information, etc.; a transaction component (transaction) used to store the interface information collected by the monitor; an agent component (agent) used to instantiate uvc, and connect the monitor and other components to ensure that the collected data is connected through the interface component and sent to other components for subsequent processing. Moreover, the floating-point atomic operation verification component (fpatomic_uvc) can exchange information with the data comparison module (scoreboard) through the interface component, wherein the data comparison module may include a reference storage model (Refmem) and a comparison model (compare) for storing corresponding data to verify the arbitration strategy of the continuous access request.

[0073] As an optional implementation, Figure 1 An exemplary schematic diagram of an optional structure of the arbitration strategy verification system of an embodiment of the present application is shown. Figure 1 As shown, the arbitration strategy verification system may include: a design to be tested, a floating-point atomic operation verification component, and a data comparison module.

[0074] The design to be tested is used to execute continuous memory access requests. Specifically, the continuous memory access requests can be executed based on the execution module in the cache. In a multi-level cache structure, the cache can be, for example, an L2 cache.

[0075] The router in the design to be tested may be one or more. In the case of multiple routers, the multiple routers may continuously send memory access requests to the arbitration module, which arbitrates the processing of the continuous memory access requests and sends them to the L2 cache and the system storage model for execution. The system storage module is, for example, a memory. In an optional example, the memory access request sent by the L2 cache to the system storage model may be implemented by a bus functional model (BFM).

[0076] Among them, the continuous memory access request may correspond to a special arbitration strategy verification scenario. Based on the long processing time of floating-point atomic operations, the special arbitration strategy verification scenario refers to a scenario in which a continuous memory access request containing a floating-point atomic request is verified by executing a policy arbitration. The continuous memory access request may at least include a floating-point atomic request (Floatpoint Atomic, fpatomic) and a read request (read) corresponding to the same address. Moreover, for the performance optimization considerations of the design to be tested, the read request may be a 64B read request and / or a 128B read request. Specifically, the continuous memory access request may include the following situations:

[0077] Case 1: The continuous memory access requests include: fpatomic+read, that is, the fpatomic request is sent in the first clock (cycle), and the read request is sent in the next cycle, and the access address of the two requests is the same; or, fpatomic+read_high64B, that is, the fpatomic request is sent in the first cycle, and the read request is sent in the next cycle, and the address of the fpatomic request is the same as the high 64B address of the read 128B request; or, fpatomic+read_low64B, that is, the fpatomic request is sent in the first clock (cycle), and the read request is sent in the next cycle, and the address of the fpatomic request is the same as the low 64B address of the read128B request.

[0078] It is understandable that each address is usually composed of 64 bits. If the amount of data in a read request is larger than a single memory block (such as 128 bytes), the operating system or application may break it down into smaller read units to facilitate the efficient processing capabilities of the underlying hardware. Therefore, for a read request with a byte count of 128B, it will be divided into two parts, namely the low64B (low 64-bit byte) address and the high64B (high 64-bit byte) address.

[0079] Case 2: The continuous memory access requests include: fpatomic+misc+read, that is, the fpatomic request and the read request are sent continuously with a cycle interval, and the access address of the two requests is the same; or, fpatomic+misc+read_high64B, that is, the fpatomic request and the read request are sent continuously with a cycle interval, and the address of the fpatomic request is the same as the high 64B address of the read 128B request; or, fpatomic+misc+read_low64B, that is, the fpatomic request and the read request are sent continuously with a cycle interval, and the address of the fpatomic request is the same as the low 64B address of the read 128B request.

[0080] Case three, the continuous memory access requests include: fpatomic+read0+read1, that is, the fpatomic request, read0 request and read1 request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the read1 request address; or, fpatomic+read0+read1_high64B, that is, the fpatomic request, read0 request and read1 request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the high 64B address of the read1 128B request; or, fpatomic+read0+read1_low64B, that is, the fpatomic request, read0 request and read1 request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the low 64B address of the read1 128B request.

[0081] Case 4: The continuous memory access requests include: fpatomic+write+read, that is, the fpatomic request, write request (write request) and read request are sent for three consecutive cycles, and the address of the fpatomic request, the address of the write request are the same as the address of the read request; or, fpatomic+write+read_high64B, that is, the fpatomic request, write request and read request are sent for three consecutive cycles, and the address of the fpatomic request, the address of the write request are the same as the high 64B address of the read 128B request; or, fpatomic+write+read_low64B, that is, the fpatomic request, write request and read request are sent for three consecutive cycles, and the address of the fpatomic request, the address of the write request are the same as the low 64B address of the read 128B request.

[0082] Case 5: The continuous memory access requests include: fpatomic+intatomic+read, that is, the fpatomic request, the intatomic request (integer atomic request) and the read request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the address of the read request, which is different from the address of the intatomic request; or, fpatomic+intatomic+read_high64B, that is, the fpatomic request, the intatomic request and the read request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the high 64B address of the read128B request, which is different from the address of the intatomic request; or, fpatomic+intatomic+read_low64B, that is, the fpatomic request, the intatomic request and the read request are sent for three consecutive cycles, and the address of the fpatomic request is the same as the low 64B address of the read 128B request, which is different from the address of the intatomic request.

[0083] The floating-point atomic operation verification component is used to obtain the continuous memory access request of the design to be tested, which can be specifically obtained through an interface. Then, a continuous memory access request transaction is generated according to the continuous memory access request through a transaction, wherein the continuous memory access request transaction carries a request tag, and the request tag is calculated by a calculation unit according to the continuous memory access request.

[0084] Wherein, the request tag can be used to indicate the special arbitration strategy verification scenario corresponding to the continuous memory access request. Corresponding to the above-mentioned continuous memory access request, the request tag can be fpatomic_read, fpatomic_misc_read, fpatomic_rd_rd, fpatomic_wr_rd and fpatomic_inatomic_rd. As an optional implementation, the request tag can be obtained by the computing unit through combinatorial logic calculation of the content information of the continuous memory access request. Wherein, the content information of the continuous memory access request may include relevant signals corresponding to the memory access request, such as the address tag Tag of the cached data corresponding to the memory access request, the operation code Op indicating the operation type of the memory access request, the flag Valid indicating that the memory access request is valid, the cache address Cacheline of the cached data corresponding to the memory access request, and other signals. The computing unit performs combinatorial logic calculations based on the content information of the continuous memory access request, for example:

[0085] fpatomic_read=(d1_valid&fpatomic)&(d2_valid&read)&(d1_caheline==d2_cacheline)&(d1_tag!=d2_tag);

[0086] Among them, d1_valid means that the request of the first cycle is valid, (d1_valid&read) means that the first cycle sends an fpatomic request, and (d2_valid&read) means the read request sent by the next cycle;

[0087] (d1_cacheline==d2_cacheline) indicates that two consecutive requests correspond to the same address, and (d1_tag!=d2_tag) indicates that the tags of the two requests are inconsistent.

[0088] Another example:

[0089] fpatomic+read_high64B=(d1_valid&fpatomic)&(d2_valid&read)&(d1_caheline==d2_cache line1)&(d1_tag!=d2_tag)&d2_128B;

[0090] Among them, (d1_valid&fpatomic) means that the first cycle sends an fpatomic request, ((d2_valid&read) means that the next cycle sends a read request; d1_caheline==d2_cacheline1 means that the cacheline of the fpatomic request is the same as the cacheline1 of the read request, (d1_tag!=d2_tag) means that the tags of the two requests are inconsistent; d2_128B means that the read is a 128B request.

[0091] fpatomic+read_low64B=(d1_valid&fpatomic)&(d2_valid&read)&(d1_caheline==d2_cachel ine2)&(d1_tag!=d2_tag)&d2_128B;

[0092] Among them, (d1_valid&fpatomic) means that the first cycle sends an fpatomic request, ((d2_valid&read) means that the next cycle sends a read request; d1_caheline==d2_cacheline1 means that the cacheline of the fpatomic request is the same as the cacheline2 of the read request, (d1_tag!=d2_tag) means that the tags of the two requests are inconsistent; d2_128B means that the read is a 128B request.

[0093] In response to the cache of the design to be tested responding to the continuous memory access request, the floating-point atomic operation verification component can also obtain the request response information of the design to be tested, and generate a request response transaction according to the request response information. Furthermore, the floating-point atomic operation verification component sends the continuous memory access request transaction carrying the request tag and the request response transaction to the data comparison module.

[0094] The request response transaction generated by the floating-point atomic operation verification component may include a request response function and response data, wherein the request response function is a response of the design under test to the continuous memory access request, and the operation code of the operation type of the current request can be determined by the request response function. The response data may be data determined by the execution of the corresponding continuous memory access request in the cache.

[0095] It should be noted that, corresponding to the above-mentioned continuous memory access request, after the continuous memory access request is arbitrated by the arbitration module, it will continuously enter the execution module for data processing. Since the calculation of the fpatomic operation corresponding to the fpatomic request requires 2 clock cycles before the calculation result can be written into the corresponding cache line, and the read operation corresponding to the read request only requires one clock cycle to be executed, when the fpatomic operation is executing the calculation, the data read by the read operation from the same cache line is uncertain, which will cause the data comparison module to have a data comparison error when comparing the response data of the design under test with the reference data obtained. To avoid the occurrence of data comparison errors, the response data of the design under test in the embodiment of the present application can be the data in the cache before the floating-point atomic request is executed, that is, corresponding to the above-mentioned situations one to four, the response data is the data stored in the cacheline before the fpatomic operation returned by the read operation; corresponding to the above-mentioned situation five, the response data is the data written to the cacheline by the write operation returned by the read operation.

[0096] The data comparison module is used to obtain the continuous memory access request transaction of the design to be tested and the request response transaction of the design to be tested, and perform arbitration strategy verification according to the continuous memory access request transaction and the request response transaction. Wherein, based on the acquisition of the continuous memory access request transaction and the request response transaction by the data comparison module, the data comparison module may include a corresponding atomic transaction queue to record the transaction. Based on the continuous memory access request transaction carrying a request tag generated by the floating-point atomic operation verification component, after obtaining the continuous memory access request transaction, the data comparison module may record the continuous memory access request transaction into the atomic transaction queue based on the request tag carried by the continuous memory access request transaction. Wherein, different atomic transaction queues correspond to different request tags.

[0097] It should be noted that, in the data comparison module, there is no timing restriction on the processing of continuous memory access requests, and the requests can be executed sequentially in the order in which they are sent.

[0098] As an optional implementation, Figure 2 The optional flow chart of the arbitration strategy verification method in the embodiment of the present application is exemplarily shown. The flow can be implemented based on the arbitration strategy verification system mentioned above, and can be implemented by the data comparison module. Figure 2 As shown, the process may include the following steps:

[0099] Step S10, obtaining continuous memory access request transactions of the design to be tested, and recording the continuous memory access request transactions into an atomic transaction queue based on a request tag.

[0100] Wherein, the continuous memory access request transaction is generated by the floating-point atomic operation verification component according to the continuous memory access request of the design to be tested, and the continuous memory access request at least includes a floating-point atomic request and a read request corresponding to the same address, and the read request is a 64B read request and / or a 128B read request. In addition, the continuous memory access request transaction carries a request tag, which is calculated by the floating-point atomic operation verification component according to the continuous memory access request of the design to be tested, and is used to indicate the special arbitration strategy verification scenario corresponding to the continuous memory access request.

[0101] Moreover, in order to record the acquired continuous memory access request transactions, an atomic transaction queue may be provided in the data comparison module. Thus, after acquiring the continuous memory access request transaction, the data comparison module may record the continuous memory access request transaction into the atomic transaction queue based on the request tag carried by the continuous memory access request transaction. Among them, the request tags corresponding to different atomic transaction queues may be different. Taking the above-mentioned several cases of continuous memory access requests as examples: for fpatomic_rd, the transaction is stored in queue0; for fpatomic_misc_rd, the transaction is stored in queue1; for fpatomic_rd_rd, the transaction is stored in queue2; for fpatomic_wr_rd, the transaction is stored in queue3; for fpatomic_intatomic_rd, the transaction is stored in queue4.

[0102] Step S20, obtaining the request response transaction of the design to be tested.

[0103] The request response transaction is generated by the floating point atomic operation verification component according to the acquired request response information of the design to be tested. The request response transaction may include response data, which is the data in the cache before the floating point atomic request is executed.

[0104] Since the atomic transaction queue records the continuous memory access request transactions generated according to the continuous memory access requests, step S40 may be further performed to calculate and obtain the corresponding reference data of the continuous memory access request based on the continuous memory access request transactions recorded in the atomic transaction queue.

[0105] Wherein, based on the continuous memory access request including at least a floating-point atomic request and a read request corresponding to the same address, in an optional example, step S40 may be performed when it is determined that the operation type of the request response transaction is a floating-point atomic operation.

[0106] The reference data may be data used by the data comparison module to compare with the response data in the request response transaction.

[0107] Step S50, comparing the reference data and the response data to see if they are the same.

[0108] If the comparison reference data is the same as the response data, it means that no data error occurs in the execution of the continuous memory access request by the design under test, and the arbitration strategy verification is passed.

[0109] It can be seen that the embodiment of the present application records the continuous memory access request transaction carrying the request tag into the atomic transaction queue corresponding to the request tag. When the operation type of the request response transaction is a floating-point atomic operation, the reference data of the continuous memory access request is calculated based on the continuous memory access request transaction recorded in the atomic transaction queue, and then the reference data is compared with the response data to see if they are the same. When the two are the same, the arbitration strategy verification is passed, thereby achieving effective verification of the arbitration strategy of the continuously executed memory access request and ensuring the data calculation accuracy of the chip. Moreover, in the special arbitration strategy verification scenario where the request tag indicates the continuous memory access request, the arbitration mechanism of the continuous memory access request is reflected through the request tag, ensuring the arbitration strategy verification in the special arbitration strategy verification scenario.

[0110] In some embodiments, corresponding to the signal content in the continuous memory access request, the request response transaction obtained by the data comparison module may also include a request response function, and the request response function includes an operation code indicating the operation type of executing the continuous memory access request.

[0111] in, Figure 3 Another optional flow chart of the arbitration strategy verification method in the embodiment of the present application is shown as an example. Figure 3 As shown, after step 20, step S30 is also included, which determines whether the operation of executing the request response transaction to obtain the request response transaction is a floating-point atomic operation based on the operation code of the request response function.

[0112] If not, that is, the operation of executing the request response transaction is not a floating-point atomic operation, it means that the operation type of executing the request response transaction is a read operation, which is a conventional arbitration scenario that does not include a floating-point atomic operation.

[0113] In an optional example, if the operation type of the request response transaction executed is a read operation, when calculating the reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue, it can be specifically as follows: step S60, based on the continuous memory access request transaction recorded in the atomic transaction queue, obtain the read operation request corresponding to the response data, and calculate the read reference data according to the calling function of the read operation request.

[0114] When comparing whether the reference data and the response data are the same, it can be specifically as follows: step S70 , comparing whether the reference data and the response data are the same.

[0115] When the read reference data is the same as the response data, that is, the "yes" case, the arbitration strategy verification passes; when the read reference data is different from the response data, that is, the "no" case, the arbitration strategy verification fails.

[0116] If so, it means that the operation type of executing the request response transaction is a floating-point atomic operation.

[0117] In another optional example, if the operation type of the request response transaction executed is a floating-point atomic operation, since the operation time of the floating-point atomic operation is relatively long, when calculating the reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue, it can be specifically as follows: step S41, based on the continuous memory access request transaction recorded in the atomic transaction queue, determine whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0118] Among them, corresponding to the content information of the continuous memory access request, the continuous memory access request transaction may at least include a memory access address tag; the request response transaction may include not only the response data, but also the response address tag and the response address corresponding to the response data. Thus, as an optional implementation, refer to Figure 4 As shown, step S41 may specifically include the following steps:

[0119] Step S411: Based on the continuous memory access request transactions recorded in the atomic transaction queue, it is determined whether the response address tag is the same as the memory access address tag in the first continuous memory access request transaction recorded in the atomic transaction queue.

[0120] If the address tags are the same, it means that the request response transaction and the first continuous memory access request transaction recorded in the atomic transaction queue correspond to the cache address of the same data, and step S412 can be further executed.

[0121] If the address tags are different, it means that the request response transaction and the first continuous memory access request transaction recorded in the atomic transaction queue do not correspond to the cache address of the same data, and the memory access request corresponding to the request response transaction needs to be obtained and verified.

[0122] Step S412, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request.

[0123] In a specific example, the continuous memory access request transaction may further include a request flag, and the request flag is used to indicate the number of bytes of the continuous memory access request corresponding to the continuous memory access request transaction. Thus, when determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, it can be specifically determined, based on the request flag, whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request.

[0124] If it is determined that the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, that is, the determination result is yes, then step S413 is further executed.

[0125] If it is determined that the continuous memory access request corresponding to the first continuous memory access request transaction is not a 128B request, that is, the judgment result is no, that is, the continuous memory access request corresponding to the first continuous memory access request transaction is a non-128B request, that is, the continuous memory access request corresponding to the first continuous memory access request transaction is a 64B request. Since the floating-point atomic request corresponding to the floating-point atomic operation is a 64B request, when it is determined that the continuous memory access request corresponding to the first continuous memory access request transaction is also a 64B request, the floating-point atomic operation address is the same as the read request address in the first continuous memory access request transaction recorded in the atomic transaction queue, and step S60 can be executed.

[0126] Step S413, determining whether the response address is the same as the lower 64B memory access address of the 128B request.

[0127] In a specific example, the continuous memory access request transaction may further include a memory access address, so step S413 may specifically include: judging, based on the memory access address, whether the response address is the same as the lower 64B memory access address of the 128B request.

[0128] If the judgment result is yes, the floating-point atomic operation address is the same as the lower 64B memory access address of the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0129] As an optional implementation, if the judgment result is no, the floating-point atomic operation address is the same as the high 64B memory access address of the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0130] Continue to see Figure 3 As shown, if the judgment result of step S41 is yes, that is, the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue, step S43 is executed to obtain the continuous memory access request corresponding to the first continuous memory access request transaction, and calculate the reference data of the continuous memory access request.

[0131] It should be noted that floating-point atomic operations are special operations that can ensure that the operation process will not be interrupted by other concurrent accesses in a multi-processor or multi-threaded environment, and the final result will not be disturbed by the intermediate state. When floating-point atomic operations are used to modify shared data, no return value is required after the execution is completed. This operation is called a non-return operation; when floating-point atomic operations are used to check whether data meets the conditions and change the data, such as comparing and swapping (compareAndSwap) data, the value before the operation needs to be returned after the execution is completed. This operation is called a return operation.

[0132] Therefore, in some embodiments, if the floating-point atomic operation corresponds to the first consecutive memory access request transaction recorded in the atomic transaction queue, in order to ensure the accuracy of the verification of the arbitration strategy, see Figure 3 As shown, before step S43, step S42 may be further included to determine the operation type of the floating-point atomic operation according to the operation code.

[0133] Wherein, the operation type of the floating-point atomic operation may include an operation with return and an operation without return. When the operation type of the floating-point atomic operation is an operation with return, after the floating-point atomic operation is executed, the operation result will be returned through the return data function. When the operation type of the floating-point atomic operation is an operation without return, after the floating-point atomic operation is executed, whether the operation is successfully completed will be returned through the return response function.

[0134] It is understandable that the functions executed for different floating-point atomic operation types are different. Therefore, as an optional implementation, if the operation type of the floating-point atomic operation is a return operation, step S43, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction, and calculating the reference data of the continuous memory access request, can be to obtain the continuous memory access request corresponding to the first continuous memory access request transaction, and calculate the first reference data of the floating-point atomic request in the continuous memory access request according to the return data function of the floating-point atomic operation.

[0135] As another optional implementation, if the operation type of the floating-point atomic operation is a non-return operation, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating the reference data of the continuous memory access request may be to obtain the continuous memory access request corresponding to the first continuous memory access request transaction, and calculate the second reference data of the floating-point atomic request in the continuous memory access request based on the return response function of the floating-point atomic operation.

[0136] In some embodiments, in order to ensure the completeness of the recording of the atomic transaction queue and to facilitate the execution of the same comparison of the reference data and the response data, the embodiment of the present application may further include step S44, after calculating the reference data of the continuous memory access request in step S43, to record the reference data into the corresponding atomic transaction queue.

[0137] In some embodiments, if it is determined that the floating-point atomic operation does not correspond to the first continuous memory access request transaction recorded in the atomic transaction queue, step S60 is executed accordingly.

[0138] In some embodiments, corresponding to the above-mentioned continuous memory access request situation, the special arbitration verification scenario of the embodiment of the present application may include a first scenario, a second scenario, a third scenario, a fourth scenario and a fifth scenario.

[0139] Among them, the first scenario corresponds to a floating-point atomic request and a read request that are sent continuously. The second scenario corresponds to a floating-point atomic request and a read request that are sent continuously, and there is a clock cycle between the floating-point atomic request and the read request. The third scenario corresponds to a floating-point atomic request and two read requests that are sent continuously. The fourth scenario corresponds to a floating-point atomic request, an integer atomic request, and a read request that are sent continuously, and the address of the integer atomic request is different from the floating-point atomic request and the read request. The fifth scenario corresponds to a floating-point atomic request, a write request, and a read request that are sent continuously.

[0140] As an optional implementation, when executing step S44, the reference data is recorded in the corresponding atomic transaction queue, which can be recorded based on the corresponding scenario. If the special arbitration strategy verification scenario is any scenario from the first scenario to the fourth scenario, the first reference data is recorded in the corresponding atomic transaction queue. If the special arbitration strategy verification scenario is the fifth scenario, the response data is ORed with the second reference data to obtain the third reference data; the third reference data is recorded in the corresponding atomic transaction queue.

[0141] It should be noted that, since the continuous memory access request under the fifth scene includes a floating-point atomic request, a write request and a read request, and the floating-point atomic request, the write request and the read request correspond to the same address, the floating-point atomic operation of the floating-point atomic request at this time requires three clock cycles to be executed, and then the calculated result is written to the corresponding address, and the operations of the write request and the read request can be completed in one clock cycle. To ensure the accuracy of the verification of the arbitration strategy, the response data in the request response transaction corresponding to the fifth scene in the present application embodiment is the data before the floating-point atomic operation is executed, that is, the read operation returns the data written to the cache line address by the write operation (i.e., the new value). According to the return response function of the floating-point atomic operation, the second reference data of the floating-point atomic request in the continuous memory access request calculated is the data in the cache address before the write operation executes the data (i.e., the old value), so that the third reference data can be obtained according to the response data (new value) and the second reference data (old value) by performing an or operation, and the third reference data is the latest value of the address read by the read operation, and the third reference data is recorded in the corresponding atomic transaction queue.

[0142] In some embodiments, the reference data obtained in the verification scenarios corresponding to different special arbitration strategies are different. When comparing whether the reference data is the same as the response data, as an optional implementation, if the special arbitration strategy verification scenario is any one of the first to fourth scenarios, then the first reference data is compared to see if the response data is the same. As another optional implementation, if the special arbitration strategy verification scenario is the fifth scenario, then the third reference data is compared to see if the response data is the same.

[0143] It can be seen that the embodiment of the present application records the continuous memory access request transaction carrying the request tag into the atomic transaction queue corresponding to the request tag. When the operation type of the request response transaction is a floating-point atomic operation, the reference data of the continuous memory access request is calculated based on the continuous memory access request transaction recorded in the atomic transaction queue, and then the reference data is compared with the response data to see if they are the same. When the two are the same, the arbitration strategy verification is passed, thereby achieving effective verification of the arbitration strategy of the continuously executed memory access request and ensuring the data calculation accuracy of the chip. Moreover, in the special arbitration strategy verification scenario where the request tag indicates the continuous memory access request, the arbitration mechanism of the continuous memory access request is reflected through the request tag, ensuring the arbitration strategy verification in the special arbitration strategy verification scenario.

[0144] The present application also provides an arbitration strategy verification system, the structure of which can be referred to as Figure 1 As shown, the content described below can be considered as the functional modules that need to be set up by the arbitration strategy verification system to implement the arbitration strategy verification method provided by the embodiment of the present application, and the content described below can be referenced to the content described above. The arbitration strategy verification system includes: a design to be tested, a floating-point atomic operation verification component, and a data comparison module;

[0145] The design to be tested is used to execute a continuous memory access request, wherein the continuous memory access request corresponds to a special arbitration strategy verification scenario, the continuous memory access request at least includes a floating point atomic request and a read request, and the read request is a 64B read request and / or a 128B read request;

[0146] The floating-point atomic operation verification component is used to obtain a continuous memory access request of the design to be tested; generate a continuous memory access request transaction according to the continuous memory access request, wherein the continuous memory access request transaction carries a request tag, the request tag is calculated according to the continuous memory access request, and is used to indicate a special arbitration strategy verification scenario corresponding to the continuous memory access request; and obtain request response information of the design to be tested; generate a request response transaction according to the request response information, the request response transaction includes a request response function and response data; send the continuous memory access request transaction and the request response transaction to the data comparison module;

[0147] The data comparison module is used to obtain continuous memory access request transactions and request response transactions of the design to be tested, and perform arbitration strategy verification according to the continuous memory access request transactions and the request response transactions.

[0148] Optionally, after the data comparison module obtains the continuous memory access request transaction of the design to be tested, based on the request tag carried by the continuous memory access request transaction, the continuous memory access request transaction is recorded in an atomic transaction queue; wherein different atomic transaction queues correspond to different request tags;

[0149] The step of the data comparison module performing arbitration strategy verification according to the continuous memory access request transaction and the request response transaction includes:

[0150] If the operation type of the request response transaction obtained by execution is a floating-point atomic operation, based on the continuous memory access request transaction recorded in the atomic transaction queue, the reference data of the corresponding continuous memory access request is calculated;

[0151] The reference data is compared with the response data to see if they are the same. If so, the arbitration strategy verification is passed.

[0152] Optionally, the request response transaction acquired by the data comparison module further includes a request response function, and the request response function includes an operation code indicating an operation type of executing a continuous memory access request;

[0153] After the data comparison module obtains the request response transaction of the design to be tested, it is also used to:

[0154] Based on the operation code of the request response function, it is determined whether the operation executed to obtain the request response transaction is a floating-point atomic operation.

[0155] Optionally, the step of the data comparison module calculating reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue includes:

[0156] Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue;

[0157] If so, a continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and reference data of the continuous memory access request is calculated.

[0158] Optionally, the continuous memory access request transaction acquired by the data comparison module at least includes a memory access address tag; the request response transaction also includes a response address tag and a response address corresponding to the response data;

[0159] The step of the data comparison module determining whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue based on the continuous memory access request transactions recorded in the atomic transaction queue includes:

[0160] Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the response address tag is the same as the memory access address tag in the first continuous memory access request transaction recorded in the atomic transaction queue;

[0161] If so, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request;

[0162] If yes, determine whether the response address is the same as the lower 64B memory access address in the 128B request;

[0163] If so, the floating-point atomic operation address is the same as the lower 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0164] Optionally, the continuous memory access request transaction acquired by the data comparison module further includes a request flag and a memory access address;

[0165] The data comparison module determines whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, specifically, according to the request flag bit, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request;

[0166] The data comparison module determines whether the response address is the same as the lower 64B memory access address in the 128B request. Specifically, based on the memory access address, it determines whether the response address is the same as the lower 64B memory access address in the 128B request.

[0167] Optionally, when the data comparison module determines whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, if the continuous memory access request corresponding to the first continuous memory access request transaction is a non-128B request, the floating-point atomic operation address is the same as the read request address in the first continuous memory access request transaction recorded in the atomic transaction queue;

[0168] When the data comparison module determines whether the response address is the same as the low address bit of the continuous memory access request, if the response address is different from the lower 64B memory access address of the 128B request, then the floating-point atomic operation address is the same as the upper 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

[0169] Optionally, if the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue, before the data comparison module obtains the continuous memory access request corresponding to the first continuous memory access request transaction and calculates reference data of the continuous memory access request, it is further used to:

[0170] According to the operation code, an operation type of the floating-point atomic operation is determined; wherein the operation type of the floating-point atomic operation includes an operation with a return and an operation without a return.

[0171] Optionally, if the operation type of the floating-point atomic operation is a return operation, the step of the data comparison module obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request includes:

[0172] A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and first reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return data function of the floating-point atomic operation.

[0173] Optionally, if the operation type of the floating-point atomic operation is a non-return operation, the step of the data comparison module acquiring the continuous memory access request and calculating reference data of the continuous memory access request includes:

[0174] A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and second reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return response function of the floating-point atomic operation.

[0175] Optionally, after the data comparison module calculates and obtains the reference data of the continuous memory access request, it is further used to:

[0176] The reference data is recorded into the corresponding atomic transaction queue.

[0177] Optionally, the special arbitration policy verification scenarios include the first scenario, the second scenario, the third scenario, the fourth scenario, and the fifth scenario:

[0178] The first scenario corresponds to floating point atomic requests and read requests sent continuously;

[0179] The second scenario corresponds to a floating-point atomic request and a read request that are sent continuously, wherein the floating-point atomic request and the read request are separated by a clock cycle;

[0180] The third scenario corresponds to a floating point atomic request and two read requests sent continuously;

[0181] The fourth scenario corresponds to a floating-point atomic request, an integer atomic request, and a read request that are sent continuously, wherein an address of the integer atomic request is different from an address of the floating-point atomic request and the read request;

[0182] The fifth scenario corresponds to floating point atomic requests, write requests and read requests that are sent continuously.

[0183] Optionally, the step of the data comparison module recording the reference data into a corresponding atomic transaction queue includes:

[0184] If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, the first reference data is recorded in the corresponding atomic transaction queue;

[0185] If the special arbitration strategy verification scenario is the fifth scenario, an OR operation is performed on the response data and the second reference data to obtain third reference data; and the third reference data is recorded in the corresponding atomic transaction queue.

[0186] Optionally, the data comparison module compares whether the reference data is identical to the response data, including:

[0187] If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, comparing whether the first reference data is the same as the response data;

[0188] If the special arbitration strategy verification scenario is the fifth scenario, the third reference data is compared with the response data to see whether they are the same.

[0189] Optionally, if the operation type of executing the request response transaction is a read operation;

[0190] The data comparison simulation is based on the continuous memory access request transactions recorded in the atomic transaction queue, and the reference data of the continuous memory access request is calculated. Specifically, based on the continuous memory access request transactions recorded in the atomic transaction queue, the read operation request corresponding to the response data is obtained, and the read reference data is calculated according to the calling function of the read operation request;

[0191] The comparing whether the reference data is the same as the response data is specifically comparing whether the read reference data is the same as the response data.

[0192] It can be seen that the arbitration strategy verification system of the embodiment of the present application can effectively verify the arbitration strategy in the special arbitration strategy scenario of continuous memory access requests with floating-point atomic operations in chip design, thereby ensuring the data calculation accuracy of the chip. Moreover, the arbitration strategy verification system based on the embodiment of the present application can also verify the arbitration strategy in the conventional arbitration strategy scenario, thereby providing technical guarantee for the arbitration strategy verification in special scenarios.

[0193] An embodiment of the present application further provides a verification platform, which may include the above-mentioned arbitration strategy verification system to execute the above-mentioned arbitration strategy verification method.

[0194] An embodiment of the present application further provides a computing device, which includes a processor and a memory, wherein the hardware logic design of the memory is verified by the arbitration strategy verification method described above.

[0195] An embodiment of the present application further provides a computer program product, comprising one or more computer executable instructions, wherein the one or more computer executable instructions, when executed, can implement the arbitration policy verification method as described above.

[0196] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0197] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for verifying an arbitration strategy, characterized in that: include: Obtaining a continuous memory access request transaction of the design to be tested, wherein the continuous memory access request transaction is generated according to a continuous memory access request, wherein the continuous memory access request at least includes a floating-point atomic request and a read request corresponding to the same address, and the read request is a 64B read request and / or a 128B read request; The continuous memory access request transaction carries a request tag, and the request tag is used to indicate a special arbitration strategy verification scenario corresponding to the continuous memory access request; Based on the request tag, the continuous memory access request transaction is recorded into an atomic transaction queue; wherein different atomic transaction queues correspond to different request tags; Obtaining a request response transaction of the design to be tested, wherein the request response transaction includes response data, and the response data is data in the cache before the floating-point atomic request is executed; If the operation type of the request response transaction obtained by execution is a floating-point atomic operation, based on the continuous memory access request transaction recorded in the atomic transaction queue, the reference data of the corresponding continuous memory access request is calculated; The reference data is compared with the response data to see if they are the same. If so, the arbitration strategy verification is passed.

2. The method according to claim 1, characterized in that The request response transaction further includes a request response function, wherein the request response function includes an operation code indicating an operation type of executing a continuous memory access request; After obtaining the request response transaction of the design to be tested, the method further includes: Based on the operation code of the request response function, it is determined whether the operation executed to obtain the request response transaction is a floating-point atomic operation.

3. The method according to claim 2, characterized in that If yes, the step of calculating reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue includes: Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue; If so, a continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and reference data of the continuous memory access request is calculated.

4. The method according to claim 3, characterized in that The continuous memory access request transaction at least includes a memory access address tag; the request response transaction also includes a response address tag and a response address corresponding to the response data; The determining, based on the continuous memory access request transactions recorded in the atomic transaction queue, whether the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue comprises: Based on the continuous memory access request transactions recorded in the atomic transaction queue, determining whether the response address tag is the same as the memory access address tag in the first continuous memory access request transaction recorded in the atomic transaction queue; If so, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request; If yes, determine whether the response address is the same as the lower 64B memory access address in the 128B request; If so, the floating-point atomic operation address is the same as the lower 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

5. The method according to claim 4, characterized in that The continuous memory access request transaction also includes a request flag and a memory access address; The determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request is specifically, according to the request flag bit, determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request; The determining whether the response address is the same as the lower 64B memory access address in the 128B request is specifically, according to the memory access address, determining whether the response address is the same as the lower 64B memory access address in the 128B request.

6. The method according to claim 5, characterized in that When determining whether the continuous memory access request corresponding to the first continuous memory access request transaction is a 128B request, if the continuous memory access request corresponding to the first continuous memory access request transaction is a non-128B request, the floating-point atomic operation address is the same as the read request address in the first continuous memory access request transaction recorded in the atomic transaction queue; When determining whether the response address is the same as the low address bit of the continuous memory access request, if the response address is different from the low 64B memory access address of the 128B request, then the floating-point atomic operation address is the same as the high 64B memory access address in the 128B request corresponding to the first continuous memory access request transaction recorded in the atomic transaction queue.

7. The method according to claim 3, characterized in that If the floating-point atomic operation corresponds to the first continuous memory access request transaction recorded in the atomic transaction queue, before obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request, the method further includes: According to the operation code, an operation type of the floating-point atomic operation is determined; wherein the operation type of the floating-point atomic operation includes an operation with a return and an operation without a return.

8. The method according to claim 7, characterized in that If the operation type of the floating-point atomic operation is a return operation, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request includes: A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and first reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return data function of the floating-point atomic operation.

9. The method according to claim 7, characterized in that: If the operation type of the floating-point atomic operation is a non-return operation, obtaining the continuous memory access request corresponding to the first continuous memory access request transaction and calculating reference data of the continuous memory access request includes: A continuous memory access request corresponding to the first continuous memory access request transaction is obtained, and second reference data of the floating-point atomic request in the continuous memory access request is calculated according to a return response function of the floating-point atomic operation.

10. The method according to any one of claims 8 or 9, characterized in that: After the reference data of the continuous memory access request is obtained by calculation, the method further includes: The reference data is recorded into the corresponding atomic transaction queue.

11. The method according to claim 10, characterized in that Special arbitration policy verification scenarios include the first scenario, the second scenario, the third scenario, the fourth scenario, and the fifth scenario: The first scenario corresponds to floating point atomic requests and read requests sent continuously; The second scenario corresponds to a floating-point atomic request and a read request that are sent continuously, wherein the floating-point atomic request and the read request are separated by a clock cycle; The third scenario corresponds to a floating point atomic request and two read requests sent continuously; The fourth scenario corresponds to a floating-point atomic request, an integer atomic request, and a read request that are sent continuously, wherein an address of the integer atomic request is different from an address of the floating-point atomic request and the read request; The fifth scenario corresponds to floating point atomic requests, write requests and read requests that are sent continuously.

12. The method according to claim 11, characterized in that The step of recording the reference data into a corresponding atomic transaction queue includes: If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, the first reference data is recorded in the corresponding atomic transaction queue; If the special arbitration strategy verification scenario is the fifth scenario, an OR operation is performed on the response data and the second reference data to obtain third reference data; and the third reference data is recorded in the corresponding atomic transaction queue.

13. The method according to claim 12, characterized in that Comparing whether the reference data is the same as the response data comprises: If the special arbitration strategy verification scenario is the first scenario to the fourth scenario, comparing whether the first reference data is the same as the response data; If the special arbitration strategy verification scenario is the fifth scenario, the third reference data is compared with the response data to see whether they are the same.

14. The method according to claim 2, characterized in that If not, the operation type of executing the request response transaction is a read operation; The step of calculating reference data of the continuous memory access request based on the continuous memory access request transaction recorded in the atomic transaction queue is specifically, based on the continuous memory access request transaction recorded in the atomic transaction queue, obtaining a read operation request corresponding to the response data, and calculating read reference data according to a calling function of the read operation request; The comparing whether the reference data is the same as the response data is specifically comparing whether the read reference data is the same as the response data.

15. An arbitration strategy verification system, characterized in that: include: Design under test, floating point atomic operation verification component and data comparison module; The design to be tested is used to execute a continuous memory access request, wherein the continuous memory access request corresponds to a special arbitration strategy verification scenario, the continuous memory access request at least includes a floating point atomic request and a read request, and the read request is a 64B read request and / or a 128B read request; The floating-point atomic operation verification component is used to obtain a continuous memory access request of the design to be tested; generate a continuous memory access request transaction according to the continuous memory access request, wherein the continuous memory access request transaction carries a request tag, the request tag is calculated according to the continuous memory access request, and is used to indicate a special arbitration strategy verification scenario corresponding to the continuous memory access request; and obtain request response information of the design to be tested; generate a request response transaction according to the request response information, the request response transaction includes a request response function and response data; send the continuous memory access request transaction and the request response transaction to the data comparison module; The data comparison module is used to obtain continuous memory access request transactions and request response transactions of the design to be tested, and perform arbitration strategy verification according to the continuous memory access request transactions and the request response transactions.

16. The arbitration strategy verification system according to claim 15, characterized in that: After the data comparison module obtains the continuous memory access request transaction of the design to be tested, based on the request tag carried by the continuous memory access request transaction, the continuous memory access request transaction is recorded into the atomic transaction queue; wherein different atomic transaction queues correspond to different request tags; The step of the data comparison module performing arbitration strategy verification according to the continuous memory access request transaction and the request response transaction includes: If the operation type of the request response transaction obtained by execution is a floating-point atomic operation, based on the continuous memory access request transaction recorded in the atomic transaction queue, the reference data of the corresponding continuous memory access request is calculated; The reference data is compared with the response data to see if they are the same. If so, the arbitration strategy verification is passed.

17. A verification platform, characterized in that: The method comprises the arbitration strategy verification system as claimed in any one of claims 15 to 16.

18. A computing device comprising a processor and a memory, characterized in that: The hardware logic design of the memory is verified by the arbitration strategy verification method according to any one of claims 1 to 14.

19. A computer program product, characterized in that The method comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the arbitration strategy verification method according to any one of claims 1 to 14 is implemented.

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