Display panel, display device and driving method

Abstract

The invention discloses a display panel, a display device and a driving method, the display panel comprises a plurality of pixel circuits and a switch module electrically connected with the plurality of pixel circuits, the switch module comprises a first switch member, the first switch member comprises a first input end, a first output end and a first control end, the first input end is used for inputting a first voltage signal, and the first output end is used for outputting a second voltage signal; the first control end is used for inputting a first control signal; the second switch piece comprises a second input end, a second output end and a second control end, the second input end is used for inputting a second voltage signal, the second control end is used for inputting a second control signal, and the second voltage signal is different from the first voltage signal; wherein the first switch piece controlled by the first control signal and the second switch piece controlled by the second control signal cannot be turned on at the same time, the first output end and the second output end are electrically connected, and the first output end and the second output end are electrically connected with the pixel circuits so as to reset the pixel circuits. According to the structure, the brightness difference between different partitions of the display panel can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display device and a driving method. Background Art

[0002] With the development of display technology, partition multi-frequency technology has been developed to further reduce the power consumption of display panels. Partition multi-frequency technology means that the display panel can divide the entire display area into multiple partitions. The refresh rates of adjacent partitions are different. In other words, the entire display area will be divided into multiple partitions such as high-frequency area and low-frequency area according to the refresh rate. However, the partition multi-frequency technology is not mature at present, and there are differences in brightness between partitions. Summary of the invention

[0003] The present application provides a display panel, a display device and a driving method, which can reduce the brightness difference between different display areas.

[0004] According to a first aspect of the present application, a display panel is provided, which includes a plurality of pixel circuits and a switch module electrically connected to the plurality of pixel circuits, wherein the switch module includes: a first switch element, including a first input terminal, a first output terminal and a first control terminal, wherein the first input terminal is used to input a first voltage signal, and the first control terminal is used to input a first control signal; a second switch element, including a second input terminal, a second output terminal and a second control terminal, wherein the second input terminal is used to input a second voltage signal, and the second control terminal is used to input a second control signal, wherein the second voltage signal is different from the first voltage signal; wherein the first switch element controlled by the first control signal and the second switch element controlled by the second control signal cannot be turned on at the same time, and the first output terminal and the second output terminal are electrically connected, and are electrically connected to the plurality of pixel circuits to reset the plurality of pixel circuits.

[0005] In one embodiment, the first switch element and the second switch element are both thin film transistors.

[0006] Preferably, the first output terminal and the second output terminal are electrically connected, and are both electrically connected to each of the pixel circuits to reset each of the pixel circuits.

[0007] In one embodiment, the first switch element and the second switch element are both P-type thin film transistors or both N-type thin film transistors, and at the same time, the phases of the signals input to the first control terminal and the second control terminal are opposite.

[0008] In one embodiment, one of the first switch element and the second switch element is a P-type thin film transistor, and the other is an N-type thin film transistor. At the same time, the signals input to the first control terminal and the second control terminal have the same phase.

[0009] Preferably, the first control end is electrically connected to the second control end to form a first connection point, and the first connection point is connected to the switch signal.

[0010] In one embodiment, a plurality of pixel circuits are arranged into a plurality of pixel rows, and the display panel further includes: a gate driving circuit, including a plurality of data output terminals, the plurality of data output terminals correspond one-to-one to the plurality of pixel rows, the data output terminals are electrically connected to the pixel circuits in the corresponding pixel rows; a third switch element, electrically connecting the data output terminals to the pixel circuits in the pixel rows corresponding to the data output terminals.

[0011] Preferably, the third switch element includes a third input terminal, a third output terminal and a third control terminal, the third input terminal is electrically connected to the data output terminal, the third output terminal is electrically connected to the pixel circuit in the pixel row, and the third control terminal is electrically connected to the first control terminal.

[0012] Preferably, the first switch element and the third switch element are both thin film transistors.

[0013] Preferably, the first switch element and the third switch element are both P-type thin film transistors or both N-type thin film transistors.

[0014] In one embodiment, when the pixel circuit is in a refresh state, the first switch is turned on and the second switch is turned off, and when the pixel circuit is in a hold state, the first switch is turned off and the second switch is turned on, wherein the first voltage signal is less than the second voltage signal.

[0015] A second aspect of the present application provides a display device, comprising a display panel as described in any of the above embodiments.

[0016] The third aspect of the present application provides a display device, including: a display panel, including multiple pixel circuits; a driving chip, the multiple pixel circuits are electrically connected to the driving chip; the driving chip includes a first switch element and a second switch element; the first switch element includes a first input terminal, a first output terminal and a first control terminal, the first input terminal is used to input a first voltage signal, and the first control terminal is used to input a first control signal; the second switch element includes a second input terminal, a second output terminal and a second control terminal, the second input terminal is used to input a second voltage signal, and the second control terminal is used to input a second control signal, and the second voltage signal is different from the first voltage signal; wherein the first switch element controlled by the first control signal and the second switch element controlled by the second control signal cannot be turned on at the same time, the first output terminal and the second output terminal are electrically connected, and are electrically connected to the multiple pixel circuits to reset the multiple pixel circuits.

[0017] In a fourth aspect, the present application provides a driving method, which is applied to a display panel as in any of the above embodiments, and the method includes: obtaining a display driving state of pixels in a current scanning row; in response to the obtained display driving state being a refresh state, controlling a first switch element to be turned on in a reset phase and a second switch element to be turned off in a reset phase, so that a first voltage signal resets a pixel circuit through the first switch element; in response to the obtained display driving state being a hold state, controlling the first switch element to be turned off in a reset phase and a second switch element to be turned on in a reset phase, so that a second voltage signal resets the pixel circuit through the second switch element, and the second voltage signal is different from the first voltage signal.

[0018] In one embodiment, a plurality of pixel circuits are arranged into a plurality of pixel rows, and the display panel further includes: a gate driving circuit, including a plurality of data output terminals, the plurality of data output terminals correspond one-to-one to the plurality of pixel rows, the data output terminals are electrically connected to the pixel circuits in the corresponding pixel rows; a third switch element, electrically connecting the data output terminals to the pixel circuits in the pixel rows corresponding to the data output terminals.

[0019] In one embodiment, the third switch element includes a third input terminal, a third output terminal and a third control terminal, the third input terminal is electrically connected to the data output terminal, the third output terminal is electrically connected to the pixel circuit in the pixel row, and the third control terminal is electrically connected to the first control terminal; the method also includes: in response to the acquired display driving state being a refresh state, controlling the first switch element to be turned on in the reset phase, the second switch element to be turned off in the reset phase, and controlling the third switch element to be turned on in the data writing phase, so that in the data writing phase, the data voltage of the gate driving circuit is output to the pixel circuit in the pixel row through the third switch element, and so that in the reset phase, the first voltage signal resets the pixel circuit in the pixel row through the first switch element; in response to the acquired display driving state being a hold state, controlling the second switch element to be turned on in the reset phase, the first switch element to be turned off in the reset phase, and controlling the third switch element to be turned off in the data writing phase, so that in the data writing phase, the data voltage of the gate driving circuit cannot be output to the pixel circuit in the pixel row through the third switch element, and so that in the reset phase, the second voltage signal resets the pixel circuit in the pixel row through the second switch element, and the second voltage signal is different from the first voltage signal.

[0020] The beneficial effect is: the display panel of the present application includes multiple pixel circuits and a switching module electrically connected to the multiple pixel circuits, the switching module includes a first switching element and a second switching element, the first input terminal of the first switching element is a first voltage signal, the second input terminal of the second switching element is a second voltage signal, the first output terminal and the second output terminal are electrically connected to the multiple pixel circuits to reset the multiple pixel circuits, and through the control of the first control terminal and the second control terminal, different reset voltages can be input to the pixel circuits of different partitions of the display panel to reduce the brightness difference between different partitions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0022] Figure 1 It is a schematic structural diagram of an embodiment of a display panel of the present application;

[0023] Figure 2 yes Figure 1 A schematic structural diagram of a switch module in one embodiment;

[0024] Figure 3 yes Figure 2 The timing diagram of the switch module in an application scenario;

[0025] Figure 4 yes Figure 1 A schematic structural diagram of another embodiment of the switch module;

[0026] Figure 5 yes Figure 4 The timing diagram of the switch module in an application scenario;

[0027] Figure 6 is a schematic structural diagram of another embodiment of the display panel of the present application;

[0028] Figure 7 yes Figure 6 A schematic structural diagram of a switch module in one embodiment;

[0029] Figure 8 yes Figure 7 The timing diagram of the switch module in an application scenario;

[0030] Fig. 9 It is a structural schematic diagram of an embodiment of a display device of the present application;

[0031] Fig.10is a schematic structural diagram of another embodiment of the display device of the present application;

[0032] Fig.11 is a structural schematic diagram of another embodiment of the display device of the present application;

[0033] Fig.12 is a schematic diagram of a process of driving a display panel of the present application;

[0034] Fig.13 It is a flow chart of the driving method of the display panel of the present application in an application scenario. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] It should be noted that the terms "first" and "second" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0037] In the prior art, the partitioned multi-frequency technology of the display panel is to divide the display area into multiple partitions, and the refresh rates of adjacent partitions are different. The high-frequency area adopts multiple write frames, and the low-frequency area adopts a mixture of write frames and hold frames. The timing of the pixel circuit in the write frame includes a data write stage and a reset stage, and the timing of the pixel circuit in the hold frame includes a data hold stage and a reset stage. That is to say, in the hold frame, the data voltage is no longer written to the pixel circuit, but the drive is still maintained with the data write voltage of the write frame before the hold frame. This can reduce the display power consumption in the low-frequency area, but due to the difference in data writing in the write frame and data retention in the hold frame, there is also a difference in the actual display brightness, which results in the phenomenon of low-frequency flickering.

[0038] See also Figure 1 and Figure 2 The present application provides a display panel 10, which includes a plurality of pixel circuits P and a switch module SW electrically connected to the plurality of pixel circuits P, wherein the switch module SW includes a first switch element 110 and a second switch element 120. The first switch element 110 includes a first input terminal A1, a first output terminal B1 and a first control terminal C1, wherein the first input terminal A1 is used to input a first voltage signal VEN1, and the first control terminal C1 is used to input a first control signal S1; the second switch element 120 includes a second input terminal A2, a second output terminal B2 and a second control terminal C2, wherein the second input terminal A2 is used to input a second voltage signal VEH2, and the second control terminal C2 is used to input a second control signal S2, wherein the second voltage signal VEH2 is different from the first voltage signal VEH1; wherein the first switch element 110 controlled by the first control signal S1 and the second switch element 120 controlled by the second control signal S2 cannot be turned on at the same time, the first output terminal B1 and the second output terminal B2 are electrically connected, and are electrically connected to the plurality of pixel circuits P, so as to reset the plurality of pixel circuits P.

[0039] Specifically, the display panel 10 includes a switch module SW, and the switch module SW includes two switch elements, a first switch element 110 and a second switch element 120. Specifically, the switch module SW includes two input ends, a first input end A1 and a second input end A2, two control ends, a first control end C1 and a second control end C2, and two output ends, a first output end B1 and a second output end B2. The two output ends are electrically connected to each other and are electrically connected to multiple pixel circuits P. That is to say, the pixel circuits P connected to the two output ends are exactly the same, but the voltages input to the two input ends are different, and through the control of the first control end C1, it can be selected whether the first voltage signal VEH1 input from the first input end A1 can be output from the first output end B1, and through the control of the second control end C2, it can be selected whether the second voltage signal VEH2 input from the second input end A2 can be output from the second output end B2. Since the first switch 110 and the second switch 120 cannot be turned on at the same time under the control of the first control signal S1 and the second control signal S2, that is, at the same time, at most only one of the first switch 110 and the second switch 120 is turned on, at any time, at most only one of the first voltage signal VEH1 through the first switch 110 and the second voltage signal VEH2 through the second switch 120 can be output to the pixel circuit P. For example, the first output terminal B1 outputs at the first moment, and the second output terminal B2 does not output at the first moment; the second output terminal B2 outputs at the second moment, and the first output terminal B1 does not output at the second moment.

[0040] Furthermore, in the partition multi-frequency display technology, there are brightness differences in each partition, causing the problem of low-frequency flicker. The present application adds a switch module SW on the basis of the prior art, and controls the output of two different voltages through the switch module SW, one of which is used to reset the pixel circuit under the write frame in the reset stage, and the other voltage is used to reset the pixel circuit under the hold frame in the reset stage. The reset can be for the source of the driving transistor in the pixel circuit P and / or the drain of the driving transistor and / or the anode of the light-emitting element. The brightness difference between the write frame and the hold frame can be eliminated by two different voltages, thus avoiding the problem of low-frequency flicker.

[0041] In one embodiment, see Figure 1 and Figure 2 The first output terminal B1 and the second output terminal B2 are electrically connected, and are both electrically connected to each pixel circuit P to reset each pixel circuit P. This has the advantage that the reset voltage of all pixel circuits P of the entire display panel 10 can be controlled, thereby ensuring that the entire display area of ​​the display panel 10 avoids the problem of low-frequency flicker.

[0042] In one embodiment, see Figure 2 The first switch element 110 and the second switch element 120 are both thin film transistors. The thin film transistors can be manufactured using the existing display panel process, and the manufacturing is convenient.

[0043] Of course, the first switch element 110 and the second switch element 120 may also be other switch structures, as long as they can realize the on-off of the control voltage signal from the input end to the output end, and this application does not impose any limitation.

[0044] In one embodiment, in combination Figure 1 , Figure 2 and Figure 3 The first switch element 110 and the second switch element 120 are both P-type thin film transistors. At the same time, the phases of the signals input to the first control terminal C1 and the second control terminal C2 are opposite.

[0045] Specifically, for the sake of convenience, the voltage signal output by the switch module SW is defined as the output signal VEH. The output signal VEH can be the first voltage signal VEH1 output by the first switch element 110 controlled by the first control signal S1 at the first moment, or it can be the second voltage signal VEH2 output by the second switch element 120 controlled by the second control signal S2 at the second moment.

[0046] Figure 3The first frame is divided into a first frame and a second frame. In the first frame, all n rows of pixel circuits P perform data writing. In the second frame, the pixel circuits P in the 1st to mth rows perform data writing, and the pixel circuits P in the m+1th to nth rows perform data retention. In the first frame, by setting the first control signal S1 to a low potential L, the first switch element 110 is controlled to be turned on, and the second control signal S2 is set to a high potential H, the second switch element 120 is controlled to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the n rows of pixel circuits P are reset by the first voltage signal VEH1. In the second frame, when scanning the pixel circuits P from the 1st to the mth rows, the first control signal S1 is set to a low potential L to control the first switch element 110 to be turned on, the second control signal S2 is set to a high potential H to control the second switch element 120 to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the pixel circuits P from the 1st to the mth rows are reset by the first voltage signal VEH1; when scanning the pixel circuits P from the m+1th to the nth rows, the first control signal S1 is set to a high potential H to control the first switch element 110 to be turned off, the second control signal S2 is set to a low potential L, and the second switch element 120 is controlled to be turned on, and the output signal VEH is made to be the second voltage signal VEH2, and the pixel circuits P from the m+1th to the nth rows are reset by the second voltage signal VEH2. It can be seen from the above process that different output signals VEH are provided for resetting according to whether the pixel circuit P performs data writing or data retention, and at the same time, the phases of the signals input to the first control terminal C1 and the second control terminal C2 are opposite, thereby ensuring the uniformity of the output signal VEH, thereby improving the brightness difference caused by the difference between data writing and data retention.

[0047] In another embodiment, the first switch 110 and the second switch 120 are both N-type thin film transistors (not shown), and at the same time, the signals input to the first input control terminal C1 and the second input control terminal C2 are in opposite phases. This embodiment is different from the above embodiment in that the first switch 110 and the second switch 120 are N-type thin film transistors, which are turned on at a high potential H and turned off at a low potential L. The other principles are similar to the above embodiment, and will not be described in detail in this application.

[0048] In one embodiment, in combination Figure 1 , Figure 4 and Figure 5 The first switch element 110 is a P-type thin film transistor, the second switch element 120 is an N-type thin film transistor, and at the same time, the signals input to the first control terminal C1 and the second control terminal C2 have the same phase.

[0049] Specifically, for the sake of convenience, the voltage signal output by the switch module SW is defined as the output signal VEH. The output signal VEH can be the first voltage signal VEH1 output by the first switch element 110 controlled by the first control signal S1 at the first moment, or it can be the second voltage signal VEH2 output by the second switch element 120 controlled by the second control signal S2 at the second moment.

[0050] Figure 5 The first frame is divided into a first frame and a second frame. In the first frame, data is written to the n-row pixel circuits P. In the second frame, data is written to the 1st to m-th row pixel circuits P, and data is retained to the m+1-th to n-th row pixel circuits P. In the first frame, the first control signal S1 is set to a low potential L to control the first switch element 110 to be turned on, the second control signal S2 is set to a low potential L to control the second switch element 120 to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the n-row pixel circuits P are reset by the first voltage signal VEH1. In the second frame, when scanning the pixel circuits P from the 1st to the mth rows, the first control signal S1 is set to a low potential L to control the first switch element 110 to be turned on, the second control signal S2 is set to a low potential L to control the second switch element 120 to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the pixel circuits P from the 1st to the mth rows are reset by the first voltage signal VEH1; when scanning the pixel circuits P from the m+1th to the nth rows, the first control signal S1 is set to a high potential H to control the first switch element 110 to be turned off, the second control signal S2 is set to a high potential H, and the second switch element 120 is controlled to be turned on, and the output signal VEH is made to be the second voltage signal VEH2, and the pixel circuits P from the m+1th to the nth rows are reset by the second voltage signal VEH2. It can be seen from the above process that different output signals VEH are provided for resetting according to whether the pixel circuit P performs data writing or data retention, and at the same time, the signal phases input to the first control terminal C1 and the second control terminal C2 are the same, thereby ensuring the uniformity of the output signal VEH, thereby improving the brightness difference caused by the difference between data writing and data retention.

[0051] In another embodiment, the first switch 110 is an N-type thin film transistor, and the second switch 120 is a P-type thin film transistor (not shown), and at the same time, the signals input to the first control terminal C1 and the second control terminal C2 have the same phase. This embodiment is different from the above embodiment in that the conduction conditions of the first switch 110 and the second switch 120 are opposite, and the other principles are similar to the above embodiment, and this application will not repeat them.

[0052] In one embodiment, in combination Figure 6 , Figure 7 and Figure 8The first control terminal C1 is electrically connected to the second control terminal C2 to form a first connection point A, and the first connection point A is connected to the switch signal S.

[0053] Specifically, Figure 4 The difference is that the first control terminal C1 and the second control terminal C2 of this embodiment can realize time-sharing output of different output signals VEH by controlling the input switch signal S. At the first moment, the switch signal S is set to a low potential L to control the first voltage signal VEH1 output by the first switch element 110, and at the second moment, the switch signal S is set to a high potential H to control the second voltage signal VEH2 output by the second switch element 120.

[0054] Figure 8 The first frame is divided into a first frame and a second frame. In the first frame, data is written to the n-row pixel circuits P. In the second frame, data is written to the 1st to m-th row pixel circuits P, and data is retained to the m+1-th to n-th row pixel circuits P. In the first frame, by setting the switch signal S to a low potential L, the first switch element 110 is controlled to be turned on, and the second switch element 120 is controlled to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the n-row pixel circuits P are reset by the first voltage signal VEH1. In the second frame, when scanning the pixel circuits P of the 1st to the mth rows, the switch signal S is set to a low potential L, the first switch element 110 is controlled to be turned on, and the second switch element 120 is controlled to be turned off, and the output signal VEH is made to be the first voltage signal VEH1, and the pixel circuits P of the 1st to the mth rows are reset by the first voltage signal VEH1; when scanning the pixel circuits P of the m+1st to the nth rows, the switch signal S is set to a high potential H, the first switch element 110 is controlled to be turned off, and the second switch element 120 is controlled to be turned on, and the output signal VEH is made to be the second voltage signal VEH2, and the pixel circuits P of the m+1st to the nth rows are reset by the second voltage signal VEH2. It can be seen from the above process that different output signals VEH are provided for resetting according to whether the pixel circuit P performs data writing or data retention, and at the same time, the signals input to the first control terminal C1 and the second control terminal C2 are the low potential signal or the high potential signal in the switch signal S, so as to ensure the singleness of the output signal VEH, thereby improving the brightness difference caused by the difference in data writing and data retention.

[0055] Of course, in other implementations, different from the above embodiments, the first voltage signal VEH1 can be output to reset the pixel circuit P that performs data retention, and the second voltage signal VEH2 can be output to reset the pixel circuit P that performs data writing, and the present application does not limit this.

[0056] In one embodiment, see Figure 1, a plurality of pixel circuits P are arranged into a plurality of pixel rows L, and the display panel 10 further includes a gate driving circuit GIP and a third switch element 130. The gate driving circuit GIP includes a plurality of data output terminals O, the plurality of data output terminals O correspond to the plurality of pixel rows L one by one, and the data output terminals O are electrically connected to the pixel circuits P in the corresponding pixel rows L; the third switch element 130 is electrically connected to the data output terminals O and the pixel circuits P in the pixel rows L corresponding to the data output terminals O.

[0057] Specifically, the gate driving circuit GIP includes multiple data output terminals O. The gate driving circuit GIP outputs the data voltage to the pixel circuit P through the data output terminal O during the data writing phase, and a third switch element 130 is set between each data output terminal O and the corresponding pixel circuit P of each pixel row L, and the data voltage input is controlled by the third switch element 130.

[0058] In one embodiment, see Figure 1 and Figure 2 The third switch element 130 includes a third input terminal A3, a third output terminal B3 and a third control terminal C3, the third input terminal A3 is electrically connected to the data output terminal O, the third output terminal B3 is electrically connected to the pixel circuit P in the pixel row L, and the third control terminal C3 is electrically connected to the first control terminal C1.

[0059] Specifically, the third switch element 130 controls the conduction or cutoff of the third switch element 130 through the control signal received by the third control terminal C3, and then controls whether the data voltage transmitted by the data output terminal O can be transmitted from the third input terminal A3 to the third output terminal B3, and finally transmitted to the pixel circuit P of the corresponding pixel row L, and the third control terminal C3 is electrically connected to the first control terminal C1. Although the first control terminal C1 controls the pixel circuit P for resetting in the reset phase, and the third control terminal C3 controls the pixel circuit P for performing data writing in the data writing phase, the control actions of the two are in different stages, but the first control terminal C1 and the third control terminal C3 are both controlled by the same control signal (first control signal S1), so that the phase misalignment problem caused by controlling the reset and data writing respectively by different signals can be avoided, and the phase misalignment problem may cause the pixel circuit corresponding to the reset and the pixel circuit for data writing to not completely match.

[0060] In one embodiment, the first switch 110 and the third switch 130 are both thin film transistors. Thin film transistors are easy to manufacture and have low cost. Of course, the first switch 110 and the third switch 130 can also be other switch structures, as long as they can realize the switching functions of the first switch 110 and the third switch 130, and this application does not limit them.

[0061] In one embodiment, the first switch element 110 and the third switch element 130 are both P-type thin film transistors or both N-type thin film transistors, so that the conditions for controlling the on and off of the first switch element 110 and the third switch element 130 are consistent, making the control simpler.

[0062] Of course, in some other implementations, one of the first switch element 110 and the third switch element 130 may be a P-type thin film transistor and the other may be an N-type thin film transistor.

[0063] In another embodiment, see Figure 6 and Figure 7 Similar to the above embodiment, the third control terminal C3 is electrically connected to the first control terminal C1, and the first control terminal C1 is electrically connected to the second control terminal C2. Although the first control terminal C1 and the second control terminal C2 are used to reset the pixel circuit P in the reset stage, and the third control terminal C3 is used to control the pixel circuit P to perform data writing in the data writing stage or to control the pixel circuit P to perform data retention in the data retention stage, the control actions of the two are in different stages, but the first control terminal C1, the second control terminal C2 and the third control terminal C3 are all controlled by the same control signal (switch signal S), so that the phase misalignment problem caused by controlling the reset, data writing and data retention respectively by different signals can be avoided.

[0064] In one embodiment, when the pixel circuit P is in a refresh state, the first switch element 110 is turned on and the second switch element 120 is turned off, and when the pixel circuit P is in a hold state, the first switch element 110 is turned off and the second switch element 120 is turned on, wherein the first voltage signal VEH1 is less than the second voltage signal VEH2.

[0065] Specifically, the pixel circuit P is in a refresh state, that is, the pixel circuit P needs to perform data writing, and the pixel circuit P is in a hold state, that is, the pixel circuit P needs to perform data retention. Generally speaking, the refresh rate of the pixel circuit P is relatively high and relatively stable in the refresh state, while the refresh rate of the pixel circuit P is 0 in the hold state, and a higher reset voltage is required to maintain its stability. Therefore, the first voltage signal VEH1 is less than the second voltage signal VEH2, and the brightness difference of the area corresponding to the pixel circuit P in the above two states can be reduced by resetting. Of course, the voltage magnitude relationship in this embodiment is not absolute. In other embodiments, it needs to be set in combination with specific display panel partitions, pixel circuit structures, refresh rates and other conditions, and this application does not limit this.

[0066] In an application scenario, refer to the following table:

[0067] Table 1 Low-frequency flicker degree corresponding to the first voltage signal and the second voltage signal

[0068]

[0069] It can be seen from the above table that compared with the case where the first voltage signal and the second voltage signal have the same voltage value, the low-frequency flicker degree (i.e., Flicker value) decreases when some of the first voltage signals and the second voltage signals have different voltage values. Therefore, by setting the first voltage signal and the second voltage signal to be different, the low-frequency flicker phenomenon in the prior art can be improved.

[0070] It should be noted that the first voltage signal VEH1 is different from the second voltage signal VEH2, which means that there is no voltage drop between the components and lines in the circuit. It can be understood that if the voltage drop in the circuit of the present application is taken into account, it means that the reset voltage finally output to the pixel circuit P is different.

[0071] See also Fig. 9 In a second aspect, the present application provides a display device 20, comprising the display panel 10 in any of the above embodiments.

[0072] Specifically, the display device 20 can be any display device such as a notebook, a desktop, a tablet computer, a mobile phone, a smart watch, a virtual display terminal, etc., and is not limited here.

[0073] See also Fig.10 In a third aspect, the present application provides a display device 30, the display device 30 includes a display panel 40 and a driving chip 50, the display panel 40 includes a plurality of pixel circuits P; the plurality of pixel circuits P are electrically connected to the driving chip 50; the driving chip 50 includes a first switch element 110 and a second switch element 120; the first switch element 110 includes a first input terminal A1, a first output terminal B1 and a first control terminal C1, the first input terminal A1 is used to input a first voltage signal VEH1, the first control terminal C1 is used to input a first control signal S1; the second switch element 12 ... The second input terminal A2, the second output terminal B2 and the second control terminal C2 are included. The second input terminal A2 is used to input the second voltage signal VEH2. The second control terminal C2 is used to input the second control signal S2. The second voltage signal VEH2 is different from the first voltage signal VEH1. The first switch 110 controlled by the first control signal S1 and the second switch 120 controlled by the second control signal S2 cannot be turned on at the same time. The first output terminal B1 and the second output terminal B2 are electrically connected and are electrically connected to a plurality of pixel circuits P to reset the plurality of pixel circuits P. The difference between this embodiment and the above embodiment is that the switch module is arranged on the driving chip 50 in this embodiment, which can simplify the structure of the display panel. However, the principle is almost the same as that in the above embodiment, and this application will not repeat it again.

[0074] See also Fig.11In one embodiment, the first control terminal C1 of the first switch element 110 and the second control terminal C2 of the second switch element 120 are electrically connected. At this time, the first switch element 110 and the second switch element 120 can be controlled by a control signal S.

[0075] The fourth aspect of the present application provides a driving method, combined with Figure 1 , Figure 2 , Figure 3 and Fig.12 The method is applied to any display panel in the above embodiments, and the method includes:

[0076] S100: Obtain the display driving state of the pixels in the current scanning row.

[0077] Specifically, the display drive state includes a refresh state and a hold state. The refresh state means that in the data writing stage, the data voltage needs to be written into the pixel circuit. The hold state means that in the data holding stage, the data does not need to be written into the pixel circuit, and the pixel circuit maintains the data voltage written in the previous data writing stage. In addition, the current row of pixels can be a row of pixels or multiple rows of pixels. S200: In response to the acquired display drive state being the refresh state, the first switch element 110 is controlled to be turned on in the reset stage, and the second switch element 120 is turned off in the reset stage, so that the first voltage signal VEH1 resets the pixel circuit P through the first switch element 110.

[0078] Specifically, when the display driving state of the pixels in the current row is the refresh state, it is equivalent to only transmitting the first voltage signal VEH1 to the pixels in the current row through the switch module SW, and resetting the pixel circuits P in the pixels in the current row through the first voltage signal VEH1.

[0079] S300: In response to the acquired display driving state being a hold state, the first switch element 110 is controlled to be turned off in the reset phase, and the second switch element 120 is turned on in the reset phase, so that the second voltage signal VEH2 resets the pixel circuit P through the second switch element 120, and the second voltage signal VEH2 is different from the first voltage signal VEH1.

[0080] Specifically, when the display driving state of the pixels in the current row is the hold state, it is equivalent to only transmitting the second voltage signal VEH2 to the pixels in the current row through the switch module SW, and resetting the pixel circuit P in the pixels in the current row through the second voltage signal VEH2.

[0081] According to the above method, when different display driving states are obtained, in response to different display driving states, the reset voltage for resetting the pixel circuit P of the corresponding row of pixels is also different through the control of the switch module, wherein the reset can be to reset the anode of the light-emitting element in the pixel circuit P, and / or, the drain of the driving transistor, and / or, the source of the driving transistor, thereby reducing the brightness difference of the area where the pixel circuit is located under the two display driving states, thereby avoiding the low-frequency flicker problem.

[0082] In one embodiment, see Figure 1 , multiple pixel circuits P are arranged into multiple pixel rows, and the display panel 10 also includes a gate driving circuit GIP and a third switch element 130. The gate driving circuit GIP includes multiple data output terminals O, and the multiple data output terminals O correspond to multiple pixel rows L one by one, and the data output terminals O are electrically connected to the pixel circuits P in the corresponding pixel rows L; the third switch element 130 electrically connects the data output terminals O with the pixel circuits P in the pixel rows L corresponding to the data output terminals O, and the third switch element 130 includes a third input terminal A3, a third output terminal B3 and a third control terminal C3, the third input terminal A3 is electrically connected to the data output terminal O, the third output terminal B3 is electrically connected to the pixel circuits P in the pixel row L, and the third control terminal C3 is electrically connected to the first control terminal C1. The introduction of the relevant structure can refer to the above embodiments, and this application will not be repeated here.

[0083] The method further includes:

[0084] S210: In response to the acquired display driving state being a refresh state, the first switch element 110 is controlled to be turned on in the reset phase, the second switch element 120 is turned off in the reset phase, and the third switch element 130 is controlled to be turned on in the data writing phase, so that in the data writing phase, the data voltage of the gate drive circuit GIP is output to the pixel circuit P in the pixel row L through the third switch element 130, and in the reset phase, the first voltage signal VEH1 resets the pixel circuit P in the pixel row L through the first switch element 110.

[0085] Specifically, based on the above step S200, this step further includes controlling the third switch 130 to be turned on in the data writing stage when the display driving state is the refresh state. Since the third control terminal C3 is electrically connected to the first control terminal C1, the third switch 130 and the first switch 110 are controlled by the same control signal, so the pixel circuit in the refresh state can avoid the phase misalignment problem that may occur under different signal control conditions. At the same time, the data writing stage and the reset stage are two different stages, and there is a sequence of the data writing stage and the reset stage. However, this application does not limit which of the data writing stage and the reset stage in the refresh state has a higher priority, and it can be adjusted according to actual conditions.

[0086] S310: In response to the acquired display driving state being a holding state, the second switch element 120 is controlled to be turned on in the reset phase, the first switch element 110 is turned off in the reset phase, and the third switch element 130 is controlled to be turned off in the data holding phase, so that in the data writing phase, the data voltage of the gate drive circuit GIP cannot be output to the pixel circuit P in the pixel row L through the third switch element 130, and so that in the reset phase, the second voltage signal VEH2 resets the pixel circuit P in the pixel row L through the second switch element 120, and the second voltage signal VEH2 is different from the first voltage signal VEH1.

[0087] Specifically, based on the above step S300, this step further includes controlling the third switch 130 to be turned off in the data retention phase when the display driving state is the retention state, and the third switch 130 and the first switch 110 are controlled by the same control signal, thereby ensuring the synchronization effect of resetting the third switch 130 and maintaining the data of the first switch 110. Similarly, the data writing phase and the reset phase are two different phases, even if the data is not written in full in the data writing phase, the data writing phase and the reset phase still have a sequence, but the present application does not limit which of the retention state data writing phase and the reset phase has a higher priority, and it can be adjusted according to actual conditions.

[0088] Through the above method, it can be known that electrically connecting the first control terminal C1 of the first switch element 110 in the switch module SW with the third control terminal C3 can ensure the synchronization of the signals of all pixel circuits P in the display panel 10 in the reset stage and the data writing / data holding stage, and ensure that the pixel circuit corresponding to the reset matches the pixel circuit for data writing / data holding, and there will be no phase misalignment problem. The above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel circuits and a switch module electrically connected to the plurality of pixel circuits, wherein the switch module includes: A first switch element, comprising a first input terminal, a first output terminal and a first control terminal, wherein the first input terminal is used to input a first voltage signal, and the first control terminal is used to input a first control signal; A second switch element comprises a second input terminal, a second output terminal and a second control terminal, wherein the second input terminal is used to input a second voltage signal, the second control terminal is used to input a second control signal, and the second voltage signal is different from the first voltage signal; The first switch element controlled by the first control signal and the second switch element controlled by the second control signal cannot be opened at the same time, and the first output end and the second output end are electrically connected and electrically connected to the plurality of pixel circuits to reset the plurality of pixel circuits.

2. The display panel according to claim 1, characterized in that: The first switch element and the second switch element are both thin film transistors; Preferably, the first output terminal and the second output terminal are electrically connected, and are both electrically connected to each of the pixel circuits to reset each of the pixel circuits.

3. The display panel according to claim 2, characterized in that: The first switch element and the second switch element are both P-type thin film transistors or both are N-type thin film transistors. At the same time, the phases of the signals input to the first control terminal and the second control terminal are opposite.

4. The display panel according to claim 2, characterized in that: One of the first switch element and the second switch element is a P-type thin film transistor, and the other is an N-type thin film transistor. At the same time, the signals input to the first control terminal and the second control terminal have the same phase. Preferably, the first control end is electrically connected to the second control end to form a first connection point, and the first connection point is connected to a switch signal.

5. The display panel according to claim 1, characterized in that: The plurality of pixel circuits are arranged into a plurality of pixel rows, and the display panel further comprises: A gate driving circuit, comprising a plurality of data output terminals, the plurality of data output terminals corresponding to the plurality of pixel rows one by one, the data output terminals being electrically connected to the pixel circuits in the corresponding pixel rows; a third switch element, electrically connecting the data output terminal and the pixel circuit in the pixel row corresponding to the data output terminal; Preferably, the third switch element comprises a third input terminal, a third output terminal and a third control terminal, the third input terminal is electrically connected to the data output terminal, the third output terminal is electrically connected to the pixel circuit in the pixel row, and the third control terminal is electrically connected to the first control terminal; Preferably, the first switch element and the third switch element are both thin film transistors; Preferably, the first switch element and the third switch element are both P-type thin film transistors or both N-type thin film transistors.

6. The display panel according to claim 1, characterized in that: When the pixel circuit is in a refresh state, the first switch element is turned on and the second switch element is turned off. When the pixel circuit is in a hold state, the first switch element is turned off and the second switch element is turned on, wherein the first voltage signal is less than the second voltage signal.

7. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-6.

8. A display device, characterized in that: include: A display panel including a plurality of pixel circuits; A driving chip, wherein the plurality of pixel circuits are electrically connected to the driving chip; the driving chip comprises a first switch element and a second switch element; the first switch element comprises a first input terminal, a first output terminal and a first control terminal, the first input terminal is used to input a first voltage signal, and the first control terminal is used to input a first control signal; the second switch element comprises a second input terminal, a second output terminal and a second control terminal, the second input terminal is used to input a second voltage signal, and the second control terminal is used to input a second control signal, and the second voltage signal is different from the first voltage signal; wherein the first switch element controlled by the first control signal and the second switch element controlled by the second control signal cannot be opened at the same time, the first output terminal and the second output terminal are electrically connected, and are electrically connected to the plurality of pixel circuits to reset the plurality of pixel circuits.

9. A driving method, characterized in that: The method is applied to the display panel according to any one of claims 1 to 6, and the method comprises: Get the display driver status of the pixels in the current scan line; In response to the acquired display driving state being a refresh state, controlling the first switch element to be turned on in a reset phase and the second switch element to be turned off in the reset phase, so that the first voltage signal resets the pixel circuit through the first switch element; In response to the acquired display driving state being a hold state, the first switch element is controlled to be turned off in a reset phase, and the second switch element is turned on in a reset phase, so that the second voltage signal resets the pixel circuit through the second switch element, and the second voltage signal is different from the first voltage signal.

10. The driving method according to claim 9, characterized in that: The plurality of pixel circuits are arranged into a plurality of pixel rows, and the display panel further comprises: A gate driving circuit, comprising a plurality of data output terminals, the plurality of data output terminals corresponding to the plurality of pixel rows one by one, the data output terminals being electrically connected to the pixel circuits in the corresponding pixel rows; a third switch element, electrically connecting the data output terminal and the pixel circuit in the pixel row corresponding to the data output terminal; Preferably, the third switch element comprises a third input terminal, a third output terminal and a third control terminal, the third input terminal is electrically connected to the data output terminal, the third output terminal is electrically connected to the pixel circuit in the pixel row, and the third control terminal is electrically connected to the first control terminal; The method further comprises: In response to the acquired display driving state being a refresh state, controlling the first switch element to be turned on in a reset phase, the second switch element to be turned off in the reset phase, and controlling the third switch element to be turned on in a data writing phase, so that in the data writing phase, the data voltage of the gate driving circuit is output to the pixel circuit in the pixel row through the third switch element, and so that in the reset phase, the first voltage signal resets the pixel circuit in the pixel row through the first switch element; In response to the acquired display driving state being a hold state, the second switch element is controlled to be turned on in a reset phase, the first switch element is turned off in a reset phase, and the third switch element is controlled to be turned off in a data writing phase, so that in the data writing phase, the data voltage of the gate drive circuit cannot be output to the pixel circuit in the pixel row through the third switch element, and so that in the reset phase, the second voltage signal resets the pixel circuit in the pixel row through the second switch element, and the second voltage signal is different from the first voltage signal.

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