Cache processing method of heterogeneous device, heterogeneous system, product, device and medium

Abstract

The invention discloses a cache processing method of heterogeneous equipment, a heterogeneous system, a product, a device and a medium, and relates to the technical field of data storage. And according to the target virtual address access times corresponding to each device in the heterogeneous system, realizing a global data caching mechanism. And determining a file page corresponding to the target heterogeneous device based on the target virtual address access frequency, so that the file system layer has the capability of managing the memory cache of the heterogeneous device. And the predicted file page of the target heterogeneous device is verified, and the file page is moved under the condition that the verification is passed, so that the distribution accuracy of the target heterogeneous device is improved. The file page of the target heterogeneous device is mapped and moved to the memory of the host side, the target heterogeneous device does not need to be accessed, the file page stored in the memory of the processor is directly accessed, the increased access rate of the processor accessing the target heterogeneous device is avoided, the delay of accessing the memory of the target heterogeneous device is reduced, and the access efficiency is improved. And the data transmission rate and the system efficiency of the heterogeneous system are improved.

Description

Technical Field

[0001] The present invention relates to the field of data storage technology, and in particular to a cache processing method, a heterogeneous system, a product, a device and a medium for heterogeneous devices. Background Art

[0002] When the central processing unit (CPU) in a heterogeneous system accesses a heterogeneous device, the rate at which the CPU accesses the memory of a heterogeneous device (such as a field-programmable gate array (FPGA)) is significantly lower than the rate at which the CPU accesses its own memory, resulting in a longer delay in accessing the memory of the heterogeneous device and a lower bandwidth corresponding to the data transmission rate. Frequent access to the memory of heterogeneous devices will reduce the system efficiency of the heterogeneous system.

[0003] Therefore, how to improve the system efficiency of heterogeneous systems is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] The purpose of the present invention is to provide a cache processing method, heterogeneous system, product, device and medium for heterogeneous devices to solve the problem of long delay in accessing the memory of heterogeneous devices, reduced bandwidth corresponding to the data transmission rate, and thus reduced system efficiency of the heterogeneous system.

[0005] In order to solve the above technical problems, the present invention provides a cache processing method for heterogeneous devices, comprising: Obtain the number of target virtual address accesses corresponding to each device in a heterogeneous system; Determine the file page corresponding to the target heterogeneous device based on the target virtual address access count; and perform verification processing on the file page; If the verification passes, the file page is moved to the memory of the processor so that the processor can access the file page of the target heterogeneous device.

[0006] On the one hand, the target virtual address access count corresponding to each device in the heterogeneous system is obtained, including: Pre-establishing a global address space allocation relationship corresponding to each device in the heterogeneous system; wherein the global address space allocation relationship stores address space access information corresponding to the processor and the heterogeneous device; the virtual address access number of the address space access information includes a first virtual address access number corresponding to the external device accessing the local device and / or a second virtual address access number corresponding to the local device accessing; The target virtual address access times are determined according to the global address space allocation relationship.

[0007] On the other hand, determining the target virtual address access count according to the global address space allocation relationship includes: Obtaining a preset virtual address access count and / or a preset local access ratio; Determine a local access ratio according to the first virtual address access number and the second virtual address access number; In the global address space allocation relationship, if the number of virtual address accesses exceeds the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio, the number of virtual address accesses corresponding to the number of virtual address accesses exceeding the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio will be taken as the target virtual address access number.

[0008] On the other hand, when the number of virtual address accesses includes the first virtual address access number or the second virtual address access number, and the number of target virtual address accesses corresponds to multiple virtual addresses, determining the file page corresponding to the target heterogeneous device based on the target virtual address access number includes: Using the virtual address corresponding to the target virtual address access count as the second target virtual address; When there are multiple second target virtual addresses, determining whether the file pages to which the second target virtual addresses belong are the same; If they are the same, taking the heterogeneous device to which the data block corresponding to the second target virtual address belongs as the target heterogeneous device, so as to obtain the file page of the target heterogeneous device corresponding to the data block; If they are not the same, then the access times of each virtual address stored in the file page to which each second target virtual address belongs are added up to obtain the sum of their respective access times; The file page to which the access count of the virtual address having the largest sum of access counts belongs is taken as the file page corresponding to the target heterogeneous device.

[0009] On the other hand, the file page is verified, including: Obtaining the data block to which the file page belongs and the corresponding page information; Each mark bit of the data block and the page information are verified to obtain a verification result.

[0010] On the other hand, performing verification processing on each mark bit of the data block and the page information to obtain a verification result includes: Performing verification processing on each mark bit of the data block to obtain a first verification result; When the first verification result is that all verifications are passed, the page information is verified according to the file page hash value to obtain a second verification result; If the second verification result is verification passed, the final verification result is verification passed.

[0011] On the other hand, moving the file page to the memory of the processor includes: Acquire a cache mechanism corresponding to the processor in the heterogeneous system; wherein the cache mechanism is established by a file system layer of a file system; Storing the page attribute information corresponding to the file page in the target data structure corresponding to the cache mechanism; The page information corresponding to the file page is moved to the memory of the processor.

[0012] On the other hand, storing the page attribute information corresponding to the file page into the target data structure corresponding to the cache mechanism includes: Obtaining a target virtual address, a target physical address, and a target virtual address access count corresponding to the file page; The target virtual address and the target physical address are saved in the target data structure in the form of a key-value pair; wherein the target data structure at least includes a key, a value, a child node pointer, a mark bit, a file page hash value, and counting information; The page access times to which the target virtual address access times belong is saved in the counting information of the target data structure; Saving the verification result of each of the mark bits of the data block corresponding to the file page into the mark bit of the target data structure; The verification result of the page information corresponding to the file page is saved in the file page hash value of the target data structure.

[0013] On the other hand, moving the page information corresponding to the file page to the memory of the processor includes: The page information of the file page is stored in a target data structure corresponding to the cache mechanism according to the memory update cycle of the processor and the preset window.

[0014] On the other hand, the process of determining the preset window includes: Obtaining the transmission system level corresponding to the file page; Acquire a data transmission bandwidth corresponding to access between the processor and the target heterogeneous device; The preset window is determined according to the data transmission bandwidth, the memory space data of the heterogeneous device, the file page information corresponding to the preset window and the transmission system level.

[0015] On the other hand, the process of determining the memory update cycle includes: Obtaining an initial update memory cycle, a corresponding access count of the file page, and a transmission system level; The update memory cycle is determined according to the initial update memory cycle, the number of accesses corresponding to the file page, and the transmission system level.

[0016] To solve the above technical problems, the present invention further provides a heterogeneous system, comprising a storage device, a heterogeneous device, a switch and a processor; wherein at least one heterogeneous device constitutes a heterogeneous device cluster; The storage device, the heterogeneous device cluster and the processor all achieve heterogeneous consistency through the protocol of the switch; wherein the processor is used to implement the steps of the cache processing method for heterogeneous devices when executing a computer program.

[0017] In order to solve the above technical problem, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the cache processing method of the heterogeneous device when executed by a processor.

[0018] In order to solve the above technical problems, the present invention further provides a cache processing device for heterogeneous devices, comprising: Memory for storing computer programs; A processor is used to implement the steps of the cache processing method for heterogeneous devices when executing the computer program.

[0019] In order to solve the above technical problems, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the cache processing method for heterogeneous devices as described above are implemented.

[0020] The beneficial effects of the present invention are that first, the target virtual address access times corresponding to each device in the heterogeneous system are obtained. Here, the cache management of the heterogeneous devices in the heterogeneous system corresponding to the host side is taken into consideration, and a global data cache mechanism is implemented, which facilitates the subsequent cache processing of the data of the heterogeneous devices on the host side. Secondly, the file page corresponding to the target heterogeneous device is determined based on the target virtual address access times, so that the file system layer has the ability to manage the memory cache of the heterogeneous device. The determined target heterogeneous device is a frequently used target heterogeneous device predicted based on the target virtual address access times. Before the file page of the target heterogeneous device is moved to the memory of the processor, the file page of the predicted target heterogeneous device is verified and moved when the verification passes, thereby improving the allocation accuracy of the target heterogeneous device. Finally, the file page mapping of the target heterogeneous device is moved to the memory on the host side to improve the global access efficiency of the host side. When the host side accesses the target heterogeneous device, it is not necessary to access the target heterogeneous device, and the file page stored in the processor memory is directly accessed, thereby avoiding the increased access rate of the processor accessing the target heterogeneous device, reducing the delay in accessing the memory of the target heterogeneous device, and improving the data transmission rate and the system efficiency of the heterogeneous system.

[0021] Secondly, the target virtual address access times are determined based on the pre-established global address space allocation relationship. Through the address mapping mechanism, the global address space allocation of the heterogeneous device is added to allocate the address space and the corresponding cache allocation of the heterogeneous device, which lays the foundation for the subsequent allocation process and improves the accuracy of the allocation. In the global address space allocation relationship, there is a copy on each device in the heterogeneous system to ensure that each device understands the address allocation situation and related control information in real time, so as to pass the heterogeneous cache consistency protocol to ensure data consistency. By selecting the virtual address access times that exceed the preset virtual address access times and / or the local access ratio is less than the preset local access ratio in the global address space allocation relationship as the target virtual address access times, the diversity and flexibility of the judgment are improved, so as to facilitate the subsequent determination of the accuracy of the target heterogeneous device. In the case of multiple file pages, it is necessary to add the access times of all virtual addresses corresponding to the multiple file pages, and obtain the file page corresponding to the maximum access time for subsequent relocation, so as to improve the efficiency of cross-device memory access on the basis of making full use of the memory space of the processor memory. Corresponding to the verification processing of each mark bit of the data block, the integrity of the data block is ensured. Verify the page information to ensure whether the data in the data block has been updated or modified, thereby improving data security. First, verify the page information using one factor, and then verify the file page using another factor if the verification is successful, thereby improving the accuracy and efficiency of the file page verification. Storing the page attribute information corresponding to the file page in the target data structure corresponding to the cache mechanism is to improve the cache management problem of heterogeneous devices at the file system layer by improving the target data structure, thereby improving the access efficiency of the processor. Move the file page to the processor's memory, store the page attribute information in the target data structure, and move the page information to the processor's memory to improve and update the cache on the host side of the device memory and the data structure, thereby improving the global access efficiency on the host side. The window cache mechanism performs effective pre-fetching, improves cache performance, and prevents cache overflow on the receiving end. The fixed-length cache mechanism performs effective pre-fetching, saves memory space, and improves the effectiveness of data cache.

[0022] In addition, the present invention also provides a heterogeneous system, a computer program product, a cache processing device for heterogeneous devices, and a computer-readable storage medium, which have the same beneficial effects as the cache processing method for heterogeneous devices described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 This is a schematic diagram of the conventional file system cache principle; Figure 2 A flowchart of a cache processing method for heterogeneous devices provided by an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a heterogeneous system provided by an embodiment of the present invention; Figure 4 A schematic diagram of the principle of a cache mechanism provided by an embodiment of the present invention; Figure 5 A schematic diagram of another cache mechanism provided by an embodiment of the present invention; Figure 6 A schematic diagram of a cache window provided by an embodiment of the present invention; Figure 7 A structural diagram of a cache processing device for heterogeneous devices provided by an embodiment of the present invention; Figure 8 A structural diagram of a cache processing device for a heterogeneous device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The core of the present invention is to provide a cache processing method, heterogeneous system, product, device and medium for heterogeneous devices to solve the problem that the delay in accessing the memory of heterogeneous devices is long, the bandwidth corresponding to the data transmission rate is reduced, and the system efficiency of the heterogeneous system is reduced.

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0028] With the continuous development of technologies such as artificial intelligence, big data analysis, and scientific computing, the amount of global data is growing exponentially, which in turn increases the demand for data processing and analysis. In this context, traditional single-architecture database systems face huge challenges. They are not good enough in processing massive amounts of data, ensuring data real-time, and coping with diverse workloads.

[0029] FPGA heterogeneous systems usually combine FPGAs with other processors (such as CPUs, graphics processing units (GPUs), etc.) to fully utilize the advantages of different processors to achieve high-performance computing. In this architecture, FPGAs are widely used to accelerate specific computing tasks due to their programmability, low power consumption, and high parallelism.

[0030] In FPGA heterogeneous systems, data transmission speed is often a key factor affecting system performance. By using data caching technology, frequently accessed data can be stored in a high-speed cache close to the computing unit, thereby reducing data access latency and improving data access speed. At the same time, the data transmission bandwidth between FPGA and external memory is usually limited, and the use of data caching technology can reduce the number of accesses to external memory, thereby reducing data transmission bandwidth requirements. In addition, storing frequently accessed data in the cache can also reduce the number of accesses to the external memory, thereby reducing the power consumption of the system. Data caching technology can further reduce the power consumption of FPGA.

[0031] The data transmission path in the FPGA heterogeneous system is that the file data is first obtained by the process, transferred to the file system for caching, then copied to the application layer Pin page, and then transferred to the heterogeneous device through DMA. Among them, the Pin page is a page locking technology that allows the process to lock one or more memory pages in physical memory instead of letting the operating system's memory management unit (MMU) swap them out to the swap space on the disk. This is usually used for pages that need to be retained in physical memory to ensure that the target page will not be swapped to the disk during the direct memory access (DMA) hardware layer transmission process. The entire process of the traditional data transmission path, obtaining file data, transferring it from the storage device to the file system, caching it in the CPU's file system, and then copying it multiple times, accessing it to the heterogeneous device, and filtering the data by the heterogeneous device, so that it is then transmitted to the CPU, which will cause more transmission delays and higher CPU load. Figure 1 This is a schematic diagram of the conventional file system cache principle, such as Figure 1As shown in the figure, in the file system cache technology, the application layer program uses the standard Portable Operating System Interface (Posix) interface (such as open, read, write, close, etc.) to perform read and write operations on the file through the file system. Whenever a process opens a file, a file descriptor file data structure is created in the file system. This data structure maintains the read and write offset values ​​of the current process for the file. Multiple processes can open the same file at the same time, and a file data structure is generated in each process. The file entity operated by the process corresponds to a data structure corresponding to a unique index node (inode) in the file system. The inode data structure contains a file cache managed by a radix tree and a metadata cache. The file content is divided into pages of the same size for caching. The radix tree uses a file offset value as an index to quickly find the file page cache block corresponding to the index. The schematic diagram of performing file read and write operations is shown below, and the specific steps are as follows: 1. According to the read and write offset value and size of the logical file in the file data structure, the file data page cache is allocated on the host side and mounted to the radix tree. 2. Get the file's meta information from disk to determine the location of the file's data page on disk. 3. Get the corresponding file page from disk and store it in the file system cache.

[0032] In the peer-to-peer (P2P) transmission mode, data is directly transmitted from the storage device to the heterogeneous device. Although the optimized transmission architecture improves the transmission efficiency, it bypasses the existing cache mechanism. However, the final result of data filtering through the heterogeneous device will still be obtained by the CPU accessing the heterogeneous device. Regardless of the above methods, there will be CPU access to heterogeneous devices. Since the host side of the CPU has a difference in memory access performance to the heterogeneous device and access performance to the host side's own memory, the CPU access to the heterogeneous device results in a higher extension and lower bandwidth. The cache processing method for heterogeneous devices provided by the present invention can solve the above technical problems.

[0033] Figure 2 A flowchart of a cache processing method for heterogeneous devices provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the method includes: S11: Obtain the number of target virtual address accesses corresponding to each device in the heterogeneous system; S12: determining the file page corresponding to the target heterogeneous device based on the target virtual address access count; and performing verification processing on the file page; S13: If the verification passes, the file page is moved to the memory of the processor so that the processor can access the file page of the target heterogeneous device.

[0034] Specifically, the heterogeneous system in this embodiment can be a conventional FPGA heterogeneous system, in which the storage device, heterogeneous device, and processor are connected through the switch corresponding to the Peripheral Component Interconnect Express (PCIE), or it can be a switch corresponding to the Compute Express Link (CXL) protocol between the storage device, heterogeneous device, and processor in a point-to-point P2P transmission mode. It is not limited here and can be set according to actual conditions. Each device in step S11 is a global device corresponding to the heterogeneous system, including storage devices, heterogeneous devices, and processors on the host side. The heterogeneous device in this embodiment can be a single heterogeneous device or a heterogeneous device cluster composed of multiple heterogeneous devices, which is not limited here.

[0035] The basis for acquisition here can be based on the target virtual address access count of each device in the established database, or it can be obtained from the virtual addresses of each device stored in a list, table or other form, and there is no limitation here.

[0036] The target virtual address access count may be based on the total access count corresponding to the target virtual address, specifically including the access count of the external device accessing the local device and / or the access count of the local device accessing itself. The number of target virtual addresses may be one or more.

[0037] The acquisition here may be the access number corresponding to the highest virtual address access number among all devices in the heterogeneous system, or the access number corresponding to the virtual address access number among all devices exceeding a certain threshold, etc., which is not limited here.

[0038] Determining the file page corresponding to the target heterogeneous device based on the target virtual address access count in step S12 may be based on the target virtual address access count itself, or may be based on the target virtual address access count and combined with other parameters, without limitation.

[0039] If it is determined based on the target virtual address access times itself, since the target virtual address access times can include the access times of external devices accessing the local device and / or the access times of the local device accessing itself, when it is only based on the access times of external devices accessing the local device, the virtual address with the access times exceeding a certain threshold can be used as the target virtual address, and the file page corresponding to the target virtual address can be directly obtained. When it is only based on the access times of the local device accessing itself, the local access ratio or the access times of a certain threshold can be used. If the access times are lower than the local access ratio or the access times of a certain threshold, it means that the external device has accessed the local device more times, and its corresponding virtual address needs to be used as the target virtual address.

[0040] Based on the number of target virtual address accesses, if there are multiple target virtual addresses corresponding to different file pages, considering the limited memory space of the processor, the number of accesses of all virtual addresses in different file pages can be summed up to obtain the sum of the number of accesses of each file page, and the file page corresponding to the highest sum of accesses can be selected as the final file page, etc.

[0041] Before moving the file page to the processor's memory, considering the accuracy of the file page, the file page needs to be verified. The verification process here can be performed on the data of the file page, or on the mark bit of the file, or it can be a combination of the two. The specific verification process is not limited here and can be set according to the actual situation. If the verification process fails, it can return to step S11 to re-acquire the number of accesses to other target virtual addresses, or it can be corrected for the file page, etc., which is not limited here.

[0042] In the migration process in step S13, the cache mechanism of the original file system can be used, or a new file system cache mechanism can be established to update the page attribute information of the file page to the cache mechanism, and store the page information of the file page in the memory of the processor. The cache mechanism corresponds to the storage of the data structure, and its data structure is not limited, and can be a tree structure or other data storage structure.

[0043] It should be noted that the present invention is based on frequent use, and the file page of the target heterogeneous device determined by the number of target virtual address accesses is moved to the memory of the processor, and the corresponding processor's cache mechanism is added to the target heterogeneous device to minimize the processor's access to the heterogeneous device, and the file page corresponding to the heterogeneous device is stored in the processor's memory. When the processor needs to access the file page of the heterogeneous device, it first searches whether the file page of the heterogeneous device is stored in the processor's own memory. If so, it directly accesses the file page of the heterogeneous device stored in its own memory without accessing the heterogeneous device. That is, the file page of the heterogeneous device is moved to the processor's memory in advance to reduce access delay.

[0044] The embodiment of the present invention provides a cache processing method for heterogeneous devices, which obtains the target virtual address access times corresponding to each device in the heterogeneous system; determines the file page corresponding to the target heterogeneous device based on the target virtual address access times; and verifies the file page; if the verification passes, the file page is moved to the memory of the processor, so that the processor can access the file page of the target heterogeneous device. First, the target virtual address access times corresponding to each device in the heterogeneous system are obtained. Here, considering the cache management of the heterogeneous devices in the heterogeneous system on the host side, a global data cache mechanism is implemented to facilitate the subsequent cache processing of the data of the heterogeneous devices on the host side. Secondly, the file page corresponding to the target heterogeneous device is determined based on the target virtual address access times, so that the file system layer has the ability to manage the memory cache of the heterogeneous device. The determined target heterogeneous device is a frequently used target heterogeneous device predicted based on the target virtual address access times. Before moving the file page of the target heterogeneous device to the memory of the processor, the file page of the predicted target heterogeneous device is verified and moved if the verification passes, thereby improving the allocation accuracy of the target heterogeneous device. Finally, the file page mapping of the target heterogeneous device is moved to the memory on the host side to improve the global access efficiency on the host side. When the host side accesses the target heterogeneous device, there is no need to access the target heterogeneous device, and the file page stored in the processor memory can be directly accessed, thereby avoiding the increased access rate of the processor to the target heterogeneous device, reducing the delay in accessing the target heterogeneous device memory, and improving the data transmission rate and system efficiency of the heterogeneous system.

[0045] In some embodiments, obtaining the target virtual address access count corresponding to each device in the heterogeneous system includes: Pre-establishing a global address space allocation relationship corresponding to each device in the heterogeneous system; wherein the global address space allocation relationship stores address space access information corresponding to the processor and the heterogeneous device; the number of virtual address accesses in the address space access information includes a first virtual address access number corresponding to the external device accessing the local device and / or a second virtual address access number corresponding to the local device accessing; The target virtual address access count is determined based on the global address space allocation relationship.

[0046] It should be noted that the global address space allocation relationship is to achieve unified addressing of system memory through heterogeneous cache consistency protocol and establish an address mapping mechanism. The global address space allocation relationship can be in the form of a table, database, collection, etc., which is not limited here. It mainly stores the address space access information corresponding to the processor and the heterogeneous devices. The number of virtual address accesses to the address space access information here can be the first virtual address access number corresponding to the external device accessing the local device and the second virtual address access number corresponding to the local device accessing, or the first virtual address access number corresponding to the external device accessing the local device, or the second virtual address access number corresponding to the local device accessing, which is not limited here.

[0047] The target virtual address access count is determined based on the global address space allocation relationship. Since the global address space allocation relationship stores the virtual address access counts corresponding to all devices in the current heterogeneous system, the virtual address with the most frequent access counts can be used as the target virtual address, and the corresponding access counts can be used as the target virtual address access counts. The screening corresponding to the frequent access counts can be to select the virtual address corresponding to the highest access count, or to select the virtual address corresponding to the higher access count, which can be set according to the actual situation.

[0048] This embodiment provides a method for determining the number of target virtual address accesses based on a pre-established global address space allocation relationship. Through an address mapping mechanism, the global address space allocation of heterogeneous devices is added to allocate address space and corresponding cache allocation of heterogeneous devices, laying the foundation for subsequent allocation processes and improving the accuracy of allocation.

[0049] In some embodiments, the global address space allocation relationship is replicated in each device in a heterogeneous system so as to achieve consistency in address space access information of each device when an address change occurs in any device.

[0050] Specifically, in the global address space allocation relationship, there is a copy on each device in the heterogeneous system to ensure that each device understands the address allocation status and related control information in real time to transmit the heterogeneous cache consistency protocol to ensure data consistency.

[0051] In some embodiments, if any device has an address change, the method further includes: receiving broadcast message delivery instructions; The global address space allocation relationship corresponding to the address change is updated according to the broadcast message transmission instruction.

[0052] Specifically, if the address of any device changes, such as the file page corresponding to the virtual address of the heterogeneous device has been moved to the processor's memory, it is necessary to immediately initiate a broadcast message transmission instruction, such as a message corresponding to the write update mechanism. Coordination is performed between the devices in the heterogeneous system to keep the corresponding copies in the cache consistent. The hardware circuit in the heterogeneous device is used for decoding to accurately map the address in the unified address space to the corresponding actual storage module location, so that when a processing unit initiates an access request to a unified address, it can find the specific cache or main memory area where the corresponding storage location is located according to the mapping relationship.

[0053] This embodiment provides that when an address change occurs in any device, other devices are notified by broadcasting a message to pass instructions so that the copy information in the cache remains consistent, thereby ensuring data consistency.

[0054] In some embodiments, the address space access information of the global address space allocation relationship further includes device type, cluster structure type, on-chip memory channel, channel access times, current access ratio, virtual address, physical address, and read / write permission flag; The process of determining the read and write permission mark includes: Determine, according to a preset process, a first read-write permission mark of an access control register of a device corresponding to the heterogeneous system and a second read-write permission mark at a software level corresponding to the preset process; If the first read-write permission mark and the second read-write permission mark are different, the final read-write permission mark is determined according to the first read-write permission mark.

[0055] Specifically, the main memory in each device will be divided into different address segments, which will correspond to a unified virtual address space. In addition to the records of virtual addresses and the number of times the virtual addresses are accessed, it also includes the physical address mapped by the virtual address, the device type, the cluster structure type, the on-chip memory channel, the number of channel accesses, the current access ratio, and the read and write permission flags. Table 1 is a global address space allocation relationship table. As shown in Table 1, device type (2 bits, 2'b00 indicates CPU host device, 2'b01 indicates heterogeneous device, 2'10 indicates memory expansion device, 2'b11 is reserved), FPGA / CPU cluster identification number (Identification, ID) (4 bits, 4'h0 indicates cluster 0, 4'h1 indicates cluster 1, 4'h2 indicates cluster 2, in turn), FPGA / CPU ID (4 bits, 4'h0 represents device 0, 4'h1 represents device 1, 4'h2 represents device 2, in sequence), on-chip memory channel ID (4 bits, 4'h0 represents channel 0, 4'h1 represents channel 1, 4'h2 represents channel 2, in sequence), 64 bits for the start address, 64 bits for the end address, channel access times (10 bits, unit MB / min), local access ratio (8 bits, unit %), update flag (1 bit, 1'b0 represents no update, 1'b1 represents update required), permission flag (2 bits, 2'b00 represents no access permission, 2'b01 represents read only, 2'b10 represents write only, 2'b11 represents both read and write).

[0056] Table 1

[0057] The current access ratio corresponds to the number of accesses to the local device virtual address divided by the total number of accesses. By counting the number of virtual address accesses, we can understand the different popularity of virtual addresses, provide support for optimization operations such as prefetching, and improve the overall file access efficiency. In a system with the same addressing, the access rights of different locations may be different, and they need to be taken into consideration as a whole to ensure the normal operation of the system and data security. For some shared data in a unified address range, multiple devices can dynamically coordinate read and write permissions according to the cache consistency protocol. It is also necessary to set the corresponding access control register at the hardware level, and the hardware priority is greater than the software dynamic adjustment priority. When the permissions do not match, access is denied and corresponding exception prompts may be generated, thereby ensuring the orderly data access and operation of the entire heterogeneous system under the unified memory addressing. That is, when the read and write permission tags corresponding to the update of the hardware-level read and write permission tags are different from the software-level read and write permission tags, the hardware-level read and write permission tags need to be used as the main one.

[0058] In the application, a virtual address for memory read and write access is issued, and the virtual address is converted into a physical address (corresponding to the page number and the offset within the page) by looking up Table 1. If the data accessed by the physical address is in the processor's memory (Cache), it is read directly from the processor's memory. If it is not in the processor's memory, the device memory space (DeviceMemory) is accessed based on the physical address through the host bridge (Host Bridge) in the root complex (Root Complex).

[0059] The multiple address access information of the global address space allocation relationship provided in this embodiment is used for auxiliary functions in the subsequent file page update process to ensure the normal operation of the system and data security.

[0060] In some embodiments, determining the target virtual address access count according to the global address space allocation relationship includes: Obtaining a preset virtual address access count and / or a preset local access ratio; Determine the local access ratio according to the first virtual address access number and the second virtual address access number; In the global address space allocation relationship, if the number of virtual address accesses exceeds the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio, the number of virtual address accesses corresponding to the number of virtual address accesses exceeding the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio will be used as the target virtual address access number.

[0061] Specifically, the target virtual address access count is determined based on the global address space allocation relationship. Considering that the virtual address access count may be the first virtual address access count and / or the second virtual address access count, a preset virtual address access count and / or a preset local access ratio may be set. Corresponding to the preset virtual address access count, it is compared with the first virtual address access count. If the first virtual address access count exceeds the preset virtual address access count, it is used as the target virtual address. Corresponding to the preset local access ratio, the local access ratio corresponding to each virtual address needs to be calculated (second virtual address access count / first virtual address access count). If the actual local access ratio is less than the preset local access ratio, it means that the local access is less and the external device access is more, which indirectly confirms that the external device access count is more.

[0062] In this embodiment, the number of virtual address accesses is the relationship between the first virtual address access number and / or the second virtual address access number, and the final target virtual address access number is determined by using the relationship of and / or corresponding to the comparison situation.

[0063] The number of corresponding target virtual addresses here can be one or more, which is not limited here.

[0064] In this embodiment, the virtual address access times that exceed the preset virtual address access times and / or the local access ratio that is less than the preset local access ratio are selected from the global address space allocation relationship as the target virtual address access times, thereby improving the diversity and flexibility of the judgment, so as to facilitate the subsequent determination of the accuracy of the target heterogeneous device.

[0065] In some embodiments, when the number of virtual address accesses includes the first virtual address access number or the second virtual address access number, and the virtual address corresponding to the target virtual address access number is one, determining the file page corresponding to the target heterogeneous device based on the target virtual address access number includes: The virtual address corresponding to the number of target virtual address accesses is used as the first target virtual address; The heterogeneous device to which the data block corresponding to the target virtual address belongs is taken as the target heterogeneous device to obtain the file page of the data block corresponding to the target heterogeneous device.

[0066] Specifically, through the above embodiment, when the number of virtual address accesses includes the first virtual address accesses or the second virtual address accesses, and the number of virtual addresses corresponding to the target virtual address accesses is one, the virtual address is used as the first target virtual address, and the heterogeneous device to which the corresponding data block belongs is the target heterogeneous device, and its file page can be obtained. A data block generally refers to a basic unit for storing data in a file system, which may correspond to a file page, or a smaller storage unit. In a file system, a data block is a logical unit allocated to a file to store data, which may contain part or all of a file page. File pages are read from data blocks in the file system.

[0067] The method provided in this embodiment for determining the file page corresponding to the target heterogeneous device by the target virtual address access times is only determined by the target virtual address corresponding to the target virtual address access times, thereby improving the speed and simplicity of determining the target heterogeneous device.

[0068] In some other embodiments, when the number of virtual address accesses includes the first virtual address access number or the second virtual address access number, and the number of target virtual address accesses corresponds to multiple virtual addresses, determining the file page corresponding to the target heterogeneous device based on the target virtual address access number includes: Using the virtual address corresponding to the target virtual address access count as the second target virtual address; When there are multiple second target virtual addresses, determining whether the file pages to which the second target virtual addresses belong are the same; If they are the same, taking the heterogeneous device to which the data block corresponding to the second target virtual address belongs as the target heterogeneous device to obtain the file page of the data block corresponding to the target heterogeneous device; If they are not the same, then the access times of each virtual address stored in the file page to which each second target virtual address belongs are summed up to obtain the sum of their respective access times; The file page to which the access count of the virtual address having the largest sum of access counts belongs is taken as the file page corresponding to the target heterogeneous device.

[0069] Specifically, in the case where the number of target virtual address accesses corresponds to multiple virtual addresses, since the file page of the target heterogeneous device is ultimately moved, multiple virtual addresses are included in one file page. Considering that the memory space of the processor memory is limited, it is necessary to fully utilize the memory space of the processor memory. In the case of multiple file pages, screening is required again.

[0070] The virtual address corresponding to the target virtual address access count is used as the second target virtual address. When there are multiple second target virtual addresses, it is necessary to determine whether the file pages to which the second target virtual addresses belong are the same. If so, the method of determining the file page is the same as in the above embodiment, and the above embodiment can be referred to. If they are not the same file page, it is necessary to add up the access counts of all virtual addresses of each file page to obtain the sum of their respective access counts, so as to select the file page corresponding to the largest sum of virtual address access counts as the final file page.

[0071] In the case where multiple file pages exist, the present embodiment provides that the access times of all virtual addresses corresponding to the multiple file pages need to be added together to obtain the file page corresponding to the maximum access time for subsequent movement, thereby improving the efficiency of cross-device memory access while fully utilizing the memory space of the processor memory.

[0072] In some embodiments, the file page is verified, including: Get the data block to which the file page belongs and the corresponding page information; Each mark bit and page information of the data block is verified to obtain a verification result.

[0073] It is understandable that before actually moving the file page of the target heterogeneous device, it is necessary to check whether the file page is correct, which corresponds to the verification processing of each mark bit of the data block to ensure the integrity of the data block. The page information is verified to ensure whether the data in the data block has been updated or modified, thereby improving the security of the data.

[0074] The specific process of the verification processing corresponding to each mark block and page data is not limited here and can be set according to actual conditions.

[0075] The present embodiment provides a check process corresponding to each mark bit of the data block to ensure the integrity of the data block and a check process for the page information to ensure whether the data in the data block has been updated or modified, thereby improving the security of the data.

[0076] In some embodiments, the verification process is performed on each mark bit and page information of the data block to obtain a verification result, including: Performing verification processing on each mark bit of the data block to obtain a first verification result; When the first verification result is that all verifications are passed, the page information is verified according to the file page hash value to obtain a second verification result; If the second verification result is verification passed, the final verification result is verification passed.

[0077] It should be noted that the verification process of each mark bit and page information here can be based on the completion of the verification of one factor (each mark bit or page information), and when the verification passes, the verification of another factor (page information or each mark bit) can be performed. It can also be that the two factors are verified separately and the verification results are finally summarized. Only when the verification results of the two factors are passed, the final verification result is passed, so as to facilitate the migration of file pages.

[0078] During the verification process of the first method, if the verification of the first factor fails, there is no need to perform subsequent verification of the second factor.

[0079] In this embodiment, verification is first completed using one factor, and if the verification passes, verification of another factor is performed to improve the verification accuracy and verification efficiency of the file page.

[0080] In some embodiments, moving a file page to a memory of a processor includes: Obtaining a cache mechanism corresponding to a processor in a heterogeneous system; wherein the cache mechanism is established by a file system layer of a file system; Store the page attribute information corresponding to the file page into the target data structure corresponding to the cache mechanism; Move the page information corresponding to the file page to the processor's memory.

[0081] It is understandable that during the file page migration process, the page attribute information corresponding to the file page needs to be stored in the target data structure of the cache mechanism to complete and update the cache mechanism of the processor for subsequent access calls. The page attribute information mainly includes the integrity of the data block of the file page, whether the data of the data block is modified, and the corresponding virtual address and physical address information, so as to manage and schedule the file cache.

[0082] Figure 3 A schematic diagram of a heterogeneous system provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the hard disk storage device, the heterogeneous device cluster, and the storage devices have a view of heterogeneous consistency through the switch. Corresponding to the inside of the processor, it is managed by the global data cache management module in the cache mechanism of the file system layer and the device memory host-side cache management module. The global data cache management module is implemented through the global address space allocation relationship corresponding to the same addressing of the address mapping, and the device memory host-side cache management module implements the file page movement process.

[0083] In some embodiments, the process of establishing a cache mechanism includes: Acquire a first file system layer of the file system; wherein the first file system layer includes a file system standard interface and metadata information; On the basis of the first file system layer, a second file system layer is added; wherein the second file system layer uses the file system standard interface and metadata information of the first file system layer, and the second file system layer contains a target data structure to maintain the read and write offset values ​​of the target process for the file; A caching mechanism is determined based on the first file system layer and the second file system layer.

[0084] Specifically, Figure 3As shown in the figure, a kernel-mode custom stacked file system layer, i.e., the second file system layer, is created on the original virtual file system (VFS) layer, i.e., the original file system layer, and read and write files in accordance with the standard Posix interface. In VFS, each file corresponds to an inode node with a unique number, and each inode node corresponds to a file cache managed by a tree structure. When data is read and written, a fixed-size file cache page is allocated from the host-side memory, and VFS starts DMA to move the data block from the disk to the file cache, and mounts it on the radix tree for maintenance. According to the offset value of the file read, the corresponding cache block is searched from the radix tree for reading and writing. When each process opens a file, a File data structure is created in VFS, which maintains the read and write offset value of the current process for the file. In the second file system layer, the file page cache strategy managed by the tree structure is allocated by overloading the file's inode, and memory allocation and transmission on the host side and FPGA side are added. In conventional technology, the file system only manages the host-side memory, and all the contents of the file need to be cached on the host side. The unified addressing of system memory (global address space allocation relationship) is achieved through the heterogeneous cache consistency protocol, and the information of FPGA side memory is added to the file cache on the host side, which is managed using a radix tree.

[0085] It should be noted that the creation of its cache mechanism can also be based on a new file system layer setting, which is not limited here.

[0086] This embodiment provides for creating a second file system layer on the original file system layer, creating its cache mechanism here, and loading the memory allocation and transmission of heterogeneous devices into the memory of the processor to facilitate processor access to improve access efficiency.

[0087] Figure 4 A schematic diagram of a cache mechanism provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, in the processor, the target data structure corresponding to storing the page attribute information in the cache mechanism can be a tree data structure or other data structures, which are not limited here. It should be noted that the cache mapping relationship of the memory of the heterogeneous device on the host side is actually to move the file page of the target heterogeneous device to the memory of the processor, thereby reducing the access efficiency of the processor to the heterogeneous device.

[0088] In some embodiments, storing the page attribute information corresponding to the file page into the target data structure corresponding to the cache mechanism includes: Get the target virtual address, target physical address and target virtual address access count corresponding to the file page; The target virtual address and the target physical address are saved in a target data structure in the form of a key-value pair; wherein the target data structure at least includes a key, a value, a child node pointer, a mark bit, a file page hash value, and a count information; The page access count to which the target virtual address access count belongs is saved in the counting information of the target data structure; The verification results of each mark bit of the data block corresponding to the file page are saved in the mark bit of the target data structure; The verification result of the page information corresponding to the file page is saved in the file page hash value of the target data structure.

[0089] Specifically, Table 2 is a composition table of the target data structure, including keys, values, child node pointers, mark bits, file page hash values ​​and count information, and also includes accompanying control information.

[0090] Table 2

[0091] As shown in Table 2, the key is the logical address (virtual address) of the file, which contains the file page number and page offset. The method uses the corresponding file page number as the key. In this way, no matter how the specific storage location of the file in the system changes, as long as the logical address remains unchanged, the corresponding cache node (the page corresponding to the virtual address) can be found through the page number. The value is the location information of the specific data block storing the file page in the system, which is recorded in the form of a pointer. Each pointer points to the specific node storing the file page (which can be a node of different devices such as a CPU memory node and an FPGA memory node). At the same time, it contains the size, offset and other information of the valid data of each page, which is convenient for assembling and restoring data. Child node pointer (ChildPointers): According to the different bits of the page number, the branches are divided to build a tree structure. According to each 4-bit binary bit corresponding to a branch direction, there can be a total of 16 branch selections. By continuously subdividing the path according to the 4-bit binary bit to build a tree structure, 16 branches are processed at a time, which is convenient for fast search and comparison. Flags: "Integrity Flag" is used to verify whether the cache is complete and undamaged. This flag is updated regularly by using a cyclic redundancy check (CRC). Of course, other verification processing methods can also be used, which are not limited here. If the flag shows that the data block is incomplete, the system will trigger the re-acquisition of the corresponding data block from other backup nodes to repair the cache content. File page hash value: Use the unique hash value generated by the file page content through a hash algorithm (such as SHA256, etc.), so that it is easy to quickly determine whether different files have been modified. As long as the page is modified, the hash value will change. Count Information: "Page Access Frequency" counts the number of times each file page is accessed. Based on this statistic, you can understand the access popularity. For hot data blocks, you can consider migrating to device nodes with better performance or performing optimization operations such as pre-fetching to improve the overall file access efficiency.

[0092] It should be noted that, in the present invention, a file page cache of a target data structure is allocated to the inode of each file, and caches of the memory on the host side and the memory on the heterogeneous device side are included. Figure 5 A schematic diagram of another cache mechanism provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the child node pointer can realize 16 branch selections according to one branch direction for every 4 binary bits, thereby speeding up the traversal and search for data reading corresponding to each heterogeneous device.

[0093] In addition, the accompanying control information may include the total size of the file, creation time, last access time, valid flag, etc., so that the system can manage and schedule the file cache as a whole.

[0094] It can be understood that the target virtual address and the target physical address are saved in the target data structure in the form of a key-value pair, and the target physical address can be obtained through Table 1 in the above embodiment. The page access times to which the target virtual address access times belong is saved in the counting information, and the verification results of each flag bit are saved in the flag bit of the target data structure. The verification results of the page information are saved in the file page hash value.

[0095] The present embodiment provides for storing the page attribute information corresponding to the file page in the target data structure corresponding to the cache mechanism, which solves the cache management problem of heterogeneous devices at the file system layer and improves the access efficiency of the processor by improving the target data structure.

[0096] The page information migration process corresponding to the file page can be based on the processor's update memory cycle and the preset window corresponding page information migration, thereby improving the efficiency of data migration.

[0097] In some embodiments, moving page information corresponding to a file page to a memory of a processor includes: The page information of the file page is stored in a target data structure corresponding to the cache mechanism according to the processor's update memory cycle and the preset window.

[0098] Specifically, unlike the host-side memory, the CPU host side has higher latency and lower bandwidth when accessing the memory of heterogeneous devices. Frequent access to the memory of FPGA heterogeneous devices will reduce system efficiency. This embodiment enables the FPGA memory to have a partial cache on the host side to improve the efficiency of cross-device memory access, thereby improving the global memory access efficiency on the host side. The memory update cycle is based on the existing storage data of the processor memory for subsequent update processing. The data with a long storage cycle and infrequent use is deleted regularly to save more memory space for storing the page information of the file page. The preset window is a cache mechanism that implements data cache management based on a serial port of a specific size.

[0099] This embodiment provides for moving file pages to the processor's memory, storing page attribute information in a target data structure, and moving page information to the processor's memory, thereby achieving device memory host-side cache and data structure improvement and update, and improving global access efficiency on the host side.

[0100] In some embodiments, the process of determining the preset window includes: Get the transmission system level corresponding to the file page; Obtaining data transmission bandwidth corresponding to access between the processor and the target heterogeneous device; The preset window is determined according to the data transmission bandwidth, the memory space data of the heterogeneous device, the file page information corresponding to the preset window and the transmission system level.

[0101] Specifically, the access heat is judged by the number of "page access frequency" in the cache management tree node, and whether to map the FPGA memory to the host side for caching is determined based on the data access history. Since the data that is frequently accessed in the recent period is likely to be accessed in the future, it is necessary to map the FPGA cache to the host side, and the default access heat is greater than 10,000 times / minute.

[0102] Effective pre-fetching is performed through the window cache mechanism to improve cache performance. The window cache mechanism is used for the accelerated computing unit. The window cache implements data cache management based on a "window" of a specific size. The default window size is 64 file pages (default 4KB). At the same time, the window size can usually be set according to characteristics such as data transmission bandwidth and transmission system level (real-time level, such as level 1 for normal, level 2 for general real-time, and level 3 for advanced real-time). The transmission system level here can be set in real time based on the application scenario.

[0103] Window size (number of pages) = (data transmission bandwidth / 8GB / s)*64*system real-time level.

[0104] If the transmission bandwidth is high and the data real-time requirement is high, the window is set larger to allow more data to wait in the cache for processing. Otherwise, it should be set smaller to avoid problems such as buffer overflow at the receiving end. When new data sources are continuously generated and transmitted, they will enter the tree cache management structure designed in the previous article in sequence. Figure 6 A schematic diagram of a cache window provided by an embodiment of the present invention, such as Figure 6 As shown, based on request a, corresponding cache windows are set based on different accelerated computing units, and each cache window is entered in sequence.

[0105] The window cache mechanism provided in this embodiment performs effective pre-fetching, improves cache performance, and prevents cache overflow at the receiving end.

[0106] In some embodiments, the process of determining the update memory cycle includes: Get the initial update memory cycle, the number of accesses corresponding to the file page, and the transmission system level; The update memory cycle is determined according to the initial update memory cycle, the number of accesses corresponding to the file page, and the transmission system level.

[0107] Specifically, cache data updates use a fixed-duration cache mechanism, which manages the validity period of data by setting a timer or timestamp mechanism. When data is first mapped to the host and stored in the cache, a timestamp (to represent the time of storage) is recorded synchronously, and a fixed duration is set as the validity period. The default duration is 30 seconds. The setting of the fixed duration is determined by the number of data accesses, the transmission system level corresponding to the target process (real-time level, such as level 1 for normal, level 2 for general real-time, and level 3 for advanced real-time), and whether there is a data consistency requirement.

[0108] Fixed duration (s) = ((data access frequency / 10000)*system real-time level*30.

[0109] The data access frequency is high, the data update rate is high, and the data real-time level is high. The cache validity period is long, otherwise the cache validity period should be short. For each access request to cached data, the system checks whether the difference between the current time and the stored timestamp exceeds the set fixed time. If it does not exceed, the data is considered to be still valid. By calculating the SHA256 hash value of the file page, if it is equal to the file page hash value, the data can be directly obtained and returned from the cache. If it times out or does not match the file page hash value, the cached data is determined to have expired. The expired data processing triggers a write-back and invalidation operation to release the cache space. The specific system invalidates the mapped cache through the CXL heterogeneous cache consistency protocol message to ensure data consistency.

[0110] The fixed-duration cache mechanism provided in this embodiment performs effective pre-fetching, saves memory space, and improves the effectiveness of data cache.

[0111] Furthermore, the present invention also provides a heterogeneous system, comprising a storage device, a heterogeneous device, a switch and a processor; wherein at least one heterogeneous device constitutes a heterogeneous device cluster; The storage device, the heterogeneous device cluster and the processor all achieve heterogeneous consistency through the switch protocol; wherein the processor is used to implement the steps of the cache processing method of the heterogeneous device when executing the computer program.

[0112] It should be noted that the heterogeneous system in this embodiment can be based on conventional Figure 1 The heterogeneous system shown may also be a heterogeneous system based on a P2P transmission mode. If it is the latter, the heterogeneous consistency of the corresponding switches is implemented based on the CXL protocol.

[0113] For an introduction to a heterogeneous system provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the cache processing method of the above heterogeneous device.

[0114] The above describes in detail various embodiments corresponding to the cache processing method for heterogeneous devices. On this basis, the present invention also discloses a cache processing device for heterogeneous devices corresponding to the above method. Figure 7 A structural diagram of a cache processing device for heterogeneous devices provided by an embodiment of the present invention. Figure 7 As shown, the device includes: An acquisition module 11 is used to acquire the number of target virtual address accesses corresponding to each device in the heterogeneous system; A determination module 12 is used to determine the file page corresponding to the target heterogeneous device based on the target virtual address access count; and perform verification processing on the file page; The moving module 13 is used to move the file page to the memory of the processor when the verification is passed, so that the processor can access the file page of the target heterogeneous device.

[0115] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0116] For an introduction to a cache processing device for a heterogeneous device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the cache processing method for the heterogeneous device.

[0117] Figure 8 A structural diagram of a cache processing device for a heterogeneous device provided by an embodiment of the present invention, such as Figure 8 As shown, the device comprises: A memory 21, used for storing computer programs; The processor 22 is used to implement the steps of the cache processing method for heterogeneous devices when executing a computer program.

[0118] The cache processing apparatus for heterogeneous devices provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0119] Among them, the processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 22 can be implemented in at least one hardware form of a digital signal processor (DSP), an FPGA, and a programmable logic array. The processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU; the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 22 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 22 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0120] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the processor 22, the relevant steps of the cache processing method of the heterogeneous device disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, data involved in the cache processing method of heterogeneous devices, etc.

[0121] In some embodiments, the cache processing device of the heterogeneous device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0122] Those skilled in the art can understand that Figure 8 The structure shown in the figure does not constitute a limitation on the cache processing device of the heterogeneous device, and may include more or fewer components than those shown in the figure.

[0123] The processor 22 implements the cache processing method for heterogeneous devices provided by any of the above embodiments by calling instructions stored in the memory 21.

[0124] For an introduction to a cache processing device for a heterogeneous device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the cache processing method for heterogeneous devices mentioned above.

[0125] Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the processor 22, the steps of the cache processing method for heterogeneous devices as described above are implemented.

[0126] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0127] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. It has the same beneficial effects as the cache processing method of the above heterogeneous device.

[0128] Furthermore, the present invention also provides a computer program product, including a computer program / instruction, which implements the steps of the cache processing method for heterogeneous devices when executed by a processor.

[0129] For an introduction to a computer program product provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. It has the same beneficial effects as the cache processing method for heterogeneous devices described above.

[0130] The above is a detailed introduction to a cache processing method, heterogeneous system, product, device and medium for heterogeneous devices provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0131] It should also be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A cache processing method for heterogeneous devices, characterized in that: include: Obtain the number of target virtual address accesses corresponding to each device in a heterogeneous system; Determine the file page corresponding to the target heterogeneous device based on the target virtual address access count; and verifying the file page; If the verification passes, the file page is moved to the memory of the processor so that the processor can access the file page of the target heterogeneous device.

2. The cache processing method for heterogeneous devices according to claim 1, characterized in that: Get the target virtual address access count corresponding to each device in the heterogeneous system, including: Pre-establishing a global address space allocation relationship corresponding to each device in the heterogeneous system; wherein the global address space allocation relationship stores address space access information corresponding to the processor and the heterogeneous device; the virtual address access number of the address space access information includes a first virtual address access number corresponding to the external device accessing the local device and / or a second virtual address access number corresponding to the local device accessing; The target virtual address access times are determined according to the global address space allocation relationship.

3. The cache processing method for heterogeneous devices according to claim 2, characterized in that: Determining the target virtual address access times according to the global address space allocation relationship includes: Obtaining a preset virtual address access count and / or a preset local access ratio; Determine a local access ratio according to the first virtual address access number and the second virtual address access number; In the global address space allocation relationship, if the number of virtual address accesses exceeds the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio, the number of virtual address accesses corresponding to the number of virtual address accesses exceeding the preset number of virtual address accesses and / or the local access ratio is less than the preset local access ratio will be taken as the target virtual address access number.

4. The cache processing method for heterogeneous devices according to claim 3, characterized in that: When the number of virtual address accesses includes the first virtual address access number or the second virtual address access number, and the number of target virtual address accesses corresponds to multiple virtual addresses, determining a file page corresponding to a target heterogeneous device based on the number of target virtual address accesses includes: Using the virtual address corresponding to the target virtual address access count as the second target virtual address; When there are multiple second target virtual addresses, determining whether the file pages to which the second target virtual addresses belong are the same; If they are the same, taking the heterogeneous device to which the data block corresponding to the second target virtual address belongs as the target heterogeneous device, so as to obtain the file page of the target heterogeneous device corresponding to the data block; If they are not the same, then the access times of each virtual address stored in the file page to which each second target virtual address belongs are added up to obtain the sum of their respective access times; The file page to which the access count of the virtual address having the largest sum of access counts belongs is taken as the file page corresponding to the target heterogeneous device.

5. The cache processing method for heterogeneous devices according to claim 1, characterized in that: The file page is verified, including: Obtaining the data block to which the file page belongs and the corresponding page information; Each mark bit of the data block and the page information are verified to obtain a verification result.

6. The cache processing method for heterogeneous devices according to claim 5, characterized in that: Verifying each mark bit of the data block and the page information to obtain a verification result includes: Performing verification processing on each mark bit of the data block to obtain a first verification result; When the first verification result is that all verifications are passed, the page information is verified according to the file page hash value to obtain a second verification result; If the second verification result is verification passed, the final verification result is verification passed.

7. The cache processing method for heterogeneous devices according to claim 6, characterized in that: Moving the file page to the processor's memory includes: Acquire a cache mechanism corresponding to the processor in the heterogeneous system; wherein the cache mechanism is established by a file system layer of a file system; Storing the page attribute information corresponding to the file page in the target data structure corresponding to the cache mechanism; The page information corresponding to the file page is moved to the memory of the processor.

8. The cache processing method for heterogeneous devices according to claim 7, characterized in that: Storing the page attribute information corresponding to the file page in the target data structure corresponding to the cache mechanism includes: Obtaining a target virtual address, a target physical address, and a target virtual address access count corresponding to the file page; The target virtual address and the target physical address are saved in the target data structure in the form of a key-value pair; wherein the target data structure at least includes a key, a value, a child node pointer, a mark bit, a file page hash value, and counting information; The page access times to which the target virtual address access times belong is saved in the counting information of the target data structure; Saving the verification result of each of the mark bits of the data block corresponding to the file page into the mark bit of the target data structure; The verification result of the page information corresponding to the file page is saved in the file page hash value of the target data structure.

9. The cache processing method for heterogeneous devices according to claim 7, characterized in that: Moving page information corresponding to the file page to the memory of the processor includes: The page information of the file page is stored in a target data structure corresponding to the cache mechanism according to the memory update cycle of the processor and the preset window.

10. The cache processing method for heterogeneous devices according to claim 9, characterized in that: The process of determining the preset window includes: Obtaining the transmission system level corresponding to the file page; Acquire a data transmission bandwidth corresponding to access between the processor and the target heterogeneous device; The preset window is determined according to the data transmission bandwidth, the memory space data of the heterogeneous device, the file page information corresponding to the preset window and the transmission system level.

11. The cache processing method for heterogeneous devices according to claim 9, characterized in that: The process of determining the memory update cycle includes: Obtaining an initial update memory cycle, a corresponding access count of the file page, and a transmission system level; The update memory cycle is determined according to the initial update memory cycle, the number of accesses corresponding to the file page, and the transmission system level.

12. A heterogeneous system, characterized in that: It includes a storage device, a heterogeneous device, a switch and a processor; wherein at least one heterogeneous device constitutes a heterogeneous device cluster; The storage device, the heterogeneous device cluster and the processor all achieve heterogeneous consistency through the protocol of the switch; wherein the processor is used to implement the steps of the cache processing method for heterogeneous devices as described in any one of claims 1 to 11 when executing a computer program.

13. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the cache processing method for a heterogeneous device described in any one of claims 1 to 11 are implemented.

14. A cache processing device for heterogeneous devices, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the cache processing method for a heterogeneous device as described in any one of claims 1 to 11 when executing the computer program.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the cache processing method for a heterogeneous device according to any one of claims 1 to 11 are implemented.

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