Control method, control device and system of PIM equipment, storage medium and electronic equipment

Abstract

The invention discloses a control method, a control device and a system of PIM equipment, a storage medium and electronic equipment. The method comprises the steps that in response to a received new PIM instruction, the state of data in a data space corresponding to the new PIM instruction in a cache is modified, and whether a previous PIM instruction exists in PIM equipment or not is judged; storing the new PIM instruction as a PMI instruction to be executed in response to the existence of a previous PIM instruction in the PIM equipment; the new PIM instruction is sent to a memory controller corresponding to the PIM equipment in response to the fact that the PIM equipment does not have the previous PIM instruction, and the memory controller sends the new PIM instruction to the PIM equipment; wherein the previous PIM instruction of the PIM equipment is updated in real time. By adopting the scheme, the software execution efficiency can be improved while the data consistency between the CPU and the PIM equipment is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory processors, and in particular to a control method, a control device, a system, a storage medium and an electronic device for a PIM device. Background Art

[0002] As artificial intelligence (AI) computing becomes more and more popular, the demand for computing power and bandwidth is also getting higher and higher. Limited by the memory bandwidth, the computing power of the central processing unit (CPU) cannot be increased. Therefore, the processor-in-memory (PIM) has emerged, which embeds the processor into the memory to perform computing tasks. Among them, the device that includes PIM and memory is denoted as PIM device.

[0003] The PIM device can use its internal processing resources to perform logical operations on the data stored in the internal storage array. Since the PIM device has the function of performing operations, it can reduce the communication between the PIM device and the external processor (such as the CPU) to save time and power, and can reduce the computing pressure of the central processor, but it brings about the problem of data consistency between the CPU and the PIM.

[0004] Existing solutions for achieving data consistency between CPU and PIM devices result in low software execution efficiency. Summary of the invention

[0005] The problem to be solved by the present invention is: to improve the software execution efficiency while achieving data consistency between the CPU and the PIM device.

[0006] To solve the above problem, an embodiment of the present invention provides a method for controlling a PIM device, the method comprising:

[0007] In response to receiving a new PIM instruction, modify the state of data in a data space corresponding to the new PIM instruction in a cache, and determine whether the PIM device has a previous PIM instruction; the previous PIM instruction includes: a PIM instruction being executed by the PIM device and a PIM instruction waiting to be executed;

[0008] In response to the existence of a previous PIM instruction in the PIM device, storing the new PIM instruction as a PMI instruction waiting to be executed;

[0009] In response to the PIM device not having a previous PIM instruction, sending the new PIM instruction to a memory controller corresponding to the PIM device, and the memory controller sending the new PIM instruction to the PIM device;

[0010] Wherein, the previous PIM instruction of the PIM device is updated in real time.

[0011] In a possible embodiment, the new PIM instruction is received through the first PIM interface or generated through an internal register.

[0012] In a possible embodiment, the method further includes:

[0013] The instruction execution status of the PIM device is monitored to update the previous PIM instruction based on the monitoring result.

[0014] In a possible embodiment, monitoring the instruction execution status of the PIM device includes any one of the following:

[0015] Receiving a first instruction status feedback signal sent by the PIM device;

[0016] A second instruction status feedback signal sent by the memory controller is received.

[0017] In a possible embodiment, the method further includes:

[0018] After obtaining the monitoring result, the instruction execution status of the PIM device is fed back to the CPU.

[0019] In a possible embodiment, the method further includes:

[0020] In response to receiving a non-PMI instruction, acquiring a data space accessed by the non-PMI instruction;

[0021] In response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, sending the non-PMI instruction to a memory controller corresponding to the PIM device, and the memory controller sending the non-PMI instruction to the PIM device;

[0022] In response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, the non-PMI instruction is stored as a non-PMI instruction waiting to be executed.

[0023] An embodiment of the present invention further provides a PIM device control device, the device comprising:

[0024] A previous PIM instruction storage unit, adapted to store previous PIM instructions of a PIM device, wherein the previous PIM instructions include: PIM instructions being executed by the PIM device and PIM instructions waiting to be executed;

[0025] and a control unit adapted to, in response to receiving a new PIM instruction, modify the state of data in a data space corresponding to the new PIM instruction in a cache, and determine whether the PIM device has a previous PIM instruction; in response to the PIM device having a previous PIM instruction, store the new PIM instruction as a PIM instruction waiting to be executed; and in response to the PIM device not having a previous PIM instruction, send the new PIM instruction to a memory controller corresponding to the PIM device, and the memory controller sends the new PIM instruction to the PIM device;

[0026] Wherein, the previous PIM instructions stored in the previous PIM instruction storage unit are updated in real time.

[0027] In a possible embodiment, the device further includes:

[0028] The first PIM interface is adapted to receive the new PIM instruction.

[0029] In a possible embodiment, the device further includes:

[0030] A first AXI interface, adapted to receive a register configuration instruction sent by the CPU;

[0031] The control unit is adapted to modify the internal register configuration based on the register configuration instruction to generate the new PIM instruction.

[0032] In a possible embodiment, the device further includes:

[0033] The state monitoring unit is adapted to monitor the instruction execution state of the PIM device and send the monitoring result to the previous PIM instruction storage unit, so that the previous PIM instruction storage unit updates the previous PIM instruction based on the monitoring result.

[0034] In a possible embodiment, the apparatus further includes: a second PIM interface, adapted to receive a first instruction state feedback signal sent by the PIM device;

[0035] The state monitoring unit is adapted to obtain the instruction execution state of the PIM device through the first instruction state feedback signal.

[0036] In a possible embodiment, the device further includes: a second AXI interface, adapted to receive a second instruction status feedback signal sent by the memory controller;

[0037] The state monitoring unit is adapted to obtain the instruction execution state of the PIM device through the second instruction state feedback signal.

[0038] In a possible embodiment, the status monitoring unit is further adapted to feed back the instruction execution status of the PIM device to the CPU after obtaining the monitoring result.

[0039] In a possible embodiment, the device further includes:

[0040] The address monitoring unit is adapted to, in response to receiving a non-PMI instruction, obtain a data space accessed by the non-PMI instruction; in response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, send the non-PMI instruction to a memory controller corresponding to the PIM device, and the memory controller sends the non-PMI instruction to the PIM device; and in response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, store the non-PMI instruction as a non-PMI instruction waiting to be executed.

[0041] An embodiment of the present invention further provides a PIM system, the system comprising:

[0042] Any of the above PIM equipment control devices;

[0043] Memory controller;

[0044] and PIM equipment;

[0045] Wherein, the control device of the PIM device is located between the memory controller and the CPU; the memory controller is located between the control device of the PIM device and the PIM device;

[0046] The control device of the PIM device is adapted to receive instructions sent by the CPU, and control the PIM device through the memory controller based on the received instructions.

[0047] In a possible embodiment, the memory in the PIM device is a double rate synchronous dynamic random access memory.

[0048] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any of the above methods.

[0049] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.

[0050] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0051] By applying the scheme of the present invention, when a PIM instruction is received, on the one hand, the state of the data in the data space corresponding to the new PIM instruction in the cache is modified, so as to avoid the CPU obtaining a data copy from the cache when the new PIM instruction is being executed or waiting to be executed, thereby affecting the atomic operability of the new PIM instruction; on the other hand, it is determined whether the PIM device has a previous PIM instruction. If there is a previous PIM instruction, the new PIM instruction is stored as a PIM instruction waiting to be executed, rather than directly executing the new PIM instruction. Only when the PIM device does not have a previous PIM instruction, the PIM device is controlled to execute the new PIM instruction, thereby ensuring the atomic operability of the previous PIM instruction. Thus, the consistency of data between the CPU and the PIM device can be achieved. Compared with the method of inserting the order-preserving instruction to achieve the consistency of data between the CPU and the PIM device, the corresponding control operation is executed based on the PIM instruction sent by the CPU, and the software developer does not need to decide when to start the execution, thereby reducing the difficulty of software development and avoiding the impact of the software execution efficiency due to the insertion of the order-preserving instruction. Compared with making the memory in the PIM device a dedicated memory to achieve data consistency between the CPU and the PIM device, the CPU can indirectly access the PIM device when the PIM device needs to perform corresponding operations, without spending extra time on message interaction, thereby improving software execution efficiency. In addition, by indirectly accessing the PIM device, the storage space of the PIM device can be used to avoid storage space waste, and the memory in the PIM device and the memory inside the CPU can be uniformly addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of the structure of a PIM system in an embodiment of the present invention;

[0053] Figure 2 is a workflow diagram of a PIM system in an embodiment of the present invention;

[0054] Figure 3 is a structural schematic diagram of a PIM device control device in an embodiment of the present invention;

[0055] Figure 4 The present invention is a flowchart of a PIM device control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] Currently, the application of PIM is still in its early stages. To solve the problem of data consistency between CPU and PIM devices, the following two methods are usually used:

[0057] 1) Data synchronization through software instructions;

[0058] Specifically, special instructions such as the Instruction Synchronization Barrier (ISB) can be used for data synchronization. Taking the ISB instruction as an example, by inserting the ISB instruction in the software, the CPU will refresh all instructions in the pipeline, thereby ensuring that the previous instructions will not affect the execution of subsequent instructions, and that subsequent instructions will be re-acquired from the correct context.

[0059] With this method, data consistency relies on software programming, does not require special hardware, and is not dependent on the hardware environment. However, its disadvantages are: software development is difficult and execution efficiency is low.

[0060] Specifically, software developers originally did not need to care about the underlying hardware implementation. However, after the introduction of PIM, software developers need to clarify which calculations are performed by PIM and which are performed by CPU, so that they can insert ISB instructions at the correct location of the software program to avoid data inconsistency. This is not friendly to software development and makes software development difficult.

[0061] In addition, after inserting the ISB instruction, due to the existence of data crossing, the CPU often cannot run programs that are not related to data before executing the ISB instruction. It needs to wait until the ISB instruction is executed before it can run programs that are not related to data, which results in low software execution efficiency.

[0062] 2) Make the memory in the PIM device into a dedicated memory;

[0063] Specifically, the memory in the PIM device is used as a dedicated memory, which is not accessed by the CPU in the system when performing AI acceleration. This eliminates the possibility of data sharing and thus eliminates data consistency issues.

[0064] This method can fundamentally prevent data access interference without requiring special hardware and software. However, its disadvantages are: waste of storage space, low software execution efficiency and inflexible application.

[0065] Specifically, since the storage array in the memory is configured as a dedicated storage array for PIM operations, even if there is free storage space, it cannot be used by the CPU, resulting in a waste of storage space. In addition, the PIM device and the CPU need to spend extra time on message exchange before data exchange, resulting in very low software execution efficiency. Furthermore, in this method, the PIM plays the role of a graphics processing unit (GPU), and the memory in the PIM device and the memory inside the CPU cannot be uniformly addressed.

[0066] In view of this problem, the present invention provides a control method for a PIM device. With this method, when a PIM instruction is received, on the one hand, the atomic operability of the new PIM instruction can be guaranteed by modifying the state of the data in the data space corresponding to the new PIM instruction in the cache; on the other hand, when there is a previous PIM instruction, the new PIM instruction is stored as a PMI instruction waiting to be executed, rather than directly executing the new PIM instruction, thereby ensuring the atomic operability of the previous PIM instruction, and finally achieving data consistency between the CPU and the PIM device. Compared with the existing solution for achieving data consistency between the CPU and the PIM device, it can not only improve the software execution efficiency, but also reduce the difficulty of software development, be friendly to software developers, reduce the waste of storage space, and achieve unified addressing of the memory in the PIM device and the memory inside the CPU.

[0067] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0068] Figure 1 The figure is a schematic diagram of the structure of a PIM system in an embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram of the workflow of the PIM system in an embodiment of the present invention. Figure 2 The memory controller is omitted. Figure 1 and Figure 2 , the PIM system may include:

[0069] A control device 10 for the PIM device;

[0070] Memory controller 20;

[0071] and a PIM device 30 .

[0072] The control device 10 of the PIM device is located between the memory controller 20 and the CPU 50; the memory controller 20 is located between the control device 10 of the PIM device and the PIM device 30. The control device of the PIM device is adapted to receive instructions sent by the CPU, and control the PIM device 30 through the memory controller 20 based on the received instructions.

[0073] In a specific implementation, the PIM device 30 refers to a storage device including a PIM 301 and a memory 302. The PIM device 30 can use its own processing resources to perform operations on the data stored in the internal memory 302, and the operations include but are not limited to logical operations such as AND operations, NAND operations, or NOR operations.

[0074] In addition to the PIM 301 and the memory 302, the PIM device 30 may also include a logic control module 303. The logic control module 303 is used to control the operation logic of the data inside the memory 302, including timing, data encoding, data decoding, etc. The PIM device 30 also has a memory interface 304, through which the PIM device 30 can interact with the memory controller 20.

[0075] In a specific implementation, the memory controller 20 is located between the control device 10 of the PIM device and the PIM device 30 , and is used to directly control the PIM device 30 and is responsible for data exchange between the PIM device 30 and the CPU 50 .

[0076] In some embodiments, the memory 302 in the PIM device 30 may be a double data rate synchronous dynamic random access memory (DDR), and accordingly, the memory controller 20 may be a DDR controller, and the memory interface 304 may be an Advanced Extensible Interface (AXI).

[0077] In other embodiments, the memory 302 in the PIM device 30 may also be a flash memory. Accordingly, the memory controller 20 may be a flash memory controller, and the memory interface 304 may be an AXI interface.

[0078] In a specific implementation, the PIM system may further include: a cache 40 and a CPU 50. Figure 2 , the CPU 50 may be provided with a PIM interface, through which the CPU 50 may send a PIM instruction to the control device 10 of the PIM device. The CPU 50 may also be provided with an AXI interface, through which the CPU 50 may send a register configuration instruction to the control device 10 of the PIM device. After receiving the register configuration instruction, the control device 10 of the PIM device will modify the internal register to generate a PIM instruction. The CPU 50 also sends a non-PIM instruction (i.e., a normal memory access instruction) to the control device 10 of the PIM device through the AXI interface, thereby accessing the memory 302 inside the PIM device 30 through the control device 10 of the PIM device, including reading data from the memory 302 or writing data to the memory 302, etc.

[0079] The cache 40 serves as a buffer for data exchange between the CPU 50 and the memory 302, and stores a copy of part of the data in the memory 302. Figure 2In the cache 40, each cache line includes a tag bit, a valid bit, and a data item. The tag bit is used to identify the storage location of the data, the valid bit is used to identify the state of the data, and the data item is a copy of the data stored in the cache line.

[0080] When the CPU 50 needs to read data, it will first search for the required data from the cache 40, that is, query the flag bit of each cache line to determine whether the accessed data exists in the cache 40. If the data is found, a copy of the data can be directly read from the cache 40, and the valid bit of the data in the cache line is modified to an invalid (Invlid) state. If the data is not found, the CPU 50 will wait for the operation result of the PIM device 30.

[0081] In a specific implementation, the control device 10 of the PIM device may be provided with a cache interface. When receiving a PIM instruction, the cache 40 (eg, Figure 2 ⑤), the state of the data corresponding to the PIM instruction in the cache 40 is modified to an invalid state in time to avoid data inconsistency between the CPU 50 and the PIM device 30 due to the CPU 50 reading data from the cache 40 and processing it after sending the PIM instruction.

[0082] In the PIM system, the access of the CPU 50 to the PIM device 30 is divided into PIM access and ordinary access. Regardless of PIM access or ordinary access, when the CPU 50 needs to access the PIM device 30, it needs to first send an instruction to the control device 10 of the PIM device. If the instruction sent by the CPU 50 is a PIM instruction, the control device 10 of the PIM device translates the PIM instruction into an instruction that can be recognized by the memory controller 20, and then the memory controller 20 sends the instruction output by the control device 10 of the PIM device to the PIM 301 of the PIM device 30 (such as Figure 2 ①), so that PIM301 performs corresponding operations to complete the PIM access. After completing the access, PIM301 can feedback the instruction completion status to the control device 10 of the PIM device (as shown in FIG. Figure 2 After the PIM instruction access is completed, the corresponding data will be released, and the released data can be accessed again (such as Figure 2 (as shown in ③).

[0083] If the instruction sent by the CPU 50 is a non-PIM instruction, the control device 10 of the PIM device does not process the non-PIM instruction and directly forwards it to the memory controller 20, which then sends the non-PIM instruction to the PIM device 30 (e.g. Figure 2As described in ④), corresponding data operations are performed on the memory 302 to complete normal access.

[0084] Figure 3 1 is a schematic diagram of the structure of a PIM device control device 10 in an embodiment of the present invention. Figure 2 , the PIM device control device 10 may include: a prior PIM instruction storage unit 11 and a control unit 12. Wherein:

[0085] The previous PIM instruction storage unit 11 is adapted to store previous PIM instructions of the PIM device, wherein the previous PIM instructions include: PIM instructions being executed by the PIM device and PIM instructions waiting to be executed.

[0086] The control unit 12 is adapted to, in response to receiving a new PIM instruction, modify the state of data in a data space corresponding to the new PIM instruction in a cache, and determine whether the PIM device has a previous PIM instruction; in response to the existence of a previous PIM instruction for the PIM device, store the new PIM instruction as a PMI instruction waiting to be executed; and in response to the absence of a previous PIM instruction for the PIM device, send the new PIM instruction to a memory controller corresponding to the PIM device, and the memory controller sends the new PIM instruction to the PIM device.

[0087] In an embodiment of the present invention, the previous PIM instruction of the PIM device is updated in real time.

[0088] In a specific implementation, the previous PIM instructions stored in the previous PIM instruction storage unit 11 include the PIM instructions currently being executed by the PIM device and the PIM instructions waiting to be executed. The previous PIM instruction storage unit 11 can store the PIM instructions in a queue manner, for example, the PIM instructions can be stored in the order in which the PIM instructions are received. The PIM instructions received first can be located at the head of the queue, and the PIM instructions received later can be located at the tail of the queue. The PIM instructions at the head of the queue are preferentially sent to the PIM device for execution.

[0089] In a specific implementation, after the execution of the PIM instruction is completed, the previous PIM instruction stored in the previous PIM instruction storage unit 11 can be updated in real time, so that the previous PIM instruction stored in the previous PIM instruction storage unit 11 remains in the latest state, avoiding the execution of the PIM instruction being affected by the untimely update of the previous PIM instruction.

[0090] In an embodiment of the present invention, the control unit 12 may include: a cache modification subunit, a judgment subunit and a control subunit; wherein:

[0091] The cache modification subunit is adapted to modify the state of data in the data space corresponding to the new PIM instruction in the cache in response to receiving the new PIM instruction;

[0092] The determination subunit is adapted to determine whether the PIM device has a previous PIM instruction;

[0093] The execution subunit is adapted to store the new PIM instruction as a PMI instruction waiting to be executed in response to the existence of a previous PIM instruction in the PIM device; and send the new PIM instruction to a memory controller corresponding to the PIM device in response to the absence of a previous PIM instruction in the PIM device, and the memory controller sends the new PIM instruction to the PIM device.

[0094] Specifically, the PIM device control device 10 may be provided with a cache interface 13. When a new PIM instruction is received, the cache modification subunit queries whether there is a corresponding data copy in the cache through the cache interface. If there is a corresponding data copy, the cache modification subunit may modify the state of the data in the data space corresponding to the new PIM instruction in the cache to an invalid state. If there is no corresponding data copy, there is no need to modify the data state.

[0095] After the PIM device control apparatus 10 receives a new PIM instruction, the determination subunit may determine whether the PIM device has a previous PIM instruction, that is, query whether the previous PIM instruction storage unit 11 stores a previous PIM instruction. The previous PIM instruction may be a PIM instruction being executed by the PIM device or a PIM instruction waiting to be executed.

[0096] If there is a previous PIM instruction, the execution subunit can store the new PIM instruction as a PIM instruction waiting to be executed in the previous PIM instruction storage unit 11, and the new PIM instruction is stored in the queue of the previous PIM instruction. When all the PIM instructions before the new PIM instruction are executed, the new PIM instruction is sent to the PIM device through the memory controller. If there is no previous PIM instruction, the execution subunit does not need to store the new PIM instruction, and can send the new PIM instruction to the PIM device through the memory controller.

[0097] In a specific implementation, the PIM device control apparatus 10 may be provided with a first PIM interface 14 , through which the PIM instruction sent by the CPU is received.

[0098] In other embodiments, the PIM device control device 10 may also be provided with a first AXI interface 15. The PIM device control device 10 may receive a register configuration instruction through the first AXI interface 15. Accordingly, a register may be provided in the control unit 12, and upon receiving the register configuration instruction, the control unit 12 may modify the internal register configuration based on the register configuration instruction, thereby generating the new PIM instruction.

[0099] In an embodiment of the present invention, the PIM device control apparatus 10 may further include: a state monitoring unit 16. The state monitoring unit 16 is adapted to monitor the instruction execution state of the PIM device and send the monitoring result to the previous PIM instruction storage unit 11, so that the previous PIM instruction storage unit updates the previous PIM instruction based on the monitoring result 11.

[0100] In a specific implementation, the status monitoring unit 16 may monitor the instruction execution status of the PIM device in a variety of ways, which are not limited here.

[0101] In an embodiment of the present invention, the PIM device control apparatus 10 may further include: a second PIM interface 14, through which data interaction with the PIM device can be performed directly.

[0102] Specifically, the first instruction status feedback signal sent by the PIM device can be received through the second PIM interface 14. Accordingly, the status monitoring unit 16 is adapted to obtain the instruction execution status of the PIM device through the first instruction status feedback signal. At this time, the PIM device can directly feedback the instruction execution status to the PIM device control device 10 without feedback of the instruction execution status to the PIM device control device 10 through the memory controller, thereby reducing the inefficient reliance on the second AXI interface.

[0103] In an embodiment of the present invention, the PIM device control apparatus 10 may further include: a second AXI interface 17. The second AXI interface 17 may perform data exchange with a memory controller.

[0104] Specifically, the second AXI interface 17 receives the second instruction status feedback signal sent by the memory controller. At this time, the PIM device first feeds back the instruction execution status to the memory controller, and then the memory controller feeds back the instruction execution status fed back by the PIM device to the PIM device control device 10. The instruction execution status feedback can be performed using a conventional AXI interface, so that the PIM device control device 10 has better compatibility.

[0105] In a specific implementation, the status monitoring unit 16 may monitor each PIM instruction, or may monitor only some PIM instructions. When only some PIM instructions are monitored, the monitoring requirement may be indicated in the PIM instruction, thereby informing the status monitoring unit 16 whether the PIM instruction needs to be monitored.

[0106] Specifically, the PIM instruction may include the following contents: operation code, monitoring requirement, valid bit, data start address, data end address, result start address, and result end address. The operation code refers to the operation identifier indicated by the PIM instruction, such as indicating an OR operation or a NAND operation. The monitoring requirement refers to whether the execution of this instruction is monitored. The data start address and the data end address refer to the storage location of the operation to be performed by this instruction, so that the corresponding operation data can be obtained. The result start address and the result end address refer to the storage location of the operation result obtained after the completion of this operation.

[0107] By indicating the monitoring requirement in the PIM instruction, it is not necessary to monitor each PIM instruction. For example, PIM instructions that do not affect atomic operability may not be monitored, thereby improving the execution efficiency of the PIM device control apparatus 10 and reducing power consumption.

[0108] In an embodiment of the present invention, the state monitoring unit 16 is further adapted to feedback the instruction execution state of the PIM device to the CPU after obtaining the monitoring result. After receiving the monitoring result fed back by the state monitoring unit 16, the CPU can know that the corresponding PIM operation is completed, and obtain the data operation result from the result operation address set in the PIM instruction, and continue to execute the subsequent process.

[0109] In a specific implementation, the CPU can send not only PIM instructions but also non-PIM instructions to the PIM device control device 10. The PIM device control device 10 can receive non-PIM instructions through the first AXI interface 15, and the non-PIM instructions are common memory access instructions used to read or write data from the memory in the PIM device.

[0110] Since non-PIM instructions may access the space where data corresponding to the previous PIM instruction is located, in order to prevent the data corresponding to the previous PIM instruction from being read or written, thereby ensuring the atomic operability of the previous PIM instruction, the PIM device control apparatus 10 may further include: an address monitoring unit 18 .

[0111] The address monitoring unit 18 is adapted to, in response to receiving a non-PMI instruction, obtain a data space accessed by the non-PMI instruction; in response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, send the non-PMI instruction to a memory controller corresponding to the PIM device, and the memory controller sends the non-PMI instruction to the PIM device; and in response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, store the non-PMI instruction as a non-PMI instruction waiting to be executed.

[0112] Specifically, the address monitoring unit 18 may store the data space accessed by each previous PIM instruction. When a non-PMI instruction is received, the data space accessed by the non-PMI instruction may be compared with the data space accessed by each previous PIM instruction, so as to determine whether the non-PMI instruction accesses the data space accessed by the previous PIM instruction. If the non-PMI instruction does not access the data space accessed by the previous PIM instruction, the address monitoring unit 18 may directly send the non-PMI instruction to the memory controller through the second AXI interface 17. If the non-PMI instruction accesses the data space accessed by the previous PIM instruction, the non-PMI instruction needs to be stored as a non-PMI instruction waiting to be executed.

[0113] In a specific implementation, not only the first PIM instruction but also the non-PIM instruction can be stored in the first instruction storage unit 11. The non-PIM instruction can also be stored in a queue manner, and the first received non-PIM instruction is stored at the head of the queue and the second received non-PIM instruction is stored at the tail of the queue according to the instruction receiving order.

[0114] At this time, after obtaining the monitoring result, the status monitoring unit 16 can first send the monitoring result to the address monitoring unit 18, and the address monitoring unit 18 can update the data space accessed by the stored previous PIM instruction based on the monitoring result on the one hand, and send the monitoring result to the previous instruction storage unit 11 on the other hand, and the previous instruction storage unit 11 can update the previous instruction.

[0115] In a specific implementation, the PIM device control apparatus 10 may further include a gating unit MUX. The gating unit MUX may be connected to the control unit 12 and the address monitoring unit 18. The control unit 12 may provide a PIM instruction to the gating unit MUX, and the address monitoring unit 18 may provide a non-PIM instruction to the gating unit MUX.

[0116] The selection unit MUX can select the corresponding instructions to the second AXI interface 17 in a round robin manner. Specifically, when the selection unit MUX receives only the PIM instruction, the PIM instruction can be sent through the second AXI interface 17. When the selection unit MUX receives only the non-PIM instruction, the non-PIM instruction can be sent through the second AXI interface 17. When the selection unit MUX receives both the non-PIM instruction and the PIM instruction, the non-PIM instruction and the PIM instruction can be selected and sent through the second AXI interface 17 respectively.

[0117] It should be noted that the address monitoring unit 18 provides the non-PIM instruction to the selection unit MUX, which is a non-PIM instruction that does not overlap with the data space accessed by the previous instruction.

[0118] In a specific implementation, since the amount of data operated by the PIM instruction is usually large, the address monitoring requirements cannot be met through ordinary AXI access. Therefore, by setting the address monitoring unit 18, the amount of data monitored by the address can be adjusted to meet the PIM operation requirements. For example, the maximum amount of data monitored by the address monitoring unit 18 can be set to 16KB, thereby ensuring the effectiveness and accuracy of address monitoring.

[0119] The PIM device control device 10 in the embodiment of the present invention not only provides a data consistency solution for the PIM system, but also can effectively improve the software execution efficiency of the CPU. In addition, it can be easily integrated into the existing system on chip (SOC), with little cost for modifying the existing system on chip architecture and hardware, and can leave scalability for compatible PIM devices and memory controllers.

[0120] In order to enable those skilled in the art to better understand and implement the present invention, the method, computer-readable storage medium and electronic device corresponding to the above-mentioned device are described in detail below.

[0121] Reference Figure 4 , an embodiment of the present invention provides a method for controlling a PIM device, the method may include the following steps:

[0122] Step 41: in response to receiving a new PIM instruction, modify the state of data in a data space corresponding to the new PIM instruction in a cache.

[0123] In a specific implementation, the new PIM instruction may be received through the first PIM interface or generated through an internal register.

[0124] After receiving the new PIM instruction, the control device of the PIM device can query the cache to confirm whether there is a data copy in the data space corresponding to the new PIM instruction in the cache. If so, the state of the cache corresponding data copy is modified to avoid the CPU reading the data copy from the buffer later, which leads to data inconsistency. If not, the PIM device does not need to modify the state of the cache corresponding data copy.

[0125] Step 42, determining whether the PIM device has a previous PIM instruction.

[0126] The previous PIM instructions include: PIM instructions being executed by the PIM device and PIM instructions waiting to be executed.

[0127] In a specific implementation, the control device of the PIM device may confirm whether there is a previous PIM instruction by searching the stored previous instruction queue, so as to avoid directly sending the new PIM instruction to the PIM device and affecting the atomic operability of the previous PIM instruction.

[0128] Step 43: In response to the existence of a previous PIM instruction in the PIM device, the new PIM instruction is stored as a PMI instruction waiting to be executed.

[0129] In a specific implementation, when there is a previous PIM instruction, the new PIM instruction needs to wait until all current previous instructions are fully executed before being sent to the PIM device.

[0130] Step 44: In response to the PIM device not having a previous PIM instruction, the new PIM instruction is sent to a memory controller corresponding to the PIM device, and the memory controller sends the new PIM instruction to the PIM device.

[0131] In a specific implementation, if the PIM device does not have a previous PIM instruction, the new PIM instruction may be directly sent to the memory controller corresponding to the PIM device, so that the PIM device executes the new PIM instruction.

[0132] In a specific implementation, step 41 and step 42 may be executed simultaneously or sequentially, as long as the state of the data in the data space corresponding to the new PIM instruction in the cache can be modified before the CPU reads the data from the cache.

[0133] In some embodiments, the method may further include:

[0134] Step 45: monitor the instruction execution status of the PIM device to update the previous PIM instruction based on the monitoring result.

[0135] In a specific implementation, the instruction execution state of the PIM device can be monitored by receiving a first instruction state feedback signal sent by the M device, or by receiving a second instruction state feedback signal sent by the memory controller.

[0136] In some embodiments, the method may further include:

[0137] Step 46: After obtaining the monitoring result, the instruction execution status of the PIM device is fed back to the CPU.

[0138] In a specific implementation, after receiving the monitoring result fed back by the status monitoring unit 16, the CPU can know that the corresponding PIM operation is finished, and obtain the data operation result from the result operation address set in the PIM instruction, and continue to execute the subsequent process.

[0139] In some embodiments, the method may further include:

[0140] Step 47: In response to receiving a non-PMI instruction, obtaining a data space accessed by the non-PMI instruction.

[0141] In a specific implementation, if a non-PIM instruction is received, the data space to be accessed can be directly extracted from the non-PIM instruction.

[0142] Step 48: Determine whether the data space accessed by the non-PMI instruction overlaps with the data space accessed by the previous PIM instruction.

[0143] In order to ensure the atomic operability of the PIM instruction, after receiving the non-PIM instruction, the data space accessed by the non-PIM instruction may be compared with the data space accessed by the previous PIM instruction to determine whether the two overlap.

[0144] Step 49: In response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, the non-PMI instruction is sent to a memory controller corresponding to the PIM device, and the memory controller sends the non-PMI instruction to the PIM device.

[0145] In a specific implementation, the data space accessed by the non-PMI instruction does not overlap with the data space accessed by the previous PIM instruction, indicating that the non-PMI instruction will not access the data space accessed by the previous PIM instruction, so the non-PMI instruction can be sent to the PIM device for execution.

[0146] Step 50: In response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, storing the non-PMI instruction as a non-PMI instruction waiting to be executed.

[0147] In a specific implementation, if the data space accessed by the non-PMI instruction partially overlaps or completely overlaps with the data space accessed by the previous PIM instruction, it indicates that the non-PMI instruction will access the data space accessed by the previous PIM instruction, and therefore the non-PMI instruction needs to be controlled to wait for execution. For example, the non-PMI instruction can be stored in a non-PMI instruction waiting queue to wait for execution.

[0148] It can be seen from the above content that the control method of the PIM device in the embodiment of the present invention can not only achieve data consistency, but also is friendly to software programming, can be used in the system on chip, and can perform unified addressing with the CPU.

[0149] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any of the above methods.

[0150] In a specific implementation, the computer-readable storage medium may include: ROM, RAM, magnetic disk or optical disk, etc.

[0151] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor executes the steps of any of the above methods when running the computer program.

[0152] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units can be implemented in the form of hardware such as circuits. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits.

[0153] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for controlling a PIM device, characterized in that: include: In response to receiving a new PIM instruction, modifying the state of data in a data space corresponding to the new PIM instruction in a cache, and determining whether the PIM device has a previous PIM instruction; the previous PIM instruction includes: a PIM instruction being executed by the PIM device and a PIM instruction waiting to be executed; in response to the PIM device having a previous PIM instruction, storing the new PIM instruction as a PIM instruction waiting to be executed; In response to the PIM device not having a previous PIM instruction, sending the new PIM instruction to a memory controller corresponding to the PIM device, and the memory controller sending the new PIM instruction to the PIM device; Wherein, the previous PIM instruction of the PIM device is updated in real time.

2. The method for controlling a PIM device according to claim 1, wherein: The new PIM instruction is received through the first PIM interface or generated through an internal register.

3. The method for controlling a PIM device according to claim 1, wherein: Also includes: The instruction execution status of the PIM device is monitored to update the previous PIM instruction based on the monitoring result.

4. The method for controlling a PIM device according to claim 3, wherein: The monitoring of the instruction execution status of the PIM device includes any one of the following: Receiving a first instruction status feedback signal sent by the PIM device; A second instruction status feedback signal sent by the memory controller is received.

5. The method for controlling a PIM device according to claim 3, wherein: Also includes: After obtaining the monitoring result, the instruction execution status of the PIM device is fed back to the CPU.

6. The method for controlling a PIM device according to claim 1, wherein: Also includes: In response to receiving a non-PMI instruction, acquiring a data space accessed by the non-PMI instruction; In response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, sending the non-PMI instruction to a memory controller corresponding to the PIM device, and the memory controller sending the non-PMI instruction to the PIM device; In response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, the non-PMI instruction is stored as a non-PMI instruction waiting to be executed.

7. A PIM device control device, characterized in that: include: A previous PIM instruction storage unit, adapted to store previous PIM instructions of a PIM device, wherein the previous PIM instructions include: PIM instructions being executed by the PIM device and PIM instructions waiting to be executed; and a control unit adapted to, in response to receiving a new PIM instruction, modify the state of data in a data space corresponding to the new PIM instruction in a cache, and determine whether the PIM device has a previous PIM instruction; in response to the PIM device having a previous PIM instruction, store the new PIM instruction as a PIM instruction waiting to be executed; and in response to the PIM device not having a previous PIM instruction, send the new PIM instruction to a memory controller corresponding to the PIM device, and the memory controller sends the new PIM instruction to the PIM device; Wherein, the previous PIM instructions stored in the previous PIM instruction storage unit are updated in real time.

8. The PIM device control device according to claim 7, characterized in that: Also includes: The first PIM interface is adapted to receive the new PIM instruction.

9. The PIM device control device according to claim 7, characterized in that: Also includes: A first AXI interface, adapted to receive a register configuration instruction sent by the CPU; The control unit is adapted to modify the internal register configuration based on the register configuration instruction to generate the new PIM instruction.

10. The PIM device control device according to claim 7, characterized in that: Also includes: The state monitoring unit is adapted to monitor the instruction execution state of the PIM device and send the monitoring result to the previous PIM instruction storage unit, so that the previous PIM instruction storage unit updates the previous PIM instruction based on the monitoring result.

11. The PIM device control device according to claim 10, characterized in that: Also includes: A second PIM interface, adapted to receive a first instruction status feedback signal sent by the PIM device; The state monitoring unit is adapted to obtain the instruction execution state of the PIM device through the first instruction state feedback signal.

12. The PIM device control device according to claim 10, characterized in that: Also includes: A second AXI interface, adapted to receive a second instruction status feedback signal sent by the memory controller; The state monitoring unit is adapted to obtain the instruction execution state of the PIM device through the second instruction state feedback signal.

13. The PIM device control device according to claim 10, characterized in that: The state monitoring unit is further adapted to feed back the instruction execution state of the PIM device to the CPU after obtaining the monitoring result.

14. The PIM device control device according to claim 8, characterized in that: Also includes: an address monitoring unit adapted to, in response to receiving a non-PMI instruction, obtain a data space accessed by the non-PMI instruction, and in response to the data space accessed by the non-PMI instruction not overlapping with the data space accessed by the previous PIM instruction, send the non-PMI instruction to a memory controller corresponding to the PIM device, and the memory controller sends the non-PMI instruction to the PIM device; And in response to the data space accessed by the non-PMI instruction at least partially overlapping with the data space accessed by the previous PIM instruction, storing the non-PMI instruction as a non-PMI instruction waiting to be executed.

15. A PIM system, characterized in that: include: The PIM device control device according to any one of claims 7 to 14; Memory controller; and PIM equipment; Wherein, the control device of the PIM device is located between the memory controller and the CPU; The memory controller is located between the control device of the PIM device and the PIM device; the control device of the PIM device is adapted to receive instructions sent by the CPU, and control the PIM device through the memory controller based on the received instructions.

16. The PIM system according to claim 15, wherein: The memory in the PIM device is a double rate synchronous dynamic random access memory.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 6.

18. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor runs the computer program, the steps of the method according to any one of claims 1 to 6 are performed.

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