Transistor structure and method for forming the same

Abstract

The present disclosure relates to a transistor structure and a method for forming the same. The transistor structure comprises: a first dielectric layer, the first dielectric layer comprising passivating oxygen vacancies; an active layer located on the surface of the first dielectric layer, the active layer comprising a channel region and a source / drain region located outside the channel region; a gate layer located on the side of the channel region facing away from the first dielectric layer; and a barrier layer located between the first dielectric layer and the source / drain region, the barrier layer being used to block oxygen from entering the source / drain region. The present disclosure enables a positive shift in the threshold voltage of the transistor structure and reduces the subthreshold swing of the transistor structure, thereby improving the response speed of the transistor structure and preventing an increase in RC delay.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a transistor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to a capacitor. The word line voltage on the word line can control the on and off of the transistor, thereby allowing data stored in the capacitor to be read or written through the bit line.

[0003] The presence of oxygen vacancies in transistor structures can seriously affect the performance of the transistor structure. For example, oxygen vacancies can cause the threshold voltage of the transistor structure to shift negatively, thereby causing substrate leakage or retention time, ultimately affecting the performance of semiconductor devices such as DRAM.

[0004] Therefore, how to improve the performance of transistor structures and thus improve the performance of semiconductor devices such as DRAM is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a transistor structure and a method for forming the same, for improving the performance of the transistor structure.

[0006] According to some embodiments, the present disclosure provides a transistor structure including:

[0007] a first dielectric layer, wherein the first dielectric layer includes passivating oxygen vacancies;

[0008] an active layer located on a surface of the first dielectric layer, wherein the active layer includes a channel region and a source / drain region located outside the channel region;

[0009] a gate layer, located on a side of the channel region away from the first dielectric layer;

[0010] The barrier layer is located between the first dielectric layer and the source / drain region, and is used to block oxygen from entering the source / drain region.

[0011] In some embodiments, the active layer is distributed around the periphery of the first dielectric layer, the gate layer is distributed around the periphery of the channel region, and the barrier layer is distributed around an end portion of the first dielectric layer.

[0012] In some embodiments, the first dielectric layer includes a first portion corresponding to the channel region, and a second portion located outside the first portion and corresponding to the source and drain region;

[0013] The sum of the thickness of the second portion and the thickness of the barrier layer is equal to the thickness of the first portion.

[0014] In some embodiments, it further includes:

[0015] The second dielectric layer is located between the gate layer and the channel region, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

[0016] In some embodiments, the material of the channel region and the material of the source and drain regions both include oxide semiconductor materials, and the resistance value of the source and drain regions is smaller than the resistance value of the channel region.

[0017] In some embodiments, the active layer includes a first active layer and a second active layer distributed on opposite sides of the first dielectric layer along a first direction, the channel region includes a first channel region located in the first active layer and a second channel region located in the second active layer, and the first channel region and the second channel region are symmetrically distributed with respect to the first dielectric layer;

[0018] The gate layer includes a first gate layer and a second gate layer distributed on opposite sides of the first dielectric layer along the first direction. The first gate layer is located on the first channel region, and the second gate layer is located on the second channel region.

[0019] According to some other embodiments, the present disclosure further provides a method for forming a transistor structure, comprising the following steps:

[0020] providing a substrate;

[0021] A first dielectric layer, an active layer, a gate layer, and a barrier layer are formed on the substrate, wherein the first dielectric layer includes passivated oxygen vacancies, the active layer is located on the surface of the first dielectric layer, and the active layer includes a channel region and a source / drain region located outside the channel region, the gate layer is located on a side of the channel region facing away from the first dielectric layer, and the barrier layer is located between the first dielectric layer and the source / drain region, and is used to prevent oxygen from entering the source / drain region.

[0022] In some embodiments, the specific steps of forming the first dielectric layer, the active layer, the gate layer, and the barrier layer on the substrate include:

[0023] forming the first dielectric layer on the substrate;

[0024] forming the barrier layer distributed around the end of the first dielectric layer;

[0025] forming the active layer distributed around the periphery of the first dielectric layer and the periphery of the barrier layer, wherein the channel region in the active layer is distributed around the periphery of the first dielectric layer, and the source / drain region in the active layer is distributed around the periphery of the barrier layer;

[0026] forming the gate layer distributed around the periphery of the channel region;

[0027] The oxygen vacancies in the first dielectric layer are passivated to form the passivated oxygen vacancies.

[0028] In some embodiments, the specific steps of forming the first dielectric layer, the active layer, the gate layer, and the barrier layer on the substrate include:

[0029] forming a first gate layer on the substrate;

[0030] forming a first active layer on the first gate layer;

[0031] forming a first barrier layer on the first active layer;

[0032] forming a first dielectric layer on the first active layer and the first barrier layer;

[0033] forming a second barrier layer on the first dielectric layer, wherein the first barrier layer and the second barrier layer together serve as the barrier layer;

[0034] forming a second active layer on the first dielectric layer and the second barrier layer, and using the first active layer and the second active layer together as the active layer;

[0035] forming a second gate layer on the second active layer, and using the first gate layer and the second gate layer together as the gate layer;

[0036] The oxygen vacancies in the first dielectric layer are passivated to form the passivated oxygen vacancies.

[0037] In some embodiments, the specific steps of forming the first active layer on the first gate layer include:

[0038] forming a first isolation layer on the substrate and located on opposite sides of the first gate layer;

[0039] Depositing a first oxide semiconductor material on the substrate to form a first channel region above the first gate layer and an initial first source and drain region above the first isolation layer;

[0040] The initial first source and drain regions are subjected to a resistance reduction treatment to form first source and drain regions.

[0041] Some embodiments of the present disclosure provide transistor structures and methods for forming the same. By providing a first dielectric layer with an active layer located on the surface of the first dielectric layer, the first dielectric layer includes passivating oxygen vacancies, thereby shifting the threshold voltage of the transistor structure positively, reducing substrate leakage, and enabling the transistor structure to have a longer retention time. The present disclosure also provides a barrier layer between the first dielectric layer and the source and drain regions of the active layer to prevent oxygen from entering the source and drain regions when passivating the oxygen vacancies in the first dielectric layer, thereby preventing an increase in RC (resistance-capacitance) delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Attachment Figure 1 is a schematic cross-sectional view of a transistor structure in a specific embodiment of the present disclosure;

[0043] Attachment Figure 2 is a three-dimensional schematic diagram of a transistor structure in a specific embodiment of the present disclosure;

[0044] Attachment Figure 3 is a flow chart of a method for forming a transistor structure in a specific embodiment of the present disclosure;

[0045] Attachment Figure 4 -Attached Figure 13 It is a schematic diagram of the main process structure in the process of forming a transistor structure in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The specific embodiments of the transistor structure and the method for forming the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0047] This embodiment provides a transistor structure. Figure 1 is a cross-sectional schematic diagram of a transistor structure in a specific embodiment of the present disclosure, Figure 2 FIG. 1 is a perspective diagram of a transistor structure in a specific embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the transistor structure includes:

[0048] A first dielectric layer 15, wherein the first dielectric layer 15 includes passivating oxygen vacancies;

[0049] an active layer 17 located on a surface of the first dielectric layer 15 , wherein the active layer 17 includes a channel region 10 and source and drain regions located outside the channel region 10 ;

[0050] a gate layer 13 located on a side of the channel region 10 away from the first dielectric layer 15;

[0051] The barrier layer 16 is located between the first dielectric layer 15 and the source / drain region. The barrier layer 16 is used to prevent oxygen from entering the source / drain region.

[0052] The transistor structure described in this specific embodiment may be a transistor structure located in a semiconductor device such as a DRAM. In one example, the transistor structure is used to constitute a memory cell in a semiconductor device such as a DRAM. The material of the first dielectric layer 15 may be an oxide material, such as silicon dioxide. The inclusion of passivated oxygen vacancies in the first dielectric layer 15 means that the oxygen vacancies in the first dielectric layer 15 are passivated to form the passivated oxygen vacancies. The active layer 17 covers the surface of the first dielectric layer 15, and the active layer 17 includes the channel region 10, and an active layer 17 extending in the direction of the active layer 17 (e.g., Figure 1 The gate layer 13 is located on the channel region 10 along a first direction D1, and the first direction D1 intersects the second direction D2. The barrier layer 16 is located between the first dielectric layer 15 and the source region 11, and between the first dielectric layer 15 and the drain region 12.

[0053] This specific embodiment provides the first dielectric layer 15 in the transistor structure and passivates the oxygen vacancies in the first dielectric layer 15 to form passivated oxygen vacancies. This reduces the concentration of oxygen vacancies in the first dielectric layer 15, thereby shifting the threshold voltage of the transistor structure positively, reducing substrate leakage, and providing the transistor structure with a longer retention time. It also reduces the subthreshold swing of the transistor structure, thereby improving the response speed of the transistor structure. Furthermore, this specific embodiment provides the barrier layer 16 between the source and drain regions of the transistor structure and the first dielectric layer 15. This prevents oxygen, or other atmosphere, from entering the source and drain regions when the first dielectric layer 15 is annealed in an atmosphere such as oxygen to passivate the oxygen vacancies in the first dielectric layer 15, thereby preventing an increase in RC (resistance-capacitance) delay.

[0054] In some embodiments, the active layer 17 is distributed around the periphery of the first dielectric layer 15 , the gate layer 13 is distributed around the periphery of the channel region 10 , and the barrier layer 16 is distributed around an end portion of the first dielectric layer 15 .

[0055] For example, if Figure 2As shown, the transistor structure has a vertical gate-all-around (VGAA) structure. The active layer 17 is entirely distributed around the periphery of the first dielectric layer 15, the gate layer 13 is distributed around the periphery of the channel region 10, and the barrier layer is distributed around the peripheries of both ends of the first dielectric layer 15. By adopting the method of distributing the active layer 17 entirely around the periphery of the first dielectric layer 15 and the gate layer 13 around the periphery of the channel region 10, the size of the transistor structure can be further reduced, thereby further increasing the storage density of the memory including the transistor structure.

[0056] In some embodiments, the first dielectric layer 15 includes a first portion corresponding to the channel region 10 and a second portion located outside the first portion and corresponding to the source and drain regions;

[0057] The sum of the thickness of the second portion and the thickness of the barrier layer 16 is equal to the thickness of the first portion.

[0058] Specifically, the first dielectric layer 15 includes a first portion covered by the channel region 10 and a second portion covered by the source and drain regions. The second portion is distributed along the second direction D2 on opposite sides of the first portion. The sum of the thickness of the second portion along the first direction D1 and the thickness of the barrier layer 16 along the first direction D1 is equal to the thickness of the first portion along the first direction D1. This simplifies the formation process of the active layer 17, resulting in a flat surface of the formed active layer 17, thereby further ensuring the stability of the performance of the transistor structure. In one example, the second portion of the first dielectric layer 15 is connected to the end of the first portion, and the first and second portions are made of the same material and formed simultaneously.

[0059] In some embodiments, the transistor structure further comprises:

[0060] The second dielectric layer 14 is located between the gate layer 13 and the channel region 10 . The dielectric constant of the second dielectric layer 14 is greater than that of the first dielectric layer 15 .

[0061] Specifically, the second dielectric layer 14 is located between the gate layer 13 and the channel region 10, serving as the gate dielectric layer of the transistor structure. The material of the second dielectric layer 14 can be a high-K dielectric material, such as one or a combination of two or more of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide, and strontium titanate. By setting the dielectric constant of the second dielectric layer 14 to be greater than the dielectric constant of the first dielectric layer 15, the short channel effect of the transistor structure is further suppressed, and the gate control capability of the transistor structure is improved.

[0062] In some embodiments, the material of the channel region 10 and the material of the source and drain regions both include oxide semiconductor materials, and the resistance value of the source and drain regions is smaller than the resistance value of the channel region 10 .

[0063] For example, the channel region 10 and the source / drain region (including the source region 11 and the drain region 12) are both made of IGZO (Indium Gallium Zinc Oxide). By performing a resistance-reducing treatment on the IGZO in the source / drain region, the resistance of the source / drain region can be made lower than that of the channel region 10, thereby ensuring the conductive performance of the source / drain region.

[0064] In some embodiments, the active layer 10 includes a first active layer and a second active layer distributed on opposite sides of the first dielectric layer 15 along a first direction D1, and the channel region 10 includes a first channel region 101 located in the first active layer and a second channel region 102 located in the second active layer, and the first channel region 101 and the second channel region 102 are symmetrically distributed with respect to the first dielectric layer 15;

[0065] The gate layer 13 includes a first gate layer 131 and a second gate layer 132 distributed on opposite sides of the first dielectric layer 15 along the first direction D1. The first gate layer 131 is located on the first channel region 101 , and the second gate layer 132 is located on the second channel region 102 .

[0066] For example, if Figure 1As shown, the first active layer includes a first channel region 101, and a first source region 111 and a first drain region 121 distributed along the second direction D2 on opposite sides of the first channel region 101. The first source region 111 and the first drain region 121 together constitute the first source and drain region of the first active layer. The second active layer is located on a side of the first dielectric layer 15 facing away from the first active layer along the first direction D1. The second active layer includes a second channel region 102, and a second source region 112 and a second drain region 122 distributed along the second direction D2 on opposite sides of the second channel region 102. The second source region 112 and the second drain region 122 together constitute the second source and drain region of the second active layer. The first channel region 101 and the second channel region 102 together constitute the channel region 10 of the active layer, and the first source and drain regions together constitute the source and drain regions of the active layer. The first channel region 101 and the second channel region 102 are symmetrically distributed with respect to the first dielectric layer 15. The first source region 111 and the second source region 112 are symmetrically distributed with respect to the first dielectric layer 15. The first drain region 121 and the second drain region 122 are also symmetrically distributed with respect to the first dielectric layer 15. The barrier layer 16 includes a first barrier layer 161 located between the first dielectric layer 15 and the first source and drain regions, and a second barrier layer 162 located between the first dielectric layer 15 and the second source and drain regions. The second dielectric layer 14 includes a first gate dielectric layer 141 located between the first channel region 101 and the first gate layer 131, and a second gate dielectric layer 142 located between the second channel region 102 and the second gate layer 132. The above structure forms a transistor structure having a dual-gate structure, thereby further improving the gate control capability of the transistor structure.

[0067] This embodiment also provides a method for forming a transistor structure. Figure 3 is a flow chart of a method for forming a transistor structure in a specific embodiment of the present disclosure, Figure 4 -Attached Figure 13 This is a schematic diagram of the main process structure in the process of forming a transistor structure in the specific embodiment of the present disclosure. The schematic diagram of the transistor structure formed in this specific embodiment can be found in Figure 1 and Figure 2 .like Figures 1-13 As shown, the method for forming the transistor structure includes the following steps:

[0068] Step S31, providing a substrate 40, such as Figure 4 As shown;

[0069] Step S32: forming a first dielectric layer 15, an active layer 17, a gate layer 13, and a barrier layer 16 on the substrate 40, wherein the first dielectric layer 15 includes passivated oxygen vacancies, the active layer 17 is located on the surface of the first dielectric layer 15, and the active layer 17 includes a channel region 10 and a source / drain region located outside the channel region 10, the gate layer 13 is located on a side of the channel region 10 away from the first dielectric layer 15, and the barrier layer 16 is located between the first dielectric layer 15 and the source / drain region, and the barrier layer 16 is used to prevent oxygen from entering the source / drain region. Figure 1 、 Figure 13 or Figure 2 shown.

[0070] The substrate 40 may be, but is not limited to, a silicon substrate. This embodiment is described using a silicon substrate as an example. In other embodiments, the substrate 40 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.

[0071] In order to further reduce the size of the transistor structure, in some embodiments, the specific steps of forming the first dielectric layer 15, the active layer 17, the gate layer 13 and the barrier layer 16 on the substrate 40 include:

[0072] forming the first dielectric layer 15 on the substrate 40;

[0073] forming the barrier layer 16 distributed around the end of the first dielectric layer 15;

[0074] forming the active layer 17 distributed around the periphery of the first dielectric layer 15 and the periphery of the barrier layer 16, wherein the channel region 10 in the active layer 17 is distributed around the periphery of the first dielectric layer 15, and the source and drain regions in the active layer 17 are distributed around the periphery of the barrier layer 16;

[0075] forming the gate layer 13 distributed around the periphery of the channel region 10;

[0076] The oxygen vacancies in the first dielectric layer 15 are passivated to form the passivated oxygen vacancies, such as Figure 2 shown.

[0077] For example, an oxide material (e.g., silicon dioxide) is deposited on the substrate 40 to form the first dielectric layer 15. Subsequently, the opposite ends of the first dielectric layer 15 are laterally etched to reduce the thickness of the opposite ends of the first dielectric layer 15. Next, a material such as a nitride (e.g., silicon nitride) is deposited on the ends of the thinned first dielectric layer 15 to form the barrier layer 16 distributed around the ends of the first dielectric layer 15. Then, an oxide semiconductor material such as IGZO is deposited on the first dielectric layer 15 and the barrier layer 16 to form an initial active layer. An initial channel region, as well as initial source and drain regions located on opposite sides of the initial channel region, are defined in the initial active layer. The initial source and drain regions are subjected to a resistance reduction treatment (e.g., rapid thermal annealing or ion implantation) to form the source and drain regions 11 and 12. The initial channel region that has not undergone the resistance reduction treatment serves as the channel region 10. A high-K dielectric material is deposited on the channel region 10 to form a second dielectric layer 14 surrounding the periphery of the channel region 10. A conductive material such as TiN or metal tungsten is deposited on the second dielectric layer 14 to form the gate layer 13 surrounding the periphery of the channel region 10. Figure 2 shown.

[0078] In order to further improve the gate control performance of the transistor structure, in some other embodiments, the specific steps of forming the first dielectric layer 15, the active layer 17, the gate layer 13 and the barrier layer 16 on the substrate 40 include:

[0079] A first gate layer 131 is formed on the substrate 40, as shown in FIG. Figure 6 As shown;

[0080] A first active layer is formed on the first gate layer 131, such as Figure 10 As shown;

[0081] A first barrier layer 161 is formed on the first active layer, such as Figure 11 As shown;

[0082] A first dielectric layer 15 is formed on the first active layer and the first barrier layer 161, as shown in FIG. Figure 12 As shown;

[0083] A second barrier layer 162 is formed on the first dielectric layer 15. The first barrier layer 161 and the second barrier layer 162 serve together as the barrier layer 16. Figure 12 As shown;

[0084] A second active layer is formed on the first dielectric layer 15 and the second barrier layer 162, and the first active layer and the second active layer are used together as the active layer 17. Figure 13 As shown;

[0085] A second gate layer 132 is formed on the second active layer, and the first gate layer 131 and the second gate layer 132 are used together as the gate layer 13. Figure 13 As shown;

[0086] The oxygen vacancies in the first dielectric layer 15 are passivated to form the passivated oxygen vacancies, such as Figure 1 and Figure 13 shown.

[0087] In some embodiments, the specific steps of forming the first active layer on the first gate layer 131 include:

[0088] A first isolation layer 70 is formed on the substrate 40 and located on opposite sides of the first gate layer 131. Figure 7 As shown;

[0089] Depositing a first oxide semiconductor material on the substrate 40 to form a first channel region 101 located above the first gate layer 131 and forming an initial first source and drain region located above the first isolation layer 70;

[0090] The initial first source and drain regions are subjected to a resistance reduction treatment to form first source and drain regions, such as Figure 10 shown.

[0091] For example, a conductive material such as TiN or metal tungsten is deposited on the surface of the substrate 40 to form the first gate layer 131, and a high-K material is deposited on the surface of the first gate layer 131 to form the first gate dielectric layer 141. Figure 5 The first gate layer 131 and the first gate dielectric layer 141 are patterned by dry etching process to remove part of the first gate layer 131 and part of the first gate dielectric layer 141, and the following is obtained: Figure 6 Next, a dielectric material such as oxide is deposited on the substrate 40 to form the first isolation layer 70 located on opposite sides of the first gate layer 131 and the first gate dielectric layer 141, as shown in FIG. Figure 7 As shown. The top surface of the first isolation layer 70 (i.e., the surface of the first isolation layer 70 facing away from the substrate 40) is flush with the top surface of the first gate dielectric layer 141 (i.e., the surface of the first gate dielectric layer 141 facing away from the first gate layer 131) to facilitate the subsequent formation of the first active layer. Afterwards, an oxide semiconductor material such as IGZO is deposited on the substrate 40 to form an initial first active layer 80 covering the first gate dielectric layer 141 and the first isolation layer 70, as shown. Figure 8As shown. An initial first channel region, and an initial first source region and an initial first drain region located on opposite sides of the initial first channel region are defined in the initial first active layer 80. For example, the initial first active layer 80 above the first gate dielectric layer 141 is used as the initial first channel region, and the initial first active layer 80 above the first isolation layer 70 is used as the initial first source region and the initial first drain region, respectively. Next, a resistance reduction treatment is performed on the oxide semiconductor material in the initial first source region and the first drain region. The resistance reduction treatment step includes: forming a first protective layer 90 covering the initial first channel region in the initial first active layer 80, as shown in FIG. Figure 9 As shown; the exposed initial first source region and the exposed initial first drain region are subjected to rapid thermal annealing treatment, or doping ions are implanted into the exposed initial first source region and the exposed initial first drain region, so that the resistance of the initial first source region is reduced to form a first source region 111, and the resistance of the initial first drain region is reduced to form a first drain region 121. The initial first channel region that has not been subjected to the resistance reduction treatment is used as the first channel region 101. After removing the first protective layer 90, the following is obtained: Figure 10 In the structure shown, the first channel region 101 , the first source region 111 and the first drain region 121 together constitute the first active layer.

[0092] After forming the first active layer, a first barrier material such as nitride (e.g., silicon nitride) is deposited on the first active layer, and the first barrier material on the first channel region 101 is removed. The remaining first barrier material above the first source region 111 and the first drain region 121 serves as the first barrier layer 161. Figure 11 Next, an oxide material (e.g., silicon dioxide) is deposited on the first barrier layer 161 and the first channel region 101 to form the first dielectric layer 15. The top of the first dielectric layer 15 is etched back to form a trench corresponding to the first barrier layer 161. A second barrier material such as nitride (e.g., silicon nitride) is filled in the trench to form the second barrier layer 162. Figure 12 In one example, the top surface of the second barrier layer 162 is flush with the top surface of the first dielectric layer 15 to simplify the implementation of subsequent processes.

[0093] An oxide semiconductor material, such as IGZO, is deposited on the first dielectric layer 15 and the second barrier layer 162 to form an initial second active layer. An initial second channel region, as well as an initial second source region and an initial second drain region located on opposite sides of the initial second channel region, are defined in the initial second active layer. The initial second channel region and the first channel region 101 are symmetrically arranged with respect to the first dielectric layer 15. The initial second source region and the first source region 111 are symmetrically arranged with respect to the first dielectric layer 15. The initial second drain region and the second drain region 121 are symmetrically arranged with respect to the first dielectric layer 15. Afterwards, the initial second source region and the initial second drain region are subjected to a resistance reduction treatment. The resistance reduction treatment includes: forming a second protective layer covering the initial second channel region in the initial second active layer; performing a rapid thermal annealing treatment (e.g., annealing at 400°C for 1 minute) on the exposed initial second source region and the exposed initial second drain region; or, alternatively, implanting dopant ions into the exposed initial second source region and the exposed initial second drain region, thereby reducing the resistance of the initial second source region to form the second source region 112, and reducing the resistance of the initial second drain region to form the second drain region 122. Next, the second protective layer is removed. The initial second channel region that has not undergone the resistance reduction treatment serves as the second channel region 102. The second channel region 102, the second source region 112, and the second drain region 122 together constitute the second active layer. The first active layer and the second active layer together constitute the active layer 17. After forming the active layer, a second gate dielectric layer 142 is formed above the second channel region 102 in the second active layer, a second gate layer 132 is formed above the second gate dielectric layer 142, and a second isolation layer 130 is formed above the second source region 112 and the second drain region 122 in the second active layer. In one example, the top surface of the second isolation layer 130 (i.e., the surface of the second isolation layer 130 facing away from the second active layer) is flush with the top surface of the second gate layer 132 (i.e., the surface of the second gate layer 132 facing away from the second gate dielectric layer 142). Figure 13 shown.

[0094] In the formation of Figure 13After the structure shown, the first dielectric layer 15 can be annealed in an oxygen atmosphere to passivate the oxygen vacancies in the first dielectric layer 15, forming passivated oxygen vacancies, thereby reducing the concentration of oxygen vacancies in the first dielectric layer 15, thereby shifting the threshold voltage of the transistor structure positively. During the annealing of the first dielectric layer 16, annealing parameters (e.g., annealing atmosphere, annealing time, annealing temperature, etc.) can be selected based on actual needs, for example, based on the concentration of oxygen vacancies in the first dielectric layer 16. When the first dielectric layer 16 is annealed in an oxygen atmosphere, the first barrier layer 161 can block oxygen from entering the first source region 111 and the first drain region 121, and the second barrier layer 162 can block oxygen from entering the second source region 112 and the second drain region 122, thereby preventing the annealing process from affecting the first source region 111, the first drain region 121, the second source region 112, and the second drain region 122.

[0095] Some embodiments of this specific embodiment provide transistor structures and methods for forming the same. By providing a first dielectric layer with an active layer positioned on the surface of the first dielectric layer, the first dielectric layer includes passivating oxygen vacancies, thereby shifting the threshold voltage of the transistor structure positively, reducing substrate leakage, and enabling the transistor structure to have a longer retention time. The subthreshold swing of the transistor structure is also reduced, thereby improving the response speed of the transistor structure. This specific embodiment also provides a barrier layer between the first dielectric layer and the source and drain regions of the active layer to prevent oxygen from entering the source and drain regions when passivating the oxygen vacancies in the first dielectric layer, thereby preventing an increase in RC (resistance-capacitance) delay.

[0096] The above is only a preferred embodiment of the present disclosure. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A transistor structure, characterized in that: include: a first dielectric layer, wherein the first dielectric layer includes passivating oxygen vacancies; an active layer located on a surface of the first dielectric layer, wherein the active layer includes a channel region and a source / drain region located outside the channel region; a gate layer, located on a side of the channel region away from the first dielectric layer; The barrier layer is located between the first dielectric layer and the source / drain region, and is used to block oxygen from entering the source / drain region.

2. The transistor structure according to claim 1, wherein: The active layer is distributed around the periphery of the first dielectric layer, the gate layer is distributed around the periphery of the channel region, and the barrier layer is distributed around the end of the first dielectric layer.

3. The transistor structure according to claim 1, wherein: The first dielectric layer includes a first portion corresponding to the channel region, and a second portion located outside the first portion and corresponding to the source and drain region; The sum of the thickness of the second portion and the thickness of the barrier layer is equal to the thickness of the first portion.

4. The transistor structure according to claim 1, wherein: Also includes: The second dielectric layer is located between the gate layer and the channel region, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

5. The transistor structure according to claim 1, wherein: The material of the channel region and the material of the source / drain region both include an oxide semiconductor material, and the resistance value of the source / drain region is smaller than the resistance value of the channel region.

6. The transistor structure according to claim 1, wherein: The active layer includes a first active layer and a second active layer distributed on opposite sides of the first dielectric layer along a first direction, the channel region includes a first channel region located in the first active layer and a second channel region located in the second active layer, and the first channel region and the second channel region are symmetrically distributed with respect to the first dielectric layer; The gate layer includes a first gate layer and a second gate layer distributed on opposite sides of the first dielectric layer along the first direction. The first gate layer is located on the first channel region, and the second gate layer is located on the second channel region.

7. A method for forming a transistor structure, characterized in that: The steps include: providing a substrate; A first dielectric layer, an active layer, a gate layer, and a barrier layer are formed on the substrate, wherein the first dielectric layer includes passivated oxygen vacancies, the active layer is located on the surface of the first dielectric layer, and the active layer includes a channel region and a source / drain region located outside the channel region, the gate layer is located on a side of the channel region facing away from the first dielectric layer, and the barrier layer is located between the first dielectric layer and the source / drain region, and is used to prevent oxygen from entering the source / drain region.

8. The method for forming a transistor structure according to claim 7, wherein: The specific steps of forming a first dielectric layer, an active layer, a gate layer and a barrier layer on the substrate include: forming the first dielectric layer on the substrate; forming the barrier layer distributed around the end of the first dielectric layer; forming the active layer distributed around the periphery of the first dielectric layer and the periphery of the barrier layer, wherein the channel region in the active layer is distributed around the periphery of the first dielectric layer, and the source / drain region in the active layer is distributed around the periphery of the barrier layer; forming the gate layer distributed around the periphery of the channel region; The oxygen vacancies in the first dielectric layer are passivated to form the passivated oxygen vacancies.

9. The method for forming a transistor structure according to claim 7, wherein: The specific steps of forming a first dielectric layer, an active layer, a gate layer and a barrier layer on the substrate include: forming a first gate layer on the substrate; forming a first active layer on the first gate layer; forming a first barrier layer on the first active layer; forming a first dielectric layer on the first active layer and the first barrier layer; forming a second barrier layer on the first dielectric layer, wherein the first barrier layer and the second barrier layer together serve as the barrier layer; forming a second active layer on the first dielectric layer and the second barrier layer, and using the first active layer and the second active layer together as the active layer; forming a second gate layer on the second active layer, and using the first gate layer and the second gate layer together as the gate layer; The oxygen vacancies in the first dielectric layer are passivated to form the passivated oxygen vacancies.

10. The method for forming a transistor structure according to claim 9, wherein: The specific steps of forming the first active layer on the first gate layer include: forming a first isolation layer on the substrate and located on opposite sides of the first gate layer; Depositing a first oxide semiconductor material on the substrate to form a first channel region above the first gate layer and an initial first source and drain region above the first isolation layer; The initial first source and drain regions are subjected to a resistance reduction treatment to form first source and drain regions.

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