Driving backplane, display panel, and display apparatus

Abstract

The present application belongs to the technical field of display, and discloses a driving backplane, a display panel, and a display apparatus. The driving backplane comprises a substrate, a first transistor, and a second transistor. The first transistor comprises a first gate, a first active layer, and a first auxiliary electrode, and the second transistor comprises a second gate, a second active layer, and a third gate. The distance between the first active layer and the first auxiliary electrode is less than the distance between the second active layer and the third gate. The distance between the first active layer and the first auxiliary electrode is small, and the subthreshold swing of the first transistor is large, so that the voltage of the first active layer can reach a threshold voltage over a relatively long time, and sufficient grayscale can be expressed even at a low grayscale, thereby effectively reducing the possibility of screen contamination in low grayscale. The distance between the second active layer and the third gate is large, and the subthreshold swing of the second transistor is small, so that switching characteristics thereof are good. A display panel in which such a driving backplane is used has a good display effect.

Description

Drive backplane, display panel and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving backplane, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are hailed as the next generation of display devices due to their advantages such as self-illumination, high efficiency, vibrant colors, thinness, energy saving, and rollability, and have attracted increasing attention in recent years.

[0003] The display panel includes a driving backplane and multiple light-emitting devices. The driving backplane has multiple pixel driving circuits, each corresponding to a light-emitting device and electrically connected to that device. The pixel driving circuit typically includes driving transistors and switching transistors; through the cooperation of these transistors, the light emission of the light-emitting devices can be controlled.

[0004] Currently, the effect of controlling the light emission of light-emitting devices by coordinating driving transistors and switching transistors is poor, resulting in poor display effects of display panels. Summary of the Invention

[0005] This application provides a driving backplane, a display panel, and a display device. It can solve the problem of poor display performance in existing OLED display panels. The technical solution is as follows:

[0006] On one hand, a drive backplane is provided, comprising: a substrate, and a first transistor and a second transistor located on the same side of the substrate and connected to each other;

[0007] The first transistor has a first active layer and a first auxiliary electrode; the first auxiliary electrode is located on the side of the first active layer facing the substrate and is electrically connected to the first active layer; the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate;

[0008] The second transistor has a second active layer and a third gate; the third gate is located on the side of the second active layer facing the substrate and is insulated from the second active layer; the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the third gate on the substrate;

[0009] The distance between the first active layer and the first auxiliary electrode is less than the distance between the second active layer and the third gate.

[0010] Optionally, the first active layer and the second active layer are disposed in the same layer and made of the same material; the first auxiliary electrode and the third gate are disposed in different layers, and the third gate is closer to the substrate than the first auxiliary electrode.

[0011] Optionally, the drive backplate further includes: a second auxiliary electrode, the second auxiliary electrode being located on the side of the first auxiliary electrode facing the substrate and being insulated from the first auxiliary electrode; the orthographic projection of the second auxiliary electrode on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate;

[0012] The second auxiliary electrode and the third gate are disposed in the same layer and are made of the same material.

[0013] Optionally, the drive backplane further includes: a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first active layer and the first auxiliary electrode, and the second insulating layer is located between the first auxiliary electrode and the second auxiliary electrode.

[0014] Optionally, the first transistor further has a first gate located on the side of the first active layer opposite to the substrate and insulated from the first active layer; the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the first gate on the substrate.

[0015] The second transistor further has a second gate located on the side of the second active layer away from the substrate and insulated from the second active layer; the second gate is electrically connected to the third gate; the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second gate on the substrate;

[0016] The first gate and the second gate are disposed in the same layer and are made of the same material.

[0017] Optionally, the driving backplane has a display area and a non-display area located around the display area, wherein both the first transistor and the second transistor are located within the display area;

[0018] The driving backplane further includes a third transistor, which is located on the side of the substrate where the first transistor and the second transistor are disposed, and the third transistor is located within the non-display area;

[0019] The third transistor has a fourth gate and a third active layer. The fourth gate is located on the side of the third active layer away from the substrate and is insulated from the third active layer. The orthographic projection of the fourth gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

[0020] The fourth gate, the first gate, and the second gate are disposed in the same layer and are made of the same material; at least a portion of the third active layer is disposed in the same layer as the first active layer and the second active layer and is made of the same material.

[0021] Optionally, the third transistor further has a fifth gate located on the side of the third active layer facing the substrate and insulated from the third active layer; the fifth gate is electrically connected to the fourth gate; and the orthographic projection of the fifth gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

[0022] Optionally, the fifth gate electrode is disposed in the same layer as the first auxiliary electrode and is made of the same material;

[0023] Alternatively, the fifth gate is disposed in the same layer as the third gate and is made of the same material;

[0024] Alternatively, the fifth gate includes: a first sub-gate and a second sub-gate electrically connected to the fourth gate, wherein the first sub-gate is disposed in the same layer as the first auxiliary electrode and is made of the same material, and the second sub-gate is disposed in the same layer as the third gate and is made of the same material.

[0025] Optionally, if the fifth gate includes a first sub-gate and a second sub-gate, the third transistor further includes: a first connection electrode and a second connection electrode, wherein the first connection electrode is used to connect the fourth gate and a first end of the first sub-gate, and the second connection electrode is used to connect the fourth gate and a first end of the second sub-gate;

[0026] Wherein, the orthographic projection of the second end of the first sub-gate on the substrate overlaps with the orthographic projection of the second end of the second sub-gate on the substrate.

[0027] Optionally, the driving backplane further includes: a third insulating layer, the third insulating layer being located between the first active layer and the first gate, and the third insulating layer having a first groove and a second groove;

[0028] The third active layer includes: a planar portion, a first vertical portion, and a second vertical portion. The planar portion is disposed in the same layer as the first active layer and the second active layer and is made of the same material. The orthographic projections of the first groove and the second groove on the substrate are both located within the orthographic projection of the planar portion on the substrate and are distributed on opposite sides of the planar portion. The first vertical portion is located in the first groove and is connected to the planar portion. The second vertical portion is located in the second groove and is connected to the planar portion.

[0029] Optionally, the driving backplane includes: a pixel driving circuit located in the display area, and a gate driving circuit located in the non-display area;

[0030] Wherein, the first transistor is the driving transistor in the pixel driving circuit, the second transistor is the switching transistor in the pixel driving circuit, and the gate driving circuit includes a plurality of the third transistors.

[0031] Optionally, the first transistor further has a first electrode and a second electrode, and the first active layer includes: a first conductor portion and a second conductor portion disposed opposite to each other, and a first channel region located between the first conductor portion and the second conductor portion;

[0032] The first electrode is electrically connected to the first conductor portion and the first auxiliary electrode, the second electrode is connected to the second conductor portion, the orthographic projection of the first channel region on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the second conductor portion on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate.

[0033] Optionally, the second transistor further includes a third electrode, a fourth electrode, and a third connection electrode, and the second active layer includes: a third conductor portion and a fourth conductor portion disposed opposite to each other, and a second channel region located between the third conductor portion and the fourth conductor portion;

[0034] The third electrode is electrically connected to the third conductor portion, and the fourth electrode is connected to the fourth conductor portion; the orthographic projection of the second channel region on the substrate is located within the orthographic projection of the second gate on the substrate, and is also located within the orthographic projection of the third gate on the substrate; the third connecting electrode is connected to the second gate and also to the third gate.

[0035] On the other hand, a display panel is provided, including:

[0036] The driving backplate and a plurality of light-emitting devices are provided, wherein the driving backplate is any of the driving backplates described above, and the plurality of light-emitting devices are electrically connected to the driving backplate.

[0037] In another aspect, a display device is provided, comprising:

[0038] The display panel is the same as described above, and the driver chip is used to apply a driving signal to the display panel.

[0039] The beneficial effects of the technical solutions provided in this application include at least the following:

[0040] The first transistor in the driving backplane can serve as a driving thin-film transistor in the pixel driving circuit, and the second transistor in the driving backplane can serve as a switching thin-film transistor in the pixel driving circuit. The first transistor includes a first gate, a first active layer, and a first auxiliary electrode, while the second transistor includes a second gate, a second active layer, and a third gate. The distance between the first active layer and the first auxiliary electrode is smaller than the distance between the second active layer and the third gate. This smaller distance between the first active layer and the first auxiliary electrode results in a larger parasitic capacitance between them, leading to a smaller actual current value in the first active layer and a larger subthreshold swing in the first transistor. This allows the voltage in the first active layer to reach the threshold voltage over a relatively long period and maintain a relatively stable threshold voltage. Even at low grayscale levels, the light-emitting device can be precisely controlled to express sufficient grayscale, effectively reducing the possibility of screen contamination at low grayscale levels. The larger distance between the second active layer and the third gate results in a smaller parasitic capacitance between them, leading to a larger actual current value in the second active layer. Furthermore, both the second and third gates of the second transistor can control the second active layer, further increasing the current. This results in a smaller subthreshold swing and better switching characteristics for the second transistor. After forming multiple light-emitting devices on this driving backplane to obtain the display panel, each pixel driving circuit in the driving backplane can more precisely control its corresponding light-emitting device, resulting in a better display effect. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 is a top view of a drive backplate provided in an embodiment of this application;

[0043] Figure 2 is a schematic diagram of a membrane structure at A-A' in Figure 1;

[0044] Figure 3 is a schematic diagram of another membrane structure at A-A' in Figure 1;

[0045] Figure 4 is a top view of a second transistor provided in an embodiment of this application;

[0046] Figure 5 is a schematic diagram of a membrane structure at B-B' in Figure 1;

[0047] Figure 6 is a schematic diagram of another membrane structure at B-B' in Figure 1;

[0048] Figure 7 is a top view of a third transistor provided in an embodiment of this application;

[0049] Figure 8 is a schematic diagram of another membrane structure at B-B' in Figure 1;

[0050] Figure 9 is a schematic diagram of another membrane structure at B-B' in Figure 1;

[0051] Figure 10 is a top view of another third transistor provided in an embodiment of this application;

[0052] Figure 11 is a schematic diagram of the membrane structure of a driving backplate provided in an embodiment of this application;

[0053] Figure 12 is a schematic diagram of the film structure of a third transistor provided in the embodiment of the application;

[0054] Figure 13 is a display panel provided in an embodiment of this application. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0056] Please refer to Figures 1 and 2. Figure 1 is a top view of a driving backplane provided in an embodiment of this application, and Figure 2 is a schematic diagram of a film layer structure at A-A' in Figure 1. The driving backplane 000 may have a display area 00a and a non-display area 00b located around the display area. Here, the driving backplane 000 includes: a substrate 100, and a first transistor 200 and a second transistor 300 located on the same side of the substrate 100 and connected to each other. The first transistor 200 and the second transistor 300 in the driving backplane 000 may both be located within the display area 00a.

[0057] The first transistor 200 in the drive backplane 000 has a first active layer 220 and a first auxiliary electrode 230. The first auxiliary electrode 230 is located on the side of the first active layer 220 facing the substrate 100 and is electrically connected to the first active layer 220. The orthographic projection of the first active layer 220 on the substrate 100 overlaps with the orthographic projection of the first auxiliary electrode 230 on the substrate 100.

[0058] In this embodiment of the application, the first transistor 200 in the driving backplane 000 further has a first gate 210. The first gate 210 is located on the side of the first active layer 220 away from the substrate 100 and is insulated from the first active layer 220. The orthographic projection of the first active layer 220 on the substrate 100 overlaps with the orthographic projection of the first gate 210 on the substrate 100.

[0059] In this embodiment, the first transistor 200 in the driving backplane 000 further has a first electrode 240 and a second electrode 250. Here, the first electrode 240 can be one of the source and drain of the first transistor 200, and the second electrode 250 can be the other of the source and drain of the first transistor 200. Furthermore, the first active layer 220 in the first transistor 200 includes: a first conductor portion 221 and a second conductor portion 222 disposed opposite to each other, and a first channel region 223 located between the first conductor portion 221 and the second conductor portion 222.

[0060] In this configuration, the first electrode 240 of the first transistor 200 is electrically connected to the first conductor portion 221 and the first auxiliary electrode 230, respectively. The second electrode 250 of the first transistor 200 is connected to the second conductor portion 222. The orthographic projection of the first channel region 223 in the first active layer 220 onto the substrate 100 lies within the orthographic projection of the first gate 210 onto the substrate 100. Thus, when a gate drive signal is applied to the first gate 210, charge carriers can be generated in the first channel region 223 of the first active layer 220, enabling electrical connection between the first conductor portion 221 and the second conductor portion 222 of the first active layer 220.

[0061] It should be noted that the orthographic projection of the first active layer 220 onto the substrate 100 lies within the orthographic projection of the first auxiliary electrode 230 onto the substrate 100. In this way, the first auxiliary electrode 230 can serve as a light-shielding structure for the first active layer 220, blocking light incident from the outside onto the first active layer 220, preventing the first active layer 220 from being affected by external light, and improving the stability of the first transistor 200.

[0062] The second transistor 300 in the drive backplane 000 has a second active layer 320 and a third gate 330. The third gate 330 is located on the side of the second active layer 320 facing the substrate 100 and is insulated from the second active layer 320. The orthographic projection of the second active layer 320 on the substrate 100 overlaps with the orthographic projection of the third gate 330 on the substrate.

[0063] In this embodiment, the second transistor 300 in the driving backplane 000 further includes a second gate 310. The second gate 310 is located on the side of the second active layer 320 facing away from the substrate 100 and is insulated from the second active layer 320. The second gate 310 is electrically connected to the third gate 330. The orthographic projection of the second active layer 320 onto the substrate 100 overlaps with the orthographic projection of the second gate 310 onto the substrate 100.

[0064] In this embodiment, the second transistor 300 in the driving backplane 000 further includes a third electrode 340, a fourth electrode 350, and a third connection electrode 360. Here, the third electrode 340 can be one of the source and drain of the second transistor 300, and the fourth electrode 350 can be the other of the source and drain of the second transistor 300. Furthermore, the second active layer 320 in the second transistor 300 includes: a third conductor portion 321 and a fourth conductor portion 322 disposed opposite to each other, and a second channel region 323 located between the third conductor portion 321 and the fourth conductor portion 322.

[0065] In this configuration, the third electrode 340 of the second transistor 300 is electrically connected to the third conductor portion 321. The fourth electrode 350 of the second transistor 300 is electrically connected to the fourth conductor portion 322. The orthogonal projection of the second channel region 323 in the second active layer 320 onto the substrate 100 lies within the orthogonal projection of the second gate 310 onto the substrate 100, and also within the orthogonal projection of the third gate 330 onto the substrate 100. The third connection electrode 360 ​​of the second transistor 300 is connected to both the second gate 310 and the third gate 330. Thus, the third connection electrode 360 ​​allows the second gate 310 and the third gate 330 to be connected to the same potential, ensuring that both can jointly control the second channel region 323 in the second active layer 320. For example, when a gate drive signal is applied to the second gate 310 and the third gate 330, carriers can be generated in the second channel region 323 of the second active layer 320, enabling electrical connection between the third conductor portion 321 and the fourth conductor portion 322 of the second active layer 320. With the combined action of the second gate 310 and the third gate 330, the threshold voltage of the second transistor 300 can be made more stable, allowing more carriers to be generated in the second channel region 323 of the second active layer 320, resulting in a larger current in the second active layer 320. This effectively improves the stability and reliability of the second transistor 300.

[0066] It should be noted that the orthographic projection of the second active layer 320 onto the substrate 100 lies within the orthographic projection of the third gate 330 onto the substrate 100. In this way, the third gate 330 can serve as a light-shielding structure for the second active layer 320, blocking light incident from the outside onto the second active layer 320, preventing the second active layer 320 from being affected by external light, and improving the stability of the second transistor 300.

[0067] In this embodiment, the driving backplane 000 may have multiple pixel driving circuits, all of which can be used to drive light-emitting devices subsequently disposed on the driving backplane 000, so that the light-emitting devices can emit light under the driving action of the pixel driving circuits. Each pixel driving circuit may include a first transistor 200 and a second transistor 300.

[0068] Here, the first transistor 200 can be a driving thin-film transistor for supplying driving current to operate the light-emitting device, and the second transistor 300 can be a switching thin-film transistor for supplying a gate signal to the driving thin-film transistor. Therefore, the first transistor 200 requires a larger subthreshold swing, while the second transistor 300 requires a smaller subthreshold swing. To meet the requirements of the first transistor 200 and the second transistor 300, the distance between the first active layer 220 and the first auxiliary electrode 230 is reduced, and the distance between the second active layer 320 and the third gate 330 is increased, such that the distance between the first active layer 220 and the first auxiliary electrode 230 is smaller than the distance between the second active layer 320 and the third gate 330.

[0069] For example, in the first transistor 200, since the orthographic projection of the second conductor portion 222 of the first active layer 220 onto the substrate 100 overlaps with the orthographic projection of the first auxiliary electrode 230 onto the substrate 100, a parasitic capacitance can be formed between the second conductor portion 222 of the first active layer 220 and the first auxiliary electrode 230. Here, when the distance between the first active layer 220 and the first auxiliary electrode 230 in the first transistor 200 is small, it is possible to ensure that the parasitic capacitance between the second conductor portion 222 and the first auxiliary electrode 230 is large, thereby reducing the actual current in the first active layer 220. In this way, the first transistor 200 can obtain a large subthreshold swing, so that the voltage in the first active layer 220 can reach the threshold voltage for a relatively long time and the threshold voltage is relatively stable. Even at low gray levels, the light-emitting device can be precisely controlled to express sufficient gray levels, effectively reducing the possibility of screen contamination at low gray levels.

[0070] In the second transistor 300, since the orthogonal projections of the third conductor portion 321 and the fourth conductor portion 322 of the second active layer 320 onto the substrate 100 overlap with the orthogonal projection of the third gate 330 onto the substrate 100, parasitic capacitances can be formed between the third conductor portion 321 and the third gate 330 of the second active layer 320, and also between the fourth conductor portion 322 and the third gate 330. Here, when the distance between the second active layer 320 and the third gate 330 is large, the parasitic capacitance between the third conductor portion 321 and the third gate 330 is small, and the parasitic capacitance between the fourth conductor portion 322 and the third gate 330 is also small, thereby increasing the actual current value in the second active layer 320. Furthermore, since both the second gate 310 and the third gate 330 in the second transistor 300 can control the second channel region 323 in the second active layer 320, the current in the second active layer 320 can be further increased. In this way, the second transistor 300 can achieve a smaller subthreshold swing, and the switching characteristics of the second transistor 300 are better.

[0071] Therefore, after forming multiple light-emitting devices on such a driving backplate 000 to obtain a display panel, each pixel driving circuit in the driving backplate 000 can more accurately control the corresponding light-emitting devices, resulting in a better display effect of the display panel.

[0072] In summary, the driving backplane provided in this application includes a substrate, and a first transistor and a second transistor located on the same side of the substrate and connected to each other. The first transistor can serve as a driving thin-film transistor in a pixel driving circuit, and the second transistor can serve as a switching thin-film transistor in a pixel driving circuit. The first transistor includes a first gate, a first active layer, and a first auxiliary electrode, and the second transistor includes a second gate, a second active layer, and a third gate. The distance between the first active layer and the first auxiliary electrode is smaller than the distance between the second active layer and the third gate. This smaller distance between the first active layer and the first auxiliary electrode results in a larger parasitic capacitance between them, leading to a smaller actual current value in the first active layer and a larger subthreshold swing in the first transistor. This allows the voltage in the first active layer to reach the threshold voltage over a relatively long period and maintain a relatively stable threshold voltage. Even at low grayscale levels, the light-emitting device can be precisely controlled to express sufficient grayscale, effectively reducing the possibility of screen contamination at low grayscale levels. The larger distance between the second active layer and the third gate results in a smaller parasitic capacitance between them, leading to a larger actual current value in the second active layer. Furthermore, both the second and third gates of the second transistor can control the second active layer, further increasing the current. This results in a smaller subthreshold swing and better switching characteristics for the second transistor. After forming multiple light-emitting devices on this driving backplane to obtain the display panel, each pixel driving circuit in the driving backplane can more precisely control its corresponding light-emitting device, resulting in a better display effect.

[0073] In this embodiment of the application, as shown in FIG3, FIG3 is a schematic diagram of another film layer structure at A-A' in FIG1. ​​The first active layer 220 in the first transistor 200 and the second active layer 320 in the second transistor 300 are disposed in the same layer and made of the same material. The first auxiliary electrode 230 in the first transistor 200 and the third gate 330 in the second transistor 300 are disposed in different layers. Moreover, the third gate 330 is closer to the substrate 100 than the first auxiliary electrode 230. In this way, the distance between the first active layer 220 and the first auxiliary electrode 230 is small, and the distance between the second active layer 320 and the third gate 330 is large.

[0074] It should be noted that, in this application, "two structures are co-located and identical" means that the film layer containing these two structures is the same film layer, which can be formed simultaneously through the same patterning process. For example, the film layer containing the first active layer 220 in the first transistor 200 and the film layer containing the second active layer 320 in the second transistor 300 are the same conductive layer, and the first active layer 220 and the second active layer 320 can be formed through the same patterning process. Thus, in the fabrication process of the driving backplane 000, the first active layer 220 and the second active layer 320 can be obtained using only the same patterning process, simplifying the fabrication process of the driving backplane 000.

[0075] It should also be noted that the "different layer configuration" of two structures in this application refers to the fact that the film layers on which these two structures are located are not the same film layer, and an insulating layer may be disposed between the two film layers. For example, the film layer on which the first auxiliary electrode 230 in the first transistor 200 is located is not the same conductive layer as the film layer on which the third gate 330 in the second transistor 300 is located, and an insulating layer is disposed between the two conductive layers.

[0076] In this application, both the first transistor 200 and the second transistor 300 can be oxide thin-film transistors (TFTs). That is, the first active layer 220 in the first transistor 200 and the second active layer 320 in the second transistor 300 are both made of oxide semiconductor materials. For example, IGZO can be used to fabricate the first active layer 220 and the second active layer 320. Oxide thin-film transistors have advantages such as high mobility, low off-state current, simple manufacturing process, and large-size capability. Display panels using this driving backplane 000 can improve performance while meeting low-power consumption requirements.

[0077] In this embodiment of the application, as shown in FIG3, the driving backplane 000 may further include a second auxiliary electrode 400. The second auxiliary electrode 400 is located on the side of the first auxiliary electrode 230 in the first transistor 200 facing the substrate 100, and is insulated from the first auxiliary electrode 230.

[0078] In this design, the second auxiliary electrode 400 in the driving backplane 000 can be disposed on the same layer and made of the same material as the third gate 330 in the second transistor 300. It should be noted that the orthographic projection of the second auxiliary electrode 400 in the driving backplane 000 onto the substrate 100 overlaps with the orthographic projection of the first auxiliary electrode 230 in the first transistor 200 onto the substrate 100. Thus, the second auxiliary electrode 400 and the first auxiliary electrode 230 can form a storage capacitor, which is also part of the pixel driving circuit. Data signals can be stored in the storage capacitor formed by the second auxiliary electrode 400 and the first auxiliary electrode 230 to ensure that the first transistor 200 is in a conducting state during the frame period, thereby controlling the driving current in the first transistor 200, so that the light-emitting device driven by the first transistor 200 can continuously emit light throughout the entire frame period.

[0079] In this case, by setting a second auxiliary electrode 400 in the driving backplane 000 that is distributed in the same layer as the third gate 330, not only can the second auxiliary electrode 400 and the first auxiliary electrode 230 be used to form the storage capacitor in the pixel driving circuit, but it can also ensure that the second auxiliary electrode 400 and the third gate 330 can be obtained in the same patterning process during the fabrication of the driving backplane 000, thereby simplifying the fabrication process of the driving backplane 000.

[0080] In this embodiment, the driving backplane 000 may further include a first insulating layer 500 and a second insulating layer 600. The first insulating layer 500 in the driving backplane 000 is located between the first active layer 220 and the first auxiliary electrode 230 of the first transistor 200, and is used to achieve electrical insulation between the first active layer 220 and the first auxiliary electrode 230. The second insulating layer 600 in the driving backplane 000 is located between the first auxiliary electrode 230 and the second auxiliary electrode 400, and is used to achieve electrical insulation between the second auxiliary electrode 400 and the first auxiliary electrode 230.

[0081] In this configuration, since the first active layer 220 in the first transistor 200 and the second active layer 320 in the second transistor 300 are disposed on the same layer, and the second auxiliary electrode 400 and the third gate 330 in the second transistor 300 are disposed on the same layer, it can be ensured that only the first insulating layer 500 exists between the first active layer 220 and the first auxiliary electrode 230, while the first insulating layer 500 and the second insulating layer 600 are simultaneously stacked between the second active layer 320 and the third gate 330. This ensures that the distance between the first active layer 220 and the first auxiliary electrode 230 is small, while the distance between the second active layer 320 and the third gate 330 is large.

[0082] It should be noted that, since a first insulating layer 500 and a second insulating layer 600 are stacked between the second active layer 320 and the third gate 330 in the second transistor 300, the second active layer 320 and the third gate 330 in the second transistor 300 can be insulated from each other by the first insulating layer 500 and the second insulating layer 600.

[0083] In this embodiment, the first gate 210 of the first transistor 200 and the second gate 310 of the second transistor 300 can be disposed in the same layer and made of the same material. In this way, it can be ensured that the first gate 210 and the second gate 310 can be obtained using only the same patterning process during the fabrication of the driving backplane 000, thereby simplifying the fabrication process of the driving backplane 000.

[0084] Optionally, as shown in Figure 3, the driving backplane 000 may further include a third insulating layer 700. The third insulating layer 700 is located between the first active layer 220 and the first gate 210 in the first transistor 200, and is used to achieve electrical insulation between the first active layer 220 and the first gate 210.

[0085] It should be noted that, since the first gate 210 of the first transistor 200 and the second gate 310 of the second transistor 300 are disposed on the same layer, and the first active layer 220 of the first transistor 200 and the second active layer 320 of the second transistor 300 are disposed on the same layer, the third insulating layer 700 is also located between the second active layer 320 and the second gate 310 in the second transistor 300, for the purpose of achieving electrical insulation between the second active layer 320 and the second gate 310.

[0086] Optionally, as shown in Figure 3, the drive backplane 000 may further include a fourth insulating layer 800. The fourth insulating layer 800 is located on the side of the first gate 210 of the first transistor 200 and the second gate 310 of the second transistor 300 facing away from the substrate 100. The first electrode 240 and the second electrode 250 of the first transistor 200, and the third electrode 340, the fourth electrode 350, and the third connection electrode 360 ​​of the second transistor 300 are all located on the side of the fourth insulating layer 800 facing away from the substrate 100. Furthermore, the first electrode 240 and the second electrode 250 of the first transistor 200, and the third electrode 340, the fourth electrode 350, and the third connection electrode 360 ​​of the second transistor 300 are disposed in the same layer and are made of the same material. In this way, it can be ensured that the first electrode 240 and the second electrode 250 of the first transistor 200, as well as the third electrode 340, the fourth electrode 350 and the third connection electrode 360 ​​of the second transistor 300, can be obtained through only one patterning process during the fabrication of the drive backplane 000, thereby simplifying the manufacturing process of the drive backplane 000.

[0087] In this embodiment of the application, please refer to Figure 3. The drive backplate 000 may also have a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6 and a seventh via V7.

[0088] A first via V1 passes through the fourth insulating layer 800, the third insulating layer 700, and the first insulating layer 500 in sequence, allowing the first electrode 240 of the first transistor 200 to be connected to the first auxiliary electrode 230 of the first transistor 200 through the first via V1. A second via V2 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, allowing the first electrode 240 of the first transistor 200 to be connected to the first conductor portion 221 of the first active layer 220 through the second via V2. Thus, the first auxiliary electrode 230 and the first conductor portion 221 of the first active layer 220 are electrically connected through the first electrode 240.

[0089] The third via V3 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, so that the second electrode 250 of the first transistor 200 can be electrically connected to the second conductor portion 222 of the first active layer 220 through the third via V3.

[0090] The fourth via V4 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, so that the third electrode 340 of the second transistor 300 can be electrically connected to the third conductor portion 321 of the second active layer 320 through the fourth via V4.

[0091] The fifth via V5 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, so that the fourth electrode 350 of the second transistor 300 can be electrically connected to the fourth conductor portion 322 of the second active layer 320 through the fifth via V5.

[0092] The sixth via V6 sequentially penetrates the fourth insulating layer 800, the third insulating layer 700, the first insulating layer 500, and the second insulating layer 600, allowing the third connection electrode 360 ​​of the second transistor 300 to be connected to the third gate 330 via V6. The seventh via V7 penetrates the fourth insulating layer 800, allowing the third connection electrode 360 ​​of the second transistor 300 to be connected to the second gate 310 of the second transistor 300 via V7. Thus, the second gate 310 and the third gate 330 are electrically connected via the third connection electrode 360.

[0093] It should be noted that, please refer to Figure 4, which is a top view of a second transistor provided in an embodiment of this application. The third connecting electrode 360 ​​in the second transistor 300 is arranged around the periphery of the third electrode 340, thereby avoiding a short circuit between the third connecting electrode 360 ​​and the third electrode 340.

[0094] In this embodiment, please refer to Figures 1 and 5. Figure 5 is a schematic diagram of a film structure at B-B' in Figure 1. The driving backplane 000 may further include a third transistor 900, which is located on the side of the substrate 100 where the first transistor 200 and the second transistor 300 are disposed, and the third transistor 900 may be located within the non-display area 00b.

[0095] For example, the driving backplane 000 may further include gate driving circuitry 00c distributed within the non-display area 00b. Gate driving circuitry 00c may include a plurality of third transistors 900. Here, gate driving circuitry 00c may provide gate scan signals to pixel driving circuitry, enabling the pixel driving circuitry to operate based on the gate scan signals.

[0096] In this application, as shown in FIG5, the third transistor 900 in the drive backplane 000 has a fourth gate 910 and a third active layer 920.

[0097] The fourth gate 910 is located on the side of the third active layer 920 away from the substrate 100 and is insulated from the third active layer 920. The orthogonal projection of the third active layer 920 on the substrate 100 overlaps with the orthogonal projection of the fourth gate 910 on the substrate 100, and also overlaps with the orthogonal projection of the fifth gate 950 on the substrate 100.

[0098] In this application, the fourth gate 910 of the third transistor 900, the first gate 210 of the first transistor 200, and the second gate 310 of the second transistor 300 are disposed in the same layer and made of the same material. Furthermore, at least a portion of the third active layer 920 of the third transistor 900 is disposed in the same layer and made of the same material as the first active layer 220 of the first transistor 200 and the second active layer 320 of the second transistor 300. Thus, the first gate 210, the second gate 310, and the fourth gate 910 can be obtained simultaneously using only one patterning process, and at least a portion of the first active layer 220, the second active layer 320, and the third active layer 920 can be obtained simultaneously using another patterning process, thereby simplifying the fabrication process of the drive backplane 000.

[0099] In this case, the third insulating layer 300 may also be located between the fourth gate 910 of the third transistor 900 and at least part of the third active layer 920 to achieve electrical insulation between the fourth gate 910 and the third active layer 920.

[0100] In this embodiment of the application, as shown in FIG5, the third transistor 900 in the driving backplane 000 further has a fifth electrode 930 and a sixth electrode 940. Here, the fifth electrode 930 can be one of the source and drain of the third transistor 900, and the sixth electrode 940 can be the other of the source and drain of the third transistor 900. Furthermore, the third active layer 920 in the third transistor 900 includes: a fifth conductor portion 921 and a sixth conductor portion 922 disposed opposite to each other, and a third channel region 923 located between the fifth conductor portion 921 and the sixth conductor portion 922.

[0101] In this design, the fifth terminal 930 of the third transistor 900 is electrically connected to the fifth conductor portion 921. The sixth terminal 940 of the third transistor 900 is electrically connected to the sixth conductor portion 922. The orthogonal projection of the third channel region 923 in the third active layer 920 onto the substrate 100 lies within the orthogonal projection of the fourth gate 910 onto the substrate 100. When a gate drive voltage is applied to the fourth gate 910, the fourth gate 910 can control the third channel region 923 in the third active layer 920. Driven carriers can be generated in the third channel region 923 of the third active layer 920, enabling the fifth conductor portion 921 and the sixth conductor portion 922 of the third active layer 920 to be electrically connected.

[0102] It should also be noted that the fifth electrode 930 and the sixth electrode 940 of the third transistor 900 can both be located on the side of the fourth insulating layer 800 facing away from the substrate 100. Furthermore, the first electrode 240 and the second electrode 250 of the first transistor 200, the third electrode 340, the fourth electrode 350 and the third connecting electrode 360 ​​of the second transistor 300, and the fifth electrode 930 and the sixth electrode 940 of the third transistor 900 are disposed in the same layer and made of the same material. Thus, the first electrode 240 and the second electrode 250 of the first transistor 200, the third electrode 340, the fourth electrode 350 and the third connecting electrode 360 ​​of the second transistor 300, and the fifth electrode 930 and the sixth electrode 940 of the third transistor 900 can be obtained using only one patterning process, thereby simplifying the fabrication process of the drive backplane 000.

[0103] In this embodiment of the application, as shown in FIG5, the drive backplate 000 also has an eighth via V8 and a ninth via V9.

[0104] The eighth via V8 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, so that the fifth terminal 930 of the third transistor 900 can be electrically connected to the fifth conductor portion 921 of the third active layer 920 through the eighth via V8.

[0105] The ninth via V9 passes through the fourth insulating layer 800 and the third insulating layer 700 in sequence, so that the sixth terminal 940 of the third transistor 900 can be electrically connected to the sixth conductor portion 922 of the third active layer 920 through the ninth via V9.

[0106] In this embodiment, please refer to FIG6, which is a schematic diagram of another film structure at B-B' in FIG1. ​​The third transistor 900 in the driving backplane 000 also has a fifth gate 950. The fifth gate 950 is located on the side of the third active layer 920 facing the substrate 100 and is insulated from the third active layer 920. The fifth gate 950 is electrically connected to the fourth gate 910. The orthographic projection of the fifth gate 950 on the substrate 100 overlaps with the orthographic projection of the third active layer 920 on the substrate 100.

[0107] In this design, the orthographic projection of the third channel region 923 in the third active layer 920 onto the substrate 100 lies within the orthographic projection of the fourth gate 910 onto the substrate 100, and also within the orthographic projection of the fifth gate 950 onto the substrate 100. Since the fourth gate 910 and the fifth gate 950 are electrically connected, they can be connected to the same potential, ensuring that they can jointly control the third channel region 923 in the third active layer 920. For example, when a gate drive voltage is applied to the fourth gate 910 and the fifth gate 950, driving carriers can be generated in the third channel region 923 of the third active layer 920, enabling the fifth conductor portion 921 and the sixth conductor portion 922 of the third active layer 920 to be electrically connected. With the combined action of the fourth gate 910 and the fifth gate 950, the threshold voltage of the third transistor 900 can be made more stable, allowing more charge carriers to be generated in the third channel region 923 of the third active layer 920, resulting in a larger current in the third active layer 920. This effectively improves the reliability and stability of the third transistor.

[0108] Here, the orthographic projection of the third active layer 920 of the third transistor 900 onto the substrate 100 lies within the orthographic projection of the fifth gate 950 of the third transistor 900 onto the substrate 100. Thus, the fifth gate 950 can serve as a light-shielding structure for the third active layer 920, blocking light incident from the outside onto the third active layer 920, preventing the third active layer 920 from being affected by external light, and improving the stability of the third transistor 900.

[0109] In this application embodiment, the fifth gate 950 in the third transistor 900 has multiple possible implementations. This application uses the following three possible implementations as examples for illustration:

[0110] In one possible implementation, as shown in Figure 6, the fifth gate 950 in the third transistor 900 is disposed in the same layer as the first auxiliary electrode 230 in the first transistor 200 and is made of the same material.

[0111] Since at least a portion of the third active layer 220 in the third transistor 900 is disposed on the same layer as the first active layer 220 in the first transistor 200, and the fifth gate 950 in the third transistor 900 is disposed on the same layer as the first auxiliary electrode 230 in the first transistor 200, a first insulating layer 500 is provided between the third active layer 220 and the fifth gate 950 in the third transistor 900. The first insulating layer 500 is used to achieve electrical insulation between the third active layer 220 and the fifth gate 950 in the third transistor 900.

[0112] In this application, the third transistor 900 in the driving backplane 000 may also have a fourth connection electrode 960. The fourth connection electrode 960 is connected to the fourth gate 910 and the fifth gate 950. In this way, the fourth gate 910 and the fifth gate 950 can be connected to the same potential through the fourth connection electrode 960, so as to ensure that they can jointly control the third channel region 923 in the third active layer 920.

[0113] It should be noted that the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 are all located on the side of the fourth insulating layer 800 facing away from the substrate 100. Furthermore, the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 are disposed in the same layer and are made of the same material. Thus, the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 can be obtained using only a single patterning process, thereby simplifying the fabrication process of the drive backplane 000.

[0114] In this configuration, the drive backplane 000 also has a tenth via V10 and an eleventh via V11. The tenth via V10 penetrates the fourth insulating layer 800, allowing the fourth connection electrode 960 of the third transistor 900 to be connected to the fourth gate 910 of the third transistor 900 via the tenth via V10. The eleventh via V11 sequentially penetrates the fourth insulating layer 800, the third insulating layer 700, and the first insulating layer 500, allowing the fourth connection electrode 960 of the third transistor 900 to be connected to the fifth gate 950 of the third transistor 900 via the eleventh via V11. Thus, the fifth gate 950 and the fourth gate 910 are electrically connected via the fourth connection electrode 960.

[0115] It should be noted that, please refer to Figure 7, which is a top view of a third transistor provided in an embodiment of this application. The fourth connection electrode 960 of the third transistor 900 is disposed around the periphery of the sixth electrode 940 of the third transistor 900, thereby avoiding a short circuit between the fourth connection electrode 960 and the sixth electrode 940.

[0116] The second possible implementation is shown in Figure 8, which is a schematic diagram of another film structure at B-B' in Figure 1. The fifth gate 950 and the third gate 330 in the second transistor 300 are disposed in the same layer and made of the same material.

[0117] Since at least a portion of the third active layer 220 in the third transistor 900 is disposed on the same layer as the first active layer 220 in the first transistor 200, and the fifth gate 950 of the third transistor 900 is disposed on the same layer as the third gate 330 in the second transistor 300, a first insulating layer 500 and a second insulating layer 600 are simultaneously disposed between the third active layer 920 and the fifth gate 950 of the third transistor 900. The first insulating layer 500 and the second insulating layer 600 are used together to achieve insulation between the third active layer 920 and the fifth gate 950.

[0118] In this application, the third transistor 900 in the driving backplane 000 may also have a fourth connection electrode 960. The fourth connection electrode 960 is connected to the fourth gate 910 and the fifth gate 950. In this way, the fourth gate 910 and the fifth gate 950 can be connected to the same potential through the fourth connection electrode 960, so as to ensure that they can jointly control the third channel region 923 in the third active layer 920.

[0119] It should be noted that the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 are all located on the side of the fourth insulating layer 800 facing away from the substrate 100. Furthermore, the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 are disposed in the same layer and are made of the same material. Thus, the fifth electrode 930, the sixth electrode 940, and the fourth connection electrode 960 of the third transistor 900 can be obtained using only a single patterning process, thereby simplifying the fabrication process of the drive backplane 000.

[0120] In this configuration, the drive backplane 000 also has a twelfth via V12. The twelfth via V12 sequentially penetrates the fourth insulating layer 800, the third insulating layer 700, the first insulating layer 500, and the second insulating layer 600, allowing the fourth connection electrode 960 of the third transistor 900 to be connected to the fifth gate 950 of the third transistor 900 via the eleventh via V11. Furthermore, the fourth connection electrode 960 of the third transistor 900 can be connected to the fourth gate 910 of the third transistor 900 via the tenth via V10. Thus, the fifth gate 950 and the fourth gate 910 are electrically connected via the fourth connection electrode 960.

[0121] For a third possible implementation, please refer to Figure 9, which is a schematic diagram of another film structure at B-B' in Figure 1. The fifth gate 950 of the third transistor 900 includes a first sub-gate 951 and a second sub-gate 952 that are electrically connected to the fourth gate 910.

[0122] The first sub-gate 951 of the fifth gate 950 is disposed on the same layer as the first auxiliary electrode 230 of the first transistor 200 and is made of the same material. The second sub-gate 952 of the fifth gate 950 is disposed on the same layer as the third gate 330 of the second transistor 300 and is made of the same material. Since at least a portion of the third active layer 220 in the third transistor 900 is disposed on the same layer as the first active layer 220 in the first transistor 200, only the first insulating layer 500 exists between the third active layer 920 and the first sub-gate 951 of the third transistor 900, while the first insulating layer 500 and the second insulating layer 600 are stacked together between the third active layer 920 and the second sub-gate 952 of the third transistor 900. Thus, the third active layer 920 and the first sub-gate 951 are electrically insulated from each other by the first insulating layer 500, and the third active layer 920 and the second sub-gate 952 are electrically insulated from each other by the stacked first insulating layer 500 and the second insulating layer 600.

[0123] In this configuration, the third transistor 900 has a first connection electrode 970 and a second connection electrode 980. The first connection electrode 970 connects the first ends of the fourth gate 910 and the first sub-gate 951, and the second connection electrode 980 connects the first ends of the fourth gate 910 and the second sub-gate 952. Thus, the fourth gate 910 can be connected to the same potential as the first sub-gate 951 via the first connection electrode 970, and can be connected to the same potential as the second sub-gate 952 of the fifth gate 950 via the second connection electrode 980. This ensures that the fourth gate 910, the first sub-gate 951 of the fifth gate 950, and the second sub-gate 952 of the fifth gate 950 can jointly control the third channel region 923 in the third active layer 920.

[0124] It should be noted that the orthographic projection of the second end of the first sub-gate 951 onto the substrate 100 overlaps with the orthographic projection of the second end of the second sub-gate 952 onto the substrate 100. Thus, the combined action of the first sub-gate 951 and the second sub-gate 952 blocks light incident from the outside onto the third active layer 920, preventing the third active layer 920 from being affected by external light and improving the stability of the third transistor 900.

[0125] Here, as shown in Figure 9, the drive backplate 000 also has a fourteenth via V14 and a fifteenth via V15.

[0126] The fourteenth via V14 sequentially penetrates the fourth insulating layer 800, the third insulating layer 700, and the first insulating layer 500, allowing the first connection electrode 970 of the third transistor 900 to be connected to the first sub-gate 951 of the third transistor 900 via the fourteenth via V14. Furthermore, the first connection electrode 970 of the third transistor 900 can be connected to the fourth gate 910 of the third transistor 900 via the tenth via V10. Thus, the first sub-gate 951 and the fourth gate 910 are electrically connected via the first connection electrode 970.

[0127] The fifteenth via V15 sequentially penetrates the fourth insulating layer 800, the third insulating layer 700, the first insulating layer 500, and the second insulating layer 600, allowing the second connection electrode 980 of the third transistor 900 to be connected to the second sub-gate 952 of the third transistor 900 through the fifteenth via V15, and the second connection electrode 980 of the third transistor 900 to be connected to the fourth gate 910 of the third transistor 900 through the tenth via V10. Thus, the second sub-gate 952 and the fourth gate 910 are electrically connected through the second connection electrode 980.

[0128] It should be noted that, referring to Figure 10, which is a top view of another third transistor provided in an embodiment of this application, the first connection electrode 970 of the third transistor 900 is disposed around the periphery of the sixth electrode 940 in the third transistor 900, thus avoiding a short circuit between the second connection electrode 980 and the sixth electrode 950. The second connection electrode 980 of the third transistor 900 is disposed around the periphery of the fifth electrode 930 in the third transistor 900, thus avoiding a short circuit between the second connection electrode 980 and the fifth electrode 930.

[0129] It should also be noted that the fifth electrode 930, sixth electrode 940, first connecting electrode 970, and second connecting electrode 980 of the third transistor 900 are all located on the side of the fourth insulating layer 800 facing away from the substrate 100. Furthermore, the first electrode 240 and second electrode 250 of the first transistor 200, the third electrode 340, fourth electrode 350, and third connecting electrode 360 ​​of the second transistor 300, and the fifth electrode 930, sixth electrode 940, first connecting electrode 970, and second connecting electrode 980 of the third transistor 900 are all disposed in the same layer and made of the same material. Thus, the first electrode 240 and second electrode 250 of the first transistor 200, the third electrode 340, fourth electrode 350, and third connecting electrode 360 ​​of the second transistor 300, and the fifth electrode 930, sixth electrode 940, first connecting electrode 970, and second connecting electrode 980 of the third transistor 900 can be obtained using only one patterning process, thereby simplifying the fabrication process of the drive backplane 000. One patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.

[0130] In this application, the above embodiments illustrate various possible implementations of the fifth gate 950 of the third transistor 900. Based on this, the third active layer 920 of the third transistor 900 also has various possible implementations. The following are two optional implementations as examples:

[0131] In a first optional implementation, as shown in Figures 5, 6, 8, and 9, the third active layer 920 of the third transistor 900 is a planar structure. Parts at various locations within this third active layer 920 are co-located with and made of the same material as the first active layer 220 of the first transistor 200 and the second active layer 320 of the second transistor 300. In this case, the third channel region 923 in the third active layer 920, as well as the fifth conductor portion 921 and the sixth conductor portion 922 located on either side of the third channel region 923, are all planar structures parallel to the substrate 100.

[0132] The second optional implementation is illustrated in Figure 11, which is a schematic diagram of the film structure of a driving backplane provided in an embodiment of this application. A portion of the third active layer 920 of the third transistor 900 is co-located and made of the same material as the first active layer 220 of the first transistor 200 and the second active layer 320 of the second transistor 300. That is, a portion of the third active layer 920 is formed in the same patterning process as the first active layer 220 and the second active layer 320, while another portion of the third active layer 920 needs to be formed in a separate patterning process.

[0133] In this configuration, the third insulating layer 920 of the third transistor 900 may have a first groove O1 and a second groove O2. The third active layer 920 of the third transistor 900 includes a planar portion 920a, a first vertical portion 920b, and a second vertical portion 920c. The planar portion 920a of the third active layer 920 is co-located with the first active layer 220 of the first transistor 200 and the second active layer 320 of the second transistor 300, and is made of the same material. The orthographic projections of the first groove O1 and the second groove O2 onto the substrate 100 are both located within the orthographic projection of the planar portion 920a of the third active layer 920 onto the substrate 100, and are distributed on opposite sides of the planar portion 920a. The first vertical portion 920b of the third active layer 920 is located within the first groove O1 and is connected to the planar portion 920a of the third active layer 920; the second vertical portion 920c of the third active layer 920 is located within the second groove O2 and is connected to the planar portion 920a of the third active layer 920. Here, the planar portion 920a of the third active layer 920 is formed in the same patterning process as the first active layer 220 and the second active layer 320, while the first vertical portion 920b and the second vertical portion 920c of the third active layer 920 need to be formed simultaneously in another patterning process.

[0134] Thus, the third active layer 920 has a U-shaped structure, resulting in a smaller size of the third active layer 920 in the direction parallel to the substrate 100. This effectively reduces the size of the third transistor 900, making the space occupied by the third transistor 900 in the non-display area 00b of the driving backplane 000 smaller, thereby reducing the width of the non-display area 00b of the driving backplane 000. After forming multiple light-emitting devices on this driving backplane 000 to obtain a display panel, the bezel width of the display panel can be ensured to be small, resulting in a high screen-to-body ratio.

[0135] It should be noted that, within the third active layer 920 of the third transistor 900, at least a portion of the planar portion 920a can serve as the third channel region 923 of the third active layer 920; at least a portion of the first vertical portion 920b can serve as the fifth conductor portion 921 of the third active layer 920, which can be electrically connected to the fifth electrode 930 of the third transistor 900; and at least a portion of the second vertical portion 920c can serve as the sixth conductor portion 922 of the third active layer 920, which can be electrically connected to the fifth electrode 940 of the third transistor 900.

[0136] In this application, the steps for forming the third active layer 920 as shown in FIG11 may include:

[0137] Step S11: A planar portion 920a of the third active layer 920 is formed on the side of the first insulating layer 500 away from the substrate 100.

[0138] Step S12: A third insulating layer 700 is formed on the side of the planar portion 920a of the third active layer 920 that is away from the substrate 100.

[0139] Step S13: A first groove O1 and a second groove O2 are formed on the side of the third insulating layer 700 opposite to the substrate 100. The orthographic projections of the first groove O1 and the second groove O2 on the substrate 100 are both located within the orthographic projection of the planar portion 920a on the substrate 100, and are distributed on opposite sides of the planar portion 920a.

[0140] Step S14: A first vertical portion 920b is formed in the first groove O1, and a second vertical portion 920c is formed in the second groove O2.

[0141] It should be noted that, please refer to Figure 12, which is a schematic diagram of the film structure of a third transistor provided in the embodiment of the application. When forming the planar portion 920a of the third active layer 920, a support groove O can be formed first on the first insulating layer 500 away from the substrate 100, and then the planar portion 920a of the third active layer 920 can be formed on the side of the first insulating layer 500 away from the substrate 100, such that the planar portion 920a is located in the support groove O. Afterwards, steps S12 and S13 described above are performed.

[0142] In summary, the driving backplane provided in this application includes a substrate, and a first transistor and a second transistor located on the same side of the substrate and connected to each other. The first transistor can serve as a driving thin-film transistor in a pixel driving circuit, and the second transistor can serve as a switching thin-film transistor in a pixel driving circuit. The first transistor includes a first gate, a first active layer, and a first auxiliary electrode, and the second transistor includes a second gate, a second active layer, and a third gate. The distance between the first active layer and the first auxiliary electrode is smaller than the distance between the second active layer and the third gate. This smaller distance between the first active layer and the first auxiliary electrode results in a larger parasitic capacitance between them, leading to a smaller actual current value in the first active layer and a larger subthreshold swing in the first transistor. This allows the voltage in the first active layer to reach the threshold voltage over a relatively long period and maintain a relatively stable threshold voltage. Even at low grayscale levels, the light-emitting device can be precisely controlled to express sufficient grayscale, effectively reducing the possibility of screen contamination at low grayscale levels. The larger distance between the second active layer and the third gate results in a smaller parasitic capacitance between them, leading to a larger actual current value in the second active layer. Furthermore, both the second and third gates of the second transistor can control the second active layer, further increasing the current. This results in a smaller subthreshold swing and better switching characteristics for the second transistor. After forming multiple light-emitting devices on this driving backplane to obtain the display panel, each pixel driving circuit in the driving backplane can more precisely control its corresponding light-emitting device, resulting in a better display effect.

[0143] This application embodiment also provides a display panel, which may include: a driving backplane 000 and a plurality of light-emitting devices, the plurality of light-emitting devices being electrically connected to the driving backplane 000. Here, the driving backplane 000 may be the driving backplane 000 shown in FIG1, FIG2, FIG3, FIG5, FIG6, FIG8, FIG9 or FIG11. For example, please refer to FIG13, FIG13 is a display panel provided in an embodiment of this application. The driving backplane 000 includes a plurality of pixel driving circuits, each pixel driving circuit may include a first transistor 200 and a second transistor 300. Each pixel driving circuit corresponds to a light-emitting device 001, the light-emitting device 001 being electrically connected to the second terminal 250 of the first transistor 200 in the corresponding pixel driving circuit, so that the light-emitting device 001 can emit light under the drive of the first transistor 200 of the pixel driving circuit.

[0144] This application also provides a display device, which can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The display device may include a display panel and a driver chip, wherein the display panel is the aforementioned display panel, and the driver chip is used to apply drive signals to the display panel.

[0145] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0146] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0147] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A drive backplane, characterized by, The drive backplane includes: a substrate, and a first transistor and a second transistor located on the same side of the substrate and connected to each other; The first transistor has a first active layer and a first auxiliary electrode; the first auxiliary electrode is located on the side of the first active layer facing the substrate and is electrically connected to the first active layer; the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate; The second transistor has a second active layer and a third gate; the third gate is located on the side of the second active layer facing the substrate and is insulated from the second active layer; the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the third gate on the substrate; The distance between the first active layer and the first auxiliary electrode is less than the distance between the second active layer and the third gate.

2. The drive backplane of claim 1, wherein, The first active layer and the second active layer are disposed in the same layer and are made of the same material; the first auxiliary electrode and the third gate are disposed in different layers, and the third gate is closer to the substrate than the first auxiliary electrode.

3. The drive backplane of claim 2, wherein, The drive backplate further includes: a second auxiliary electrode, which is located on the side of the first auxiliary electrode facing the substrate and is insulated from the first auxiliary electrode; the orthographic projection of the second auxiliary electrode on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate; The second auxiliary electrode and the third gate are disposed in the same layer and are made of the same material.

4. The drive backplane of claim 3, wherein, The drive backplane further includes: a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first active layer and the first auxiliary electrode, and the second insulating layer is located between the first auxiliary electrode and the second auxiliary electrode.

5. The drive backplane of any of claims 1-4, wherein, The first transistor further has a first gate located on the side of the first active layer away from the substrate and is insulated from the first active layer; the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the first gate on the substrate. The second transistor further has a second gate located on the side of the second active layer away from the substrate and insulated from the second active layer; the second gate is electrically connected to the third gate; the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second gate on the substrate; The first gate and the second gate are disposed in the same layer and are made of the same material.

6. The drive backplane of claim 5, wherein, The driving backplane has a display area and a non-display area located around the display area, and the first transistor and the second transistor are both located within the display area; The driving backplane further includes a third transistor, which is located on the side of the substrate where the first transistor and the second transistor are disposed, and the third transistor is located within the non-display area; The third transistor has a fourth gate and a third active layer. The fourth gate is located on the side of the third active layer away from the substrate and is insulated from the third active layer. The orthographic projection of the fourth gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate. The fourth gate, the first gate, and the second gate are disposed in the same layer and are made of the same material; at least a portion of the third active layer is disposed in the same layer as the first active layer and the second active layer and is made of the same material.

7. The drive backplane of claim 6, wherein, The third transistor also has a fifth gate located on the side of the third active layer facing the substrate and insulated from the third active layer; the fifth gate is electrically connected to the fourth gate; the orthographic projection of the fifth gate on the substrate overlaps with the orthographic projection of the third active layer on the substrate.

8. The drive backplane of claim 7, wherein, The fifth gate electrode is disposed in the same layer as the first auxiliary electrode and is made of the same material; Alternatively, the fifth gate is disposed in the same layer as the third gate and is made of the same material; Alternatively, the fifth gate includes: a first sub-gate and a second sub-gate electrically connected to the fourth gate, wherein the first sub-gate is disposed in the same layer as the first auxiliary electrode and is made of the same material, and the second sub-gate is disposed in the same layer as the third gate and is made of the same material.

9. The drive backplane of claim 8, wherein, In the case where the fifth gate includes a first sub-gate and a second sub-gate, the third transistor further includes: a first connection electrode and a second connection electrode, wherein the first connection electrode is used to connect the fourth gate and a first end of the first sub-gate, and the second connection electrode is used to connect the fourth gate and a first end of the second sub-gate; Wherein, the orthographic projection of the second end of the first sub-gate on the substrate overlaps with the orthographic projection of the second end of the second sub-gate on the substrate.

10. The drive backplane of claims 6-9, wherein, The driving backplane further includes: a third insulating layer, the third insulating layer being located between the first active layer and the first gate, and the third insulating layer having a first groove and a second groove; The third active layer includes: a planar portion, a first vertical portion, and a second vertical portion. The planar portion is disposed in the same layer as the first active layer and the second active layer and is made of the same material. The orthographic projections of the first groove and the second groove on the substrate are both located within the orthographic projection of the planar portion on the substrate and are distributed on opposite sides of the planar portion. The first vertical portion is located in the first groove and is connected to the planar portion. The second vertical portion is located in the second groove and is connected to the planar portion.

11. The drive backplane of claims 6-9, wherein, The driving backplane includes: a pixel driving circuit located in the display area, and a gate driving circuit located in the non-display area; Wherein, the first transistor is the driving transistor in the pixel driving circuit, the second transistor is the switching transistor in the pixel driving circuit, and the gate driving circuit includes a plurality of the third transistors.

12. The drive backplane of any of claims 5, wherein, The first transistor further has a first electrode and a second electrode, and the first active layer includes: a first conductor portion and a second conductor portion disposed opposite to each other, and a first channel region located between the first conductor portion and the second conductor portion; The first electrode is electrically connected to the first conductor portion and the first auxiliary electrode, the second electrode is connected to the second conductor portion, the orthographic projection of the first channel region on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the second conductor portion on the substrate overlaps with the orthographic projection of the first auxiliary electrode on the substrate.

13. The drive backplane of claim 12, wherein, The second transistor also has a third electrode, a fourth electrode and a third connection electrode, and the second active layer includes: a third conductor portion and a fourth conductor portion disposed opposite to each other, and a second channel region located between the third conductor portion and the fourth conductor portion; The third electrode is electrically connected to the third conductor portion, and the fourth electrode is connected to the fourth conductor portion; the orthographic projection of the second channel region on the substrate is located within the orthographic projection of the second gate on the substrate, and is also located within the orthographic projection of the third gate on the substrate; the third connecting electrode is connected to the second gate and also to the third gate.

14. A display panel, characterized by The display panel includes a driving backplate and a plurality of light-emitting devices, wherein the driving backplate is the driving backplate according to any one of claims 1 to 13, and the plurality of light-emitting devices are electrically connected to the driving backplate.

15. A display device comprising: The display device includes a display panel and a driver chip, wherein the display panel is the display panel as described in claim 14, and the driver chip is used to apply a driving signal to the display panel.

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