Display substrate, manufacturing method thereof and display device
By covering the first active layer with a metal oxide layer before high-temperature annealing, the problems of process stability and high cost of LTPO Oxide BCE structure display substrate are solved, achieving higher process stability and lower cost.
Patent Information
- Application Number
- CN202210303696.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-24
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2042-03-24
AI Technical Summary
The existing LTPO Oxide BCE structure display substrate has problems with poor process stability and high process cost in the process, mainly because the SiO film is easily damaged during the etching process, resulting in defects in the third gate insulation layer and poor product display.
The exposed first active layer is covered with a metal oxide layer before high-temperature annealing to avoid etching and removing the oxide layer on the surface of the first active layer, thereby omitting the etching process, improving process stability and reducing costs.
By covering the metal oxide layer, defects in the third gate insulating layer caused by etching are avoided, process stability is improved, product display defects are reduced, and process costs are reduced.
Smart Images
Figure CN114725015B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art
[0002] The semiconductor types used in OLED (Organic Light-Emitting Diode) display panels mainly include LTPO (Low Temperature Polycrystalline Oxide), LTPS (Low Temperature Poly-silicon), and oxide. Among them, LTPO semiconductors combine LTPS semiconductors and oxide semiconductors, combining the advantages of LTPS semiconductors, such as high mobility and fast charging, with the advantages of oxide, such as low leakage current and low power consumption. Therefore, OLED display panels using LTPO semiconductors have become the mainstream development trend in the industry.
[0003] The process of LTPO semiconductors includes the production of LTPS TFT and Oxide TFT. Among them, according to the different film layer structures, Oxide TFT can be subdivided into three structures: Top Gate, BCE and EXL. At present, the LTPO semiconductor with Top Gate structure (which can be called LTPO Oxide TOP Gate structure) is the mainstream development structure, but compared with the LTPO semiconductor with BCE structure (which can be called LTPO Oxide BCE structure), its process is complex and the process cost is high. The LTPO semiconductor with BCE structure has poor process stability, which has become the main factor restricting its development. Summary of the Invention
[0004] The present application provides a display substrate, a manufacturing method thereof, and a display device to improve the process stability of the existing LTPO Oxide BCE structure display substrate.
[0005] According to a first aspect of an embodiment of the present application, a method for manufacturing a display substrate is provided, comprising the steps of:
[0006] providing a substrate;
[0007] forming a first active layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, a first interlayer dielectric layer and a third gate insulating layer in sequence on the base substrate;
[0008] forming a via hole above the first active layer, wherein the via hole passes through the third gate insulating layer and extends to the first active layer;
[0009] Depositing a metal oxide layer for forming a second active layer, wherein the metal oxide layer covers the first active layer located at the via hole position;
[0010] Performing high temperature annealing to improve the subthreshold swing of the first active layer;
[0011] The metal oxide layer is patterned to form a second active layer.
[0012] In one embodiment, depositing a metal oxide layer for forming the second active layer specifically comprises the steps of:
[0013] A metal oxide layer for forming a second active layer is deposited on the surface of the third gate insulating layer and the bottom and wall of the via hole.
[0014] In one embodiment, patterning the metal oxide layer to form a second active layer specifically includes the steps of:
[0015] The metal oxide layer in the via hole is etched away, and the metal oxide layer on the surface of the third gate insulating layer is patterned to form a second active layer.
[0016] In one embodiment, patterning the metal oxide layer to form a second active layer specifically includes the steps of:
[0017] The metal oxide layer in the via hole is retained, and the metal oxide layer on the surface of the third insulating layer is patterned to form a second active layer.
[0018] In one embodiment, after forming the second active layer, further forming the first source electrode and the first drain electrode specifically includes the following steps:
[0019] depositing a metal layer on the metal oxide layer in the via hole, on the third insulating layer, and on the second active layer;
[0020] The metal layer is patterned to form the first source electrode and the first drain electrode.
[0021] In one embodiment, the metal oxide layer in the via hole extends to a surface of the third insulating layer.
[0022] In one embodiment, the metal oxide layer is made of IGZO, IZO or GZO.
[0023] In one embodiment, the third gate insulating layer is made of SiO.
[0024] According to a second aspect of an embodiment of the present application, a display substrate is provided. The display substrate is a display substrate manufactured according to any of the above-mentioned manufacturing methods.
[0025] According to a third aspect of an embodiment of the present application, a display device is provided, comprising a display substrate manufactured according to any of the above-mentioned manufacturing methods.
[0026] The beneficial effects of the technical solution provided by the embodiments of the present application are:
[0027] When manufacturing a display substrate using the method of the present application, the exposed first active layer is covered with a metal oxide layer before high-temperature annealing. This prevents the formation of an oxide layer on the surface of the first active layer during high-temperature annealing. Consequently, after high-temperature annealing, the oxide layer on the surface of the first active layer does not need to be removed by etching. This eliminates the need for an etching process, thereby substantially avoiding defects in the third gate insulating layer caused by etching. This, in turn, substantially avoids issues such as low process stability and poor product display caused by etching. Furthermore, eliminating the etching process effectively reduces process costs.
[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1a-Figure 1d This is a flow chart of film layer production of a display substrate provided by an embodiment of the prior art;
[0030] Figure 2 Schematic diagram of a defect in which a defect occurs in the third gate insulating layer at the chamfer of the second gate;
[0031] Figure 3 is the surface morphology of the third gate insulating layer before etching;
[0032] Figure 4 is the cross-sectional morphology of the third gate insulating layer before etching;
[0033] Figure 5 is the surface morphology of the third gate insulating layer after etching;
[0034] Figure 6 is the cross-sectional morphology of the third gate insulating layer after etching;
[0035] Figure 7 This is a flowchart of the steps of displaying a substrate provided by an embodiment of the present application;
[0036] Figure 8a-8c This is a flow chart of film production of a display substrate provided in an embodiment of the present application;
[0037] Figure 9is another structural schematic diagram of a display substrate provided in an embodiment of the present application;
[0038] Figure 10 This is another step flow chart of the display substrate provided in an embodiment of the present application.
[0039] The symbols in the accompanying drawings are:
[0040] First active layer 1'; first gate insulating layer 2'; first gate electrode 3'; second gate insulating layer 4'; second gate electrode 5'; first interlayer dielectric layer 6'; third gate insulating layer 7'; second active layer 8'; first source electrode 9'; first drain electrode 10'; via 11';
[0041] First active layer-1; first gate insulating layer-2; first gate electrode-3; second gate insulating layer-4; second gate electrode-5; first interlayer dielectric layer-6; third gate insulating layer-7; metal oxide layer-8; second active layer-81; via-9; first buffer layer-10. DETAILED DESCRIPTION
[0042] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
[0043] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0044] In existing related technologies, the basic process of display substrates using LTPO Oxide BCE structure mainly includes:
[0045] A first active layer 1', a first gate insulating layer 2', a first gate electrode 3', a second gate insulating layer 4', a second gate electrode 5', a first interlayer dielectric layer 6' and a third gate insulating layer 7' are sequentially formed on the substrate. Figure 1a As shown;
[0046] A via hole 11' is formed above the first active layer 1'. Figure 1b As shown;
[0047] Performing high temperature annealing to improve the subthreshold swing of the first active layer 1';
[0048] Etching (Etch) away the oxide on the surface of the first active layer 1', wherein the oxide on the surface of the first active layer 1' is formed during high-temperature annealing;
[0049] The second active layer 8' is formed as follows Figure 1c As shown;
[0050] The subsequent film layers are formed, e.g. Figure 1d As shown, a first source electrode 9 ′ and a first drain electrode 10 ′ (the first source electrode 9 ′ and the first drain electrode 10 ′ may be referred to as source and drain electrodes, ie, SD) are formed to complete the display substrate manufacturing.
[0051] However, the display substrate manufactured by the above process has the problem of process stability.
[0052] After extensive research, the inventors have discovered that the material of the third gate insulating layer 7' is SiO (silicon oxide) thin film. The film quality of SiO thin film is relatively poor. When etching the oxide on the surface of the first active layer 1', the SiO thin film is easily damaged by etching, which leads to two problems:
[0053] 1) If Figure 2 As shown, the SiO film is prone to cracks at the chamfer of the second gate 5', which makes it easy for the second gate 5' to short-circuit with the SD at the defect, resulting in poor product display.
[0054] 2) If Figure 3 、 Figure 4 As shown in Figure 2, before the etching process, the surface of the SiO film is relatively smooth and has a small roughness; however, Figure 5 、 Figure 6 As shown, after the etching process, the surface of the SiO film becomes uneven and rough, and in severe cases, pinholes may even appear on the surface. Since the SiO film is the gate insulating layer in contact with the channel of the second active layer 8', the pinholes and roughness on the surface of the SiO film will affect the characteristic stability of the second active layer 8'.
[0055] To this end, the present application provides a method for manufacturing a display substrate, such as Figure 7 As shown, the specific steps include:
[0056] Step S10, providing a base substrate;
[0057] Step S20, forming a first active layer 1, a first gate insulating layer 2, a first gate electrode 3, a second gate insulating layer 4, a second gate electrode 5, a first interlayer dielectric layer 6 and a third gate insulating layer 7 in sequence on the base substrate;
[0058] Step S30: forming a via hole 9 above the first active layer 1. Figure 8a As shown;
[0059] Step S40, depositing a metal oxide layer 8 for forming a second active layer 81, and covering the first active layer 1 at the position of the via hole 9 with the metal oxide layer 8, as shown in FIG. Figure 8b As shown;
[0060] Step S50, performing high temperature annealing to improve the subthreshold swing of the first active layer 1;
[0061] Step S60: patterning the metal oxide layer 8 to form a second active layer 81. Figure 8c shown.
[0062] When manufacturing a display substrate using the above method, the exposed first active layer 1 is covered with a metal oxide layer 8 before high-temperature annealing (CNT annealing). This prevents the formation of an oxide layer on the surface of the first active layer 1 during the high-temperature annealing. Consequently, after the high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching. This eliminates the need for an etching process, thereby substantially avoiding defects in the third gate insulating layer 7 caused by etching. This, in turn, substantially avoids issues such as low process stability and poor product display caused by etching. Furthermore, eliminating the etching process effectively reduces process costs.
[0063] In step S10, the base substrate may be made of glass, preferably white glass, which has high transparency.
[0064] In step S20 , the first active layer 1 , the first gate insulating layer 2 , the first gate electrode 3 , the second gate insulating layer 4 , the second gate electrode 5 , the first interlayer dielectric layer 6 and the third gate insulating layer 7 can all be formed through a single patterning process.
[0065] The first active layer 1 can also be referred to as an LTPS TFT. The material of the first active layer 1 is preferably p-Si (polycrystalline silicon), which has a fast electron migration rate. After forming the first active layer 1, defects within and on its surface need to be repaired using hydrogen (H). However, hydrogen is relatively unstable and easily escapes from the surface of the first active layer 1.
[0066] The material of the first gate insulating layer 2 and the second gate insulating layer 4 is preferably SiO 2 (silicon oxide), which has good stability.
[0067] The third gate insulating layer 7 is preferably made of SiO (silicon oxide). SiO can protect the second active layer 81 (also called oxide TFT). When the via hole 9 is provided above the first active layer 1, it can reduce the impact of hydrogen (H) escaping from the first active layer 1 on the second active layer 81.
[0068] The first gate 3 and the second gate 5 located directly above the first gate 3 are used to form a pixel capacitor. The second gate 5 located obliquely above the first gate 3 serves as the bottom gate of the oxide semiconductor portion.
[0069] Furthermore, other film layers, such as a polyimide (PI) layer, a barrier layer, and / or a first buffer layer, may be formed between the first active layer 1 and the base substrate as required. In this case, when manufacturing the display substrate, the other film layers are first formed on the base substrate, and then the first active layer 1 is formed on top of the other film layers.
[0070] In step S30, a mask process can be used to form vias 9. Vias 9 extend upward from the first active layer 1 and penetrate the third gate insulating layer 7, exposing the first active layer 1. The aperture of vias 9 is on the micrometer scale to ensure good contact between the first source and first drain electrodes deposited in vias 9 and the first active layer 1, while also facilitating deposition of the metal oxide layer 8 in vias 9. In one specific example, the aperture of vias 9 is 20-80 μm.
[0071] In step S40, a metal oxide layer 8 is deposited on the surface of the third gate insulating layer 7 and on the bottom and walls of the via hole 9, covering the third gate insulating layer 7 and the exposed first active layer 1. Depositing the metal oxide layer 8 on the bottom and walls of the via hole 9 means that the via hole 9 is not completely filled with the metal oxide layer 8, but rather that the metal oxide layer 8 is deposited only on the bottom and walls of the via hole 9. In this way, the metal oxide layer 8 can provide better protection for the third gate insulating layer 7 and the exposed first active layer 1, while substantially not affecting the subthreshold swing of the first active layer 1 during high-temperature annealing.
[0072] The thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 can be in the nanometer range, i.e., a numerical range greater than 1 nm and less than 1000 nm. Optionally, the thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 is 100-500 nm, including endpoints of 100 nm and 500 nm. Preferably, the thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 is 100-200 nm, including endpoints of 100 nm and 200 nm. When depositing the metal oxide layer 8, due to limitations of the deposition process, the thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 may be greater than the thickness of the metal oxide layer 8 in the via 9. When the metal oxide layer 8 located on the surface of the third gate insulating layer 7 is several hundred nanometers, the thickness of the metal oxide layer 8 in the via 9 is several tens of nanometers. In this case, the metal oxide layer 8 can meet the thickness requirement for forming the second active layer 81 and has little impact on improving the subthreshold swing (SS) of the first active layer 1.
[0073] In addition, the material of the metal oxide layer 8 can be any one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide) and GZO (gallium zinc oxide). Here, the material of the metal oxide layer 8 is preferably IGZO, which has a fast electron migration speed and good stability.
[0074] In step S50, the subthreshold swing is an important parameter of the MOSFET when it operates in the subthreshold state and is used as a logic switch. It is also called the S factor and is defined as: S = dVgs / d(log10 Id), with the unit being [mV / dec].
[0075] The hydrogen on the surface of the first active layer 1 is unstable and needs to be annealed at high temperature. After the annealing, the hydrogen on the surface of the first active layer 1 escapes, increasing the defects on the surface of the first active layer 1 and increasing the subthreshold swing of the first active layer 1.
[0076] After the metal oxide layer 8 is deposited on the surface of the first active layer 1 , hydrogen on the surface of the first active layer 1 can still escape during high-temperature annealing, and the metal oxide layer 8 will basically not affect the improvement of the subthreshold swing of the first active layer 1 .
[0077] It should be noted that the annealing time and annealing temperature during high temperature annealing are substantially the same as those during normal high temperature annealing.
[0078] In step S60, the second active layer 81 can be formed by a mask process. At this time, the metal oxide layer 8 in the via hole 9 can be retained (eg Figure 9 The mask pattern is set according to the requirements.
[0079] When the metal oxide layer 8 is retained in the via hole 9 , the metal oxide layer 8 can protect the first active layer 1 , thereby reducing the risk of oxidation of the first active layer 1 in subsequent manufacturing processes.
[0080] Furthermore, when the metal oxide layer 8 is retained in the via 9, the metal oxide layer 8 in the via 9 extends to the surface of the third insulating layer, thereby reducing the risk of the metal oxide layer 8 in the via 9 falling off. The width of the metal oxide layer 8 in the via 9 extending to the surface of the third insulating layer can be specifically set according to needs.
[0081] After forming the second active layer 81, subsequent film layers are formed to complete the production of the display substrate. The subsequent film layers are the same as the usual subsequent film layers, for example, including a first source electrode and a first drain electrode.
[0082] It should be noted that when the metal oxide layer 8 is retained in the via 9 , the metal layer constituting the first source and the first drain is deposited on the metal oxide layer 8 in the via 9 , and the metal layer directly contacts the metal oxide layer 8 in the via 9 .
[0083] The second embodiment of the present application provides another method for manufacturing a display substrate, such as Figure 10 As shown, the specific steps include:
[0084] Step S10, providing a base substrate;
[0085] Step S20, forming a first active layer 1, a first gate insulating layer 2, a first gate electrode 3, a second gate insulating layer 4, a second gate electrode 5, a first interlayer dielectric layer 6 and a third gate insulating layer 7 in sequence on the base substrate;
[0086] Step S30, forming a via hole 9 above the first active layer 1;
[0087] Step S40, depositing a metal oxide layer 8 for forming a second active layer 81, and covering the first active layer 1 located at the via hole 9 with the metal oxide layer 8;
[0088] Step S50 , patterning the metal oxide layer 8 to form a second active layer 81 ;
[0089] Step S60 , performing high temperature annealing to improve the subthreshold swing of the first active layer 1 .
[0090] It should be noted that in this manufacturing method, during step S50, i.e., patterning the metal oxide layer 8, it is necessary to retain the metal oxide layer 8 within the via 9. During step S60, i.e., high-temperature annealing, the metal oxide layer 8 protects the first active layer 1, preventing oxidation of the first active layer 1. Thus, after the high-temperature annealing, there is no need to etch away the oxide layer on the surface of the first active layer 1, thus eliminating the etching process. This substantially avoids defects in the third gate insulating layer 7 caused by etching, and further substantially avoids issues such as low process stability and poor product display caused by etching. Furthermore, eliminating the etching process effectively reduces process costs.
[0091] In step S10 , the material of the base substrate can be glass, preferably white glass.
[0092] In step S20 , the first active layer 1 , the first gate insulating layer 2 , the first gate electrode 3 , the second gate insulating layer 4 , the second gate electrode 5 , the first interlayer dielectric layer 6 and the third gate insulating layer 7 can all be formed through a single patterning process.
[0093] The first active layer 1 is preferably made of p-Si. After forming the first active layer 1, defects within and on its surface need to be repaired using hydrogen (H). The first gate insulating layer 2 and the second gate insulating layer 4 are preferably made of SiO2. The third gate insulating layer 7 is preferably made of SiO.
[0094] Other film layers, such as a polyimide layer, a barrier layer and / or a first buffer layer 10 , may be formed between the first active layer 1 and the base substrate as required.
[0095] In step S30, a mask process may be used to form the via hole 9. The aperture of the via hole 9 is in the micron level. In a specific example, the aperture of the via hole 9 is 20-80 μm.
[0096] In step S40 , a metal oxide layer 8 is deposited on the surface of the third gate insulating layer 7 and on the bottom and wall of the via hole 9 , and the metal oxide layer 8 covers the third gate insulating layer 7 and the exposed first active layer 1 .
[0097] The thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 can be in the nanometer range. Preferably, the thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 is 100-500 nm, including endpoints of 100 nm and 500 nm. More preferably, the thickness of the metal oxide layer 8 located on the surface of the third gate insulating layer 7 is 100-200 nm, including endpoints of 100 nm and 200 nm.
[0098] In addition, the material of the metal oxide layer 8 may be any one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and GZO (gallium zinc oxide).
[0099] In step S50, a second active layer 81 may be formed by a mask process. The metal oxide layer 8 in the via hole 9 extends to the surface of the third insulating layer.
[0100] In step S60 , the annealing time and the annealing temperature during the high temperature annealing are substantially the same as the annealing time and the annealing temperature during the normal high temperature annealing.
[0101] After forming the second active layer 81, subsequent film layers are formed to complete the display substrate. These subsequent film layers are similar to conventional film layers and include, for example, a first source electrode and a first drain electrode. The metal layer forming the first source electrode and the first drain electrode is deposited on the metal oxide layer 8 in the via hole 9, directly contacting the metal oxide layer 8 in the via hole 9.
[0102] Embodiment 3 of the present application provides a display substrate. This display substrate is a display substrate manufactured according to Embodiment 1 or Embodiment 2. In this display substrate, before high-temperature annealing, the exposed first active layer 1 is covered with a metal oxide layer 8. Thus, during high-temperature annealing, no oxide layer forms on the surface of the first active layer 1. Therefore, after high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, thus eliminating the etching process. This substantially avoids defects in the third gate insulating layer 7 caused by etching, and further substantially avoids problems such as low process stability and poor product display caused by etching. Furthermore, eliminating the etching process effectively reduces process costs.
[0103] Embodiment 4 of the present application provides a display device. The display device includes a display substrate manufactured according to embodiment 1 or embodiment 2. In this display substrate, before high-temperature annealing, the exposed first active layer 1 is covered with a metal oxide layer 8. Thus, during high-temperature annealing, no oxide layer forms on the surface of the first active layer 1. Therefore, after high-temperature annealing, the oxide layer on the surface of the first active layer 1 does not need to be removed by etching, thus eliminating the etching process. This substantially avoids defects in the third gate insulating layer 7 caused by etching, and further substantially avoids problems such as low process stability and poor product display caused by etching. Furthermore, eliminating the etching process effectively reduces process costs.
[0104] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0105] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A method for manufacturing a display substrate, characterized in that: Including steps: providing a substrate; forming a first active layer, a first gate insulating layer, a first gate electrode, a second gate insulating layer, a second gate electrode, a first interlayer dielectric layer and a third gate insulating layer in sequence on the base substrate; forming a via hole above the first active layer, wherein the via hole passes through the third gate insulating layer and extends to the first active layer; Depositing a metal oxide layer for forming a second active layer, wherein the metal oxide layer covers the first active layer located at the via hole position; After depositing the metal oxide layer for forming the second active layer, high-temperature annealing is performed to improve the subthreshold swing of the first active layer, and during the high-temperature annealing, the metal oxide layer covers the portion of the first active layer exposed by the via hole; The metal oxide layer is patterned to form a second active layer.
2. The method for manufacturing a display substrate according to claim 1, wherein: Depositing a metal oxide layer for forming a second active layer specifically comprises the steps of: A metal oxide layer for forming a second active layer is deposited on the surface of the third gate insulating layer and the bottom and wall of the via hole.
3. The method for manufacturing a display substrate according to claim 2, wherein: Patterning the metal oxide layer to form a second active layer specifically includes the steps of: The metal oxide layer in the via hole is etched away, and the metal oxide layer on the surface of the third gate insulating layer is patterned to form a second active layer.
4. The method for manufacturing a display substrate according to claim 2, wherein: Patterning the metal oxide layer to form a second active layer specifically includes the steps of: The metal oxide layer in the via hole is retained, and the metal oxide layer on the surface of the third gate insulating layer is patterned to form a second active layer.
5. The method for manufacturing a display substrate according to claim 4, wherein: After forming the second active layer, further forming a first source electrode and a first drain electrode; forming the first source electrode and the first drain electrode specifically includes the steps of: depositing a metal layer on the metal oxide layer in the via hole, on the third gate insulating layer, and on the second active layer; The metal layer is patterned to form the first source electrode and the first drain electrode.
6. The method for manufacturing a display substrate according to claim 4, wherein: The metal oxide layer in the via hole extends to a surface of the third gate insulating layer.
7. The method for manufacturing a display substrate according to any one of claims 1 to 6, wherein: The material of the metal oxide layer is IGZO, IZO or GZO.
8. The method for manufacturing a display substrate according to any one of claims 1 to 6, wherein: The material of the third gate insulating layer is SiO.
9. A display substrate, characterized in that: The display substrate is a display substrate manufactured according to the manufacturing method according to any one of claims 1 to 8.
10. A display device, characterized in that: The invention comprises a display substrate manufactured by the manufacturing method according to any one of claims 1-8.
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