A negative capacitance tunneling phototransistor, its fabrication method, and its application.

Abstract

This invention relates to the field of optoelectronic device technology, and more particularly to a negative capacitance tunneling phototransistor, its fabrication method, and its applications. The negative capacitance tunneling phototransistor of this invention is a structure combining ferroelectric materials and low-dimensional semiconductor heterojunction materials. It combines the properties of ferroelectric materials with the tunneling effect and photoelectric properties of low-dimensional semiconductor heterojunctions. Hafnium oxide-based ferroelectric gate dielectric replaces the gate dielectric layer of traditional phototransistors, providing a negative capacitance effect in the gate structure of the negative capacitance tunneling phototransistor to improve device performance. The negative capacitance effect of the ferroelectric material enhances the electrical performance of the tunneling field-effect transistor, improving the on / off ratio and on-state current, and further reducing the subthreshold swing, while simultaneously improving the photoelectric responsivity and response speed. The combination of the gate and the low-dimensional semiconductor heterojunction achieves ultra-low subthreshold swing and no hysteresis. Furthermore, it possesses advantages such as good stability, simple structure, and ease of fabrication.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic device technology, and in particular to a negative capacitance tunneling phototransistor, its fabrication method, and its application. Background Technology

[0002] Reducing power consumption and minimizing device size are key objectives in the development of integrated circuit microelectronic devices. To meet the ever-evolving demands of circuits and electronic components, the field of optoelectronics has also begun to emphasize the need for low power consumption and small size in photodetectors and other optoelectronic devices. This requires devices to maintain good performance in terms of on-state current, on-off ratio, and current hysteresis while possessing low operating voltage and low subthreshold swing. In recent years, several novel electronic devices have been proposed to overcome the Boltzmann limit on the performance of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), such as tunneling field-effect transistors (TEFETs), negative capacitance field-effect transistors (NCFETs), impulse ionization field-effect transistors (IFETs), and Dirac source field-effect transistors (DFETs). Among these, TFETs and NFETs are considered the most efficient low-power transistor devices. TFETs achieve the breakthrough of the subthreshold swing limit through the carrier band tunneling principle, while NFETs achieve the breakthrough through the negative capacitance effect of the material. This makes TFETs and NFETs highly promising for low-power and ultra-low-power electronic applications.

[0003] However, traditional tunneling field-effect transistors (TFETs) suffer from problems such as dangling bonds between the semiconductor and the gate oxide layer, affecting gate control efficiency and carrier transport, thus limiting device performance. Furthermore, the switching process in TFETs is predominantly band-to-band tunneling, meaning they need to operate at relatively low bias voltages. This results in relatively low on-state current and on-state ratios. Similarly, negative capacitance field-effect transistors (FETs) face performance limitations due to poor interfaces between the gate dielectric and the semiconductor channel. The ferroelectric material in negative capacitance FETs is prone to polarization in an electric field, leading to instability and hysteresis in their current-voltage curves. Summary of the Invention

[0004] The purpose of this invention is to provide a negative capacitance tunneling phototransistor, its fabrication method, and its applications. The negative capacitance tunneling phototransistor exhibits excellent photoelectric performance, good stability, and a simple structure.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0006] The present invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, an oxide gate dielectric layer, and a low-dimensional semiconductor material heterojunction layer stacked sequentially.

[0007] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surfaces of the first low-dimensional semiconductor material and the lower surfaces of the second low-dimensional semiconductor material are at the same horizontal height.

[0008] The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer;

[0009] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0010] It also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0011] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface.

[0012] Preferably, the substrate is a P-type doped silicon substrate.

[0013] Preferably, the oxide layer is made of silicon dioxide.

[0014] Preferably, the material of the gate electrode layer is titanium nitride.

[0015] Preferably, the material of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is a doped hafnium oxide-based ferroelectric material;

[0016] The doping elements of the hafnium oxide-based ferroelectric material are one or more of zirconium, silicon, yttrium, and aluminum.

[0017] Preferably, the material of the oxide gate dielectric layer is hafnium oxide and / or aluminum oxide.

[0018] Preferably, the first low-dimensional semiconductor material is a transition metal chalcogenide;

[0019] The second low-dimensional semiconductor material is a two-dimensional black phosphorus material.

[0020] Preferably, the metal source electrode and the metal drain electrode are both chromium electrodes and gold electrodes stacked together.

[0021] This invention also provides a method for fabricating the negative capacitance tunneling phototransistor described above, comprising the following steps:

[0022] An oxide layer was prepared on the surface of a substrate by thermal oxidation.

[0023] A gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, and an oxide gate dielectric layer are sequentially deposited on the surface of the oxide layer.

[0024] A low-dimensional semiconductor heterojunction layer was prepared on the second and third surfaces of the oxide gate dielectric layer using a mechanical peeling and transfer method.

[0025] A metal drain electrode is formed on the first surface of the oxide gate dielectric layer, and a metal source electrode is formed on the fourth surface of the oxide gate dielectric layer. Both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

[0026] The present invention also provides the application of the negative capacitance tunneling phototransistor described in the above technical solution or the negative capacitance tunneling phototransistor prepared by the preparation method described in the above technical solution in the optoelectronic field.

[0027] This invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with a negative capacitance effect, an oxide gate dielectric layer, and a low-dimensional semiconductor material heterojunction layer stacked sequentially. The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material and a second low-dimensional semiconductor material. A portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surfaces of the first and second low-dimensional semiconductor materials are at the same horizontal height. The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first and fourth surfaces located within the oxide gate dielectric layer. The outer side of the surface; the lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface; it also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface; the first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface. The negative capacitance tunneling phototransistor of the present invention is a negative capacitance tunneling phototransistor structure that combines ferroelectric materials and low-dimensional semiconductor heterojunction materials. It proposes a novel phototransistor structure that combines the characteristics of ferroelectric materials with the tunneling effect and photoelectric characteristics of low-dimensional semiconductor heterojunctions. It uses a hafnium oxide-based ferroelectric gate dielectric to replace the gate dielectric layer of a traditional phototransistor, providing a negative capacitance effect in the gate structure of the negative capacitance tunneling phototransistor to improve device performance. The electrical performance of the tunneling field-effect transistor is enhanced by utilizing the negative capacitance effect of ferroelectric materials, thereby improving the device's on / off ratio and on-state current, further reducing the subthreshold swing, and simultaneously improving the device's photoresponsivity and response speed. Furthermore, this invention achieves an ultra-low subthreshold swing and hysteresis-free negative capacitance tunneling phototransistor through the arrangement of a gate and a low-dimensional semiconductor heterojunction. The low-dimensional semiconductor heterojunction forms a gap-type band structure, promoting effective carrier tunneling between the valence band and conduction band. In addition, the negative capacitance tunneling phototransistor also possesses advantages such as good stability, simple structure, and ease of fabrication. Testing shows that the negative capacitance tunneling phototransistor of this invention achieves an ultra-low subthreshold swing of 13.4 mV / dec and a maximum on / off ratio of 10. 6Furthermore, it exhibits near-zero hysteresis in the subthreshold region. Under 520nm laser illumination, this negative capacitance tunneling phototransistor achieves a maximum responsivity of 42A / W and a fastest response time of 8μs. This negative capacitance tunneling phototransistor combines the negative capacitance effect of ferroelectric materials with the tunneling effect and optoelectronic properties of low-dimensional semiconductor heterojunctions, significantly improving its electrical and optoelectronic performance. It holds immense potential for future development in the field of low-power, small-size optoelectronic devices. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the cross-sectional structure of the negative capacitance tunneling phototransistor described in this invention;

[0029] Figure 2 This is a schematic diagram of the operation of the negative capacitance tunneling phototransistor under ferroelectric control, where V G V is the gate voltage. SD This is the source-drain bias voltage;

[0030] Figure 3 This is a schematic diagram of the equivalent capacitance of the negative capacitance tunneling phototransistor under ferroelectric control, where Ψ S Low-dimensional semiconductor channel surface potential, C S Low-dimensional semiconductor channel capacitance, C ox Gate hafnium oxide dielectric capacitor, C Fe Ferroelectric grid dielectric capacitor with negative capacitance effect;

[0031] Figure 4 The diagram shows the electrical characteristics of the negative capacitance tunneling phototransistor described in Example 1, with a source-drain bias of 0.2V. Here, a is the electrical transfer characteristic curve, and b is the calculated subthreshold swing value of the electrical transfer characteristic curve.

[0032] Figure 5 The image shows the photoelectric response characteristics of the negative capacitance tunneling phototransistor described in Example 1 under different incident light powers (incident light wavelength is 520nm), where a is the output characteristic curve of the negative capacitance tunneling phototransistor under different incident light powers, b is the responsivity of the negative capacitance tunneling phototransistor under different incident light powers, and c is the response time of the negative capacitance tunneling phototransistor under 520nm laser irradiation.

[0033] Wherein, 1-substrate, 2-oxide layer, 3-gate electrode layer, 4-hafnium oxide ferroelectric gate dielectric layer with negative capacitance effect, 5-oxide gate dielectric layer, 6-first low-dimensional semiconductor material, 7-second low-dimensional semiconductor material, 8-metal source electrode, 9-metal drain electrode. Detailed Implementation

[0034] The present invention provides a negative capacitance tunneling phototransistor, comprising a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, an oxide gate dielectric layer, and a low-dimensional semiconductor material heterojunction layer stacked sequentially.

[0035] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material and a second low-dimensional semiconductor material; a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surfaces of the first low-dimensional semiconductor material and the lower surfaces of the second low-dimensional semiconductor material are at the same horizontal height.

[0036] The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer;

[0037] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0038] It also includes a metal source electrode and a metal drain electrode; the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0039] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface.

[0040] In this invention, the substrate is preferably a p-type doped silicon substrate, and the p-type doping concentration of the p-type doped silicon substrate is preferably 4 to 9 × 10⁻⁶. 19 cm -3 More preferably 4 to 6 × 10 19 cm -3 The optimal value is 4×10 19 cm -3 In this invention, the thickness of the substrate is preferably 270–550 nm, more preferably 280–290 nm, and most preferably 285 nm. In this invention, the selection of p-type doping in the substrate serves to control the carrier type of the substrate and adjust its conductivity.

[0041] In this invention, the oxide layer is preferably made of silicon dioxide or hafnium oxide, more preferably silicon dioxide. The thickness of the oxide layer is preferably 270–300 nm, more preferably 280–290 nm, and most preferably 285 nm. In this invention, the oxide layer serves as an insulating layer and acts as a material growth platform.

[0042] In this invention, the material of the gate electrode layer is preferably titanium nitride or tantalum nitride, more preferably titanium nitride. In this invention, the thickness of the gate electrode layer is preferably 30–50 nm, more preferably 35–45 nm, and most preferably 40 nm. In this invention, the function of the gate electrode layer is to apply a gate voltage to the device.

[0043] In this invention, the material of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is preferably a doped hafnium oxide-based ferroelectric material; the doping element of the doped hafnium oxide-based ferroelectric material is preferably one or more of zirconium, silicon, yttrium, and aluminum, more preferably zirconium; when the doping element is two or more of the above specific elements, this invention does not have any special limitation on the ratio of the above specific substances, and they can be mixed in any ratio. In this invention, the molar ratio of hafnium to the doping element in the doped hafnium oxide-based ferroelectric material is preferably 1:(0.7-1), more preferably 1:(0.8-1), and most preferably 1:1. In this invention, the thickness of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is preferably 5-10 nm, more preferably 6-9 nm, and most preferably 7-8 nm. In this invention, based on considerations of the required ferroelectric performance of the ferroelectric thin film, the device structure, and the realization of room-temperature high-sensitivity photoelectric detection function, the above-mentioned doped hafnium oxide-based ferroelectric material is selected as the ferroelectric gate dielectric layer. The hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance has advantages such as ultra-thin thickness, semiconductor process compatibility, and environmental friendliness. Furthermore, the ferroelectric localized electrostatic field, the negative capacitance effect of ferroelectric materials, and the voltage amplification effect of ferroelectric field-effect transistors all contribute to its advantages. Using the hafnium oxide-based ferroelectric gate electrolyte as the gate electrolyte layer of a tunneling field-effect transistor can effectively amplify the channel potential and improve device performance. Under illumination, photoexcited carriers are transported through the tunneling effect, enabling rapid photoresponse.

[0044] In this invention, the material of the oxide gate dielectric layer is preferably hafnium oxide and / or aluminum oxide, more preferably hafnium oxide. The thickness of the oxide gate dielectric layer is preferably 10–14 nm. In this invention, the oxide gate dielectric layer matches the capacitance of the hafnium oxide-based ferroelectric gate dielectric layer, which has a negative capacitance effect, improving the interface and thus reducing hysteresis in the subthreshold region of the device transfer characteristics, thereby improving device performance.

[0045] In this invention, the first low-dimensional semiconductor material is preferably a transition metal chalcogenide, and the transition metal chalcogenide is preferably rhenium sulfide; the thickness of the first low-dimensional semiconductor material is preferably the thickness of a monolayer of ~15 nm, more preferably 6 ~10 nm.

[0046] In this invention, the second low-dimensional semiconductor material is preferably a two-dimensional black phosphorus material and / or a two-dimensional purple phosphorus material, more preferably a two-dimensional black phosphorus material. In this invention, the thickness of the second low-dimensional semiconductor material is preferably 10–40 nm, more preferably 15–20 nm, and the thickness of the second low-dimensional semiconductor material is greater than the thickness of the first low-dimensional semiconductor material.

[0047] In this invention, the low-dimensional semiconductor heterojunction formed between the first low-dimensional semiconductor material and the second low-dimensional semiconductor material serves to form a gap-type heterojunction with a tunneling effect, thereby constructing a tunneling channel.

[0048] In this invention, both the metal source electrode and the metal drain electrode preferably comprise a chromium electrode layer and a gold electrode layer stacked sequentially. The thickness of the chromium electrode layer is preferably 10–15 nm, and the thickness of the gold electrode layer is preferably 30–50 nm. In this invention, the function of the metal source electrode and the metal drain electrode is to apply a source-drain bias voltage to the device.

[0049] This invention also provides a method for fabricating the negative capacitance tunneling phototransistor described above, comprising the following steps:

[0050] An oxide layer was prepared on the surface of a substrate by thermal oxidation.

[0051] A gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, and an oxide gate dielectric layer are sequentially deposited on the surface of the oxide layer.

[0052] A low-dimensional semiconductor heterojunction layer was prepared on the second and third surfaces of the oxide gate dielectric layer using a mechanical peeling and transfer method.

[0053] A metal drain electrode is formed on the first surface of the oxide gate dielectric layer, and a metal source electrode is formed on the fourth surface of the oxide gate dielectric layer. Both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

[0054] The present invention prepares an oxide layer on the surface of a substrate by thermal oxidation.

[0055] The present invention does not impose any special limitations on the process of preparing the oxide layer by the thermal oxidation method, and any process known to those skilled in the art can be used.

[0056] After obtaining the oxide layer, the present invention sequentially deposits a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, and an oxide gate dielectric layer on the surface of the oxide layer.

[0057] In this invention, the preferred method for depositing the gate electrode layer is ion beam sputtering. This invention does not impose any special limitations on the ion beam sputtering process, and any process well known to those skilled in the art can be used.

[0058] In this invention, the deposition method of the hafnium oxide-based ferroelectric grid electrode with negative capacitance effect is preferably atomic layer deposition. This invention does not impose any special limitations on the atomic layer deposition process, and any process well known to those skilled in the art can be used.

[0059] In this invention, the deposition method of the oxide gate dielectric layer is preferably atomic layer deposition. This invention does not impose any special limitations on the atomic layer deposition process, and any process well known to those skilled in the art can be used.

[0060] After obtaining the oxide gate dielectric layer, the present invention uses a mechanical peeling and transfer method to prepare a low-dimensional semiconductor heterojunction layer on the second and third surfaces of the oxide gate dielectric layer.

[0061] The present invention does not impose any special limitations on the mechanical peeling and transfer process; any process known to those skilled in the art can be used.

[0062] After obtaining the low-dimensional semiconductor heterojunction layer, the present invention prepares a metal drain electrode on the first surface of the oxide gate dielectric layer and a metal source electrode on the fourth surface of the oxide gate dielectric layer, and both the metal drain electrode and the metal source electrode form an ohmic contact with the low-dimensional semiconductor heterojunction layer.

[0063] In this invention, the metal drain electrode and the metal source electrode are preferably prepared by electron beam etching combined with thermal evaporation and lift-off process or by ultraviolet lithography combined with thermal evaporation and lift-off process; this invention does not impose any special limitations on the above methods, and any method known to those skilled in the art can be used.

[0064] This invention also provides the application of the negative capacitance tunneling phototransistor described in the above-described technical solutions or the negative capacitance tunneling phototransistor prepared by the above-described preparation methods in the optoelectronic field. This invention does not impose any special limitations on the methods for these applications; methods well-known to those skilled in the art can be used.

[0065] The following detailed description, in conjunction with embodiments, illustrates the negative capacitance tunneling phototransistor, its fabrication method, and its applications provided by the present invention. However, these descriptions should not be construed as limiting the scope of protection of the present invention.

[0066] Example 1

[0067] like Figure 1 As shown, the negative capacitance tunneling phototransistor includes a substrate (a 550 nm thick P-type doped silicon substrate with a P-type doping concentration of 4 × 10⁻⁶) stacked sequentially. 19 cm -3 ), oxide layer (silicon dioxide layer with a thickness of 285 nm), gate electrode layer (titanium nitride gate electrode layer with a thickness of 40 nm), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (Hf nitride layer with a thickness of 10 nm). 0.5 Zr 0.5 O2 thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 10 nm), and low-dimensional semiconductor material heterojunction layer;

[0068] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multilayer rhenium disulfide with a thickness of 14 nm) and a second low-dimensional semiconductor material (the material is two-dimensional black phosphorus with a thickness of 30 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material are at the same horizontal height.

[0069] The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer;

[0070] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0071] It also includes a metal source electrode (a chromium metal layer with a thickness of 15 nm and a gold metal layer with a thickness of 50 nm stacked sequentially) and a metal drain electrode (a chromium metal layer with a thickness of 15 nm and a gold metal layer with a thickness of 50 nm stacked sequentially); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0072] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface;

[0073] The fabrication method of the negative capacitance tunneling phototransistor:

[0074] A silicon dioxide layer was prepared on the surface of a p-type doped silicon substrate using a thermal oxidation method;

[0075] A titanium nitride gate electrode layer is deposited on the surface of the silicon dioxide layer by ion beam sputtering.

[0076] At a substrate temperature of 280°C, Hf[N(C2H5)CH3]4, Zr[N(C2H5)CH3]4, and water were used as Hf, Zr, and O sources, respectively. The elemental composition was controlled by alternating deposition of one cycle of HfO2 and one cycle of ZrO2, and rapid annealing was performed for 60 s in a nitrogen atmosphere at 500°C to ensure the crystallinity of the ferroelectric crystallization, thereby growing a hafnium oxide-based ferroelectric gate dielectric layer (10 nm thick HfO2) with a negative capacitance effect on the gate electrode. 0.5 Zr 0.5 O2 thin film);

[0077] A 10 nm thick hafnium oxide gate dielectric layer was deposited on the surface of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect using an atomic layer deposition process.

[0078] A mechanical stripping and transfer method is used to transfer a low-dimensional semiconductor material heterojunction to the second and third surfaces of the hafnium oxide gate dielectric layer;

[0079] A pattern of a metal drain electrode is prepared on the first surface of the oxide gate dielectric layer using ultraviolet lithography. A pattern of a metal source electrode is prepared on the fourth surface of the oxide gate dielectric layer using exposure and development techniques. Metal electrodes (including a chromium electrode layer with a thickness of 15 mm and a gold electrode layer with a thickness of 50 mm stacked sequentially) are prepared on the sample after ultraviolet lithography using thermal evaporation. After the metal electrodes are deposited by vapor deposition, the metal film is removed by a lift-off method to obtain the metal source electrode and the metal drain electrode.

[0080] Figure 2 This is a schematic diagram of the operation of the negative capacitance tunneling phototransistor under ferroelectric control, where the gate voltage V... G The source-drain bias voltage V is applied to the gate electrode layer and the metal source electrode grounded. SD Applied to the metal drain electrode; the equivalent capacitance of this negative capacitance tunneling phototransistor is shown in the schematic diagram. Figure 3 As shown, Ψ S For the surface potential of low-dimensional semiconductor heterojunction, C S For low-dimensional semiconductor heterojunction channel capacitors, C ox For gate hafnium oxide dielectric capacitor, C Fe A zirconium-doped hafnium oxide ferroelectric grid dielectric capacitor;

[0081] Electrical Testing: A small, constant bias voltage of 0.2V was applied between the source and drain electrodes, and the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes was detected. The gate voltage scan range was then set to -2V to 2V, with the scan direction from negative to positive and back to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 were measured to determine the cutoff voltage. The test results are as follows: Figure 4 As shown, where a is the electrical transfer characteristic curve and b is the calculated subthreshold swing of the electrical transfer characteristic curve, derived from... Figure 4 It can be seen that, Figure 4 The forward and reverse transfer characteristics of the device almost completely overlap, the subthreshold swing is less than 60 mV / dec, the minimum value reaches 13.4 mV / dec, and the maximum switching ratio of the device reaches 10. 6 Therefore, the negative capacitance tunneling phototransistor with a hafnium oxide-based ferroelectric gate dielectric layer exhibiting a negative capacitance effect, as described in this invention, can achieve electrical transfer characteristics of no hysteresis, ultra-low subthreshold swing, and high on / off ratio.

[0082] Photoelectric response test: The operating gate voltage setting V of the negative capacitance tunneling phototransistor described in Example 1 g =0V, the voltage scan range between the metal source electrode and the metal drain electrode is set from 0V to 1V. Test results are as follows: Figure 5 As shown, where a is the output characteristic curve under different incident light powers, b is the responsivity of the negative capacitance tunneling phototransistor under different incident light powers, and c is the response time under 520nm laser light. Figure 5 It can be seen that when a laser with a wavelength of 520 nm and a certain power is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of the incident light power. When the incident light power is 14 nW, the photoresponsivity of the negative capacitance tunneling phototransistor is as high as 41 A / W, exhibiting extremely high photoresponse sensitivity, and the response time is 8 μs at this time.

[0083] Example 2

[0084] The negative capacitance tunneling phototransistor comprises a substrate (a 500 nm thick P-type doped silicon substrate with a P-type doping concentration of 4 × 10⁻⁶) stacked sequentially. 19 cm -3 ), oxide layer (silicon dioxide layer with a thickness of 270 nm), gate electrode layer (titanium nitride gate electrode layer with a thickness of 30 nm), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (Hf nitride layer with a thickness of 10 nm). 0.93 Zr 0.07 O2 thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 12 nm), and low-dimensional semiconductor material heterojunction layer;

[0085] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multilayer rhenium disulfide with a thickness of 10 nm) and a second low-dimensional semiconductor material (the material is two-dimensional black phosphorus with a thickness of 25 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material are at the same horizontal height;

[0086] The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer;

[0087] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0088] It also includes a metal source electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked sequentially) and a metal drain electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked sequentially); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0089] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface.

[0090] The preparation method is the same as in Example 1;

[0091] Electrical Testing: A small, constant bias voltage of 0.2V was applied between the source and drain electrodes, and the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes was detected. The gate voltage scan range was then set to -2V to 2V, with the scan direction from negative to positive and back to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 were measured to determine the cutoff voltage. The forward and reverse transfer characteristic curves almost completely overlapped, the subthreshold swing was less than 60mV / dec, and the maximum on / off ratio of the device reached 10. 6 Therefore, the negative capacitance tunneling phototransistor with a hafnium oxide-based ferroelectric gate dielectric layer exhibiting a negative capacitance effect, as described in this invention, can achieve electrical transfer characteristics of no hysteresis, ultra-low subthreshold swing, and high on / off ratio.

[0092] Photoelectric response test: The operating gate voltage of the negative capacitance tunneling phototransistor is set to V. g=0V, the voltage scan range between the metal source electrode and the metal drain electrode is set from 0V to 1V. When a certain power of 520nm laser light is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of incident light power, and the response speed is significantly improved.

[0093] Example 3

[0094] The negative capacitance tunneling phototransistor comprises a substrate (a 550 nm thick P-type doped silicon substrate with a P-type doping concentration of 4 × 10⁻⁶) stacked sequentially. 19 cm -3 ), oxide layer (silicon dioxide layer with a thickness of 270 nm), gate electrode layer (titanium nitride gate electrode layer with a thickness of 30 nm), hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect (Hf nitride layer with a thickness of 10 nm). 0.93 Zr 0.07 O2 thin film), oxide gate dielectric layer (hafnium oxide gate dielectric layer with a thickness of 14 nm), and low-dimensional semiconductor material heterojunction layer;

[0095] The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material (the material is multilayer rhenium disulfide with a thickness of 10 nm) and a second low-dimensional semiconductor material (the material is two-dimensional black phosphorus with a thickness of 40 nm); a portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the second low-dimensional semiconductor material are at the same horizontal height;

[0096] The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer;

[0097] The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface;

[0098] It also includes a metal source electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked sequentially) and a metal drain electrode (a chromium metal layer with a thickness of 12 nm and a gold metal layer with a thickness of 40 nm stacked sequentially); the second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface;

[0099] The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface.

[0100] The preparation method is the same as in Example 1;

[0101] Electrical Testing: A small, constant bias voltage of 0.2V was applied between the source and drain electrodes, and the channel current of the low-dimensional semiconductor heterojunction between the source and drain electrodes was detected. The gate voltage scan range was then set to -2V to 2V, with the scan direction from negative to positive and back to negative. The transfer characteristics of the negative capacitance tunneling phototransistor described in Example 1 were measured to determine the cutoff voltage. The forward and reverse transfer characteristic curves almost completely overlapped, the subthreshold swing was less than 60mV / dec, and the maximum on / off ratio of the device reached 10. 6 Therefore, the negative capacitance tunneling phototransistor with a hafnium oxide-based ferroelectric gate dielectric layer exhibiting a negative capacitance effect, as described in this invention, can achieve electrical transfer characteristics of no hysteresis, ultra-low subthreshold swing, and high on / off ratio.

[0102] Photoelectric response test: The operating gate voltage of the negative capacitance tunneling phototransistor is set to V. g =0V, the voltage scan range between the metal source electrode and the metal drain electrode is set from 0V to 1V. When a certain power of 520nm laser light is incident, the channel current of the low-dimensional material negative capacitance tunneling phototransistor increases significantly, and the channel current increases with the increase of incident light power, and the response speed is significantly improved.

[0103] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A negative capacitance tunneling phototransistor, characterized in that, It includes a substrate, an oxide layer, a gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, an oxide gate dielectric layer, and a low-dimensional semiconductor material heterojunction layer stacked sequentially. The low-dimensional semiconductor material heterojunction layer includes a first low-dimensional semiconductor material and a second low-dimensional semiconductor material. A portion of the first low-dimensional semiconductor material is embedded in the second low-dimensional semiconductor material, and the lower surfaces of the first and second low-dimensional semiconductor materials are at the same horizontal height. The first low-dimensional semiconductor material is rhenium sulfide; the second low-dimensional semiconductor material is a two-dimensional black scale material; a gap-type heterojunction is formed between the first low-dimensional semiconductor material and the second low-dimensional semiconductor material; The surface of the oxide gate dielectric layer is sequentially divided into a first surface, a second surface, a third surface, and a fourth surface, with the first surface and the fourth surface located on the outer side of the surface of the oxide gate dielectric layer; The lower surface of the first low-dimensional semiconductor material is in contact with the second surface, and the lower surface of the second low-dimensional semiconductor material is in contact with the third surface; It also includes a metal source electrode and a metal drain electrode; The second low-dimensional semiconductor material is embedded in the metal source electrode to form an ohmic contact, and the lower surface of the second low-dimensional semiconductor material and the lower surface of the metal source electrode are at the same horizontal height, and the lower surface of the metal source electrode is in contact with the fourth surface; The first low-dimensional semiconductor material is embedded in the metal drain electrode to form an ohmic contact, and the lower surface of the first low-dimensional semiconductor material and the lower surface of the metal drain electrode are at the same horizontal height, and the lower surface of the metal drain electrode is in contact with the first surface.

2. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, The substrate is a P-type doped silicon substrate.

3. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, The oxide layer is made of silicon dioxide.

4. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, The material of the gate electrode layer is titanium nitride.

5. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, The material of the hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect is a doped hafnium oxide-based ferroelectric material; The doping elements of the hafnium oxide-based ferroelectric material are one or more of zirconium, silicon, yttrium, and aluminum.

6. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, The oxide gate dielectric layer is made of hafnium oxide and / or aluminum oxide.

7. The negative capacitance tunneling phototransistor as described in claim 1, characterized in that, Both the metal source electrode and the metal drain electrode are chromium electrodes and gold electrodes stacked together.

8. The method for fabricating the negative capacitance tunneling phototransistor according to any one of claims 1 to 7, characterized in that, Includes the following steps: An oxide layer was prepared on the surface of a substrate by thermal oxidation. A gate electrode layer, a hafnium oxide-based ferroelectric gate dielectric layer with negative capacitance effect, and an oxide gate dielectric layer are sequentially deposited on the surface of the oxide layer. A low-dimensional semiconductor heterojunction layer was prepared on the second and third surfaces of the oxide gate dielectric layer using a mechanical peeling and transfer method. A metal drain electrode is formed on the first surface of the oxide gate dielectric layer, and a metal source electrode is formed on the fourth surface of the oxide gate dielectric layer. Both the metal drain electrode and the metal source electrode form ohmic contacts with the low-dimensional semiconductor heterojunction layer.

9. The application of the negative capacitance tunneling phototransistor according to any one of claims 1 to 7 or the negative capacitance tunneling phototransistor prepared by the preparation method according to claim 8 in the field of optoelectronics.

Images