Error correction method, memory storage device and memory control circuit unit

Abstract

The invention provides an error correction method, a memory storage device and a memory control circuit unit. The error correction method comprises the following steps: counting a first decoding rate of a first error correction process, wherein the first error correction process comprises a plurality of decoding operations executed based on a first sequence; and switching the first error correction process to a second error correction process in response to the first decoding rate being less than a first threshold, the second error correction process including a plurality of decoding operations performed based on a second order, wherein the decoding capability of the first decoding operation indicated by the second sequence is superior to the decoding capability of the first decoding operation indicated by the first sequence.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to an error correction method, a memory storage device and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] When the read data cannot be corrected, the memory storage device can perform an error correction process accordingly. In the conventional error correction process, the memory storage device will first perform the decoding operation with the shortest operation time. If the decoding fails, it will then sequentially perform the decoding operations with longer operation times and stronger decoding capabilities. When the number of error bits of the rewritable non-volatile memory module is not high, the initial decoding operation with the shortest operation time can successfully decode most of the data. However, when the number of error bits of the rewritable non-volatile memory module becomes higher, most of the data can only be successfully decoded in subsequent decoding operations with stronger decoding capabilities. In this case, the conventional error correction process will cause the average decoding time to become longer, thereby causing the performance of the memory storage device to deteriorate. Summary of the invention

[0004] The present invention provides an error correction method, a memory storage device and a memory control circuit unit, which can select different error correction processes according to actual conditions to reduce time cost and improve the performance of the memory storage device.

[0005] An exemplary embodiment of the present invention provides an error correction method for a rewritable non-volatile memory module, the error correction method comprising: calculating a first decoding rate of a first error correction process, wherein the first error correction process comprises a plurality of decoding operations executed based on a first order; and in response to the first decoding rate being less than a first threshold, switching the first error correction process to a second error correction process, wherein the second error correction process comprises a plurality of decoding operations executed based on a second order, wherein the decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

[0006] In an exemplary embodiment of the present invention, the error correction method further includes: calculating a second decoding rate of the second error correction process; and switching the second error correction process to the first error correction process in response to the second decoding rate being not less than a second threshold.

[0007] In an exemplary embodiment of the present invention, the first decoding rate is a success rate of the first decoding operation indicated by the first order.

[0008] In an exemplary embodiment of the present invention, the second decoding rate is a success rate of each of the decoding operations in the second error correction process.

[0009] In an exemplary embodiment of the present invention, the plurality of decoding operations included in the first error correction process is a first number, and the plurality of decoding operations included in the second error correction process is a second number, wherein the first number is greater than the second number.

[0010] In an exemplary embodiment of the present invention, the error correction method further includes: obtaining health status information of the rewritable non-volatile memory module; and adopting one of the first error correction process, the second error correction process and the third error correction process according to the health status information.

[0011] In an exemplary embodiment of the present invention, the third error correction process includes a plurality of decoding operations executed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

[0012] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to couple to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to count a first decoding rate of a first error correction process, wherein the first error correction process includes a plurality of decoding operations executed based on a first order. In response to the first decoding rate being less than a first threshold, the memory control circuit unit is further used to switch the first error correction process to a second error correction process, wherein the second error correction process includes a plurality of decoding operations executed based on a second order, wherein the decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

[0013] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to count a second decoding rate of the second error correction process. In response to the second decoding rate being not less than a second threshold, the memory control circuit unit is further used to switch the second error correction process to the first error correction process.

[0014] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to obtain health status information of the rewritable non-volatile memory module. The memory control circuit unit is further used to adopt one of the first error correction process, the second error correction process and the third error correction process according to the health status information.

[0015] An exemplary embodiment of the present invention further provides a memory control circuit unit, which is used to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to couple to a host system. The memory interface is used to couple to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used to count a first decoding rate of a first error correction process, wherein the first error correction process includes a plurality of decoding operations executed based on a first sequence. In response to the first decoding rate being less than a first threshold, the memory management circuit is further used to switch the first error correction process to a second error correction process, wherein the second error correction process includes a plurality of decoding operations executed based on a second sequence, wherein the decoding capability of the first decoding operation indicated by the second sequence is better than the decoding capability of the first decoding operation indicated by the first sequence.

[0016] In an exemplary embodiment of the present invention, the memory management circuit is further used to count a second decoding rate of the second error correction process. In response to the second decoding rate being not less than a second threshold, the memory management circuit is further used to switch the second error correction process to the first error correction process.

[0017] In an exemplary embodiment of the present invention, the memory management circuit is further configured to obtain health status information of the rewritable non-volatile memory module and to adopt one of the first error correction process, the second error correction process and the third error correction process according to the health status information.

[0018] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to couple to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform a first error correction process or a second error correction process. The first error correction process includes a plurality of decoding operations executed based on a first sequence, and the plurality of decoding operations included in the first error correction process is a first number. The second error correction process includes a plurality of decoding operations executed based on a second sequence, and the plurality of decoding operations included in the second error correction process is a second number. At least one decoding operation of the plurality of decoding operations included in the first error correction process is the same as at least one decoding operation of the plurality of decoding operations included in the second error correction process. The decoding capability of the first decoding operation indicated by the second sequence is better than the decoding capability of the first decoding operation indicated by the first sequence, and the first number is greater than the second number.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to execute one of the first error correction process, the second error correction process and a third error correction process, wherein the third error correction process includes a plurality of decoding operations executed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

[0020] In an exemplary embodiment of the present invention, the at least one decoding operation among the multiple decoding operations included in the first error correction process, the at least one decoding operation among the multiple decoding operations included in the second error correction process, and the at least one decoding operation among the multiple decoding operations included in the third error correction process are the same.

[0021] An exemplary embodiment of the present invention further provides a memory control circuit unit, which is used to control a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to couple to a host system. The memory interface is used to couple to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used to perform a first error correction process or a second error correction process. The first error correction process includes a plurality of decoding operations performed based on a first sequence, and the plurality of decoding operations included in the first error correction process is a first number. The second error correction process includes a plurality of decoding operations performed based on a second sequence, and the plurality of decoding operations included in the second error correction process is a second number. At least one decoding operation of the plurality of decoding operations included in the first error correction process is the same as at least one decoding operation of the plurality of decoding operations included in the second error correction process. The decoding capability of the first decoding operation indicated by the second sequence is better than the decoding capability of the first decoding operation indicated by the first sequence, and the first number is greater than the second number.

[0022] In an exemplary embodiment of the present invention, the memory management circuit is further used to execute one of the first error correction process, the second error correction process and a third error correction process, wherein the third error correction process includes a plurality of decoding operations executed based on a third order, and the decoding capability of the first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

[0023] Based on the above, the error correction method, memory storage device and memory control circuit unit of the present invention can select a suitable error correction process according to the decoding rate of the current error correction process or the health status information of the rewritable non-volatile memory module to reduce the decoding time and improve the performance of the memory storage device.

[0024] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of different types of error correction processes according to an exemplary embodiment of the present invention;

[0032] Figure 8 is a flow chart of an error correction method according to an exemplary embodiment of the present invention;

[0033] Fig. 9 is a flow chart of an error correction method according to an exemplary embodiment of the present invention;

[0034] Fig.10 is a flow chart of an error correction method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0037] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0039] In an exemplary embodiment, the host system 11 may be connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0040] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless manner.

[0041] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0043] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0044] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0045] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0046] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0047] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0048] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0049] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0050] In an exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasure unit contains the minimum number of storage cells that are erased together. For example, the physical erasure unit is a physical block.

[0051] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0052] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0053] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0054] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0055] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0056] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify commands and data of the host system 11. For example, the commands and data of the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0057] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing the read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code and a memory address may be included.

[0058] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0059] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correction code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correction code and / or error checking code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correction code and / or error checking code.

[0060] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0061] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0062] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0063] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a virtual block may include one or more physical erase units.

[0064] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0065] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0066] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0067] The memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0068] In one exemplary embodiment, the memory storage device 10 supports error correction (error handle), and the data will be encoded by the error checking and correction circuit 54 before being stored in the rewritable non-volatile memory module 43. When it is desired to read a physical unit (also referred to as a target physical unit), the memory management circuit 51 performs an initial read operation, and can first use a preset (or previously used) read voltage level to read the storage unit in the target physical unit to obtain the verification bit (for example, bit 0 or bit 1) of the storage unit. The error checking and correction circuit 54 performs a decoding operation based on the verification bits of these storage units to generate a plurality of decoded bits. These decoded bits can form a decoded data (i.e., a codeword). In one exemplary embodiment, if the error checking and correction circuit 54 cannot successfully decode, the error checking and correction circuit 54 responds to the decoding failure (i.e., too many error bits are stored in the storage unit), and the memory management circuit 51 performs an error correction process.

[0069] Figure 7 is a schematic diagram of different types of error correction processes according to an exemplary embodiment of the present invention. Figure 7 , the memory storage device 10 may, for example, support Figure 7The first error correction process EHP1, the second error correction process EHP2 and the third error correction process EHP3 are shown. When the ECC circuit 54 fails to decode successfully, the memory management circuit 51 may execute the first error correction process EHP1, the second error correction process EHP2 or the third error correction process EHP3.

[0070] In an exemplary embodiment, the memory management circuit 51 may determine the error correction process to be executed according to the decoding rate. In an exemplary embodiment, the memory management circuit 51 may determine the error correction process to be executed according to the health status information of the rewritable non-volatile memory module 43. In an exemplary embodiment, the memory management circuit 51 may determine the error correction process to be executed according to an instruction from the host system 11. In an exemplary embodiment, the memory management circuit 51 may determine the error correction process to be executed according to the actual usage.

[0071] In an exemplary embodiment, the first error correction process EHP1 includes a plurality of decoding operations performed based on a first order. The first error correction process EHP1 may, for example, include but is not limited to a retry read operation OP11, an optimal read voltage level search operation OP12, and an interference compensation read operation OP13 performed according to the first order. In an exemplary embodiment, the second error correction process EHP2 includes a plurality of decoding operations performed based on a second order. The second error correction process EHP2 may, for example, include but is not limited to an optimal read voltage level search operation OP21 and an interference compensation read operation OP22 performed according to the second order. In an exemplary embodiment, the third error correction process EHP3 includes a plurality of decoding operations performed based on a third order. The third error correction process EHP3 may, for example, include but is not limited to a retry read and interference compensation read operation OP31 and an optimal read voltage level search operation OP32 performed according to the third order.

[0072] In an exemplary embodiment, at least one decoding operation among the plurality of decoding operations included in the first error correction process EHP1 is the same as at least one decoding operation among the plurality of decoding operations included in the second error correction process EHP2. For example, the first error correction process EHP1 and the second error correction process EHP2 both include the same optimal read voltage level search operations OP12, OP21 and interference compensation read operations OP13, OP22. In an exemplary embodiment, at least one decoding operation among the plurality of decoding operations included in the first error correction process EHP1, at least one decoding operation among the plurality of decoding operations included in the second error correction process EHP2, and at least one decoding operation among the plurality of decoding operations included in the third error correction process EHP3 are the same. For example, the first error correction process EHP1, the second error correction process EHP2, and the third error correction process EHP3 all include optimal read voltage level search operations OP12, OP21, OP32.

[0073] In an exemplary embodiment, when the memory management circuit 51 executes the first error correction process EHP1 (or, the second error correction process EHP2, the third error correction process EHP3), if one of the decoding operations in the first error correction process EHP1 (or, the second error correction process EHP2, the third error correction process EHP3) is successful and obtains a codeword, the memory management circuit 51 can end the first error correction process EHP1 (or, the second error correction process EHP2, the third error correction process EHP3). If all the decoding operations in the first error correction process EHP1 (or, the second error correction process EHP2, the third error correction process EHP3) fail, the memory management circuit 51 will obtain a result that cannot be decoded, and end the first error correction process EHP1 (or, the second error correction process EHP2, the third error correction process EHP3).

[0074] In an exemplary embodiment, the retry read operation OP11 may be, for example, the memory management circuit 51 re-obtains another read voltage level to read the memory cell of the target physical unit to re-obtain the verification bit of the memory cell, and the error check and correction circuit 54 performs the above-mentioned decoding operation according to the re-obtained multiple verification bits. When there are too many error bits, by adopting another read voltage level to re-obtain the verification bit, the verification bits of some memory cells in the target physical unit can be changed, and there is a chance to change the decoding result of the decoding operation.

[0075] In an exemplary embodiment, the optimal read voltage level search operations OP12, OP21, and OP32 may be performed by, for example, the memory management circuit 51 re-obtaining a read voltage level different from the previous read voltage level to read the memory cell of the target physical cell to re-obtain the verification bit of the memory cell, and the error check and correction circuit 54 performs the above-mentioned decoding operation according to the re-obtained verification bits to obtain another data composed of a plurality of decoded bits. If the decoding fails again (that is, there are too many error bits in the re-obtained verification bits), the memory management circuit 51 re-obtains another read voltage level to try decoding again until the decoding is successful or the preset number of decoding attempts has been exceeded.

[0076] In an exemplary embodiment, the interference compensation read operations OP13 and OP22 may be performed by the memory management circuit 51, for example, when re-reading the storage cells of the target physical unit, also reading the storage cells of the adjacent physical units that may cause interference to the target physical unit, so as to perform the above-mentioned decoding operation through the verification bits obtained from the storage cells of the target physical unit and the verification bits obtained from the storage cells of the adjacent physical units, so as to improve the success rate of the decoding operation.

[0077] In an exemplary embodiment, the retry read and interference compensation read operation OP31, as the name implies, is a combination of the retry read operation OP11 and the interference compensation read operations OP13 and OP22. The retry read and interference compensation read operation OP31 may, for example, be a process in which the memory management circuit 51 re-obtains another read voltage level to read the target physical cell, and reads the storage cells of the adjacent physical cells that may interfere with the target physical cell, so as to obtain a plurality of verification bits of the target physical cell and the adjacent physical cells, and perform the above-mentioned decoding operation accordingly to improve the success rate of the decoding operation. In another exemplary embodiment, when the initial read operation is performed on the target physical cell after adjusting the error correction process, the interference compensation read operations OP13 and OP22 may also be performed, that is, the initial read operation is combined with the interference compensation read operations OP13 and OP22.

[0078] In an exemplary embodiment, the first error correction process EHP1 includes a first number of decoding operations (for example, 3), and the second error correction process EHP2 includes a second number of decoding operations (for example, 2). The first number is greater than the second number. In an exemplary embodiment, the first error correction process EHP1 includes a first number of decoding operations (for example, 3), and the third error correction process EHP3 includes a third number of decoding operations (for example, 2). The first number is greater than the third number.

[0079] In an exemplary embodiment, the decoding capability of the first decoding operation indicated by the second order (i.e., the optimal read voltage level search operation OP21) is better than the decoding capability of the first decoding operation indicated by the first order (i.e., the retry read operation OP11), and the better decoding capability means a higher probability of successful decoding. In an exemplary embodiment, the decoding capability of the first decoding operation indicated by the third order (i.e., the retry read and interference compensation read operation OP31) is better than the decoding capability of the first decoding operation indicated by the second order.

[0080] In an exemplary embodiment, the first error correction process EHP1 is a preset error correction process. That is, the memory storage device 10 is preset to use the first error correction process EHP1. The first error correction process EHP1 includes a plurality of operations that are executed based on a first order, wherein the first order may be used to indicate the decoding capabilities (or operation times) of the plurality of operations. For example, the memory management circuit 51 may first execute the operation with a weaker decoding capability according to the first order, and then execute other operations in sequence according to the decoding capability. For example, the memory management circuit 51 may first execute the operation with a shorter operation time according to the first order, and then execute other operations in sequence according to the operation time.

[0081] That is, the decoding capability of the retry read operation OP11 is lower than the decoding capability of the optimal read voltage level search operation OP12, and the decoding capability of the optimal read voltage level search operation OP12 is lower than the decoding capability of the interference compensation read operation OP13. In other words, the operation time of the retry read operation OP11 is shorter than the operation time of the optimal read voltage level search operation OP12, and the operation time of the optimal read voltage level search operation OP12 is shorter than the operation time of the interference compensation read operation OP13.

[0082] In an exemplary embodiment, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1. For example, the memory management circuit 51 may periodically count the first decoding rate of the first error correction process EHP1. For example, every time interval, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1. For example, after the rewritable non-volatile memory module 43 receives a certain number of read instruction sequences, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1. For example, the memory management circuit 51 may set a read count value, and when the read count value reaches a count threshold, the memory management circuit 51 may count the first decoding rate of the first error correction process EHP1 and recount the read count value. In an exemplary embodiment, the first decoding rate is the success rate of the first decoding operation indicated by the first sequence (that is, the retry read operation OP11).

[0083] In an exemplary embodiment, when the first decoding rate is less than the first threshold, the memory management circuit 51 may switch the first error correction process EHP1 to the second error correction process EHP2. Specifically, the first decoding rate being less than the first threshold indicates that the decoding capability of the retry read operation OP11 is insufficient. Therefore, the memory management circuit 51 may switch the first error correction process EHP1 to the second error correction process EHP2 of the first decoding operation (i.e., the optimal read voltage level search operation OP21) having a relatively strong decoding capability to reduce the decoding time.

[0084] In an exemplary embodiment, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2. For example, the memory management circuit 51 may periodically count the second decoding rate of the second error correction process EHP2. For example, every time interval, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2. For example, after the rewritable non-volatile memory module 43 receives a certain number of read instruction sequences, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2. For example, the memory management circuit 51 may set a read count value, and when the read count value reaches a count threshold, the memory management circuit 51 may count the second decoding rate of the second error correction process EHP2 and recount the read count value. In an exemplary embodiment, the second decoding rate is the success rate of each decoding operation (that is, the optimal read voltage level search operation OP21 and the interference compensation read operation OP22) in the second error correction process EHP2. In another exemplary embodiment, the second decoding rate is a success rate of the first decoding operation (ie, the optimal read voltage level search operation OP21 ) indicated by the second sequence.

[0085] In an exemplary embodiment, when the second decoding rate is not less than the second threshold, the memory management circuit 51 may switch the second error correction process EHP2 to the first error correction process EHP1. That is, when the success rate of the optimal read voltage level search operation OP21 and / or the success rate of the interference compensation read operation OP22 is not less than the second threshold, the memory management circuit 51 may restore the second error correction process EHP2 to the default first error correction process EHP1. Specifically, the second decoding rate being not less than the second threshold indicates that the success rate of reading the target physical unit from the rewritable non-volatile memory module 43 is high. Therefore, the memory management circuit 51 may restore the second error correction process EHP2 to the first error correction process EHP1 of the first decoding operation (i.e., the retry read operation OP11) having a relatively short operation time to reduce the decoding time.

[0086] In an exemplary embodiment, when the second decoding rate is less than the third threshold, the memory management circuit 51 may switch the second error correction process EHP2 to the third error correction process EHP3. Specifically, the second decoding rate being less than the third threshold indicates that the decoding capabilities of the optimal read voltage level search operation OP21 and the interference compensation operation OP22 are insufficient. Therefore, the memory management circuit 51 may switch the second error correction process EHP2 to the third error correction process EHP3 of the first decoding operation (i.e., the retry read and interference compensation read operation OP31) having a relatively strong decoding capability to reduce the decoding time.

[0087] In an exemplary embodiment, the memory management circuit 51 may count the third decoding rate of the third error correction process EHP3. The implementation details of counting the third decoding rate may refer to the aforementioned methods of counting the first decoding rate and the second decoding rate, so they are not repeated here. In an exemplary embodiment, the third decoding rate is the success rate of each decoding operation (i.e., the retry read and interference compensation read operation OP31 and the optimal read voltage level search operation OP32) in the third error correction process EHP3. In another exemplary embodiment, the third decoding rate is the success rate of the first decoding operation indicated by the third sequence (i.e., the retry read and interference compensation read operation OP31).

[0088] In an exemplary embodiment, when the third decoding rate is not less than the fourth threshold, the memory management circuit 51 may switch the third error correction process EHP3 to the second error correction process EHP2 (or the first error correction process EHP1). That is, when the success rate of the retry read and interference compensation read operation OP31 and / or the success rate of the optimal read voltage level search operation OP32 is not less than the fourth threshold, the memory management circuit 51 may switch the third error correction process EHP3 to the second error correction process EHP2 (or the first error correction process EHP1) of the first decoding operation (i.e., the optimal read voltage level search operation OP21 or the retry read operation OP11) with a relatively short operation time, so as to reduce the decoding time. In another exemplary embodiment, the fourth decoding rate of the initial read operation may also be counted. The implementation details of counting the fourth decoding rate may refer to the aforementioned method of counting the first decoding rate and the second decoding rate, so it is not repeated here. In an exemplary embodiment, the fourth decoding rate is the success rate of multiple initial read operations, wherein each read instruction sequence has one initial read operation. The memory management circuit 51 can switch the error correction process according to the fourth decoding rate. For example, when the fourth decoding rate is low, an error correction process with relatively strong decoding capability can be used instead. For another example, when the fourth decoding rate is high, an error correction process with relatively weak decoding capability can be used instead. The implementation details of switching the error correction process can refer to the aforementioned approach, so it will not be repeated here.

[0089] In an exemplary embodiment, the memory management circuit 51 may obtain health status information of the rewritable non-volatile memory module 43. The health status information may include but is not limited to at least one of the temperature, the number of reads, the number of erases, the number of writes, the fourth decoding rate, and the number of error bits of the rewritable non-volatile memory module 43. Next, the memory management circuit 51 may adopt the first error correction process EHP1, the second error correction process EHP2, or the third error correction process EHP3 according to the health status information. For example, the memory management circuit 51 may determine that the rewritable non-volatile memory module 43 is good according to the health status information, and accordingly adopt the first error correction process EHP1. For example, the memory management circuit 51 may determine that the rewritable non-volatile memory module 43 is medium according to the health status information, and accordingly adopt the second error correction process EHP2. For example, the memory management circuit 51 may determine that the rewritable non-volatile memory module 43 is poor according to the health status information, and accordingly adopt the third error correction process EHP3.

[0090] According to the above, the memory management circuit 51 can select a suitable error correction process according to the health status information to improve the performance of the memory storage device 10 .

[0091] Figure 8 is a flow chart of an error correction method according to an exemplary embodiment of the present invention. Figure 8 In step S801, the first decoding rate of the first error correction process EHP1 is counted. In step S802, it is determined whether the first decoding rate is less than the first threshold. If the first decoding rate is not less than the first threshold, return to step S801. If the first decoding rate is less than the first threshold, continue to execute step S803. In step S803, the first error correction process EHP1 is switched to the second error correction process EHP2. In step S804, the second decoding rate of the second error correction process EHP2 is counted. In step S805, it is determined whether the second decoding rate is less than the second threshold. If the second decoding rate is less than the second threshold, return to step S804. If the second decoding rate is not less than the second threshold, continue to execute step S806. In step S806, the second error correction process EHP2 is switched to the first error correction process EHP1. After executing step S806, you can return to step S801 and re-execute. Figure 8 Error correction method.

[0092] Fig. 9 is a flow chart of an error correction method according to an exemplary embodiment of the present invention. Fig. 9In step S901, the health status information of the rewritable non-volatile memory module 43 is obtained. In step S902, the first error correction process EHP1, the second error correction process EHP2 or the third error correction process EHP3 is adopted according to the health status information.

[0093] Fig.10 is a flow chart of an error correction method according to an exemplary embodiment of the present invention. Fig.10 In step S1001, a first decoding rate of a first error correction process EHP1 is counted, wherein the first error correction process EHP1 includes a plurality of decoding operations executed based on a first order. In step S1002, in response to the first decoding rate being less than a first threshold, the first error correction process EHP1 is switched to a second error correction process EHP2, wherein the second error correction process EHP2 includes a plurality of decoding operations executed based on a second order, wherein the decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

[0094] about Figures 8 to 10 The steps in the above are described in detail, so they will not be repeated here. It is worth noting that Figures 8 to 10 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 8 to 10 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0095] In summary, the error correction method, memory storage device and memory control circuit unit provided by the embodiments of the present invention provide a variety of different error correction processes, and can select a suitable error correction process according to the decoding rate of the current error correction process or the health status information of the rewritable non-volatile memory module to reduce the average decoding time, thereby improving the performance of the memory storage device.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An error correction method, characterized in that: For a rewritable non-volatile memory module, the error correction method comprises: Counting a first decoding rate of a first error correction process, wherein the first error correction process includes a plurality of decoding operations performed based on a first order; and In response to the first decoding rate being less than a first threshold, switching the first error correction process to a second error correction process, wherein the second error correction process includes a plurality of decoding operations performed based on a second order, The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

2. The error correction method according to claim 1, further comprising: Counting a second decoding rate of the second error correction process; as well as In response to the second decoding rate being not less than a second threshold, the second error correction process is switched to the first error correction process. 3 . The error correction method according to claim 1 , wherein the first decoding rate is a success rate of the first decoding operation indicated by the first order. 4 . The error correction method according to claim 2 , wherein the second decoding rate is a success rate of each of the decoding operations in the second error correction process.

5. The error correction method according to claim 1, wherein the plurality of decoding operations included in the first error correction process is a first number, and the plurality of decoding operations included in the second error correction process is a second number, wherein the first number is greater than the second number.

6. The error correction method according to claim 1, further comprising: Obtaining health status information of the rewritable non-volatile memory module; as well as According to the health status information, one of the first error correction process, the second error correction process and the third error correction process is adopted.

7. The error correction method according to claim 6, wherein the third error correction process includes multiple decoding operations performed based on a third order, and the decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

8. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used to: Counting a first decoding rate of a first error correction process, wherein the first error correction process includes a plurality of decoding operations performed based on a first order; as well as In response to the first decoding rate being less than a first threshold, switching the first error correction process to a second error correction process, wherein the second error correction process includes a plurality of decoding operations performed based on a second order, The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Counting a second decoding rate of the second error correction process; and In response to the second decoding rate being not less than a second threshold, the second error correction process is switched to the first error correction process.

10. The memory storage device of claim 8, wherein the first decoding rate is a success rate of the first decoding operation indicated by the first order.

11. The memory storage device of claim 9, wherein the second decoding rate is a success rate of each of the decoding operations in the second error correction process.

12. The memory storage device of claim 8, wherein the plurality of decoding operations included in the first error correction process is a first number, and the plurality of decoding operations included in the second error correction process is a second number, wherein the first number is greater than the second number.

13. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Obtaining health status information of the rewritable non-volatile memory module; and According to the health status information, one of the first error correction process, the second error correction process and the third error correction process is adopted.

14. The memory storage device of claim 13, wherein the third error correction process comprises a plurality of decoding operations performed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

15. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit comprises: A host interface, for connecting to a connection interface unit; A memory interface for connecting to the rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, The memory management circuit is used to: Counting a first decoding rate of a first error correction process, wherein the first error correction process includes a plurality of decoding operations performed based on a first order; and In response to the first decoding rate being less than a first threshold, switching the first error correction process to a second error correction process, wherein the second error correction process includes a plurality of decoding operations performed based on a second order, The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order.

16. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Counting a second decoding rate of the second error correction process; and In response to the second decoding rate being not less than a second threshold, the second error correction process is switched to the first error correction process. 17 . The memory control circuit unit according to claim 15 , wherein the first decoding rate is a success rate of the first decoding operation indicated by the first order.

18. The memory control circuit unit according to claim 16, wherein the second decoding rate is a success rate of each of the decoding operations in the second error correction process.

19. The memory control circuit unit according to claim 15, wherein the plurality of decoding operations included in the first error correction process is a first number, and the plurality of decoding operations included in the second error correction process is a second number, wherein the first number is greater than the second number.

20. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Obtaining health status information of the rewritable non-volatile memory module; and According to the health status information, one of the first error correction process, the second error correction process and the third error correction process is adopted.

21. The memory control circuit unit according to claim 20, wherein the third error correction process includes a plurality of decoding operations performed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

22. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; as well as A memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used to: executing a first error correction process or a second error correction process, The first error correction process includes a plurality of decoding operations performed based on a first order, and the plurality of decoding operations included in the first error correction process is a first number, The second error correction process includes a plurality of decoding operations performed based on a second order, and the plurality of decoding operations included in the second error correction process is a second number, wherein at least one decoding operation among the plurality of decoding operations included in the first error correction process is the same as at least one decoding operation among the plurality of decoding operations included in the second error correction process, The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order, and the first number is greater than the second number.

23. The memory storage device according to claim 22, wherein the memory control circuit unit is further configured to: executing one of the first error correction process, the second error correction process, and the third error correction process, The third error correction process includes a plurality of decoding operations executed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

24. The memory storage device of claim 23, wherein The at least one decoding operation among the multiple decoding operations included in the first error correction process, the at least one decoding operation among the multiple decoding operations included in the second error correction process, and the at least one decoding operation among the multiple decoding operations included in the third error correction process are the same.

25. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, the memory control circuit unit comprises: A host interface, for connecting to a connection interface unit; A memory interface for connecting to the rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, The memory management circuit is used to: executing a first error correction process or a second error correction process, The first error correction process includes a plurality of decoding operations performed based on a first order, and the plurality of decoding operations included in the first error correction process is a first number, The second error correction process includes a plurality of decoding operations performed based on a second order, and the plurality of decoding operations included in the second error correction process is a second number, wherein at least one decoding operation among the plurality of decoding operations included in the first error correction process is the same as at least one decoding operation among the plurality of decoding operations included in the second error correction process, The decoding capability of the first decoding operation indicated by the second order is better than the decoding capability of the first decoding operation indicated by the first order, and the first number is greater than the second number.

26. The memory control circuit unit according to claim 25, wherein the memory management circuit is further configured to: executing one of the first error correction process, the second error correction process, and the third error correction process, The third error correction process includes a plurality of decoding operations executed based on a third order, and a decoding capability of a first decoding operation indicated by the third order is better than the decoding capability of the first decoding operation indicated by the second order.

27. The memory control circuit unit according to claim 26, wherein The at least one decoding operation among the multiple decoding operations included in the first error correction process, the at least one decoding operation among the multiple decoding operations included in the second error correction process, and the at least one decoding operation among the multiple decoding operations included in the third error correction process are the same.

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