Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, the display panel is used for displaying a picture in multiple frames, the multiple frames comprise multiple first frames and multiple second frames, and the multiple frames comprise multiple first sub-pixel groups and multiple second sub-pixel groups which are arranged in a staggered manner, the plurality of first gate signals are used for driving the plurality of corresponding first sub-pixel groups to be opened in the first frame, the plurality of second gate signals are used for driving the plurality of corresponding second sub-pixel groups to be opened in the second frame, the first frame and the second frame have an overlapping time period, and the flicker phenomenon under low frequency is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to the manufacture of display devices, and specifically to a display panel and a driving method thereof. Background Art

[0002] The display panel will use different image refresh frequencies for display in different application scenarios. For example, in application scenarios that display dynamic images such as games and videos, the display panel is in high-frequency mode to ensure the smoothness of the displayed image; in application scenarios that display static images such as e-books, the display panel is in low-frequency mode to reduce the power consumption of the display panel.

[0003] However, when the display panel is in low-frequency mode, the leakage time increases, causing screen flickering. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a driving method thereof to solve the problem that the existing display panel flickers in a low-frequency mode.

[0005] An embodiment of the present invention provides a display panel for displaying pictures in multiple frames, wherein the multiple frames include multiple first frames and multiple second frames, including:

[0006] A plurality of sub-pixel groups, including a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged in a staggered manner;

[0007] a plurality of gate lines, including a plurality of first gate lines electrically connected to the corresponding plurality of first sub-pixel groups, and a plurality of second gate lines electrically connected to the corresponding plurality of second sub-pixel groups, the plurality of first gate lines being used to transmit the corresponding plurality of first gate signals, and the plurality of second gate lines being used to transmit the corresponding plurality of second gate signals;

[0008] Among them, multiple first gate signals are used to drive corresponding multiple first sub-pixel groups to turn on in the first frame, and multiple second gate signals are used to drive corresponding multiple second sub-pixel groups to turn on in the second frame, and the first frame and the second frame have an overlapping period.

[0009] An embodiment of the present invention further provides a method for driving a display panel, which is used to drive any of the display panels described above, comprising:

[0010] Controlling the plurality of first gate lines to transmit the corresponding plurality of first gate signals to the plurality of first sub-pixel groups, so that the corresponding plurality of first sub-pixel groups are turned on in the first frame;

[0011] The plurality of second gate lines are controlled to transmit corresponding plurality of second gate signals to the plurality of second sub-pixel groups, so that the corresponding plurality of second sub-pixel groups are turned on in the second frame, and the first frame and the second frame have an overlapping period.

[0012] The present invention provides a display panel and a driving method thereof, wherein a plurality of the first gate signals are used to drive a corresponding plurality of the first sub-pixel groups to turn on within the first frame, and a plurality of the second gate signals are used to drive a corresponding plurality of the second sub-pixel groups to turn on within the second frame, and the first frame and the second frame have an overlapping period, thereby avoiding that all sub-pixel groups in each frame leak electricity at the same time, causing a significant reduction in the overall brightness of the display panel, and improving the flickering phenomenon at low frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is further described below by means of the accompanying drawings. It should be noted that the accompanying drawings described below are only used to explain some embodiments of the present invention, and those skilled in the art can also obtain other accompanying drawings based on these accompanying drawings without creative work.

[0014] Figure 1 , Figure 4 A structural block diagram of a display panel provided by an embodiment of the present invention.

[0015] Figure 2 A brightness curve diagram of a display panel provided by an embodiment of the present invention.

[0016] Figure 3 The figure is a brightness curve diagram of a display panel in the prior art.

[0017] Figure 5 Waveform diagram of some signals of the pixel circuit provided by an embodiment of the present invention.

[0018] Figure 6 A pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0020] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined, and "electrically connected" means that there is conduction between the two, and is not limited to direct connection or indirect connection.

[0021] In addition, it should be noted that the drawings only provide structures and steps that are closely related to the present invention, and omit some details that are not closely related to the invention. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is exactly the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0022] The present invention provides a display panel, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0023] In some embodiments, in combination Figure 1 and Figure 2 As shown, the display panel 100 is used to display pictures within multiple frames, and the multiple frames include multiple first frames F1 and multiple second frames F2, including: multiple sub-pixel groups, including multiple first sub-pixel groups P1 and multiple second sub-pixel groups P2 arranged in an alternating manner; multiple gate lines (GL1 to GLn), including multiple first gate lines electrically connected to the corresponding multiple first sub-pixel groups P1, and multiple second gate lines electrically connected to the corresponding multiple second sub-pixel groups P2, the multiple first gate lines are used to transmit the corresponding multiple first gate signals, and the multiple second gate lines are used to transmit the corresponding multiple second gate signals; wherein the multiple first gate signals are used to drive the corresponding multiple first sub-pixel groups P1 to turn on within the first frame F1, and the multiple second gate signals are used to drive the corresponding multiple second sub-pixel groups P2 to turn on within the second frame F2, and the first frame F1 and the second frame F2 have an overlapping period.

[0024] The display panel 100 may be, but is not limited to, an organic self-luminous display panel, an inorganic self-luminous direct display panel, or a liquid crystal display panel. Figure 1 and Figure 2As shown, here, a plurality of sub-pixels P are arranged in an array as an example, for example, they can be arranged in n rows and m columns (n ​​and m are both positive integers), and the sub-pixel group can be a corresponding row of sub-pixels P. Further, the display panel 100 can also include a plurality of data lines (DL1 to DLm), a plurality of pixel circuits corresponding to the plurality of sub-pixels P (not shown), a source driver 206 electrically connected to the plurality of data lines, and a gate driver 201 electrically connected to the plurality of gate lines. The gate driver 201 can be a gate driving circuit located on the substrate of the display panel 100 or a separately arranged chip. Here, only the former is used as an example.

[0025] Specifically, each sub-pixel is electrically connected to a corresponding pixel circuit, each gate line is electrically connected to a plurality of pixel circuits corresponding to a plurality of sub-pixels P located in a corresponding row (for example, a first sub-pixel group P1 or a second sub-pixel group P2), and outputs a corresponding gate signal gate (including a gate effective pulse for controlling the sub-pixel P to be turned on) thereto. Under normal circumstances, a plurality of rows of sub-pixels are turned on in sequence under the control of a plurality of gate signals gate (a plurality of gate effective pulses therein), and each data line is connected to a plurality of pixel circuits corresponding to a plurality of sub-pixels P located in a corresponding column to output a corresponding data signal data (including a plurality of data voltages corresponding to the corresponding plurality of sub-pixels P) thereto. The plurality of data signals corresponding to the plurality of columns of sub-pixels are set so that when each row of sub-pixels is turned on, the corresponding plurality of data voltages are respectively transmitted to the corresponding row of sub-pixels P through a plurality of data lines.

[0026] like Figure 3 As shown, the horizontal axis is time t, and the vertical axis is brightness L. Since the first duration t1 of each frame of the display panel 100 at high frequency is shorter than the second duration t2 of each frame at low frequency, and the leakage rate is constant, the brightness L of the display panel 100 is reduced more after leakage for the longer second duration t2 at low frequency than after leakage for the shorter first duration t1 at low frequency, thereby causing flickering in multiple frames at low frequency.

[0027] like Figure 2 In the comparative example shown, only the first frame F1 of this embodiment exists, that is, in the low frequency, multiple sub-pixel groups begin to emit light in sequence at the beginning of each first frame F1 and the brightness decreases at the same time, so there is Figure 3 The flickering phenomenon in .

[0028] like Figure 2In the embodiment shown, since the multiple frames include multiple first frames F1 and multiple second frames F2, the multiple gate signals gate do not drive the multiple sub-pixel groups to turn on sequentially, but are set to include multiple first gate signals for driving the corresponding multiple first sub-pixel groups P1 to turn on sequentially in the first frame F1, and multiple second gate signals for driving the corresponding multiple second sub-pixel groups P2 to turn on sequentially in the second frame F2, and the first frame F1 and the second frame F2 have an overlapping period t0, that is, when the multiple first sub-pixel groups P1 have not yet ended leakage (that is, the multiple first sub-pixel groups P1 are still emitting light), the multiple second sub-pixel groups P2 have begun to turn on sequentially to emit light, and / or, when the multiple second sub-pixel groups P2 have not yet ended leakage (that is, the multiple first sub-pixel groups P1 are still emitting light), the multiple first sub-pixel groups P1 have begun to turn on sequentially to emit light, thereby avoiding that all sub-pixel groups in each frame (first frame F1 or second frame F2) leak at the same time, causing the overall brightness of the display panel 100 to be greatly reduced, and improving the flicker phenomenon under low frequency.

[0029] In some embodiments, in combination Figure 1 and Figure 2 As shown, the multiple sub-pixel groups are composed of a plurality of the first sub-pixel groups P1 and a plurality of the second sub-pixel groups P2 arranged alternately; the multiple frames are composed of a plurality of the first frames F1 and a plurality of the second frames F2 alternatingly, the first frame F1 and each of the two adjacent second frames F2 have a first overlapping period t01, and the second frame and each of the two adjacent first frames have a second overlapping period t02.

[0030] Specifically, in the present embodiment, it is further defined that the plurality of sub-pixel groups are composed of a plurality of first sub-pixel groups P1 and a plurality of second sub-pixel groups P2 that are alternately arranged, that is, the first sub-pixel group P1 can be one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels, and the second sub-pixel group P2 can be the other of the odd-numbered row sub-pixels and the even-numbered row sub-pixels. Correspondingly, the plurality of frames are alternately composed of a plurality of first frames F1 and a plurality of second frames F2, that is, the odd-numbered row sub-pixels and the even-numbered row sub-pixels are alternately turned on; at the same time, each adjacent first frame F1 and second frame F2 have an overlapping period t0, so that before the plurality of odd-numbered row sub-pixels have finished leaking electricity, the first frame F1 and the second frame F2 are overlapped. When the multiple even-row sub-pixels have not yet finished leaking (that is, still emitting light), the multiple odd-row sub-pixels have begun to turn on in sequence to emit light. Therefore, compared with the prior art, the time period in which the leakage amount of one of the multiple odd-row sub-pixels and the multiple even-row sub-pixels in the entire display panel 100 is larger (that is, the time period in which the brightness L decreases more) and the time period in which the leakage amount of the other is smaller (that is, the time period in which the brightness L decreases less) are overlapped, and the overall brightness of the display panel 100 in this period is improved, thereby improving the flicker phenomenon at low frequency.

[0031] Further, such as Figure 2 As shown, the duration of the first frame F1 is equal to that of the second frame F2, the duration of the two first overlapping periods t01 of the first frame F1 and the two adjacent second frames F2 are equal, and the duration of the second frame F2 and the two adjacent second overlapping periods t02 of the first frame F1 are equal.

[0032] That is, the sum of the duration of the sequential opening of the plurality of odd-numbered rows of sub-pixels and the duration of their leakage (i.e., the duration of the first frame F1) and the sum of the duration of the sequential opening of the plurality of even-numbered rows of sub-pixels and the duration of their leakage (i.e., the duration of the second frame F2) make the charging and leakage conditions of the two identical, thereby avoiding the brightness difference between the two caused by this; on this basis, the plurality of even-numbered rows of sub-pixels start to be sequentially turned on to emit light at the middle moment of the previous first frame F1, and the plurality of odd-numbered rows of sub-pixels start to be sequentially turned on to emit light at the middle moment of the previous second frame F2, so that the first frame F1 is the same as the second frame F2. The overlapping period t01 and the second overlapping period t02 are essentially the same overlapping period t0, and the first frame F1 and the second frame F2 are both divided into two overlapping periods t0, that is, multiple frames can be approximately regarded as consisting of multiple overlapping periods t0, and in each overlapping period t0, the brightness L of the display panel 100 is the brightness of multiple odd-numbered row sub-pixels with larger / smaller brightness at this time, and the brightness of multiple even-numbered row sub-pixels with smaller / larger brightness, so the brightness of the display panel 100 in each overlapping period t0 is approximately the same, which further improves the flicker phenomenon under low frequency.

[0033] Of course, in other embodiments, it can be considered that the above-mentioned first sub-pixel group P1 and the second sub-pixel group P2 can both include multiple continuous rows of sub-pixels. Correspondingly, the odd rows of sub-pixels and the even rows of sub-pixels in the above scheme are replaced by multiple rows of sub-pixels in the first sub-pixel group P1 and multiple rows of sub-pixels in the second sub-pixel group P2.

[0034] In some embodiments, the plurality of sub-pixel groups further include a plurality of third sub-pixel groups (not shown, but comparable Figure 1 The first sub-pixel group P1, the second sub-pixel group P2 and the third sub-pixel group are each provided with at least one other; the plurality of gate lines further include a plurality of third gate lines electrically connected to the corresponding plurality of third sub-pixel groups, and the plurality of third gate lines are used to transmit the corresponding plurality of third gate signals; wherein the plurality of third gate signals are used to drive the corresponding plurality of third sub-pixel groups in the third frame (not shown, but can be compared Figure 2 The plurality of frames include the first frame F1, the second frame F2 and the third frame which are sequentially arranged, and the third frame has an overlapping period with the first frame F1 and the second frame F2.

[0035] It can be understood that in the present embodiment, a plurality of sub-pixel groups are divided into a first sub-pixel group P1, a second sub-pixel group P2 and a third sub-pixel group, and the three also need to be arranged separately. For example, the order of "first sub-pixel group P1, second sub-pixel group P2, third sub-pixel group" can be repeatedly arranged as a cycle. The above "order" can also be adjusted. Of course, it can also be arranged non-repeatedly. For example, i consecutive first sub-pixel groups P1, second sub-pixel groups P2 or third sub-pixel groups can also be set, where i is a positive integer. The above i can be set based on the purpose of making the above flickering phenomenon indiscernible to the human eye.

[0036] Among them, in this embodiment, the duration of the overlapping period of the third frame with each of the first frame F1 and the second frame F2 is not limited. The duration of the two overlapping periods can be set according to the number of the first sub-pixel group P1, the second sub-pixel group P2 and the third sub-pixel group. For example, the moment when the leakage current of the first frame F1, the second frame F2 or the third frame corresponding to the larger number is larger can be used as the starting time of the subsequent second frame F2, the third frame or the first frame F1, and vice versa.

[0037] When the multiple frames include the first frame F1, the second frame F2 and the third frame F3, in any three consecutive frames (ie, three situations), the last frame has an overlapping period with the first two frames.

[0038] Similarly, in other embodiments, it can be considered that the third sub-pixel group may also include multiple consecutive rows of sub-pixels.

[0039] Furthermore, the multiple sub-pixel groups can also be divided into more types (eg, k types, k is greater than 3) of sub-pixel groups according to the situation. Similarly, in any consecutive k frames (ie, k types of situations), the last frame has an overlapping period with the previous (k-1) frame.

[0040] In some embodiments, in combination Figure 1 and Figure 4 As shown, the display panel 100 also includes the above-mentioned gate driver 201 electrically connected to the plurality of sub-pixel groups, and the gate driver 201 includes: a plurality of cascaded first gate driving units 2011, each of the first gate driving units 2011 being electrically connected to the corresponding first gate line; and a plurality of cascaded second gate driving units 2012, each of the second gate driving units 2012 being electrically connected to the corresponding second gate line.

[0041] It can be understood that in the present embodiment, a plurality of first gate signals (for example, the first gate signal may include at least one of the first sub-gate signal EM-ODD, the second sub-gate signal RST-ODD, and the third sub-gate signal SCAN-ODD) are set to be output through a plurality of cascaded first gate driving units 2011, so as to enable a plurality of gate pulses in the plurality of first gate signals to appear in sequence within the first frame F1, thereby driving a plurality of first sub-pixel groups P1 to be turned on in sequence within the first frame F1; similarly, a plurality of second gate signals (for example, the second gate signal may include at least one of the fourth sub-gate signal EM-EVEN, the fifth sub-gate signal RST-EVEN, and the sixth sub-gate signal SCAN-EVEN) are set to be output through a plurality of cascaded second gate driving units 2012, so as to enable a plurality of gate pulses in the plurality of second gate signals to appear in sequence within the second frame F2, thereby driving a plurality of second sub-pixel groups P2 to be turned on in sequence within the second frame F2.

[0042] Specific, combined Figure 1 , Figures 4 to 6 As shown, the sub-pixel group includes a plurality of the above-mentioned sub-pixels P, and the display panel 100 includes a plurality of pixel circuits 202 corresponding to the plurality of sub-pixels P, and the pixel circuit 202 includes at least a first transistor T1; the first-level first gate driving unit 2011 generates the corresponding first gate signal according to the first frame start signal (correspondingly, the first frame start signal may include at least one of the first sub-frame start signal EM-STV-ODD, the second sub-frame start signal RST-STV-ODD, and the third sub-frame start signal SCAN-STV-ODD) to turn on the corresponding first transistor T1, and the first-level second gate driving unit 2012 generates the corresponding second gate signal according to the second frame start signal (correspondingly, the second frame start signal may include at least one of the fourth sub-frame start signal EM-STV-EVEN, the fifth sub-frame start signal RST-STV-EVEN, and the sixth sub-frame start signal SCAN-STV-EVEN) to turn on the corresponding first transistor T1; wherein, the second frame start signal is obtained by shifting the first frame start signal on the time axis.

[0043] It can be understood that in this embodiment, the first-level first gate driving unit 2011 and the first-level second gate driving unit 2012 are set to be controlled by the first frame start signal and the second frame start signal with a phase difference, so that multiple gate pulses in the multiple first gate signals triggered by the former appear in sequence in the first frame F1, and multiple gate pulses in the multiple second gate signals triggered by the latter appear in sequence in the second frame F2.

[0044] Among them, the gate pulse in the second gate signal of the first stage lags behind the gate pulse of the first gate signal of the final stage to avoid turning on the first sub-pixel group P1 and the second sub-pixel group P2 at the same time. Correspondingly, the phase difference between the second frame start signal and the first frame start signal also needs to be reasonably set to meet the above requirements.

[0045] Further, combined with Figure 1 , Figures 4 to 6 As shown, the multiple first gate driving units 2011 also generate corresponding first gate signals according to a first clock signal (not shown), and the multiple second gate driving units 2012 also generate corresponding second gate signals according to a second clock signal (not shown); wherein, the second clock signal is obtained by shifting the first clock signal on the time axis.

[0046] It can be understood that the first-level first gate driving unit 2011 / non-first-level first gate driving unit 2011 can shift the first frame start signal / previous-level first gate signal according to the first clock signal to generate the first gate signal of this level, or control the corresponding pulse in the output first clock signal according to the first frame start signal / previous-level first gate signal as the gate pulse in the first gate signal; similarly, the second clock signal has a similar effect on multiple second gate driving units 2012.

[0047] Similarly, since it is necessary to satisfy that multiple gate pulses in multiple first gate signals appear sequentially in the first frame F1, and multiple gate pulses in multiple second gate signals appear sequentially in the second frame F2, differentiated settings can also be made on the phases of the first clock signal and the second clock signal.

[0048] In some embodiments, in combination Figure 1 , Figures 4 to 6As shown, the pixel circuit 202 also includes a second transistor T2; the first gate driving unit 2011 includes an electrically disconnected first sub-gate driving unit 301 and a second sub-gate driving unit 302, a plurality of the first sub-gate driving units 301 are cascaded, a plurality of the second sub-gate driving units 302 are cascaded, the first gate line includes a first sub-gate line electrically connected to the first sub-gate driving unit (for transmitting a first sub-gate signal EM-ODD) and a second sub-gate line electrically connected to the second sub-gate driving unit (for transmitting a second sub-gate signal RST-ODD); the second gate driving unit 2012 includes an electrically disconnected third sub-gate driving unit 303 and a fourth sub-gate driving unit 304, a plurality of the third sub-gate driving units 303 are cascaded, a plurality of the fourth sub-gate driving units 304 are cascaded, The gate driving unit 304 is cascaded, and the second gate line includes a third sub-gate line electrically connected to the third sub-gate driving unit (for transmitting a fourth sub-gate signal EM-EVEN), and a fourth sub-gate line electrically connected to the fourth sub-gate driving unit (for transmitting a fifth sub-gate signal RST-EVEN); wherein the first sub-gate line is electrically connected to a plurality of the first transistors T1 corresponding to the corresponding first sub-pixel group P1, and the third sub-gate line is electrically connected to a plurality of the first transistors T1 corresponding to the corresponding second sub-pixel group; wherein the second sub-gate line is electrically connected to a plurality of the second transistors T2 corresponding to the corresponding second sub-pixel group P2, and the fourth sub-gate line is electrically connected to a plurality of the second transistors T2 corresponding to the corresponding second sub-pixel group P2.

[0049] Specifically, in the present embodiment, the first gate driving unit 2011 and the second gate driving unit 2012 are further configured to include a plurality of sub-gate driving units respectively used to generate a plurality of sub-gate signals, and a plurality of sub-gate driving units of the same type for generating the same seed gate signal in the multi-level first gate driving unit 2011 / the multi-level second gate driving unit 2012 are cascaded so that a plurality of gate pulses in the generated plurality of seed gate signals appear sequentially in the first frame F1.

[0050] It should be noted that, taking multiple first sub-gate driving units 301 and multiple second sub-gate driving units 302 as an example, since at least one of the pulse width, amplitude, and phase of the pulses of the first sub-gate signal EM-ODD and the second sub-gate signal RST-ODD of the same level are different, the types of frame start signals required by the two are also different. Furthermore, similarly to the above discussion, the types of clock signals required by the two may also be different.

[0051] Similarly, the frame start signal and the clock signal required by the third sub-gate driving unit 303 and the fourth sub-gate driving unit 304 can also be set similarly.

[0052] In some embodiments, Figure 1 As shown, the multiple sub-pixels in the multiple sub-pixel groups are further arranged into multiple sub-pixel columns (for example, multiple columns of sub-pixels), and the display panel 100 further includes: the multiple data lines mentioned above, the data lines being electrically connected to the corresponding sub-pixel columns; the source driver 206 mentioned above, being electrically connected to the multiple data lines, and being used for outputting the first sub-image signals corresponding to the multiple first sub-pixel groups during the period when the first frame F1 leads the corresponding second frame F2, and being used for outputting the second sub-image signals corresponding to the multiple second sub-pixel groups during the period when the second frame F2 leads the corresponding first frame F1.

[0053] Among them, the first sub-image signal in this embodiment can be understood as a plurality of data voltages required for the plurality of first sub-pixel groups P1 to emit light in the first frame F1, and the second sub-image signal can be understood as a plurality of data voltages required for the plurality of second sub-pixel groups P2 to emit light in the second frame F2. That is, in this embodiment, the driving method of the source driver 206 is described from the perspective of the data signal, avoiding the mixed output of the plurality of data voltages of the plurality of first sub-pixel groups P1 and the plurality of data voltages of the plurality of second sub-pixel groups P2 in the overlapping period t0, thereby reducing the complexity of the source driver 206 or the timing controller 203 at the front end thereof in processing the image signal.

[0054] In some embodiments, the second sub-image signal and the first sub-image signal preceding the second sub-image signal are the same. That is, the first sub-image signal and the second sub-image signal corresponding to the adjacent first frame F1 and the second frame F2 are the same, so that the plurality of first sub-pixel groups P1 present the corresponding first sub-picture first, and the plurality of second sub-pixel groups P2 present the corresponding second sub-picture later. Since the two are arranged adjacently, even if they are the same, it is difficult for human eyes to observe them, but this can reduce the amount of data acquired by the display panel 100 and save memory for storing data.

[0055] Combination Figure 1 , Figures 4 to 6 As shown, here, it is taken as an example that the multiple sub-pixel groups only include multiple first sub-pixel groups P1 and multiple second sub-pixel groups P2, the first gate driving unit 2011 also includes a fifth sub-gate driving unit 305 for generating a third sub-gate signal SCAN-ODD, and the second gate driving unit 2012 also includes a sixth sub-gate driving unit 306 for generating a sixth sub-gate signal SCAN-EVEN. By analogy, the types of the sub-gate driving units of the first gate driving unit 2011 and the second gate driving unit 2012 should be the same, so as to provide the same number of sub-gate signals to the pixel circuit 202.

[0056] Specifically, the pixel circuit 202 includes: a data writing transistor (i.e., the fifth transistor T5), the gate of the data writing transistor is electrically connected to the corresponding first gate line or the corresponding second gate line, and one of the source and the drain of the data writing transistor is electrically connected to the corresponding data line to load the data signal data; a driving transistor (i.e., the seventh transistor T7), electrically connected to the other of the source and the drain of the data writing transistor, and one of the source and the drain of the driving transistor is connected to the corresponding sub-pixel P, and the sub-pixel P includes a self-luminous element.

[0057] Furthermore, each of the first gate line and the second gate line includes a plurality of sub-gate lines (for example, but not limited to the first sub-gate line to the fourth sub-gate line mentioned above), and the pixel circuit 202 also includes: a first reset transistor (i.e., the second transistor T2), one of the source and the drain of the first reset transistor is electrically connected to the gate of the driving transistor; one of the source and the drain of the driving transistor is electrically connected to the other of the source and the drain of the data writing transistor; the gate of the first reset transistor and one of the source and the drain of the data writing transistor are respectively electrically connected to the two sub-gate lines of the corresponding first gate line or the corresponding one of the second gate lines.

[0058] Furthermore, the pixel circuit 202 also includes: a compensation transistor (i.e., the sixth transistor T6), connected between the source and drain of the driving transistor, and the gate of the compensation transistor and one of the source and drain of the data writing transistor are electrically connected to the corresponding same sub-gate line.

[0059] Of course, the pixel circuit 202 may also include: a second reset transistor (i.e., the third transistor T3), one of the source and the drain of the second reset transistor is electrically connected to the anode of the self-luminous element; one of the source and the drain of the first switching transistor (i.e., the first transistor T1) is electrically connected to the other of the source and the drain of the driving transistor; one of the source and the drain of the second switching transistor (i.e., the fourth transistor T4) is electrically connected to one of the source and the drain of the driving transistor and the anode of the self-luminous element; the gate of the second reset transistor is electrically connected to the gate of the data writing transistor; the gate of the first switching transistor and the gate of the second switching transistor are electrically connected to the same sub-gate line of the corresponding first gate line or one of the corresponding second gate lines.

[0060] Specifically, the connection relationship between the third transistor T3 to the seventh transistor T7, the storage capacitor Cst, the first node A, the second node B, the third node C, and the fourth node Q in the pixel circuit 202 and the type of the loaded signal can refer to Figure 6 and as described above.

[0061] like Figure 5 As shown, here, the multiple sub-pixel groups only include a first sub-pixel group P1 and a second sub-pixel group P2 as an example. Therefore, in the first frame F1, the second sub-gate signal RST-ODD drives the second transistor T2 in the first sub-pixel group P1 to turn on to transmit the reset signal Vi to the fourth node Q. Thereafter, the third sub-gate signal SCAN-ODD drives the third transistor T3, the fifth transistor T5, and the sixth transistor T6 in the first sub-pixel group P1 to turn on to transmit the reset signal Vi to the third node C and the data signal data to the first node A, so that the seventh transistor T7 is turned on, and the data signal data is transmitted to the fourth node Q until the storage capacitor Cst stores the data signal data when the seventh transistor T7 is turned off. Thereafter, the first sub-gate signal EM-ODD drives the first transistor T1 and the fourth transistor T4 in the first sub-pixel group P1 to turn on, and a current path is formed between the terminal loaded with the first voltage signal VDD and the terminal loaded with the second voltage signal VSS. The driving current generated by the seventh transistor T7 drives the sub-pixel P to emit light.

[0062] Among them, it can be considered that the above process occurs in the first half of the first frame F1, and from the starting moment of the second half of the first frame F1 (corresponding to the above overlapping period t0, during which the first transistor T1 and the fourth transistor T4 are still turned on but gradually leak electricity), the second frame F2 is entered, which can also include the above processes, and the first frame F1 and the second frame F2 are performed alternately.

[0063] The present invention provides a method for driving a display panel, and the method for driving a display panel may include but is not limited to the following steps and a combination of the following steps.

[0064] S1, controlling the plurality of first gate lines to transmit the corresponding plurality of first gate signals to the plurality of first sub-pixel groups, so that the corresponding plurality of first sub-pixel groups are turned on in the first frame;

[0065] S2, controlling the plurality of second gate lines to transmit the corresponding plurality of second gate signals to the plurality of second sub-pixel groups, so that the corresponding plurality of second sub-pixel groups are turned on in the second frame, and the first frame and the second frame have an overlapping period.

[0066] Specifically, the above steps may refer to the above description of the display panel.

[0067] The structure of the display panel and the driving method thereof provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: Used to display pictures in multiple frames, wherein the multiple frames include multiple first frames and multiple second frames, including: A plurality of sub-pixel groups, including a plurality of first sub-pixel groups and a plurality of second sub-pixel groups arranged in a staggered manner; a plurality of gate lines, including a plurality of first gate lines electrically connected to the corresponding plurality of first sub-pixel groups, and a plurality of second gate lines electrically connected to the corresponding plurality of second sub-pixel groups, the plurality of first gate lines being used to transmit the corresponding plurality of first gate signals, and the plurality of second gate lines being used to transmit the corresponding plurality of second gate signals; Among them, multiple first gate signals are used to drive corresponding multiple first sub-pixel groups to turn on in the first frame, and multiple second gate signals are used to drive corresponding multiple second sub-pixel groups to turn on in the second frame, and the first frame and the second frame have an overlapping period.

2. The display panel according to claim 1, wherein: The plurality of sub-pixel groups are composed of a plurality of the first sub-pixel groups and a plurality of the second sub-pixel groups that are alternately arranged; The multiple frames are alternately composed of a plurality of the first frames and a plurality of the second frames, the first frame has an overlapping period with each of two adjacent second frames, and the second frame has an overlapping period with each of two adjacent first frames.

3. The display panel according to claim 2, wherein: The duration of the first frame is equal to that of the second frame, the duration of two overlapping periods of the first frame and two adjacent second frames is equal, and the duration of two overlapping periods of the second frame and two adjacent first frames is equal.

4. The display panel according to claim 1, wherein: The plurality of sub-pixel groups further include a plurality of third sub-pixel groups, and at least one other is disposed between each of the first sub-pixel group, the second sub-pixel group, and the third sub-pixel group; The plurality of gate lines further include a plurality of third gate lines electrically connected to the corresponding plurality of third sub-pixel groups, and the plurality of third gate lines are used to transmit the corresponding plurality of third gate signals; Among them, the multiple third gate signals are used to drive the corresponding multiple third sub-pixel groups to turn on in a third frame, and the multiple frames include the first frame, the second frame and the third frame arranged in sequence, and the third frame has an overlapping period with the first frame and the second frame.

5. The display panel according to any one of claims 1 to 4, characterized in that: Also included is a gate driver electrically connected to the plurality of sub-pixel groups, the gate driver comprising: A plurality of cascaded first gate driving units, each of the first gate driving units being electrically connected to a corresponding first gate line; A plurality of second gate driving units are cascaded, and each of the second gate driving units is electrically connected to a corresponding second gate line.

6. The display panel according to claim 5, wherein: The sub-pixel group includes a plurality of sub-pixels, the display panel includes a plurality of pixel circuits corresponding to the plurality of sub-pixels, and the pixel circuit includes at least a first transistor; The first gate driving unit of the first stage generates the corresponding first gate signal according to the first frame start signal to turn on the corresponding first transistor, and the second gate driving unit of the first stage generates the corresponding second gate signal according to the second frame start signal to turn on the corresponding first transistor; The second frame start signal is obtained by shifting the first frame start signal on the time axis.

7. The display panel according to claim 6, wherein: The plurality of first gate driving units further generate corresponding first gate signals according to the first clock signal, and the plurality of second gate driving units further generate corresponding second gate signals according to the second clock signal; The second clock signal is obtained by shifting the first clock signal on the time axis.

8. The display panel according to claim 6, wherein: The pixel circuit further includes a second transistor; The first gate driving unit includes a first sub-gate driving unit and a second sub-gate driving unit which are electrically disconnected, a plurality of the first sub-gate driving units are cascaded, a plurality of the second sub-gate driving units are cascaded, and the first gate line includes a first sub-gate line electrically connected to the first sub-gate driving unit and a second sub-gate line electrically connected to the second sub-gate driving unit; The second gate driving unit includes a third sub-gate driving unit and a fourth sub-gate driving unit which are electrically disconnected, a plurality of the third sub-gate driving units are cascaded, a plurality of the fourth sub-gate driving units are cascaded, and the second gate line includes a third sub-gate line electrically connected to the third sub-gate driving unit and a fourth sub-gate line electrically connected to the fourth sub-gate driving unit; Wherein, the first sub-gate line is electrically connected to the first transistors corresponding to the corresponding first sub-pixel group, and the third sub-gate line is electrically connected to the first transistors corresponding to the corresponding second sub-pixel group; The second sub-gate line is electrically connected to a plurality of second transistors corresponding to the corresponding first sub-pixel group, and the fourth sub-gate line is electrically connected to a plurality of second transistors corresponding to the corresponding second sub-pixel group.

9. The display panel according to any one of claims 1 to 4 and 6 to 8, characterized in that: The plurality of sub-pixels in the plurality of sub-pixel groups are further arranged into a plurality of sub-pixel columns, and the display panel further comprises: A plurality of data lines, wherein the data lines are electrically connected to the corresponding sub-pixel columns; A source driver is electrically connected to the plurality of data lines, and is used to output first sub-image signals corresponding to the plurality of first sub-pixel groups during a period when the first frame precedes the corresponding second frame, and is also used to output second sub-image signals corresponding to the plurality of second sub-pixel groups during a period when the second frame precedes the corresponding first frame.

10. The display panel according to claim 9, wherein: The second sub-image signal is the same as the first sub-image signal preceding the second sub-image signal.

11. The display panel according to any one of claims 1 to 4, 6 to 8, and 10, characterized in that: The plurality of sub-pixels in the plurality of sub-pixel groups are further arranged into a plurality of sub-pixel columns, the display panel comprises a plurality of data lines and a plurality of pixel circuits corresponding to the plurality of sub-pixels, the data lines are electrically connected to the corresponding sub-pixel columns, and the pixel circuits comprise: a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the corresponding first gate line or the corresponding second gate line, and one of a source and a drain of the data writing transistor is electrically connected to the corresponding data line; The driving transistor is electrically connected to the other of the source and the drain of the data writing transistor. One of the source and the drain of the driving transistor is connected to the corresponding sub-pixel, and the sub-pixel includes a self-luminous element.

12. The display panel according to claim 11, wherein: Each of the first gate line and the second gate line includes a plurality of sub-gate lines, and the pixel circuit further includes: a first reset transistor, wherein one of a source and a drain of the first reset transistor is electrically connected to a gate of the driving transistor; One of the source and the drain of the driving transistor is electrically connected to the other of the source and the drain of the data writing transistor; The gate of the first reset transistor and one of the source and the drain of the data writing transistor are respectively electrically connected to the two sub-gate lines of the corresponding first gate line or the corresponding second gate line.

13. The display panel according to claim 12, wherein: The pixel circuit further includes: The compensation transistor is connected between the source and the drain of the driving transistor. The gate of the compensation transistor and one of the source and the drain of the data writing transistor are electrically connected to the corresponding sub-gate line.

14. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 13, comprising: Controlling the plurality of first gate lines to transmit the corresponding plurality of first gate signals to the plurality of first sub-pixel groups, so that the corresponding plurality of first sub-pixel groups are turned on in the first frame; The plurality of second gate lines are controlled to transmit corresponding plurality of second gate signals to the plurality of second sub-pixel groups, so that the corresponding plurality of second sub-pixel groups are turned on in the second frame, and the first frame and the second frame have an overlapping period.

Images