Memory device, control method thereof, and memory system

Abstract

The embodiment of the invention discloses a memory device, a control method thereof and a memory system, and the memory device comprises a memory array which comprises a plurality of memory planes; the peripheral circuit is coupled with the plurality of storage surfaces and comprises a plurality of first micro control units (MCUs) which are coupled with the plurality of storage surfaces in a one-to-one correspondence manner; and a cache coupled to each of the plurality of first MCUs, wherein each first MCU in the plurality of first MCUs is configured to respond to an operation control signal, acquire an operation parameter from the cache according to a preset access rule, and execute an operation on the storage surface correspondingly coupled with the first MCU according to the operation parameter.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device and a control method thereof, and a memory system. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems thereof. Summary of the invention

[0004] According to some aspects of the embodiments of the present disclosure, there is provided a memory device, including:

[0005] A storage array, the storage array comprising a plurality of storage planes;

[0006] The peripheral circuit is coupled to the plurality of storage planes, comprising: a plurality of first microcontroller units (MCUs) coupled to the plurality of storage planes in a one-to-one correspondence; and a cache coupled to each of the plurality of first MCUs; wherein,

[0007] Each of the plurality of first MCUs is configured to obtain an operation parameter from the cache according to a preset access rule in response to an operation control signal, and to perform an operation on the storage plane to which it is coupled according to the operation parameter.

[0008] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the first MCU is configured to respond to the AMPI read control signal, obtain the read parameter from the cache according to a preset access rule, and perform an AMPI read operation on the storage plane to which it is correspondingly coupled according to the read parameter.

[0009] In some embodiments, the peripheral circuit further includes:

[0010] An arbitration circuit; the first MCU is coupled to the arbitration circuit, and the cache is coupled to the arbitration circuit; the arbitration circuit is configured to control the reading and writing of the cache.

[0011] In some embodiments, the arbitration circuit is configured to control data interaction between the cache and the first MCU according to the preset access rule.

[0012] In some embodiments, the arbitration circuit is further configured to:

[0013] When receiving read request signals from multiple first MCUs at the same time, authorizing the first MCU with the highest priority, reading the corresponding data in the operation parameters in the cache and sending the data to the authorized first MCU;

[0014] After the reading is completed, the current first MCU is reduced to the lowest priority.

[0015] In some embodiments, the arbitration circuit is further configured to:

[0016] Sending the authorization signal and the data read from the cache to the authorized first MCU, and the authorized first MCU determining that the data is valid;

[0017] An unauthorized signal and the data are sent to the unauthorized first MCU, and the unauthorized first MCU determines that the data is invalid.

[0018] In some embodiments, the arbitration circuit is further configured to:

[0019] When a write request signal and a read request signal are received simultaneously and / or successively, the operation parameters are preferentially written into the cache.

[0020] In some embodiments, the first MCU includes: a first register; the first register is configured to store the operating parameters sent by the cache.

[0021] In some embodiments, the peripheral circuit further includes:

[0022] A calculation subcircuit is coupled to the arbitration circuit; the calculation subcircuit is configured to generate the operation parameters and the write request signal in response to the operation control signal, and send the operation parameters and the write request signal to the arbitration circuit, so that the arbitration circuit writes the operation parameters into the cache.

[0023] In some embodiments, the calculation subcircuit includes a second register and a calculation unit;

[0024] When the memory device is powered on, the second register is configured to store initial parameters obtained from at least one of the storage planes; the calculation unit is configured to obtain the initial parameters from the second register and process them to generate the operation parameters.

[0025] In some embodiments, the peripheral circuit further includes:

[0026] The second MCU is configured to generate the operation control signal in response to the operation request, and control the calculation sub-circuit and the first MCU.

[0027] In some embodiments, the cache includes: static random access memory.

[0028] In some embodiments, the operating parameters include:

[0029] Read voltage or read voltage timing.

[0030] According to some aspects of the embodiments of the present disclosure, a control method for a memory device is provided, the memory device comprising:

[0031] A storage array, the storage array comprising a plurality of storage planes;

[0032] The peripheral circuit is coupled to the plurality of storage planes, comprising: a plurality of first microcontroller units (MCUs) coupled to the plurality of storage planes in a one-to-one correspondence; and a cache coupled to each of the plurality of first MCUs;

[0033] The control method comprises:

[0034] In response to the operation control signal, each of the plurality of first MCUs acquires an operation parameter from the cache according to a preset access rule;

[0035] The first MCU performs an operation on the storage surface to which it is coupled according to the operation parameter.

[0036] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the first MCU is configured to respond to the AMPI read control signal, obtain the read parameter from the cache according to a preset access rule, and perform an AMPI read operation on the storage plane to which it is correspondingly coupled according to the read parameter.

[0037] In some embodiments, the peripheral circuit further includes:

[0038] An arbitration circuit; the first MCU is coupled to the arbitration circuit, and the cache is coupled to the arbitration circuit;

[0039] The control method further comprises:

[0040] The arbitration circuit is enabled to control reading and writing of the cache.

[0041] In some embodiments, the control method further includes:

[0042] The arbitration circuit controls data interaction between the cache and the first MCU according to the preset access rule.

[0043] In some embodiments, the control method further includes:

[0044] When read request signals from multiple first MCUs are received simultaneously, the arbitration circuit authorizes the first MCU with the highest priority, reads the corresponding data in the operating parameters in the cache and sends it to the authorized first MCU; after the reading is completed, the current first MCU is reduced to the lowest priority.

[0045] In some embodiments, the control method further includes:

[0046] The arbitration circuit sends an authorization signal and the data read from the cache to the authorized first MCU, and the authorized first MCU determines that the data is valid;

[0047] The arbitration circuit sends an unauthorized signal and the data to the unauthorized first MCU, and the unauthorized first MCU determines that the data is invalid.

[0048] In some embodiments, the control method further includes:

[0049] When the arbitration circuit receives a write request signal and a read request signal simultaneously and / or successively, the arbitration circuit is enabled to preferentially write the operation parameter into the cache.

[0050] In some embodiments, the first MCU includes a first register; and enabling the first MCU to obtain the operation parameter from the cache includes:

[0051] The first MCU is enabled to receive the operation parameter sent by the cache, and store the operation parameter in the first register.

[0052] In some embodiments, the peripheral circuit further includes:

[0053] A calculation subcircuit is coupled to the arbitration circuit; the control method further includes:

[0054] In response to the operation control signal, the calculation subcircuit generates the operation parameter and the write request signal, sends the operation parameter and the write request signal to the arbitration circuit, and causes the arbitration circuit to write the operation parameter into the cache.

[0055] In some embodiments, the calculation subcircuit includes a second register and a calculation unit; and causing the calculation subcircuit to generate the operation parameter includes:

[0056] When the memory device is powered on, the calculation subcircuit obtains initial parameters from at least one of the storage planes and stores them in the second register; the calculation unit obtains the initial parameters from the second register and processes them to generate the operation parameters.

[0057] In some embodiments, the peripheral circuit further includes:

[0058] The second MCU; the control method further includes:

[0059] The operation control signal is generated in response to an operation request to control the calculation sub-circuit and the first MCU.

[0060] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0061] at least one memory device as described above; and

[0062] A memory controller is coupled to the memory device and controls the memory device.

[0063] The embodiment of the present disclosure provides a memory device, wherein the peripheral circuit is coupled to a plurality of storage planes, and the peripheral circuit includes a plurality of first MCUs coupled to the plurality of storage planes in a one-to-one correspondence, and a cache; each of the plurality of first MCUs responds to an operation control signal such as read, program or erase, obtains an operation parameter from the cache according to a preset access rule, and each first MCU performs an operation on the storage plane corresponding to it according to the operation parameter. On the one hand, each storage plane is configured with a first MCU, and the first MCU can be used to realize a separate control of the storage plane corresponding to it, which is conducive to realizing the synchronous operation of the plurality of storage planes and the separate asynchronous operation of each storage plane, thereby improving the operation rate of the memory device. On the other hand, the operation parameters of the memory device are stored in the cache to reduce the setting of the registers in the first MCU, reduce the control pressure of the first MCU and the circuit complexity, and multiple first MCUs share a cache, which is also conducive to reducing the excessive peripheral circuit area occupied by each first MCU when configuring a cache, and is conducive to reducing the manufacturing cost; and the access rules between the first MCU and the cache can be preset to reduce the conflict and data transmission blockage when multiple first MCUs simultaneously obtain data. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0065] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0066] Figure 2bA schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0067] Figure 3 is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0068] Figure 4 is a cross-sectional schematic diagram of a memory array including a NAND memory string according to an embodiment of the present disclosure;

[0069] Figure 5 A schematic diagram of an exemplary memory device including a memory array and a peripheral circuit according to an embodiment of the present disclosure;

[0070] Figure 6 A schematic diagram of a memory device including a plurality of first microcontrollers (MCUs) according to an embodiment of the present disclosure;

[0071] Figure 7 A schematic diagram of a memory device including a cache and an arbitration circuit according to an embodiment of the present disclosure;

[0072] Figure 8 A schematic diagram of a polling arbitration strategy of an arbitration circuit according to an embodiment of the present disclosure;

[0073] Fig. 9 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present disclosure.

[0074] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0075] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0076] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. The same reference numerals represent the same elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part. Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0078] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0079] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0080] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments without conflict.

[0081] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0082] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0083] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0084] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0085] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0086] Figure 3 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0087] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0088] like Figure 3 As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0089] like Figure 3As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of one page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates.

[0090] Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory array 301.

[0091] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0092] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0093] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0094] Return to reference Figure 3, the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0095] The page buffer / sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0096] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boost voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0097] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0098] The control logic 512 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the storage array 301 or relay or buffer data from the storage array 301.

[0099] In some embodiments, Figure 3 As shown, the memory device 104 (or memory device 300) may include a memory array 301 and a peripheral circuit 302. The memory array 301 and the peripheral circuit 302 may be arranged on the same wafer, that is, the memory array and the peripheral circuit 302 are arranged on the same die to form a chip. The memory array 301 and the peripheral circuit 302 may be arranged on different wafers, that is, the memory array Die and the peripheral circuit Die are hybrid-bonded to form a chip. A memory device 104 may be packaged into multiple chips according to the designed storage capacity. In the semiconductor manufacturing process, a wafer includes multiple Dies, and adjacent Dies are separated by cutting paths. The wafer is cut along the cutting paths to obtain Dies, and then the Dies are packaged to form chips for use in integrated circuits.

[0100] A Die of the embodiment of the present disclosure may or may not include the peripheral circuit 302. The memory array 301 may include at least one memory plane. Each Plane may include multiple pages 320. The memory cells on each page 320 share a word line. Each page 320 may be used as the minimum unit of read and write operations. Each Plane may be divided into multiple memory blocks. Each Block may be used as the minimum unit of erase operations. It should be noted that the peripheral circuit 302 of the embodiment of the present disclosure is an integral device defined for the entire memory array 301. For each memory plane, there may be a corresponding identical partial circuit or a shared partial circuit, which all belong to the integral peripheral circuit 302. Exemplarily, multiple memory planes may be coupled to one peripheral circuit 302; or each memory plane may be coupled to one peripheral circuit 302, and the memory controller 106 controls each peripheral circuit 302 to access the corresponding memory plane.

[0101] According to some aspects of the embodiments of the present disclosure, Figure 6 A schematic diagram of an exemplary memory device 104 is shown, referring to Figure 3 and Figure 6 As shown, the memory device 104 includes:

[0102] Storage array 301, the storage array 301 includes multiple storage planes (storage planes in Figure 6 not shown);

[0103] The peripheral circuit 302 is coupled to the plurality of storage planes; the peripheral circuit 302 includes: a plurality of first microcontroller units (MCUs) 610 coupled to the plurality of storage planes in a one-to-one correspondence, and a computing subcircuit 620 coupled to the plurality of first MCUs 610; the computing subcircuit 620 may be coupled to each of the first MCUs 610 in parallel;

[0104] The calculation subcircuit 620 is configured to generate an operation parameter in response to an operation control signal, and the first MCU 610 is configured to obtain the operation parameter from the calculation subcircuit 620, and perform an operation on a storage surface coupled to it according to the operation parameter, including a read operation, a programming operation or an erase operation.

[0105] In some specific embodiments, the calculation subcircuit 620 may include a second register 622 and a calculation unit 621. When the memory device 104 is powered on and reset (Power On Reset, POR), the second register 622 may be configured to store initial parameters obtained from at least one storage plane, for example, from one or more storage blocks in the storage plane; the calculation unit 621 is configured to obtain the initial parameters from the second register 622 and process them to generate operating parameters. The calculation subcircuit 620 may be coupled to Figure 6 On the first bus 641 (MBUS) shown in , multiple first MCUs 610 can also be coupled to the first bus 641, and the first bus 641 can be used to transmit operation control signals, initial parameters, and operation parameters or other parameters. The initial parameters may include the initial parameters or timing of the operation voltage for the storage unit of the memory device 104 after testing or optimization at the time of shipment. The operation parameters may include the operation parameters or timing adjusted or calculated based on the initial parameters for the specific situation of current use. For example, the operation parameter may be a read voltage or a corresponding timing, a read voltage or timing after temperature compensation or offset, or a re-read voltage determined after error correction based on the read voltage after a read failure. The first bus 641 can be used to transmit logical control signals such as control commands. The calculation unit 621 in the calculation subcircuit 620 can be coupled with multiple first MCUs 610 in parallel, and can be coupled through a single bus-port (such as the first bus 641) and transmit the operation parameters in parallel, or each first MCU 610 is coupled with the calculation unit 621 through a data line, and multiple first MCUs 610 and the calculation unit 621 have multiple data lines to achieve parallel transmission of the operation parameters. Figure 6 An example of data flow between the computing unit 621 and the first MCU 610 is shown, and no specific limitation is imposed on the physical wiring connection.

[0106] In some other specific embodiments, the memory device 104 further includes a second MCU 630 coupled to the first bus 641, and the second MCU 630 is configured to generate an operation control signal in response to an operation request, and the operation control signal can be sent to the calculation subcircuit 620 and at least one of the plurality of first MCUs 610 through the first bus 641, and control the calculation subcircuit 620 to generate an operation parameter, and control the first MCU 610 to obtain the operation parameter to operate the storage plane. The operation request may come from the memory controller.

[0107] Combination Figure 5 As shown, the first MCU 610 and the second MCU 630 may be part of the control logic 512, and the second MCU 630 is used to receive the operation request of the memory controller. In addition, the control logic 512 may also include other control circuits. The first MCU 610 is coupled with the storage surface to control a storage surface, and the second MCU 630 controls each first MCU 610, including but not limited to the operation mode and operation sequence of multiple first MCUs 610 on the storage surface. The first MCU 610 may not be part of the control logic 512, and may be set in the peripheral circuit area close to the storage surface. The second MCU 630 is part of the control logic 512 and is used to control multiple first MCUs 610, thereby optimizing the layout design of the peripheral circuit to reduce the wiring difficulty. It can be understood that the actual physical position of the first MCU 610 and the second MCU 630 in the peripheral circuit of the embodiment of the present disclosure does not limit the realization of its control function.

[0108] A plurality of first MCUs 610 are coupled to a second bus 642 (CBUS). After receiving the operation parameters, the first MCU 610 generates relevant control signals according to the operation parameters and the address information of the selected storage unit, page or storage block, and sends the signals to the voltage generator 510, the row decoder 508 or the column decoder 506 and other devices through the second bus 642 to generate corresponding operation voltages to operate the storage surface. The second bus 642 can be used to transmit analog signals such as voltage magnitude, waveform, and application timing. The second MCU 630 may include a third register 631 for storing the operation request sent by the memory controller, or storing the operation control signal of the second MCU 630 to the calculation subcircuit 620 and the first MCU 610.

[0109] In some embodiments, reference Figure 6As shown, each first MCU 610 includes a first register 611 for storing the operation parameters sent by the calculation sub-circuit 620. The operation parameters can be sent to each first MCU 610 in a parallel connection manner, and written into the first register 611 for storage and use. In this way, the first MCU 610 can be used to realize the individual control of the storage plane corresponding to it, which is conducive to the synchronous operation of multiple storage planes and the individual asynchronous operation of each storage plane, thereby improving the operation rate of the memory device 104.

[0110] In some specific embodiments, the synchronization operation may be to map the physical addresses of multiple storage planes as a whole to the logical addresses of the host to perform read, program or erase operations. When there are multiple operation requests, the memory device 104 may execute them sequentially. Taking a read operation request as an example, a read operation may be performed on a page of a storage plane, or a read operation may be performed on pages in multiple storage planes that are coupled to the same layer of word lines or located in the same row. The next read operation may be performed after the current read operation is completed.

[0111] In some specific embodiments, the asynchronous operation may be to map each storage plane as a physical address to the logical address of the host to perform a read, program or erase operation. When there are multiple operation requests, the memory device 104 may perform multiple operations simultaneously, and each storage plane may be operated separately according to different logical address-physical address mappings. Taking multiple read operation requests as an example, any page in multiple storage planes may be read separately and simultaneously, thereby improving the response rate of the memory device 104. This read mode may be referred to as asynchronous multi-plane independent (AMPI) reading, which is beneficial to improving the parallel operation efficiency of the memory device 104, and is particularly beneficial to improving the random read performance of the memory device 104. Each storage plane may also perform programming operations and erase operations independently.

[0112] In some practical use embodiments of the memory device 104, when the integration density of the storage unit of the storage plane is increasing, in order to store more operating parameters, the number of first registers 611 inside the first MCU 610 will increase accordingly, and the circuit area occupied by the first register 611 will also increase accordingly, which will occupy too much circuit area of ​​the internal control circuit of the first MCU 610. In addition, as the design becomes more and more complex, the expansion demand of the first register 611 is also increasing, and too many first registers 611 pose a very great challenge to cost control. In some embodiments, a part of the first register 611 can be replaced with a static random access memory (SRAM), and each first MCU 610 is correspondingly provided with an SRAM to meet the independent parallel operation of each storage plane, and the area occupied by the SRAM is also large. In view of this, the embodiments of the present disclosure provide a memory device 104, a control method thereof, and a memory system.

[0113] According to some aspects of the embodiments of the present disclosure, Figure 7 A memory device 104 is provided, comprising:

[0114] A storage array 301, wherein the storage array 301 includes a plurality of storage planes;

[0115] The peripheral circuit 302 is coupled to the plurality of storage planes, and includes: a plurality of first microcontroller units (MCUs) coupled to the plurality of storage planes in a one-to-one correspondence; and a cache 650 coupled to each of the plurality of first MCUs 610; wherein,

[0116] Each of the plurality of first MCUs 610 is configured to obtain an operation parameter from the cache 650 according to a preset access rule in response to an operation control signal, and to perform an operation on the storage plane coupled thereto according to the operation parameter. The operation may include a read operation, a program operation, or an erase operation.

[0117] A plurality of first MCUs 610 may share a cache 650, which may be an SRAM, a DRAM or other high-speed cache 650, and each of the plurality of first MCUs 610 may obtain operation parameters from the cache 650 according to preset access rules and perform operations on the corresponding storage plane according to the operation parameters when it is necessary to operate the storage plane. While satisfying that each storage plane can be operated independently in parallel, the circuit area occupied by the cache 650 can be reduced compared to the technical solution of configuring a cache 650 for each first MCU 610. Taking the cache 650 as an example of SRAM, when the shared SRAM is used to store operation parameters such as voltage / timing, the transistors required for the unit bit storage of the SRAM operation parameters are reduced to 1 / 6-1 / 5 compared to the register, and the circuit area occupied by the register (such as the first register 611) inside the first MCU 610 can also be reduced, and the total storage area for storing the operation parameters is reduced to Figure 6 1 / 3-1 / 2 of.

[0118] In some specific embodiments, when multiple first MCUs 610 need to operate on the corresponding storage planes at the same time, multiple first MCUs 610 need to obtain operation parameters from the cache 650. The access priority and order of the first MCUs 610 can be arbitrated by setting a preset access rule between the first MCUs 610 and the cache 650, which is used to control the order in which multiple first MCUs 610 access the cache 650. The first MCUs with higher priority can be accessed first, thereby reducing conflicts and data transmission blockages when multiple first MCUs 610 obtain data at the same time. In other specific embodiments, the preset access rule can also arbitrate the write or read-write priority of the cache 650. For example, the cache 650 will perform a write operation regardless of whether it receives a write request at the same time or is currently in a read operation and receives a write request.

[0119] In some embodiments, reference Figure 7 As shown, the first MCU 610 includes: a first register 611 ; the first register 611 is configured to store the operation parameter sent by the buffer 650 .

[0120] The first register 611 of the embodiment of the present disclosure is compared with Figure 6 The number of the first registers 611 in the first MCU 610 without the cache 650 is small, and the circuit area occupied is also small. Figure 7The first register 611 shown in is a general register, which is used to temporarily store the operating parameters obtained from the cache 650, and is used to realize the control of the storage surface. Specifically, when the first MCU 610 needs to use a certain operating parameter, the first MCU 610 loads it from the cache 650 into a general register (first register 611) for temporary storage, and the data in the general register changes dynamically according to the use. Taking the temporarily stored voltage parameter as an example, it can be written from the general register to the register of the analog circuit through the second bus 642 to realize the control output of the voltage, such as writing it into the register of the voltage generator; if the timing parameter is temporarily stored, the time control of the waveform can be realized through the timing control instruction. In some other embodiments, the first register 611 does not need to store the operating parameter for a long time, and only needs to access the cache 650 to obtain it when the operating parameter is needed. When the operating parameter does not need to be temporarily stored, it can be configured to temporarily store other instructions.

[0121] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the first MCU 610 is configured to obtain the read parameter from the cache 650 according to a preset access rule in response to the AMPI read control signal, and perform an AMPI read operation on the corresponding coupled storage plane according to the read parameter. When the storage plane performs an AMPI read, each storage plane is mapped to the logical address of the host as a physical address. Taking multiple read operation requests as an example, any page in multiple storage planes can be read separately and simultaneously, thereby improving the response rate of the memory device 104, which is beneficial to improving the parallel operation efficiency of the memory device 104, and is particularly beneficial to improving the random read performance of the memory device 104. Each storage plane can also perform programming operations and erase operations independently.

[0122] In some embodiments, the peripheral circuit 302 further includes:

[0123] Arbitration circuit 660 ; the first MCU 610 is coupled to the arbitration circuit 660 , and the cache 650 is coupled to the arbitration circuit 660 ; the arbitration circuit 660 is configured to control the reading and writing of the cache 650 . The arbitration circuit 660 implements the coupling between each first MCU 610 and the cache 650 .

[0124] The read request for the cache 650 mainly comes from the first MCU 610 , and the write request for the cache 650 may come from other circuits in the peripheral circuit 302 .

[0125] In some embodiments, the peripheral circuit 302 further includes:

[0126] The calculation subcircuit 620 is coupled to the arbitration circuit 660; the calculation subcircuit 620 is configured to generate an operation parameter and a write request signal in response to the operation control signal, and send the operation parameter and the write request signal to the arbitration circuit 660, so that the arbitration circuit 660 writes the operation parameter into the cache 650. The calculation subcircuit 620 can be a hardware calculation module, including but not limited to a hardware accelerator, an adder, or a multiplier.

[0127] In some embodiments, the calculation subcircuit 620 includes a second register 622 and a calculation unit 621; when the memory device 104 is powered on, the second register 622 is configured to store initial parameters obtained from at least one storage plane; the calculation unit 621 is configured to obtain the initial parameters from the second register 622 and process them to generate operation parameters. The second register 622 can obtain the initial parameters from one or more storage blocks in any one storage plane.

[0128] In some embodiments, the peripheral circuit 302 further includes:

[0129] The second MCU 630 ; the second MCU 630 is configured to generate an operation control signal in response to an operation request, and control the calculation sub-circuit 620 and the first MCU 610 .

[0130] Reference Figure 7As shown, a second MCU 630, a plurality of first MCUs 610 and a calculation unit 621 are coupled to a first bus 641, and an arbitration circuit 660 can also be coupled to the first bus 641 to interact with the calculation subcircuit 620 for data, or to interact with data through other ports and lines. The first bus 641 is used to transmit operation control signals, initial parameters, and operation parameters or other parameters. The initial parameters may include the initial parameters or timing of the operation voltage for the storage unit after testing or optimization of the memory device 104 at the time of leaving the factory, a voltage offset reference, etc. The operation parameters may include the operation parameters or timing adjusted or calculated based on the initial parameters for the current specific use situation. Alternatively, the initial parameters are equivalent to the operators for each operation parameter of the storage unit at the time of leaving the factory, and the operation parameters are formed after the calculation of the calculation unit 621 of the calculation subcircuit 620, and the calculation includes but is not limited to: temperature compensation, parameter offset or error correction, etc.; the specific calculation method includes but is not limited to: addition, multiplication or parity conversion. The original parameter data volume is small, and the calculation unit 621 can obtain operation parameters with more data volume and adaptable to various real-time use conditions, thereby reducing the capacity of the register and the cache 650 to reduce the occupied area. For example, the operation parameter can be a read voltage or a corresponding timing, a read voltage or timing after temperature compensation or offset, or a re-read voltage determined by error correction based on the read voltage after a read failure. The second MCU 630 may include a third register 631 for storing an operation request sent by the memory controller, or storing an operation control signal of the second MCU 630 to the calculation sub-circuit 620 and the first MCU 610.

[0131] The second MCU 630 is configured to generate an operation control signal in response to an operation request, and the operation control signal can be sent to the calculation sub-circuit 620 and at least one of the plurality of first MCUs 610 through the first bus 641, control the calculation sub-circuit 620 to generate an operation parameter, control the first MCU 610 to send a read request of the cache 650 to the arbitration circuit 660, and obtain the operation parameter to operate the storage plane. For example, after the calculation sub-circuit 620 receives the operation control signal, the calculation unit 621 obtains the initial parameters in the second register 622 to calculate and process the operation parameters such as voltage / timing required for voltage waveform control, and sends the operation parameters and a write request signal to the arbitration circuit 660 after the calculation is completed. The arbitration circuit 660 writes the operation parameter into the cache 650 in response to the write request signal. The write request signal includes a write enable signal wr_en and a corresponding cache 650 write address addr.

[0132] The first MCU 610 and the second MCU 630 may be part of the control logic 512, and the second MCU 630 is used to receive the operation request of the memory controller. In addition, the control logic 512 may also include other control circuits. The first MCU 610 may not be part of the control logic 512. Multiple first MCUs 610 are coupled to the second bus 642 (CBUS). After receiving the operation parameters, the first MCU 610 generates relevant control signals according to the operation parameters and the address information of the selected storage unit, page or storage block, and sends them to the voltage generator, row decoder or column decoder and other devices through the second bus 642 to generate corresponding operation voltages to operate the storage surface. The second bus 642 can be used to transmit analog signals such as voltage magnitude, waveform, and application timing.

[0133] In some embodiments, for the AMPI read operation, the second MCU 630 can be used as the main control core, and multiple second MCUs 630 can be used as the auxiliary control core. The second MCU 630 controls each first MCU 610 to perform a read operation on the storage surface coupled to it separately. When the AMPI read operation is not performed, the operation when multiple storage surfaces do not need to be read at the same time can be controlled and completed by the second MCU 630.

[0134] In some embodiments, arbitration circuit 660 is further configured to:

[0135] When the write request signal and the read request signal rd_req are received simultaneously and / or successively, the operation parameters are preferentially written into the cache 650. When the arbitration circuit 660 receives the write request signal, it will immediately execute the write request and write the operation parameters into the cache 650. If the cache 650 is performing a read operation at this time, the arbitration circuit 660 will cause the cache 650 to suspend the read operation and perform the write operation, and resume the suspended read operation after the write operation is completed. When the arbitration circuit 660 receives the read request and the write request at the same time, the arbitration circuit 660 controls the cache 650 to perform the write operation preferentially.

[0136] In some embodiments, the arbitration circuit 660 is configured to control data interaction between the cache 650 and the first MCU 610 according to a preset access rule.

[0137] When each first MCU 610 needs to read the operating parameters in the cache 650, it initiates a read request signal rd_req to the arbitration circuit 660, and submits the cache 650 address addr corresponding to the parameter, which is the same as the written address or has undergone other mapping conversions. If only one first MCU 610 initiates a read request, the arbitration circuit 660 directly grants the read permission to the first MCU 610, and the operation is to forward the read address of the first MCU 610 to the cache 650, and then respond with a rd_ack signal to indicate that the first MCU 610 is authorized, and at the same time forward the data read out of the cache 650 to the first MCU 610, and the first MCU 610 stores the data data in the internal first register 611

[0138] When multiple first MCUs 610 need to operate the corresponding storage planes at the same time, for example, when performing an AMPI read operation, the multiple first MCUs 610 need to obtain operation parameters from the cache 650. The access priority and order of the first MCUs 610 can be arbitrated by setting a preset access rule between the first MCUs 610 and the cache 650, so as to control the order in which the multiple first MCUs 610 access the cache 650. The first MCUs with higher priority can be accessed first, thereby reducing conflicts and data transmission blockages when the multiple first MCUs 610 obtain data at the same time.

[0139] In some embodiments, arbitration circuit 660 is further configured to:

[0140] When the read request signals rd_req of multiple first MCUs 610 are received at the same time, the first MCU 610 with the highest priority is authorized, the corresponding data in the operation parameters in the cache 650 is read and sent to the authorized first MCU 610;

[0141] After the reading is completed, the current first MCU 610 is reduced to the lowest priority.

[0142] In some embodiments, the arbitration circuit 660 is further configured to:

[0143] Sending the authorization signal and the data read from the cache 650 to the authorized first MCU 610, and the authorized first MCU 610 determines that the data is valid;

[0144] The unauthorized signal and the data are sent to the unauthorized first MCU 610, and the unauthorized first MCU 610 determines that the data is invalid.

[0145] Figure 7Taking four first MCUs 610 as an example, there may be more first MCUs 610, and the four first MCUs 610 may simultaneously initiate a total of four read request signals rd_req to the arbitration circuit 660, and submit four addresses addr corresponding to the operation parameters. The arbitration circuit 660 selects a first MCU 610 with the highest priority for authorization according to the preset access rule (or the preset arbitration strategy for the read operation), forwards the read address of the authorized first MCU 610 to the cache 650, and then responds with four rd_ack signals to the corresponding four first MCUs 610 to indicate whether authorization is obtained, and forwards the data data read from the cache 650 to the authorized first MCU 610. Here, the arbitration circuit 660 may also only send the data read from the cache 650 to the authorized first MCU 610 separately, and not send an authorization signal or an unauthorized signal to the first MCU 610. It may also be as follows Figure 7 As shown, the read data and rd_ack signal are sent to four first MCUs 610 in parallel connection. The arbitration circuit 660 responds to the authorized first MCU 610 with a high level rd_ack signal, and the authorized first MCU 610 confirms that the received data is valid after receiving the authorization signal; the arbitration circuit 660 responds to the unauthorized first MCU 610 with a low level rd_ack signal, and the unauthorized first MCU 610 confirms that the received data is invalid after receiving the unauthorized signal. The arbitration circuit 660 reduces the priority of the authorized first MCU 610 to the lowest level, and the remaining unauthorized first MCUs 610 queue up to obtain authorization according to their priorities.

[0146] In some embodiments, when the calculation subcircuit 620 initiates a write operation to the cache 650 and the first MCU 610 initiates a read operation to the cache 650 at the same time, the arbitration circuit 660 pulls down the rd_ack of the first MCU 610 to suspend the read operation until the write operation is completed and then resumes the read operation.

[0147] Figure 8 The polling arbitration table is shown taking four first MCUs 610 as an example. The four first MCUs 610 are core0 to core3, respectively, and a total of 1 to 5 polling processes (sequence 1 to 5) are shown. The priority is 0 to 3, 0 is the highest priority, and 3 is the lowest priority; a read request is 1, indicating a read request, and 0 is no read request; a response ack signal of 1 is authorized, and a response ack signal of 0 is unauthorized.

[0148] The priorities of core0 to core3 in the first polling process are 0 to 3, which can be the default priorities. The arbitration circuit 660 can define it by itself, for example, it can be defined according to the cumulative number of accesses of each core, and the one with more accesses is defined as a high priority. At this time, core0 has the highest priority 0, and its read request (request) is 1, indicating that it has a read request; the priority of core1 is 1, and there is no read request; the priority of core2 is 2, and it has a read request; the priority of core3 is 3 (the lowest priority), and it has a read request; at this time, the arbitration circuit 660 will authorize core0 as the authorized MCU, and the response ack signal is 1, and the rest of core1 to 3 are unauthorized MCUs, and the response ack signal is 0.

[0149] Entering the second polling process, core0, which was authorized in the first polling process, is downgraded to the lowest priority 3, but it has no read request; core1, which is the second lowest in the previous polling process, is upgraded to the highest priority 0, but has no read request; core2 and core3 have read requests, core2's priority is upgraded to 1, and core3's priority is upgraded to 2; core2, which has the highest priority for read requests, is authorized and responds with an ack signal of 1.

[0150] Entering the third polling process, core0 is upgraded to 2 and has a read request, core1 is at level 0 but has no read request; core2 priority is downgraded to the lowest priority 3, but has no read request; core3 priority is upgraded to 1 and has a read request; core0 and core3, which have the highest priority and have a read request, are authorized.

[0151] Entering the fourth polling process, core3 priority is downgraded to the lowest priority 3, and there is no read request; core2 priority is upgraded to 2, and there is no read request; core1 has no read request; core0 is upgraded to priority 1, and there is a request, which is authorized. The disclosed embodiment may also include more cores and more polling processes.

[0152] according to Figure 8It should be noted that for the levels of core0 to 3, in the preset access rules of the embodiment of the present disclosure, the authorized core will be downgraded to the lowest level 3 in the next polling process, and when authorizing the core, the highest priority needs to be selected from the cores with read requests. For example, in the second polling process, core1 has the highest priority 0, but it has no read request. The core2 with the highest priority between core1 and core2 with read requests is selected for authorization instead of core1. It should be noted that whether a core has a read request is determined by whether the current storage surface has an operation request, and is not determined by the arbitration circuit, and can have randomness that changes in real time.

[0153] In some embodiments, the cache 650 includes: static random access memory; or may also include dynamic random access memory, phase change memory, resistive random access memory or magnetic random access memory, etc.

[0154] In some embodiments, the operating parameter includes: a read voltage or a read voltage timing.

[0155] The read voltage or the timing of the read voltage can be for the AMPI read operation to give full play to the parallel read capability of the storage surface and improve the read rate. It should be pointed out that the read voltage and the read voltage timing can be in the form of parameters of logical data, which are sent by the first MCU 610 to a device that generates analog signals such as a voltage generator through the second bus 642. The voltage generator generates a voltage of a specific volt and applies it to the word line or bit line of the corresponding address; the timing controls the duration and interval of the voltage time, thereby completing the waveform control and output of the read voltage.

[0156] According to some aspects of the embodiments of the present disclosure, a control method of a memory device 104 is provided, referring to Figure 7 As shown, the memory device 104 includes:

[0157] A storage array 301, wherein the storage array 301 includes a plurality of storage planes;

[0158] The peripheral circuit 302 is coupled to the plurality of storage planes, and includes: a plurality of first microcontroller units (MCUs) coupled to the plurality of storage planes in a one-to-one correspondence; and a cache 650 coupled to each of the plurality of first MCUs 610;

[0159] Reference Fig. 9 As shown, the control method includes:

[0160] In response to the operation control signal, each of the plurality of first MCUs 610 acquires an operation parameter from the cache 650 according to a preset access rule;

[0161] The first MCU 610 performs an operation on the storage plane correspondingly coupled thereto according to the operation parameter.

[0162] In some embodiments, the operation control signal includes an asynchronous multi-plane independent (AMPI) read control signal; the operation parameter includes a read parameter; the first MCU 610 is configured to respond to the AMPI read control signal, obtain the read parameter from the cache 650 according to a preset access rule, and perform an AMPI read operation on the storage plane to which it is coupled according to the read parameter.

[0163] In some embodiments, the peripheral circuit 302 further includes: an arbitration circuit 660; the first MCU 610 is coupled to the arbitration circuit 660, and the cache 650 is coupled to the arbitration circuit 660;

[0164] The control method further comprises:

[0165] The arbitration circuit 660 controls the reading and writing of the cache 650 .

[0166] In some embodiments, the control method further includes:

[0167] The arbitration circuit 660 controls the data interaction between the cache 650 and the first MCU 610 according to the preset access rule.

[0168] In some embodiments, the control method further includes:

[0169] When read request signals from multiple first MCUs 610 are received simultaneously, the arbitration circuit 660 authorizes the first MCU 610 with the highest priority, reads the corresponding data in the operating parameters in the cache 650 and sends it to the authorized first MCU 610; after the reading is completed, the current first MCU 610 is reduced to the lowest priority.

[0170] In some embodiments, the control method further includes:

[0171] The arbitration circuit 660 sends an authorization signal and the data read from the cache 650 to the authorized first MCU 610, and the authorized first MCU 610 determines that the data is valid;

[0172] The arbitration circuit 660 sends an unauthorized signal and the data to the unauthorized first MCU 610, and the unauthorized first MCU 610 determines that the data is invalid.

[0173] In some embodiments, the control method further includes:

[0174] When the arbitration circuit 660 receives a write request signal and a read request signal simultaneously and / or successively, the arbitration circuit 660 is enabled to preferentially write the operation parameter into the cache 650 .

[0175] In some embodiments, the first MCU 610 includes a first register 611; and enabling the first MCU 610 to obtain an operation parameter from the cache 650 includes:

[0176] The first MCU 610 receives the operating parameters sent by the buffer 650 , and stores the operating parameters in the first register 611 .

[0177] In some embodiments, the peripheral circuit 302 further includes: a calculation subcircuit 620 coupled to the arbitration circuit 660;

[0178] The control method further includes: in response to the operation control signal, causing the calculation subcircuit 620 to generate the operation parameters and the write request signal, sending the operation parameters and the write request signal to the arbitration circuit 660, and causing the arbitration circuit 660 to write the operation parameters into the cache 650.

[0179] In some embodiments, the calculation subcircuit 620 includes a second register 622 and a calculation unit 621; the step of causing the calculation subcircuit 620 to generate the operation parameter includes:

[0180] When the memory device 104 is powered on, the calculation subcircuit 620 obtains initial parameters from at least one of the storage planes and stores them in the second register 622; the calculation unit 621 obtains the initial parameters from the second register 622 and processes them to generate the operation parameters.

[0181] In some embodiments, the peripheral circuit 302 further includes:

[0182] The second MCU 630; the control method further includes:

[0183] The operation control signal is generated in response to the operation request to control the calculation sub-circuit 620 and the first MCU 610 .

[0184] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the control method described in the above embodiments is implemented. The readable storage medium may include a NAND memory, and a storage cell of the NAND memory may include a floating gate type storage cell of a floating gate transistor, or a charge capture type storage cell including a charge capture transistor.

[0185] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0186] at least one of the above-mentioned memory devices 104; and

[0187] The memory controller 106 is coupled to the memory device 104 and controls the memory device 104 .

[0188] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory device, characterized in that: include: A storage array, the storage array comprising a plurality of storage planes; The peripheral circuit is coupled to the plurality of storage planes, and includes: a plurality of first microcontroller units MCU coupled to the plurality of storage planes in a one-to-one correspondence; and a cache coupled to each of the plurality of first MCUs; wherein, Each of the plurality of first MCUs is configured to obtain an operation parameter from the cache according to a preset access rule in response to an operation control signal, and to perform an operation on the storage plane to which it is coupled according to the operation parameter.

2. The memory device according to claim 1, wherein: The operation control signal includes an asynchronous multi-plane independent AMPI read control signal; the operation parameter includes a read parameter; the first MCU is configured to respond to the AMPI read control signal, obtain the read parameter from the cache according to a preset access rule, and perform an AMPI read operation on the storage plane corresponding to the coupling according to the read parameter.

3. The memory device according to claim 1, wherein: The peripheral circuit also includes: An arbitration circuit; the first MCU is coupled to the arbitration circuit, and the cache is coupled to the arbitration circuit; the arbitration circuit is configured to control the reading and writing of the cache.

4. The memory device according to claim 3, wherein: The arbitration circuit is configured to control data interaction between the cache and the first MCU according to the preset access rule.

5. The memory device according to claim 4, wherein: The arbitration circuit is further configured to: When receiving read request signals from multiple first MCUs at the same time, authorizing the first MCU with the highest priority, reading the corresponding data in the operation parameters in the cache and sending the data to the authorized first MCU; After the reading is completed, the current first MCU is reduced to the lowest priority.

6. The memory device according to claim 4, wherein: The arbitration circuit is further configured to: Sending the authorization signal and the data read from the cache to the authorized first MCU, and the authorized first MCU determining that the data is valid; An unauthorized signal and the data are sent to the unauthorized first MCU, and the unauthorized first MCU determines that the data is invalid.

7. The memory device according to claim 3, wherein: The arbitration circuit is further configured to: When a write request signal and a read request signal are received simultaneously and / or successively, the operation parameters are preferentially written into the cache.

8. The memory device according to claim 1, wherein: The first MCU includes: a first register; the first register is configured to store the operation parameter sent by the buffer.

9. The memory device according to claim 3, wherein: The peripheral circuit also includes: A calculation subcircuit is coupled to the arbitration circuit; the calculation subcircuit is configured to generate the operation parameters and the write request signal in response to the operation control signal, and send the operation parameters and the write request signal to the arbitration circuit, so that the arbitration circuit writes the operation parameters into the cache.

10. The memory device according to claim 9, wherein: The calculation subcircuit includes a second register and a calculation unit; When the memory device is powered on, the second register is configured to store initial parameters obtained from at least one of the memory planes; The calculation unit is configured to obtain the initial parameters from the second register and process to generate the operation parameters.

11. The memory device according to claim 9, wherein: The peripheral circuit also includes: The second MCU is configured to generate the operation control signal in response to the operation request, and control the calculation sub-circuit and the first MCU.

12. The memory device according to claim 1, wherein: The cache includes: static random access memory.

13. The memory device according to claim 1, wherein: The operating parameters include: Read voltage or read voltage timing.

14. A method for controlling a memory device, characterized in that: The memory device comprises: A storage array, the storage array comprising a plurality of storage planes; The peripheral circuit is coupled to the plurality of storage planes, and includes: a plurality of first microcontroller units MCU coupled to the plurality of storage planes in a one-to-one correspondence; and a cache coupled to each of the plurality of first MCUs; The control method comprises: In response to the operation control signal, each of the plurality of first MCUs acquires an operation parameter from the cache according to a preset access rule; The first MCU performs an operation on the storage surface to which it is coupled according to the operation parameter.

15. The control method according to claim 14, characterized in that: The operation control signal includes an asynchronous multi-plane independent AMPI read control signal; the operation parameter includes a read parameter; the first MCU is configured to respond to the AMPI read control signal, obtain the read parameter from the cache according to a preset access rule, and perform an AMPI read operation on the storage plane corresponding to the coupling according to the read parameter.

16. The control method according to claim 14, characterized in that: The peripheral circuit also includes: An arbitration circuit; the first MCU is coupled to the arbitration circuit, and the cache is coupled to the arbitration circuit; The control method further comprises: The arbitration circuit is enabled to control reading and writing of the cache.

17. The control method according to claim 16, characterized in that: The control method further comprises: The arbitration circuit controls data interaction between the cache and the first MCU according to the preset access rule.

18. The control method according to claim 17, characterized in that: The control method further comprises: When read request signals from multiple first MCUs are received simultaneously, the arbitration circuit authorizes the first MCU with the highest priority, reads the corresponding data in the operating parameters in the cache and sends it to the authorized first MCU; after the reading is completed, the current first MCU is reduced to the lowest priority.

19. The control method according to claim 18, characterized in that: The control method further comprises: The arbitration circuit sends an authorization signal and the data read from the cache to the authorized first MCU, and the authorized first MCU determines that the data is valid; The arbitration circuit sends an unauthorized signal and the data to the unauthorized first MCU, and the unauthorized first MCU determines that the data is invalid.

20. The control method according to claim 16, characterized in that: The control method further comprises: When the arbitration circuit receives a write request signal and a read request signal simultaneously and / or successively, the arbitration circuit is enabled to preferentially write the operation parameter into the cache.

21. The control method according to claim 14, characterized in that: The first MCU includes a first register; and enabling the first MCU to obtain an operation parameter from the cache includes: The first MCU is enabled to receive the operation parameter sent by the cache, and store the operation parameter in the first register.

22. The control method according to claim 16, characterized in that: The peripheral circuit also includes: A calculation subcircuit is coupled to the arbitration circuit; the control method further includes: In response to the operation control signal, the calculation subcircuit generates the operation parameter and the write request signal, sends the operation parameter and the write request signal to the arbitration circuit, and causes the arbitration circuit to write the operation parameter into the cache.

23. The control method according to claim 22, characterized in that: The calculation subcircuit includes a second register and a calculation unit; and causing the calculation subcircuit to generate the operation parameter includes: When the memory device is powered on, the calculation subcircuit obtains initial parameters from at least one of the storage planes and stores them in the second register; the calculation unit obtains the initial parameters from the second register and processes them to generate the operation parameters.

24. The control method according to claim 22, characterized in that: The peripheral circuit also includes: The second MCU; the control method further includes: The operation control signal is generated in response to an operation request to control the calculation sub-circuit and the first MCU.

25. A memory system, characterized in that: include: At least one memory device as claimed in claims 1 to 13; as well as A memory controller is coupled to the memory device and controls the memory device.

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