An FPGA-based method and system for automatically generating matching codes

Abstract

The present application provides an FPGA-based method and system for automatically generating matching codes. The method includes: writing Verilog test codes and test vectors and storing them in a table, where the test codes support dynamic parameter setting; reading the software and hardware information to be tested, executing the code generation process based on the test codes and test vectors to generate the matching code data corresponding to the software and hardware information; generating corresponding verification steps for each process in the code generation process, and sequentially verifying the matching code data generated for each process in the code generation process with the test vectors. If the verification is successful, proceed to the next code generation process and store the verification steps and verification results in the basic test plan; for the test vectors with successful code generation, automatically generate the matching code file corresponding to the software and hardware information in combination with the basic test plan. The present application realizes the comprehensive optimization of the FPGA design verification in an intelligent and automated manner, and improves the efficiency and accuracy of generating the matching code file for the FPGA design.

Description

Technical Field

[0001] This application belongs to the technical field of electronic design automation, and particularly relates to a method and system for automatically generating matching codes based on FPGA. Background Art

[0002] With the development of integrated circuit technology, EDA (Electronics Design Automation) software for FPGA (Field Programmable Gate Array) is particularly important. EDA software covers all technologies in the whole process of electronic design, simulation, verification, and manufacturing. For example: functional design, synthesis, verification, physical design (including placement, routing, layout, design rule checking, etc.) of FPGA.

[0003] In the traditional process of FPGA design and verification, manual code generation or other low - efficiency and low - reuse code - generation methods dominate. This method not only takes a lot of time and effort, but also easily introduces errors, resulting in inaccurate verification results and incomplete coverage, seriously affecting the efficiency and quality of FPGA design. With the rapid development of FPGA technology, higher requirements are put forward for the accuracy and efficiency of design verification.

[0004] Therefore, it is particularly important to develop a system that can automatically, efficiently, and accurately complete the code - generation work. Summary of the Invention

[0005] This application discloses a method and system for automatically generating matching codes based on FPGA, which can automatically generate codes for different devices through the same test code and test vectors, and accurately verify each code - generation result, solving problems such as low efficiency, poor reusability, inaccurate and unstable verification results in the traditional FPGA verification process, realizing intelligent and automatic comprehensive optimization of FPGA design verification, and improving the efficiency and accuracy of the code - generation work in FPGA design.

[0006] Other objects and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides an FPGA-based automatic code generation method, which includes: writing Verilog test code and test vectors and storing them in a table, where the test code supports dynamic parameter setting; reading the software and hardware information to be tested, and executing a code generation process based on the test code and test vectors to generate code data corresponding to the software and hardware information; generating corresponding verification steps for each process in the code generation process, and sequentially verifying the code data generated in each process of the code generation process with the test vectors. If the verification is successful, proceed to the next code generation process, and store the verification steps and verification results in the basic test plan; for the test vectors with successful code generation, automatically generate a code file corresponding to the software and hardware information in combination with the basic test plan.

[0008] In one implementation, the table is an Excel worksheet, and different Excel worksheets store test vector data of different test types; among them, the Excel worksheet at least includes a header and vector information. Each row represents a test vector, and each column represents the value corresponding to the test vector header. The Excel worksheet at least includes a serial number, vector name, parameter name, parameter value, packing rule, layout rule, and routing rule.

[0009] In one implementation, the test code is used to dynamically adjust the parameter values in the test vectors according to the software and hardware information.

[0010] In one implementation, the code generation process includes synthesis, packing, layout, routing, and generating a code stream. The method for verifying the code data generated in each code generation process includes: after executing the synthesis process, performing a primary verification on the synthesized netlist file. After the verification passes, execute the subsequent code generation process; after executing the packing process, match the pcblock file generated by the packing result with the packing rule. If the match is successful, the packing verification passes, and execute the subsequent code generation process; after executing the layout process, match the place file generated by the layout result with the layout rule. If the match is successful, the layout verification passes, and execute the subsequent code generation process; after executing the routing process, match the route file generated by the routing result with the routing rule. If the match is successful, the routing verification passes, and execute the subsequent code generation process.

[0011] In one implementation, packing includes primary packing and secondary packing. After completing the primary packing, perform secondary packing according to the corresponding packing rule in the Excel worksheet, and the packing result is the result after secondary packing.

[0012] In one implementation, the verification result is confirmed by the high and low levels of a signal, and the signal is marked in a set form.

[0013] In one implementation, the method further includes: for a test vector with successful code output, automatically extracting the code stream and the pin information associated with the code stream, and generating a code configuration file; combining the code configuration file and the basic test plan, and automatically generating the test plan for this batch, where the test plan for this batch includes the input level or input frequency of the test vector, and the output level or output frequency, and replacing the signals involved in the test plan for this batch with the corresponding pin information in the code output file.

[0014] In a second aspect, the present application provides an FPGA-based automated code configuration generation system. The system is used to implement the FPGA-based automated code configuration generation method according to any one of the first aspects. The system includes: a vector data module, configured to write Verilog test code and test vectors, and store them in a table, where the test code supports dynamic parameterization settings; a configuration reading module, configured to read the software and hardware information to be tested; an automated code configuration module, configured to execute the code output process based on the test code and test vectors, and generate the code configuration data corresponding to the software and hardware information; generating corresponding verification steps for each process in the code output process, and sequentially verifying the code configuration data generated in each process of the code output process against the test vectors. If the verification is successful, proceed to the next code output process, and store the verification steps and verification results in the basic test plan; an automated code configuration file generation module, configured to automatically generate the code configuration file corresponding to the software and hardware information in combination with the basic test plan for the test vectors with successful code output.

[0015] In a third aspect, the present application provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to execute the FPGA-based automated code configuration generation method according to any one of the first aspects.

[0016] In a fourth aspect, the present application further provides an electronic device, including one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute the FPGA-based automated code configuration generation method according to any one of the first aspects.

[0017] The above-mentioned FPGA-based automated code configuration generation method automatically generates code configurations for different devices through the same test code and test vectors, and accurately verifies each piece of code configuration data, solving problems such as low efficiency, poor reusability, inaccurate and unstable verification results in the traditional FPGA verification process. At the same time, it does not require interface operations and does not need to consider the impact brought by interface changes, realizing the comprehensive optimization of intelligent and automated FPGA design verification, and improving the efficiency and accuracy of generating code configuration files for FPGA designs.

[0018] To make the above and other objects, features, and advantages of the present application more obvious and understandable, the following specifically presents preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a schematic flowchart of the FPGA-based automatic code generation method provided by the present application.

[0021] Figure 2 It is a schematic flowchart of sequentially verifying the code output process provided by the present application.

[0022] Figure 3 It is a schematic flowchart of automatically generating a code configuration file provided by the present application.

[0023] Figure 4 It is a block diagram of the structure of the FPGA-based automatic code generation system provided by the present application. Detailed Embodiments

[0024] Regarding the foregoing and other technical contents, features, and effects of the present application, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0025] Embodiment 1

[0026] An automatic code generation method based on FPGA provided in Embodiment 1. This method includes data preparation, configuration reading and verification, step-level code generation process, step-level verification process, and automatic generation of code generation results, specifically including: writing Verilog test code and test vectors and storing them in a table, where the test code supports dynamic parameter setting; reading the software and hardware information to be tested, and executing the code generation process based on the test code and the test vectors to generate the code data corresponding to the software and hardware information; generating corresponding verification steps for each process in the code generation process, and sequentially verifying the code data generated by each process in the code generation process with the test vectors. If the verification is successful, proceed to the next code generation process, and store the verification steps and verification results in the basic test plan; for the test vectors with successful code generation, combine with the basic test plan to automatically generate the code file corresponding to the software and hardware information. The method of the present application can automatically generate codes for different devices through the same test code and test vectors, and accurately verify each code data, solving the problems of low manual code generation efficiency, poor reusability, inaccurate and unstable verification results in the traditional FPGA verification process. At the same time, there is no need for interface operation and no need to consider the impact brought by interface changes, realizing the comprehensive optimization of intelligent and automatic FPGA design verification, and improving the efficiency and accuracy of the code generation work of FPGA design.

[0027] Moreover, by binding the test vectors with the software and hardware information of the chip, the same test vectors can cover different chips. At the same time, after the test vectors are verified to be effective once, all subsequent chip and EDA software changes will not affect the accuracy of the test vectors.

[0028] The solution of the present application will be described in detail below with reference to the accompanying drawings.

[0029] Refer to Figure 1 , the embodiment of the present application provides an automatic code generation method based on FPGA, including the following steps:

[0030] Step S1: Write Verilog test code and test vectors and store them in a table, where the test code supports dynamic parameter setting.

[0031] Among them, Verilog test code and related test vector data can be written and stored in an Excel worksheet. Different test vector data of different test types can be stored in different worksheets. The Excel worksheet contains the following key data: serial number, vector name, parameter name, parameter value, and relevant rules for binning and placement and routing, so that when some test vectors need to be re-binned or specific rules are used for placement and routing, the vector requirements can be retrieved and the corresponding rules can be automatically applied. The Excel worksheet contains a header and vector information to more intuitively display these key data and quickly implement various data filtering. Refer to a part of the key data shown in Table 1.

[0032]

[0033] Table 1

[0034] At the same time, the Excel worksheet is relatively flexible and controllable. When the system needs to expand its functions, it can be quickly adapted by modifying the Excel worksheet without a large number of modifications. Each row of the Excel worksheet represents a test vector, and each column represents the parameters or parameter values of the test vector for the header. These parameter values will be applied in the subsequent code generation process. The test code supports parameterized settings, and the specified parameters can be dynamically modified later to support different devices, thereby verifying the correctness of different hardware designs.

[0035] In this embodiment, a basic test plan table can also be established through the Excel worksheet. The basic test plan table is used to record the verification steps of the test vectors and the subsequent verification results. The results are confirmed by the high and low levels of the signals. The signals are specially marked in the form of curly braces "{}" to facilitate identification and replacement. For example, if the signal is high level, it means the test passes; if the signal is low level, it means the test fails. It should be noted that the basic test plan can be set in advance or when it is needed later.

[0036] Step S2: Read the software and hardware information to be tested.

[0037] Specifically, the test code is used to dynamically adjust the parameters in the test vector according to the software and hardware information to support the code generation process corresponding to different software and hardware information. The software and hardware information includes device information and package information. The software and hardware information is converted into parameters in the test vector through the test code to support the code generation process of different devices and different packages. Among them, the device information includes the selected chip, the code stream download speed, and the relevant information of disabling / enabling pins; the package information includes the chip package form, package size, number of pins, etc.

[0038] The software and hardware information also includes the EDA design software path, the constraint conditions for each process in the code generation process, etc. The EDA design software path is used to set the installation paths of different versions of EDA software. Subsequently, during the process of generating the configuration code data, these information can be automatically extracted to obtain the required configuration code; the constraint conditions are set as the time limits for each process of generating a specific type of code stream and generating the configuration code data, etc. After setting, a preliminary check can be performed first, and the key information can also be selected to be presented to the operator in the form of an interface and the operator can be reminded to perform a secondary confirmation. After confirmation, subsequent work can be carried out.

[0039] Step S3: Execute the code generation process based on the test code and test vectors to generate the configuration code data corresponding to the software and hardware information.

[0040] Specifically, according to the read software and hardware type information, determine the device information, package information, etc. of the FPGA chip tested by the current EDA design software, and generate the corresponding configuration code data. The configuration code data refers to the configuration code file generated through the code generation process, generally in the.jpsk format, and can also be called the code stream file, which will not be elaborated further below.

[0041] In this embodiment, the code generation process includes synthesis, packing, placement, routing, and generating the code stream. There are no specific restrictions on the specific processes of each process. For example, synthesis includes parsing Verilog code through an EDA design tool, and performing optimization and mapping to output the synthesized netlist; packing includes primary packing and secondary packing. Primary packing includes allocating logic resources to corresponding logic blocks according to the packing rules, such as CLBs; secondary packing optimizes the results of primary packing according to the corresponding packing rules in the Excel worksheet; placement includes placing the logic blocks at specific positions on the FPGA chip; routing includes path allocation, channel allocation, delay optimization, etc.; generating the code stream includes generating a code stream file according to the placement and routing results, converting the code stream file into a format recognizable by the FPGA (.bit or.rbf), and outputting the final configuration code data file.

[0042] Step S4: Generate corresponding verification steps for each process in the code generation process, and sequentially verify the configuration code data generated by each process in the code generation process with the test vectors. If the verification is successful, proceed to the next code generation process, and store the verification steps and verification results in the basic test plan.

[0043] Specifically, corresponding verification steps are generated for each process in the code generation process. After each process in the above code generation process is completed, verification will be performed according to the verification steps. Only after passing the verification can the next step be carried out. The verification process is fully automated, and the verification results will be reflected in the form of logs. Refer to Figure 2 , sequentially verifying the configuration code data of each process in the code generation process with the test vectors includes the following processes:

[0044] a. Verify the synthesis result: After the synthesis process, perform an initial verification on the synthesized netlist. After passing the verification, execute the subsequent code output process. Among them, a netlist file can be generated according to the test vector data, and the parameter data in the test vector can be applied to perform the netlist generation work under different hardware. The initial verification can automatically perform syntax checking, design rule checking, timing analysis, etc. using EDA design tools, or manually verify the synthesis report.

[0045] b. Verify the packing result: After secondary packing, match the pcblock file generated by the packing result with the packing rules. If the match is successful, it means that the specified rules have been applied in the packing, then the packing verification passes, and the subsequent code output process is executed.

[0046] c. Verify the placement result: After placement, match the place file generated by the placement result with the placement rules. If the match is successful, it means that the specified rules have been applied in the placement, then the placement verification passes, and the subsequent code output process is executed.

[0047] d. Verify the routing result: After routing, the system will match the route file generated by the routing result with the routing rules. If the match is successful, it means that the specified rules have been applied in the routing, then the routing verification passes, and the subsequent code output process is executed.

[0048] After the verification is completed, store the verification result in the basic test plan for subsequent use.

[0049] Step S5: For the test vectors with successful code output, automatically generate the code matching files corresponding to the software and hardware information in combination with the basic test plan.

[0050] Among them, referring to Figure 3 , the method for automatically generating the code matching files includes:

[0051] a. For the test vectors with successful code output, automatically extract the code stream file and the PIN pin information associated with the code stream to generate the code matching files. Specifically, after the code output is completed, a large number of redundant files will be generated. By extracting the key information, the code matching JPSK files can be extracted, and the IO pin information can be extracted to generate the corresponding code matching files, which are classified and stored in the specified directory for easy submission to the manufacturing department.

[0052] b. Combine the basic test plan and the actual code output files to automatically generate the test plan for this batch, so that the manufacturing department can perform the chip verification work according to this test plan for this batch. The test plan for this batch includes the input level or frequency and the output level or frequency of the test vectors. Read the corresponding pin information of the signals involved in the test vectors from the code matching files and replace them uniformly.

[0053] To illustrate the present application more clearly, the following takes the chip EQ6HL9 as the device and uses the clearing vector of the programmable logic block CLB as an example for illustration.

[0054] The test vector Excel worksheet includes: vector name (aclr1_pos); vector function (covering the functions of signals nclr0 and nclr1 of the programmable logic block CLB, and at the same time covering part of the code block CB test); vector design (implemented through the netlist, both nclr are positive signals, there are 10 logic elements LE in one programmable logic block CLB, numbered from 0 to 9, the outputs of the 10 logic elements LE coming out of CLB1 are connected to the datad ports of the 10 logic elements LE of CLB2, the arrangement order of the logic elements LE corresponds to the signal connection order, the vertical coordinates of CLB1 and CLB2 are the same, and the horizontal coordinates differ by 3).

[0055] Automatic code generation steps: a. Read the chip information and obtain that the programmable logic blocks CLB in the chip are arranged in x rows and y columns. b. Generate the netlist of vector aclr1_pos according to the row and column information of the programmable logic block CLB of the chip. c. Perform operations such as synthesis, placement and routing, and generating the code stream according to the netlist in step b, and corresponding checks are performed in each step to ensure the correctness of the final result. d. Parse the project file in step c, generate the code generation result, generate the test plan for this batch, and the test plan for this batch will generate the verification method of the vector. Taking this vector as an example, the generated verification method is: the signal1 clock is given 1M, both signal2 and signal3 are given low, signal4 inputs a 1K square wave, and the outputs of signal5 are all 1k square waves, where the signals will generate the actual PIN pin information according to step c.

[0056] In summary, the automatic code generation method based on FPGA of the present application realizes the comprehensive optimization of the FPGA design verification process in an intelligent and automatic manner, and can support the rapid code generation of hundreds of test vectors, dozens of device and package combinations. It can achieve code generation without modifying the test vectors, and only needs to set the device and package for code generation each time. Using the same test vectors reduces the workload of the code generation personnel and also reduces the verification work of the chip verification personnel, greatly saving the time of the design department and the verification department. At the same time, it improves the accuracy and consistency of the verification results. Compared with the traditional manual code generation method, this method has the advantages of high execution efficiency, supporting multi-suite automatic code generation, intelligent recognition and adaptation, and underlying command execution. These advantages make this method have broad application prospects and important practical value in the field of FPGA design.

[0057] Embodiment 2

[0058] An automatic code generation system based on FPGA provided by Embodiment 2 can implement the above-mentioned FPGA-based automatic code generation method, such as Figure 4 As shown, the system includes:

[0059] A vector data module for writing Verilog test code and test vectors and storing them in a table, where the test code supports dynamic parameter setting.

[0060] A configuration reading module for reading the software and hardware information to be tested.

[0061] An automatic code generation module for executing a code generation process based on the test code and the test vectors to generate code data corresponding to the software and hardware information; generating corresponding verification steps for each process in the code generation process, and sequentially verifying the code data generated in each process in the code generation process with the test vectors. If the verification is successful, proceed to the next code generation process, and store the verification steps and verification results in a basic test plan.

[0062] An automatic code file generation module for automatically generating a code file corresponding to the software and hardware information in combination with the basic test plan for the test vectors with successful code generation.

[0063] It should be noted that it should be understood that the division of each module of the above system is only a division of logical functions. In actual implementation, it can be fully or partially integrated into a physical entity, or physically separated. And these modules can all be implemented in the form of software called by a processing element; they can also all be implemented in the form of hardware; or some modules can be implemented in the form of software called by a processing element, and some modules can be implemented in the form of hardware. In addition, all or part of these modules can be integrated together or can be independently implemented. Here, the processing element can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed by the integrated logic circuit in the processor element or the instruction in the form of software.

[0064] Embodiment 3

[0065] A computer-readable storage medium provided by Embodiment 3 stores program code, and the program code is called by a processor to execute the above-mentioned FPGA-based automatic code generation method.

[0066] Embodiment 4

[0067] An electronic device provided in Embodiment 4, the electronic device includes one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA-based automatic code generation method according to any one of the above.

[0068] It should be noted that for those of ordinary skill in the art of the present technology, without departing from the principle of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A method for automatically generating matching codes based on FPGA, characterized in that: The method comprises: Writing Verilog test code and test vectors, and storing them in a table, wherein the test vectors at least include vector names, parameter names, parameter values, packing rules, layout rules, and routing rules; Reading the software and hardware information to be tested, the test code dynamically adjusts the parameter value in the test vector according to the software and hardware information, and executing the code generation process based on the test code and the test vector to generate the matching code data corresponding to the software and hardware information; Generate a corresponding verification step for each process in the coding process, and verify the matching data generated by each process in the coding process and the test vector in turn. If the verification is successful, proceed to the next coding process, and store the verification step and the verification result in the basic test plan; wherein, the coding process includes synthesis, boxing, layout, routing, and code stream generation, and the method for verifying the matching data generated by each coding process includes: after executing the synthesis process, perform an initial verification on the netlist file after the synthesis, and after the verification passes, execute the subsequent coding process; after executing the boxing process, match the pcblock file generated by the boxing result with the boxing rule, if the match is successful, the boxing verification passes, and execute the subsequent coding process; after executing the layout process, match the place file generated by the layout result with the layout rule, if the match is successful, the layout verification passes, and execute the subsequent coding process; after executing the routing process, match the route file generated by the routing result with the routing rule, if the match is successful, the routing verification passes, and execute the subsequent coding process; For the test vectors that have successfully produced the code, combined with the basic test plan, the coding file corresponding to the software and hardware information is automatically generated.

2. The method for automatically generating matching codes based on FPGA according to claim 1, characterized in that: The table is an Excel worksheet, and different Excel worksheets store test vector data of different test types; wherein, the Excel worksheet includes at least a header and vector information, each row represents a test vector, and each column represents the value corresponding to the test vector header, and the Excel worksheet includes at least a serial number, a vector name, a parameter name, a parameter value, a packing rule, a layout rule, and a wiring rule.

3. The method for automatically generating matching codes based on FPGA according to claim 2, characterized in that: The packing includes primary packing and secondary packing. After the primary packing is completed, secondary packing is performed according to the corresponding packing rules in the Excel worksheet, and the packing result is the result after the secondary packing.

4. The method for automatically generating matching codes based on FPGA according to claim 1, characterized in that: The verification result is confirmed by the high and low levels of the signal, and the signal is marked in a set form.

5. The method for automatically generating matching codes based on FPGA according to claim 4, characterized in that: The method further comprises: for the test vector that has successfully generated the code, automatically extracting the code stream and the pin information associated with the code stream, and generating a code configuration file; Combine the coding file and the basic test plan to automatically generate this batch test plan, wherein the current batch test plan includes the input level or input frequency of the test vector, and the output level or output frequency, and the signals involved in the current batch test plan are replaced with the corresponding pin information in the coding file.

6. An automatic code generation system based on FPGA, characterized in that: The system is used to implement the FPGA-based automatic code generation method according to any one of claims 1 to 5, and the system includes: A vector data module, used for writing Verilog test code and test vectors, and storing them in a table, wherein the test vectors at least include vector names, parameter names, parameter values, packing rules, layout rules, and wiring rules; A configuration reading module is used to read the software and hardware information to be tested, and the test code dynamically adjusts the parameter values ​​in the test vector according to the software and hardware information; The automatic coding module is used to execute the coding process based on the test code and the test vector to generate the coding data corresponding to the software and hardware information; generate a corresponding verification step for each process in the coding process, and sequentially verify the coding data generated by each process in the coding process and the test vector; if the verification is successful, the next coding process is carried out, and the verification step and the verification result are stored in the basic test plan; wherein, the coding process includes synthesis, packaging, layout, routing, and code flow generation, and the method for verifying the coding data generated by each coding process includes: executing the synthesis flow After the process, the synthesized netlist file is initially verified. After the verification passes, the subsequent code output process is executed; after the boxing process is executed, the pcblock file generated by the boxing result is matched with the boxing rules. If the match is successful, the boxing verification passes and the subsequent code output process is executed; after the layout process is executed, the place file generated by the layout result is matched with the layout rules. If the match is successful, the layout verification passes and the subsequent code output process is executed; after the wiring process is executed, the route file generated by the wiring result is matched with the wiring rules. If the match is successful, the wiring verification passes and the subsequent code output process is executed; The module for automatically generating a code file automatically generates a code file corresponding to the software and hardware information based on the test vectors that have successfully generated the code and in combination with the basic test plan.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the FPGA-based automatic code generation method according to any one of claims 1 to 5.

8. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA-based automatic code generation method as described in any one of claims 1 to 5.

Images