Brain-computer interface signal identification circuit based on memristor neural network

Abstract

The invention discloses a brain-computer interface signal identification circuit based on a memristor neural network. The brain-computer interface signal identification circuit is composed of three neuron circuits. Each neuron circuit is composed of nine parallel branches and comprises a signal input module, a weight adjusting module, a first summing module, a memristor, a second summing module, a sampling module and a comparison module. In a single neuron circuit, after nine paths of input signals Vin1-Vin9 are respectively processed by signal input modules, weight adjusting modules, summation modules (1) and memristors of nine parallel branches, the nine paths of signals are combined together and pass through a single summation module (2), a sampling module and a comparison module, and a single identification signal of the neuron circuit is output. According to the designed circuit, a memristor neural network circuit is built by using resistance plasticity and threshold characteristics of a memristor, the meaning of a brain-computer interface signal can be preliminarily identified through a self-learning mechanism of the memristor, and the identification precision of the brain-computer interface signal can be remarkably enhanced.

Description

Technical Field

[0001] The present invention relates to the field of memristor neural network circuit design, and in particular to a brain-computer interface signal recognition circuit based on a memristor neural network. Background Art

[0002] The concept of memristor was first proposed by Chinese-American scientist Shaotang Cai in 1971. When studying the relationship between current, voltage, charge and magnetic flux, he inferred that in addition to resistors, capacitors and inductors, there should be a device that represents the relationship between charge and magnetic flux, called a memristor.

[0003] The remarkable characteristic of memristors is the plasticity of their resistance, that is, under the stimulation of an external electric field, the resistance of a memristor can change significantly, and the change in the direction of the electric field will directly cause the resistance to change in the opposite direction.

[0004] Memristors also have a threshold characteristic. The threshold characteristic of a memristor means that in the resistance switching phenomenon of a memristor, there is a specific voltage or current threshold. When the applied voltage or current exceeds this threshold, the resistance state of the memristor will change suddenly.

[0005] With the rapid development of artificial intelligence technology, traditional computer architecture has gradually shown its limitations when dealing with complex and changeable intelligent tasks. At present, the emergence of memristors has made storage-computing integrated architecture and brain-like computing hardware circuits possible, and has made it possible for computers to break through the von Neumann architecture and bring faster information processing speeds to artificial intelligence computing.

[0006] The memristor-based neural network storage and computing hardware circuit can almost complete a matrix multiplication and addition calculation (MAC) within the delay of a read operation, which is crucial to reducing energy consumption and improving speed in neural network calculations.

[0007] Currently, brain-computer interface (BCI) technology is a revolutionary way of information communication. It realizes the real-time collection, decoding and application of brain activity signals by directly establishing a connection between the human brain and external devices. This technology has shown great potential and development prospects in many research fields such as medical rehabilitation, intelligent device control, and cognitive science.

[0008] The complexity and individual differences of brain-computer interface signals pose challenges to signal processing, while neural networks, especially deep learning models, can capture and learn complex patterns and features in brain-computer interface signals through their multi-layer structure.

[0009] Traditional brain-computer interfaces usually rely on CMOS chips, which leads to challenges in power consumption and delay when the number of signal acquisition channels increases. The storage and computing integrated characteristics of memristors can effectively solve these problems and provide higher computing efficiency and lower energy consumption.

[0010] The acquisition and processing technology of brain-computer interface signals, combined with the adaptive and learning capabilities of neural networks, provides a powerful tool for decoding brain activity.

[0011] Memristive neural networks have broad application prospects in hardware-accelerated brain-computer interface signal processing. Their integrated storage and computing characteristics and their ability to imitate the processing methods of the biological brain provide technical support for improving the real-time and accuracy of brain-computer interface systems.

[0012] The brain-computer interface signal processing method has higher requirements on computing resources due to its inherent high dimensionality and complexity, and the memristor neural network has significant advantages in reducing the training time of the neural network and improving the accuracy of signal recognition. In view of this, the present invention proposes a brain-computer interface signal recognition circuit based on a memristor neural network, which is used in the initial processing stage of the brain-computer interface signal. The circuit can significantly enhance the recognition accuracy of the brain-computer interface signal. Summary of the invention

[0013] The present invention proposes a brain-computer interface signal recognition circuit based on a memristor neural network, which utilizes the resistance plasticity and threshold characteristics of a novel two-port device, a memristor, to build a memristor neural network circuit, and can preliminarily identify the meaning of the brain-computer interface signal through the self-learning mechanism of the memristor neural network circuit.

[0014] The present invention is implemented by the following technical solution: a brain-computer interface signal recognition circuit based on a memristor neural network, which consists of three neuron circuits through Figure 1 The connection method shown is shown; each neuron circuit is composed of nine parallel branches, which includes a signal input module, a weight adjustment module, a summation module①, a memristor, a summation module②, a sampling module and a comparison module.

[0015] In a single neuron circuit, when the nine input signals V in1 ~V in9 After being processed by the signal input module, weight adjustment module, summing module① and memristor of the nine parallel branches, the nine signals are merged together and passed through a single summing module②, sampling module and comparison module, and a single recognition signal of the neuron circuit is output.

[0016] As Figure 2 Taking the first neuron circuit connection relationship shown in FIG. 1 as an example, in the nine parallel input branches, the signal input module is composed of an operational amplifier A 1n1(n=1, 2, 3, ... 9), NMOS tube M 1n1 (n=1, 2, 3, ... 9) and resistor R 1n1 (n=1, 2, 3, ... 9). The first 1 in the subscript of the operational amplifier, NMOS tube and resistor indicates that the neuron is numbered as the first neuron, the second n indicates that the connected input signal is numbered as n, the third 1 indicates that the operational amplifier, NMOS tube and resistor are numbered as 1, and the subsequent numbers are deduced in the same way. Input signal V inn (n=1, 2, 3, ... 9) and operational amplifier A 1n1 The inverting input terminal is connected to transmit the input voltage signal V inn (n=1, 2, 3, ... 9); where V inn The subscript n represents the number of the input voltage signal, and the input voltage signal V inn is lower than the threshold voltage of the memristor, so it will not cause the resistance of the memristor to change; operational amplifier A 1n1 The output end is connected to the non-inverting input end and connected to the NMOS tube M 1n1 The source of NMOS tube M 1n1 The gate and control voltage signal V ctrl1 Connected, NMOS tube M 1n1 The drain and resistor R 1n1 One end of the NMOS tube M is connected 1n1 The substrate is grounded, M 1n1 The function is to control the input signal V inn The on-off resistance R 1n1 The other end of M is grounded. 1n1 The drain is also connected to the resistor R 1n3 The voltage at the junction is denoted as V' inn , and serves as one of the input signals of the next level summation module ①.

[0017] The working principle of the signal input module is as follows. Assume that a complete working cycle of the proposed circuit is 20 milliseconds. The first 10 milliseconds is the signal input period. During this stage, the control voltage V ctrl1 is high level, NMOS tube M 1n1 On, input voltage signal V inn Connect to operational amplifier A 1n1 The inverting input of the operational amplifier A 1n1 The output terminal is then output through the NMOS tube M 1n1 The next level summation module ① is input. The next 10 milliseconds is the weight adjustment period. During this stage, the control voltage V ctrl1 is low level, the control voltage Vctrl2 is high level, at this time NMOS tube M 1n1 is disconnected.

[0018] As Figure 2 Taking the first neuron circuit connection relationship shown in FIG. 1 as an example, in the nine parallel input branches, the weight adjustment module is composed of a PMOS tube M 1n2 and M 1n3 、NMOS tube M 1n4 -M 1n6 , adjust the voltage source V adj+ and V adj- , and resistor R 1n2 The analog circuit is composed of a NAND gate. 1n2 and M 1n3 The sources of the adj+ , M 1n2 and M 1n3 The drains are connected together and connected to M 1n4 The drain, M 1n2 and M 1n3 The substrate is connected to a +5V voltage source, M 1n2 The gate voltage V inn Connected, M 1n3 The gate and the comparison module output feedback adjustment voltage signal V cp1 NMOS tube M 1n4 The drain and M 1n6 The source is connected, and the voltage at the connection point is recorded as V adjn , M 1n4 Gate and input voltage V inn Connected, M 1n4 Source and M 1n5 Drain connected, M 1n4 The substrate is connected to a -5V DC voltage source. 1n5 The feedback adjustment voltage signal V output by the gate and comparison module cp1 connected, the source and the adjustment voltage V adj- The substrate is connected to a -5V DC voltage source. 1n6 Gate and control clock voltage signal V ctrl2 Connected; M 1n6 Drain and resistor R 1n2 connected, and its output voltage is used as one of the input voltages of the summing module ①, denoted as V' adjn Among them, V adj+ is an adjustment voltage slightly higher than the positive threshold voltage of the memristor, which is set to 1.1V in the present invention, V adj- It is an adjustment voltage slightly lower than the negative threshold voltage of the memristor, and is set to -1.1V in the present invention.

[0019] The working principle of the weight adjustment module is as follows. For the input voltage signal V inn The feedback adjustment voltage signal V output by the comparison module cp1 , when the voltages of the two are different in sign, it can be divided into the following four cases. inn is a positive voltage, V cp1 When the voltage is positive, the MOS tube M 1n2 Close, M 1n3 On, M 1n4 On, M 1n5 conduction, at this time the negative adjustment voltage V adj- The MOS tube can be used to adjust the voltage V adjn ; If the input voltage V inn is a positive voltage, V cp1 When the voltage is negative, the MOS tube M 1n2 Close, M 1n3 On, M 1n4 Close, M 1n5 Closed, the voltage V is being adjusted adj+ The MOS tube can be used to adjust the voltage V adjn ; If the input voltage V inn is a negative voltage, V cp1 When the voltage is positive, the MOS tube M 1n2 Open, M 1n3 Open, M 1n4 Close, M 1n5 Closed, the voltage V is being adjusted adj+ The MOS tube can be used to adjust the voltage V adjn ; If the input voltage V in1 is a negative voltage, V cp1 When the voltage is negative, the MOS tube M 1n2 Open, M 1n3 Close, M 1n4 Close, M 1n5 Turn on, and the voltage V is being adjusted adj+ Can be used as a positive adjustment voltage V through the MOS tube adjn ; When the control voltage V ctrl2 When it is a positive voltage, V adjn Through MOS tube M 1n6 Flows into the summing module ① as the adjustment signal for the memristor. At this time, the signal is recorded as V' adjn .

[0020] As Figure 2 As an example, in the nine parallel input branches, the summing module ① is composed of resistor R 1n3 -R 1n8 and operational amplifier A 1n2 , A1n3 The voltage signal V' from the signal input module inn With resistor R 1n3 One end of the weight adjustment module is connected to the adjustment voltage signal V' adjn With resistor R 1n4 One end of the resistor R 113 The other end of the resistor R 1n4 The other end is connected to the operational amplifier A 1n2 The inverting input terminal; the resistor R 1n5 One end of the operational amplifier A 1n2 The non-inverting input terminal is connected to the resistor R 1n5 The other end of the resistor R 1n6 Across operational amplifier A 1n2 Between the output terminal and the inverting input terminal. 1n7 , R 1n8 With operational amplifier A 1n3 Together they form an inverter. 1n7 One end of the operational amplifier A 1n2 The output terminal is connected to R 1n7 The other end of A 1n3 The non-inverting input terminal of R 1n8 Across operational amplifier A 1n3 Between the inverting input and output, operational amplifier A 1n3 The output voltage signal of the memristor MR 1n The input signal at one end is recorded as V sum_1n ; Memristor MR 1n The other end is connected to the resistor R of the next summing module ② 1n9 connected; here, the memristor MR 1n The first 1 in the subscript represents the first neuron, and the second n represents the serial number of the connected input voltage signal.

[0021] The working principle of summing module ① is as follows. Resistor R 1n3 -R 1n6 With operational amplifier A 1n2 Together they form an inverting adder, V' inn With V' adjn After proportional addition through the inverting adder, the resistor R 1n7 , R 1n8 and operational amplifier A 1n3 The inverter formed by the inversion is inverted, and the voltage obtained is recorded as V sum_1n ; For a complete 20 milliseconds working cycle, the first 10 milliseconds is the signal input period, at which time V ctrl1 is a positive voltage, V ctrl2 is a negative voltage, Vsum_1n It is the result obtained after the input voltage signal is calculated by the signal input module and the summing module ①, and then sampled by the memristor, the summing module ② and the sampling module, which is the output signal V of the first neuron. out1 The next 10 milliseconds is the weight adjustment period, during which the output voltage V out1 The voltage signal obtained after the weight adjustment voltage is calculated by the inverting adder and the memristor is not the target signal and is not sampled in the sampling module, so it will not be output as the target voltage signal.

[0022] As Figure 2 As an example, the connection relationship of the first neuron circuit shown in the figure is used as an example. The summing module ② is composed of a resistor R 119 -R 199 , resistor R 11 -R 14 and operational amplifier A 14 , A 15 Composition. Resistor R 1n9 To resistor R 1n9 Connected to operational amplifier A 14 Here, the operational amplifier A 14 The first number 1 in the subscript indicates the number of the neuron circuit, and the second number 4 indicates the number of the operational amplifier in the circuit; the resistor R 11 Across operational amplifier A 14 Between the output and the inverting input, the resistor R 12 One end of the operational amplifier A 14 The same-phase input terminal is connected, and the other end is grounded; the resistor R 13 One end of the operational amplifier A 14 The output end is connected to the operational amplifier A 15 The non-inverting input terminal is connected to the resistor R 14 Across operational amplifier A 15 Between the inverting input and output; A 15 The output signal at the output end is used as the input signal of the next level sampling module, denoted as V sum_1 .

[0023] The working principle of summing module ② is as follows. 119 -R 199 , R 11 , R 12 With operational amplifier A 14 Together they form an inverting adder, which performs inverting proportional addition operation on the voltage signal output from the memristor; the resistor R 13 , R 14 With operational amplifier A 15Together they form an inverter, which converts the voltage signal V' from the inverting adder sum_1 Invert and turn V sum_1 Input to the next level sampling module.

[0024] As Figure 2 Taking the connection relationship of the first neuron circuit as an example, the sampling module consists of a sample holder Q1, a capacitor C1 and a positive and negative voltage source. Capacitor C1 is used to store the sampled voltage signal, and the positive and negative voltage sources with voltage values ​​of +15V and -15V are used as the power supply of the sample holder Q1. The control voltage V ctrl1 It is used to control the sampling period of the sample-and-hold Q1. The output voltage of the sample-and-hold Q1 is the output signal V of the first neuron. out1 , and the output voltage signal V out1 As the input voltage of the next level comparison module.

[0025] The working principle of the sampling module is as follows. The positive and negative voltage sources are connected to the sample and hold Q n The positive and negative power supply terminals are used to provide power for the sample and hold operation; the capacitor C1 is used to store the collected voltage signal; the control voltage source V ctrl1 Used to control the sampling operation of the sample-and-hold device. When the control voltage source V ctrl1 When the voltage is high, the sample and hold circuit will generate the output voltage V sum_1 The sample is sampled and output to the output end of the sample-and-hold device as the output signal V of the entire neuron unit. out1 .

[0026] As Figure 2 As an example, the first neuron circuit connection relationship shown in FIG. 1 is a comparison module composed of a resistor R 15 -R 18 , reference voltage source V1 and operational amplifier A 16 The output signal of the neuron is V out1 With resistor R 15 One end of the resistor R 15 The other end is connected to the operational amplifier A 16 The inverting input terminal is connected to the resistor R 17 One end of the resistor R is connected to the reference voltage source V1. 17 The other end is connected to the operational amplifier A 16 The resistor R 18 One end of the operational amplifier A 16 Also connected to the non-inverting input terminal, the resistor R 18 The other end of the resistor R 16 Across operational amplifier A 16 Between the output and the inverting input; Operational amplifier A16 Output signal V cp1 As a feedback adjustment voltage signal, it is input into the weight adjustment module. For the complete circuit composed of three neurons in parallel in the present invention, different reference voltage sources V n (n=1, 2, 3) represents the corresponding brain-computer interface signal meaning.

[0027] The working principle of the comparison module is shown below. 15 -R 18 With operational amplifier A 16 Together they form a proportional subtractor, with V1 serving as the reference voltage and the neuron output signal V from the sampling module. out1 Compare V1 with V out1 The subtracted value is used as the feedback adjustment voltage signal V cp1 Input to the weight adjustment module, and the input voltage signal V inn (n=1, 2, 3,... 9) jointly determine the weight adjustment direction of the memristor. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a brain-computer interface signal recognition circuit based on memristor neural network.

[0029] Figure 2 This is a circuit schematic diagram of the first neuron in the present invention.

[0030] Figure 3 This is a circuit diagram of the signal input module of the first neuron in the present invention.

[0031] Figure 4 This is a circuit diagram of the weight adjustment module of the first neuron in the present invention.

[0032] Figure 5 This is the circuit diagram of the summation module ① of the first neuron in the present invention.

[0033] Figure 6 This is a circuit diagram of the memristor and summing module ② of the first neuron in the present invention.

[0034] Figure 7 This is a circuit diagram of the sampling module of the first neuron in the present invention.

[0035] Figure 8 This is a circuit diagram of the comparison module of the first neuron in the present invention.

[0036] Fig. 9 Schematic diagram of the input reference voltage for each of the three neurons.

[0037] Fig.10 This is the corresponding relationship diagram between the nine input voltage signals and the reference voltage.

[0038] Fig.11 Schematic diagram of adjusting the output voltage signal of the first neuron.

[0039] Fig.12 Schematic diagram of adjusting the output voltage signal of the second neuron.

[0040] Fig.13 Schematic diagram of adjusting the output voltage signal of the third neuron.

[0041] Fig.14 Output changes of voltage signals adjusted for feedback of three neurons. DETAILED DESCRIPTION

[0042] In order to make the technical solutions, objectives and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0043] like Figure 1 and Figure 2 As shown, the present invention proposes a brain-computer interface signal recognition circuit based on a memristor neural network. It consists of three neuron circuits through Figure 1 The connection method shown is shown; each neuron circuit is composed of nine parallel branches, which includes a signal input module, a weight adjustment module, a summation module①, a memristor, a summation module②, a sampling module and a comparison module.

[0044] As Figure 2 As an example, when the nine-way input signal V in1 ~V in9 After being processed by the signal input module, weight adjustment module, summing module① and memristor of the nine parallel branches, the nine signals are merged together and passed through a single summing module②, sampling module and comparison module, and a single recognition signal of the neuron circuit is output.

[0045] Signal input module, such as Figure 3 As shown, it consists of an operational amplifier A 1n1 (n=1, 2, 3, ... 9), NMOS tube M 1n1 (n=1, 2, 3, ... 9) and resistor R 1n1 (n=1, 2, 3, ... 9). The first 1 in the subscript of the operational amplifier, NMOS tube and resistor indicates that the neuron is numbered as the first neuron, the second n indicates that the connected input signal is numbered as n, the third 1 indicates that the operational amplifier, NMOS tube and resistor are numbered as 1, and the subsequent numbers are deduced in the same way. Input signal V inn (n=1, 2, 3, ... 9) and operational amplifier A 1n1The inverting input is connected to inn The subscript n represents the number of the input voltage signal; operational amplifier A 1n1 The output end is connected to the non-inverting input end and connected to the NMOS tube M 1n1 The source of NMOS tube M 1n1 The gate and control voltage signal V ctrl1 Connected, NMOS tube M 1n1 The drain and resistor R 1n1 One end of the NMOS tube M is connected 1n1 The substrate is grounded; the resistor R 1n1 The other end of M is grounded. 1n1 The drain is also connected to the resistor R 1n3 The voltage at the junction is denoted as V' inn , and serves as one of the input signals of the next level summation module ①.

[0046] Weight adjustment module, such as Figure 4 As shown, the PMOS tube M 1n2 and M 1n3 、NMOS tube M 1n4 -M 1n6 , adjust the voltage source V adj+ and V adj- , and resistor R 1n2 The analog circuit is composed of a NAND gate. 1n2 and M 1n3 The sources of the adj+ , M 1n2 and M 1n3 The drains are connected together and connected to M 1n4 The drain, M 1n2 and M 1n3 The substrate is connected to a +5V voltage source, M 1n2 The gate voltage V inn Connected, M 1n3 The gate and the comparison module output feedback adjustment voltage signal V cp1 NMOS tube M 1n4 The drain and M 1n6 The source is connected, and the voltage at the connection point is recorded as V adjn ;M 1n4 Gate and input voltage V inn Connected, M 1n4 Source and M 1n5 Drain connected, M 1n4 The substrate is connected to a -5V DC voltage source. 1n5 The feedback adjustment voltage signal V output by the gate and comparison module cp1 connected, the source and the adjustment voltage Vadj- The substrate is connected to a -5V DC voltage source. 1n6 Gate and control clock voltage signal V ctrl2 Connected; M 1n6 Drain and resistor R 1n2 The output voltage of the summing module ① is connected to one end of the summing module, and is recorded as V' adjn ; Resistance R 1n2 The other end is grounded.

[0047] Summation module①, such as Figure 5 As shown, it consists of a resistor R 1n3 -R 1n8 and operational amplifier A 1n2 , A 1n3 The voltage signal V' from the signal input module inn With resistor R 1n3 One end of the weight adjustment module is connected to the adjustment voltage signal V' adjn With resistor R 1n4 One end of the resistor R 113 The other end of the resistor R 1n4 The other end is connected to the operational amplifier A 1n2 The inverting input terminal; the resistor R 1n5 One end of the operational amplifier A 1n2 The non-inverting input terminal is connected to the resistor R 1n5 The other end of the resistor R 1n6 Across operational amplifier A 1n2 Between the output terminal and the inverting input terminal. 1n7 , R 1n8 With operational amplifier A 1n3 Together they form an inverter. 1n7 One end of the operational amplifier A 1n2 The output terminal is connected to R 1n7 The other end of A 1n3 The non-inverting input terminal of R 1n8 Across operational amplifier A 1n3 Between the inverting input and output, operational amplifier A 1n3 The output voltage signal of the memristor MR 1n The input signal at one end is recorded as V sum_1n ; Memristor MR 1n The other end is connected to the resistor R of the next summing module ② 1n9 connected; here, the memristor MR 1n The first 1 in the subscript represents the first neuron, and the second n represents the serial number of the connected input voltage signal.

[0048] Summing module ② and memristor, such as Figure 6 As shown; the summing module ② is composed of resistor R 119 -R 199 , resistor R 11 -R 14 and operational amplifier A 14 , A 15 Composition. sum_1n Memristor 1n (n=1, 2, 3, ... 9) is connected to one end of the memristor MR 1n The other end of the resistor R 1n9 (n=1, 2, 3, ... 9) are connected. Resistor R 119 To resistor R 199 Connected to operational amplifier A 14 Here, the operational amplifier A 14 The first number 1 in the subscript indicates the number of the neuron circuit, and the second number 4 indicates the number of the operational amplifier in the circuit; the resistor R 11 Across operational amplifier A 14 Between the output and the inverting input, the resistor R 12 One end of the operational amplifier A 14 The same-phase input terminal is connected, and the other end is grounded; the resistor R 13 One end of the operational amplifier A 14 The output end is connected to the operational amplifier A 15 The non-inverting input terminal is connected to the resistor R 14 Across operational amplifier A 15 Between the inverting input and output; A 15 The output signal at the output end is used as the input signal of the next level sampling module, denoted as V sum_1 .

[0049] Sampling modules, such as Figure 7 As shown in the figure, it consists of a sample-and-hold device Q1, a capacitor C1 and a positive and negative voltage source. Capacitor C1 is used to store the sampled voltage signal. The positive and negative voltage sources with voltage values ​​of +15V and -15V are used as the power supply for the sample-and-hold device Q1. The control voltage V ctrl1 It is used to control the sampling period of the sample-and-hold Q1. The output voltage of the sample-and-hold Q1 is the output signal V of the first neuron. out1 , and the output voltage signal V out1 As the input voltage of the next level comparison module.

[0050] Compare modules such as Figure 8 As shown, it consists of a resistor R 15 -R 18 , reference voltage source V1 and operational amplifier A16 The output signal of the neuron is V out1 With resistor R 15 One end of the resistor R 15 The other end is connected to the operational amplifier A 16 The inverting input terminal is connected to the resistor R 17 One end is connected to the reference voltage source V1, and the other end is connected to the operational amplifier A 16 At the same time, the resistor R 18 One end of the operational amplifier A 16 Also connected to the non-inverting input terminal, the resistor R 18 The other end of the resistor R 16 Across operational amplifier A 16 Between the output and the inverting input; Operational amplifier A 16 Output signal V cp1 As a feedback adjustment voltage signal, it is input into the weight adjustment module.

[0051] In a simulation example of a brain-computer interface signal recognition circuit based on a memristor neural network, Fig. 9 Schematic diagram of the input reference voltage of each of the three neurons, assuming V1 is 1V, V2 is 2V, and V3 is 3V.

[0052] Fig.10 This is the corresponding relationship diagram between the nine input voltage signals and the reference voltage. Fig.10 (a) is the corresponding position of the nine input voltage signals. Fig.10 (b) is the brain-computer interface signal image corresponding to V1. Fig.10 (c) is the brain-computer interface signal image corresponding to V2. Fig.10 (d) is the brain-computer interface signal image corresponding to V3, where the black block corresponds to 0.5V and the white block corresponds to 0V.

[0053] Fig.11 This is a schematic diagram of adjusting the output voltage signal of the first neuron. For the first neuron, its reference voltage V1 is set to 1V. This schematic diagram is the result obtained after the sampling module of the first neuron samples the output voltage. It can be seen from the figure that after two cycles of learning, the output signal of the first neuron is very close to the reference voltage. At this time, the neuron stops learning and the training is completed.

[0054] Fig.12The diagram is a schematic diagram of the output voltage signal adjustment of the second neuron. For the second neuron, its reference voltage V2 is set to 2V. This diagram is the result obtained after the sampling module of the second neuron samples the output voltage. As can be seen from the figure, after several cycles of learning, the output signal of the second neuron is slightly higher than the reference voltage. After adjustment, the neuron output is reduced, and after further adjustment, it is consistent with the reference voltage, which reflects the robustness of the neuron adjustment process.

[0055] Fig.13 This is a schematic diagram of adjusting the output voltage signal of the third neuron. For the third neuron, its reference voltage V3 is set to 3V. This schematic diagram is the result obtained after the sampling module of the third neuron samples the output voltage. It can be seen from the figure that after several cycles of learning, the output result of the third neuron is close to the reference voltage, and the output voltage fluctuates around the reference voltage, and the fluctuation value is small, which is within the acceptable error range.

[0056] Fig.14 The output change diagram of the voltage signal of the three neurons is adjusted by feedback. As can be seen from the figure, the difference between the output voltage of the three neuron circuits and the reference voltage gradually approaches 0 during the self-learning process, which verifies that the circuit proposed in the present invention can enhance the recognition accuracy of the brain-computer interface signal.

Claims

1. A brain-computer interface signal recognition circuit based on a memristor neural network, characterized in that: It consists of three neuron circuits; each neuron circuit consists of nine parallel branches, and includes a signal input module, a weight adjustment module, a summing module①, a memristor, a summing module②, a sampling module and a comparison module; In a single neuron circuit, when the nine input signals V in1 ~V in9 After being processed by the signal input module, weight adjustment module, summation module① and memristor of nine parallel branches, the nine signals are merged together and passed through a single summation module②, sampling module and comparison module, and a single identification signal of the neuron circuit is output; the designed circuit utilizes the resistance plasticity and threshold characteristics of the memristor to build a memristor neural network circuit, and can preliminarily identify the meaning of the brain-computer interface signal through its self-learning mechanism, which can significantly enhance the recognition accuracy of the brain-computer interface signal.

2. A brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The signal input module consists of an operational amplifier A 1n1 (n=1, 2, 3, ... 9), NMOS tube M 1n1 (n=1, 2, 3, ...9) and resistor R 1n1 (n=1, 2, 3, ... 9); the first 1 in the subscript of the operational amplifier, NMOS tube and resistor indicates that the neuron is numbered as the first neuron, the second n indicates that the connected input signal is numbered as n, the third 1 indicates that the operational amplifier, NMOS tube and resistor are numbered as 1, and the subsequent numbers are deduced in the same way; the input signal V inn (n=1, 2, 3, ...9) and operational amplifier A 1n1 The inverting input is connected to inn The subscript n represents the number of the input voltage signal; operational amplifier A 1n1 The output end is connected to the non-inverting input end and connected to the NMOS tube M 1n1 The source of NMOS tube M 1n1 The gate and control voltage signal V ctrl1 Connected, NMOS tube M 1n1 The drain and resistor R 1n1 One end of the NMOS tube M is connected 1n1 The substrate is grounded; the resistor R 1n1 The other end of M is grounded. 1n1 The drain is also connected to the resistor R 1n3 The voltage at the junction is denoted as V' inn , and serves as one of the input signals of the next level summation module ①.

3. The brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The weight adjustment module is composed of PMOS tube M 1n2 and M 1n3 、NMOS tube M 1n4 -M 1n6 , adjust the voltage source V adj+ and V adj- , and resistor R 1n2 Constitute an analog circuit and a NAND gate; where M 1n2 and M 1n3 The sources of the adj+ , M 1n2 and M 1n3 The drains are connected together and connected to M 1n4 The drain, M 1n2 and M 1n3 The substrate is connected to a +5V voltage source, M 1n2 The gate voltage V inn Connected, M 1n3 The gate and the comparison module output feedback adjustment voltage signal V cp1 Connected; NMOS tube M 1n4 The drain and M 1n6 The source is connected, and the voltage at the connection point is recorded as V adjn ;M 1n4 Gate and input voltage V inn Connected, M 1n4 Source and M 1n5 Drain connected, M 1n4 The substrate is connected to a -5V DC voltage source; the NMOS tube M 1n5 The feedback adjustment voltage signal V output by the gate and comparison module cp1 connected, the source and the adjustment voltage V adj- connected, the substrate is connected to a -5V DC voltage source; NMOS tube M 1n6 Gate and control clock voltage signal V ctrl2 Connected; M 1n6 Drain and R 1n2 The output voltage of the summing module ① is connected to one end of the summing module, and is recorded as V' adjn ; Resistance R 1n2 The other end is grounded.

4. The brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The summing module ① consists of resistor R 1n3 -R 1n8 and operational amplifier A 1n2 , A 1n3 Composition: voltage signal V' from the signal input module inn With resistor R 1n3 One end of the weight adjustment module is connected to the adjustment voltage signal V' adjn With resistor R 1n4 One end of the resistor R 113 The other end of the resistor R 1n4 The other end is connected to the operational amplifier A 1n2 The inverting input terminal; the resistor R 1n5 One end of the operational amplifier A 1n2 The non-inverting input terminal is connected to the resistor R 1n5 The other end of the resistor R 1n6 Across operational amplifier A 1n2 Between the output terminal and the inverting input terminal; resistor R 1n7 , R 1n8 With operational amplifier A 1n3 Together they form an inverter; the resistor R 1n7 One end of the operational amplifier A 1n2 The output terminal is connected to R 1n7 The other end of A 1n3 The non-inverting input terminal of R 1n8 Across operational amplifier A 1n3 Between the inverting input and output, operational amplifier A 1n3 The output voltage signal of the memristor MR 1n The input signal at one end is recorded as V sum_1n ; Memristor MR 1n The other end is connected to the resistor R of the next summing module ② 1n9 connected; here, the memristor MR 1n The first 1 in the subscript represents the first neuron, and the second n represents the serial number of the connected input voltage signal.

5. The brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The summing module ② and the memristor are composed of resistor R 119 -R 199 , resistor R 11 -R 14 and operational amplifier A 14 , A 15 and memristor MR 1n Composition: V sum_1n Memristor 1n (n=1, 2, 3, ... 9) is connected to one end of the memristor MR 1n The other end of the resistor R 1n9 (n=1, 2, 3, ... 9) connected; resistor R 119 To resistor R 199 Connected to operational amplifier A 14 Here, the operational amplifier A 14 The first number 1 in the subscript indicates the number of the neuron circuit, and the second number 4 indicates the number of the operational amplifier in the circuit; the resistor R 11 Across operational amplifier A 14 Between the output and the inverting input, the resistor R 12 One end of the operational amplifier A 14 The same-phase input terminal is connected, and the other end is grounded; the resistor R 13 One end of the operational amplifier A 14 The output end is connected to the operational amplifier A 15 The non-inverting input terminal is connected to the resistor R 14 Across operational amplifier A 15 Between the inverting input and output; A 15 The output signal at the output end is used as the input signal of the next level sampling module, denoted as V sum_1 .

6. The brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The sampling module consists of a sampler and holder Q1, a capacitor C1 and a positive and negative voltage source; the capacitor C1 is used to store the sampled voltage signal, and the positive and negative voltage sources with voltage values ​​of +15V and -15V are used as the power supply for the sampler and holder Q1, and the control voltage V ctrl1 It is used to control the sampling period of the sample-and-hold Q1. The output voltage of the sample-and-hold Q1 is the output signal V of the first neuron. out1 , and the output voltage signal V out1 As the input voltage of the next level comparison module.

7. The brain-computer interface signal recognition circuit based on a memristor neural network according to claim 1, characterized in that: The comparison module consists of a resistor R 15 -R 18 , reference voltage source V1 and operational amplifier A 16 Composition; the output signal V of the neuron out1 With resistor R 15 One end of the resistor R 15 The other end is connected to the operational amplifier A 16 The inverting input terminal is connected to the resistor R 17 One end is connected to the reference voltage source V1, and the other end is connected to the operational amplifier A 16 At the same time, the resistor R 18 One end of the operational amplifier A 16 Also connected to the non-inverting input terminal, resistor R 18 The other end of the resistor R 16 Across operational amplifier A 16 Between the output and the inverting input; Operational amplifier A 16 Output signal V cp1 As a feedback adjustment voltage signal, it is input into the weight adjustment module.

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