Method and system for mainboard boundary scan test and CPU simulation structure

Abstract

The invention discloses a method, a system and a CPU (central processing unit) simulation structure for a mainboard boundary scan test. According to the method, a to-be-tested mainboard is placed on a jig carrier plate, a jig acts, and a first connector in the to-be-tested mainboard is connected with a second connector in a first simulation test card and a third connector in a second simulation test card in an inserted mode; according to the method, the cascade chain of the first simulation test card and the second simulation test card is subjected to the boundary scan test through the arranged boundary scan controller, and the system and the CPU simulation structure corresponding to the method can solve the defects of the conventional CPU test, achieve the boundary scan test coverage effect better than that of the conventional CPU, and have the advantages of high test reliability, high test speed and low cost. The power-on, the power-on time sequence and the power-on time of the CPU do not need to be considered, signal receiving, transmitting and reading are all completed through the DUMMY, the test effect is completely mastered at the design end of the boundary scan test, the compatibility is high, and the safety is high.

Description

Technical Field

[0001] The invention belongs to the technical field of boundary scan test processing, and in particular relates to a method, a system and a CPU simulation structure for a mainboard boundary scan test. Background Art

[0002] At present, in the field of boundary scan testing of motherboards, with the improvement of the integration of motherboards, the CPU takes on more tasks, and the functions of coordinating motherboard communication and control through the CPU's peripheral chips are gradually integrated into the CPU. For example, the first generation of Core processors came out in 2009, bringing a new QPI bus, and the functions of the north bridge chip on the motherboard were integrated by the CPU. After that, only the south bridge chip (PCH) was left on the motherboards of major manufacturers. At present, there are many different types of CPUs that integrate the functions of the south bridge chip, such as PCIExpress controllers, USB controllers, and even sound cards and SATA controllers. These south bridge chip functions are also gradually being integrated by the CPU. For example, the ASRock Deskmini A300 STX motherboard that supports AMD Ryzen CPUs and the Zhaoxin KX-600 motherboard for domestic x86 CPUs do not have independent PCH chips. The motherboard has gradually developed into a motherboard with the CPU as the only function and control core. For the boundary scan test of the motherboard, it is only necessary to consider the boundary scan test of the connection network relationship related to the CPU on the motherboard.

[0003] The boundary scan test of the motherboard needs to consider the docking between the CPU and the CPU slot on the motherboard. In order to realize automated testing, the CPU is automatically pressed down and fixed under the pressing device. Before each test, the CPU is pressed down to the CPU slot on the motherboard through the pressing device, and a certain pressing force is given to the CPU to ensure that the BGA package pins of the CPU are in close contact with the slot pins on the motherboard. After the pressing is completed, the motherboard is powered on and then the boundary scan test is performed.

[0004] The boundary scan test of the motherboard is subject to the CPU power-on timing and the conditions for entering the boundary scan mode. First, according to the pin power-on timing defined in the chip datesheet, these pins are controlled to be powered on in sequence to ensure that the CPU power-on timing is normal. Secondly, the CPU has different IO level standards. For example, the CPU is connected to the DDR5 connector of the motherboard to be tested (mainboard), and the IO level standard is usually 1.05V. When connected to other connectors such as PCIE, the IO level standard is usually 3.3V. Therefore, it is necessary to design simulation test cards (DUMMY cards) with different level standards to connect with these connectors with different level standards for IO docking test. Then, in order to smoothly enter the boundary scan mode, it is necessary to control the level of the relevant mode pins defined in BSDL to ensure that the prerequisite for entering the boundary scan mode is met. These pin signals need to be led out and controlled from the motherboard by pin-down. In addition, the JTAG signal of the CPU also needs to be led out by pin-down. In short, the boundary scan test of the CPU needs to be compatible with multiple level standards, requires more timing and state control, and the process is relatively cumbersome, so a method is needed to solve this kind of problem.

[0005] In addition, it usually takes more than ten seconds to tens of seconds for the CPU to be stable from power on. Only after the power is stable can instructions be sent to the CPU through JTAG to perform boundary scan testing. The speed of conventional CPU power-on boundary scan testing is slow; and for boundary scan testing, all connection networks need to form a testable relationship, such as the test of the normal signal forming a send-receive relationship, the power supply, GND and the effective reading test of the pull-up and pull-down resistor signal level, and the short circuit between the connection network relationships also needs to be tested. These test contents need to be taken into account. Whether the conventional boundary scan test can achieve the purpose of testing everything that should be tested, especially for short circuit testing, needs further consideration. When using the conventional CPU boundary scan test method to solve the inherent connection network test of the motherboard, such as pull-up, pull-down, power supply and GND, false test phenomena will occur, but it cannot intervene to achieve the purpose of effective testing, which is also a problem that needs to be solved urgently. In addition, the CPU is expensive, especially the CPU of the server motherboard. If the boundary scan test of the motherboard cannot get rid of the limitations of the conventional CPU, it will not be able to effectively reduce costs.

[0006] Therefore, the boundary scan test for the above CPU needs to be compatible with multiple level standards and requires more timing and state control. The process is relatively complicated and has technical defects. It is urgent to design and develop a method, system and CPU simulation structure for motherboard boundary scan testing. Summary of the invention

[0007] In order to overcome the shortcomings and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide a method, system and CPU simulation structure for motherboard boundary scan testing, so as to solve the defects of conventional CPU testing, achieve a boundary scan test coverage effect that is better than that of conventional CPUs, and also solve the often neglected short-circuit fault test problem, test reliability, and fast test speed. Moreover, there is no need to consider the power-on, power-on timing and power-on time of the CPU, and all signal transmission, reception and reading are completed through DUMMY. The test effect is completely controlled by the design end of the boundary scan test, with strong compatibility, high security and cost savings.

[0008] The first purpose of the present invention is to provide a method for motherboard boundary scan testing; the second purpose of the present invention is to provide a system for motherboard boundary scan testing; the third purpose is to provide a CPU simulation structure for motherboard boundary scan testing.

[0009] The first object of the present invention is achieved by placing a mainboard to be tested on a jig carrier, and the jig is activated, so that a first connector in the mainboard to be tested is plugged into a second connector in a first simulation test card and a third connector in a second simulation test card respectively;

[0010] A boundary scan controller is provided to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card.

[0011] Furthermore, the method of placing the mainboard to be tested on the fixture carrier and operating the fixture, wherein the first connector in the mainboard to be tested is respectively plugged into the second connector in the first simulation test card and the third connector in the second simulation test card, further comprises:

[0012] Determine whether each type to be tested is short-circuited. If so, execute the next step. Otherwise, reconnect and determine again until each type to be tested is short-circuited.

[0013] Furthermore, the step of performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card by using a boundary scan controller further includes:

[0014] Control the first simulation test card and the second simulation test card to be powered on, and control each pin point connecting the mainboard to be tested and the power supply end to be powered off;

[0015] A boundary scan controller is provided to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, and determine whether there is a short circuit fault in the boundary scan test.

[0016] Furthermore, the step of performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card by using a boundary scan controller further includes:

[0017] Control the first simulation test card and the second simulation test card to be in a power-off state, press down the CPU simulation board, and then control the first simulation test card and the second simulation test card to be in a power-on state, and at the same time, control the power supply of each pin point connected to the mainboard to be tested and the power supply end;

[0018] A boundary scan controller is set up to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, and determine whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

[0019] Furthermore, after the boundary scan controller is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, the method further includes:

[0020] The first simulation test card and the second simulation test card are controlled to be in a power-off state, and each pin point connecting the mainboard to be tested and the power supply end is controlled not to be powered.

[0021] The second object of the present invention is achieved in this way: the system is used to implement the motherboard boundary scan test method; the system includes:

[0022] A plug-in control unit is used to place the mainboard to be tested on the fixture carrier board, and the fixture is activated, and the first connector in the mainboard to be tested is plugged with the second connector in the first simulation test card and the third connector in the second simulation test card respectively;

[0023] The test processing unit is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller.

[0024] Furthermore, the plug-in control unit further includes:

[0025] The first determination module is used to determine whether each type to be tested is short-circuited. If so, the next step is executed; otherwise, the connection is reconnected and the determination is repeated until each type to be tested is short-circuited.

[0026] And / or, the test processing unit further includes:

[0027] A first control module, used for controlling the first simulation test card and the second simulation test card to be in a power-on state, and controlling each pin point connecting the mainboard to be tested and the power supply end to be powered off;

[0028] The first test determination module is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determine whether there is a short circuit fault in the boundary scan test.

[0029] Furthermore, the test processing unit further includes:

[0030] A second control module is used to control the first simulation test card and the second simulation test card to be in a power-off state, and after pressing down the CPU simulation board, control the first simulation test card and the second simulation test card to be in a power-on state, and at the same time, control the power supply of each pin point connecting the mainboard to be tested and the power supply end;

[0031] The second test determination module is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determine whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

[0032] Furthermore, the system also includes: a third control module, which is used to control the first simulation test card and the second simulation test card to be in a power-off state, and control the pin points connecting the mainboard to be tested and the power supply end to not be powered.

[0033] The third object of the present invention is achieved as follows: the CPU simulation structure is used to implement the motherboard boundary scan test method; the CPU simulation structure includes a motherboard to be tested, and a CPU simulation board arranged on the motherboard to be tested; the motherboard to be tested is electrically connected to the power control terminal through a pin point;

[0034] The CPU simulation structure also includes a programmable logic controller for controlling the operating state of each pin point of the power control terminal and acting on the pressure control of the CPU simulation board; the programmable logic controller also realizes signal interaction with the boundary scan controller set in the CPU simulation structure;

[0035] A cascade chain consisting of a first analog test card and a second analog test card is also electrically connected between the mainboard to be tested and the boundary scan controller;

[0036] The CPU simulation structure is also provided with a GND board for realizing a common ground for a boundary scan test system.

[0037] The present invention places a mainboard to be tested on a fixture carrier board and activates the fixture, so that a first connector in the mainboard to be tested is plugged into a second connector in a first simulation test card and a third connector in a second simulation test card respectively; a boundary scan controller is provided to perform a boundary scan test on a cascade chain of the first simulation test card and the second simulation test card, and a system and a CPU simulation structure corresponding to the method can solve the defects of conventional CPU testing, achieve a boundary scan test coverage effect that is better than that of conventional CPUs, and solve the short-circuit fault test problem that is often neglected, with test reliability and fast test speed. Moreover, there is no need to consider the power-on, power-on sequence and power-on time of the CPU, and all signal transmission, reception and reading are completed through DUMMY. The test effect is completely controlled by the design end of the boundary scan test, with strong compatibility and high security. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of a framework of 13 boundary scan test types of a motherboard according to an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a supplementary framework of some types of motherboards to be tested according to an embodiment of the present invention;

[0041] Figure 3 It is a schematic diagram of the framework of a test system for 13 types of boundary scan tests on a conventional motherboard according to an embodiment of the present invention;

[0042] Figure 4 It is a schematic diagram of the framework of test scenario 1 of conventional test types 1 to 4 in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a framework of a test scenario 2 of conventional test types 1 to 4 according to an embodiment of the present invention;

[0044] Figure 6 A schematic diagram of a CPU simulation board and a testable design framework for a motherboard boundary scan test according to an embodiment of the present invention;

[0045] Figure 7 A schematic diagram of a system framework for a motherboard boundary scan test according to an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of a test framework in which DUMMY card 1 intervenes in test types 1 to 6 according to an embodiment of the present invention;

[0047] Fig. 9 The present invention is a flow chart of a method for boundary scanning a motherboard. DETAILED DESCRIPTION

[0048] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0049] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0051] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Secondly, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0052] The present invention will be further described below in conjunction with the accompanying drawings. Figure 1-Figure 7 ,as well as Fig. 9 As shown, the present invention provides a method for motherboard boundary scan testing, the method comprising the steps of:

[0053] S1. Place the motherboard to be tested on the fixture carrier, and activate the fixture. The first connector in the motherboard to be tested is respectively plugged into the second connector in the first simulation test card and the third connector in the second simulation test card. S2. Perform a boundary scan test on the cascade chain of the first simulation test card and the second simulation test card through the set boundary scan controller.

[0054] The method of placing the mainboard to be tested on the fixture carrier and operating the fixture, wherein the first connector in the mainboard to be tested is respectively plugged into the second connector in the first simulation test card and the third connector in the second simulation test card, further comprises: S11, determining whether each type to be tested is short-circuited, if so, executing the next step, otherwise, re-plugging and re-determining until each type to be tested is short-circuited.

[0055] The step of performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a boundary scan controller also includes: S21, controlling the first analog test card and the second analog test card to be powered on, and controlling each pin point connecting the mainboard to be tested and the power supply end to not be powered;

[0056] S22, performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determining whether there is a short circuit fault in the boundary scan test.

[0057] The boundary scan test is performed on the cascade chain of the first analog test card and the second analog test card through the boundary scan controller, and also includes: S23, controlling the first analog test card and the second analog test card to be in a power-off state, pressing down the CPU simulation board, and then controlling the first analog test card and the second analog test card to be in a power-on state, and at the same time, controlling the power supply of each pin point connecting the mainboard to be tested and the power supply end; S24, performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card through the boundary scan controller, and determining whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

[0058] After the boundary scan test is performed on the cascade chain of the first analog test card and the second analog test card through the boundary scan controller, it also includes: S30, controlling the first analog test card and the second analog test card to be in a power-off state, and controlling the pin points connecting the mainboard to be tested and the power supply end to not be powered.

[0059] Specifically, in an embodiment of the present invention, the smallest unit of the boundary scan test is a connection network with the ability to send, receive or read. The connection networks inside the motherboard that need to be boundary scan tested are: the pull-up and pull-down resistors inside the motherboard and the power supply and GND signals connected to the pins of the CPU slot, the direct connection of the CPU slot to the connector to be tested and the direct connection plus an external pull-up or pull-down resistor, the pull-up or pull-down resistor, power supply, and GND inside the motherboard connected to the connector to be tested, and the direct connection of the pins of the CPU slot to the pins inside the motherboard. These connection networks need to be boundary scan tested, covering all connection paths with send-receive paths and the ability to read peripheral level states based on the pins of the CPU slot and peripheral connectors, aiming to comprehensively test the open and short circuit faults that may occur in the above connection networks through boundary scan test technology.

[0060] Combination Figure 1 As shown, the connection networks to be tested are summarized into 13 types to be tested, which are: Type 1 to be tested: the connection network from the pull-up resistor RA1 of the motherboard to the power supply VA1, and the other foot of RA1 is connected to the pin a1 of the CPU card slot. Type 2 to be tested: the connection network from the power supply VA2 of the motherboard to the pin a2 of the CPU card slot. Type 3 to be tested: the connection network from the GND of the motherboard to the pin a3 of the CPU card slot. Type 4 to be tested: the connection network from the internal pull-down resistor RA2 of the motherboard to the GND, and the other foot of RA2 is connected to the pin a4 of the CPU card slot. Type 5 to be tested: the direct connection path from the pin a5 of the motherboard CPU card slot to the A5 pin of the connector 1, and the connection network from the pull-up resistor RA3 to the power supply VA3 through the direct connection path; Type 6 to be tested: the direct connection path from the pin a6 of the motherboard CPU card slot to the A6 pin of the connector 1, and the connection network from the pull-down resistor RA4 to the power supply VA4 through the direct connection path. Type 7 to be tested: the connection network from the power supply VA5 of the motherboard to the A7 pin of the connector 1. Type 8 to be tested: The pull-up resistor RA5 of the motherboard is connected to the power supply VA4, and the other pin of RA5 is connected to the connection network of the A8 pin of the connector 1. Type 9 to be tested: The pull-down resistor RA6 of the motherboard is connected to the GND, and the other pin of RA6 is connected to the connection network of the A9 pin of the connector 1. Type 10 to be tested: The GND of the motherboard is connected to the connection network of the A10 pin of the connector 1. Type 11 to be tested: The pin a11 of the CPU card slot is connected to the connection network of the A11 pin of the connector 1. Type 12 to be tested: The pin a12 of the CPU card slot is connected to the capacitor C12, and the other pin of C12 is connected to the connection network of the A12 pin of the connector 1. Type 13 to be tested: The pin a13 of the CPU card slot is connected to the connection network of the pin point A13 inside the motherboard.

[0061] Combination Figure 1 and Figure 2As shown, the test type 11 is divided into two scenarios. Scenario 1 is a pure connection between the pin a11_1 of the CPU card slot and the pin A11_1 of the connector 1, which is called the test type 11_1. Scenario 2 is that the pin a11_2 of the CPU card slot is connected to one leg of the resistor Ra, and the other leg of Ra is connected to the pin A11_2 of the connector 1, which is called the test type 11_2. Ra is usually a small resistor. The test is completed through the IEEE 1149.1 protocol and does not affect the signal transmission and reception. The test contents of the test type 11_1 and the test type 11_2 are the same, so in Figure 1 There is not too much classification in the following, and the subsequent processing methods are the same. Figure 1 and Figure 2 As shown, the test type a12 is also divided into two scenarios. Scenario 1 is to connect a capacitor C12_1 in series between the pin a12_1 of the CPU card slot and the pin A12_1 of the connector to be tested, which is called the test type 12_1. Scenario 2 is to connect at least two capacitors in series between the pin a12_2 of the CPU card slot and the pin A12_2 of the connector to be tested, which is called the test type 12_2. The test effects of these two types are also the same. The test is completed through the IEEE 1149.6 boundary scan protocol, and it does not affect the sending and receiving of signals. Therefore, in Figure 1 There is not too much classification.

[0062] Combination Figures 1 to 3 As shown, the types to be tested 1 to 4 are tested by IO_a1 to IO_a4 of the CPU respectively, and the boundary scan chip (BS chip) and the chips with JTAG interface are all BS chips, such as CPU, FPGA, ARM, PCH, CPLD, etc.

[0063] In conventional testing, the IO_a5 to a7 of the motherboard's CPU pass through the motherboard's connector 1 and the DUMMY card's connector 2, and finally connect to the DUMMY card's BS chip IO bundle. Figure 3 The JTAG of the CPU and the BS chip of the DUMMY card are cascaded together to control the JTAG of the boundary scan controller, and the signal is correctly sent or read between the CPU of the motherboard to be tested and the IO of the DUMMY card, thereby completing the boundary scan test of the types 5, 6 and 11 to be tested.

[0064] Types 7 to 10 to be tested are connected to connector 1 of the mainboard, docked with connector 2 of the DUMMY card, and then connected to each IO of the BS chip, so as to achieve correct sending, receiving or reading test for types 7 to 10 to be tested through each IO of the DUMMY card.

[0065] Type 12 to be tested is divided into type 12.1 to be tested and type 12.2 to be tested. By shorting the b_8 and b_9 pins of connector 2 through the DUMMY card, the sending and receiving test can be completed between IO_a12.1 and IO_a12.1 of the CPU. IO_a12.1 and IO_a12.1 of the CPU are AC pins with IEEE 1149.6 protocol, one is the sending pin and the other is the receiving pin. Usually, the sending and receiving pins of the chip of IEEE 1149.6 protocol exist in pairs, and one sending pin can match one receiving pin.

[0066] In addition, in the connection network where IO_a12.1 and IO_a12.1 of the CPU are short-circuited, a capacitor is connected in series in the middle. Only the AC pin that complies with the IEEE 1149.6 protocol can complete signal transmission and reception. The purpose of short-circuiting is to be able to detect the open circuit fault of the complete connection path (connection network) after IO_a12.1 and IO_a12.1 are short-circuited.

[0067] This is a relatively common test method of BSI at present. By applying a short-circuit condition to the test type 12, the IO_a12.1 and IO_a12.1 of the CPU of the motherboard to be tested can realize the self-test of sending and receiving. For example, IO_a12.1 is used as the sender, and the data sent is 0110, while IO_a12.2 is used as the receiver. If 0110 is received, it means the test has passed.

[0068] A careful study found that the above conventional tests actually have defects. If the actual automated production process Figure 3 As shown, when a short circuit occurs between A12.1 and A12.2 of the mainboard, and b_8 and b_9 of the DUMMY card are short-circuited, even if the transceiver test between IO_a12.1 and IO_a12.1 of the CPU passes (PASS), it cannot be ruled out that there is no fault. Therefore, the test method of short-circuiting b_8 and b_9 of the DUMMY card has its defects and is not reliable enough. Such problems need to be solved urgently.

[0069] Combination Figure 3 As shown, test types 1 to 4 are tested through the CPU's own IO resources IO_a1 to IO_a4, while test types 7 to 10 are tested through the IO resources of the DUMMY card. Engineers design DUMMY cards in a targeted manner to achieve the purpose of boundary scan testing of the motherboard. Test types 7 to 10 can achieve the purpose of effective testing through reasonable design of the DUMMY card, while test types 1 to 4 are fixed. This is because the motherboard and the CPU are both determined. When test types 1 to 4 cannot be effectively tested, there is nothing we can do. Such problems need to be solved urgently.

[0070] Combination Figure 1 and Figure 4As shown, Figure 4 and Figure 1 The test types correspond one to one, combined with Figure 4 As shown, when IO_a1 to IO_a4 of the CPU are in weak pull-up mode, the pull-up resistors R1.1 to R1.4 are respectively connected to the motherboard power supply Va1 to Va4. Figure 4 , the four test types are: Test type 1, pull-up resistor RA1 to motherboard power VA1, and the other leg of resistor RA1 is connected to CPU IO_a1; Test type 2, motherboard power VA2 is connected to CPU IO_a2; Test type 3: motherboard GND is connected to CPU IO_a3; Test type 4, motherboard pull-down resistor RA2 to GND, and the other leg of resistor RA2 is connected to CPU IO_a4. Figure 4 , the test types 1 to 4 are read and tested through the CPU pins IO_a1 to IO_a4 respectively, but the read tests of the test types 1 and 2 are affected by the weak pull-up inside the CPU IO_a1 and IO_a2 respectively. Regardless of whether the connection of the test type 1 and the test type 2 has an open circuit fault, the CPU IO_a1 and IO_a2 will read the high level 1. Therefore, the high level signal 1 of the CPU IO_a1 and IO_a2 is not a valid test signal. Even if the test passes (PASS), it cannot indicate whether the test type 1 and the test type 2 have an open circuit fault. This is the false test phenomenon. In summary, in scenario 1, the conventional CPU cannot effectively test the test type 1 and the test type 2.

[0071] Combination Figure 1 and Figure 5 As shown, Figure 5 and Figure 1 The test types also correspond one to one, combined with Figure 5 As shown, IO_a5 to IO_a8 of the CPU are in weak pull-down mode, which are weak pull-downs composed of GND and R2.1 to R2.4. Figure 4 and Figure 5 , Figure 5 The 4 test types and Figure 4 Same. Figure 5, the test types 1 to 4 are also read and tested through the CPU pins IO_a1 to IO_a4, but the read tests of the test types 3 and 4 are affected by the weak pull-down of the CPU's IO_a7 and IO_a8. Regardless of whether the connection of the test types 3 and 4 has an open circuit fault, the CPU's IO_a7 and IO_a8 will read a low level 0. Therefore, the high level signal 0 of IO_a7 and IO_a8 is not a valid test signal. Even if the test passes, it cannot indicate whether the test types 3 and 4 have an open circuit fault. This is also a false test phenomenon. In summary, in scenario 2, the conventional CPU cannot effectively test the test types 3 and 4.

[0072] Combination Figure 4 and Figure 5 It can be seen that the CPU is a chip with boundary scan test capability. The CPU works in Figure 4 The situation is common. Figure 5 There are few scenarios, but we cannot ignore them. The CPU itself has the above defects in the boundary scan test of the motherboard. In the face of these defects, we cannot interfere with the motherboard test, because the motherboard is designed according to the actual functional requirements of the customer, and the CPU program is also designed according to the functional needs of the motherboard, which are fixed. Therefore, the above motherboard boundary scan test defects are common.

[0073] For engineers, what they need to do is to achieve the goal of testing as much as possible through design intervention of the DUMMY card. However, conventional testing methods are powerless against defects 1 of types 1 to 4.

[0074] like Figure 6 As shown, the CPU simulation board will replace the CPU to implement boundary scan testing. The pins of the CPU simulation board are the same as those of the CPU, and correspond one-to-one with the pins of the motherboard CPU slot. However, the testing concepts of the CPU simulation board and the CPU are different. The CPU provides pins with sending and receiving capabilities for testing, while the CPU simulation board is a pure PCB board, so there are no pins with the ability to send and receive data. The principle of the CPU simulation board boundary scan test is to perform pure PCB routing inside the CPU simulation board, short-circuit the pins of the CPU simulation board, and after the pins of the CPU simulation board are connected to the pins of the CPU slot, it is equivalent to short-circuiting the pins of the motherboard CPU slot accordingly, looping all types to be tested back to connector 1 of the motherboard or leading out through pin points, and all tests of all types to be tested are implemented through the IO resources of the DUMMY card.

[0075] Now, combined with the test type, the design method is explained in detail, such as Figure 6As shown, on the CPU simulation board, pins a1 to a4 corresponding to the types 1 to 4 to be tested are respectively short-connected to pins a11.6 to a11.3 corresponding to the types 11.6 to 11.3 to be tested, and then connected to pins A11.6 to A11.3 of connector 1 of the mainboard, and then connected to b12 to b9 of connector 2 of DUMMY card 1, and finally connected to the IO bundle of DUMMY card 1, so as to read the effective level of types 1 to 4 to be tested through the IO corresponding to pins b12 to b9 of the connector of DUMMY card 1, and realize the open circuit fault coverage test of types 1 to 4 to be tested and types 11.6 to 11.3 to be tested. Through the above operations, the open circuit fault test of types 1 to 4 to be tested originally through the CPU can be completed through the external DUMMY card 1 of the mainboard, and types 11.6 to 11.3 to be tested are tested together.

[0076] On the CPU simulation board, the pins a5 and a6 corresponding to the types 5 and 6 to be tested are connected to the pins a11.2 and a11.1 corresponding to the types 11.2 and 11.1 to be tested, respectively, and then connected to the pins A11.2 and A11.1 of the connector 1 of the motherboard, and then connected to the b8 and b7 of the connector 2 of the DUMMY card 1, and finally connected to the IO bundle of the DUMMY card 1. In addition, the types 5 and 6 to be tested are connected to the b1 and b2 of the connector 2 of the DUYMMY card through the A5 and A6 of the motherboard connector 1, and then connected to DUMMY card 1 BS chip, thereby realizing a complete testable path from type 5 to type 11.2, and a complete testable path from type 5 to type 11.1. The correct level transmission and reception are completed through the DUMMY card 1 connector b1 and b8 corresponding to the BS chip IO pins, and the correct level transmission and reception are completed through the DUMMY card 1 connector b2 and b7 corresponding to the BS chip IO pins. Open circuit fault tests are performed on type 5 and type 11.2, as well as type 6 and type 11.1.

[0077] Compared with type 11, type 5 and type 6 have additional pull-up and pull-down on the direct path. It is necessary not only to test the direct path, but also to cover the pull-up and pull-down of the signal as much as possible. The test method will be further explained later.

[0078] On the motherboard, the types to be tested 7 to 10 are connected to the A7 to A10 pins of the connector 1 of the motherboard to be tested, and further connected to the b3 to b6 pins of the connector 2 of the DUMMY card 1, and finally connected to the IO bundle of the BS chip of the DUMMY card 1. The valid level is read through the IO corresponding to the b3 to b6 pins of the connector 2 of the DUMMY card 1, so as to realize the test of the types to be tested 7 to 10.

[0079] Types 7 to 10 are the connection relationship network inside the motherboard and have nothing to do with the CPU. Therefore, there is no need to short the through pin of type 11 to be tested to achieve a loop like type 1 to be tested 4.

[0080] On the CPU simulation board, the pin a11.7 corresponding to the type to be tested 11.7 is connected to the pin a11.8 corresponding to the type to be tested 11.8, wherein the a11.7 and a11.8 pins of the CPU simulation board are respectively connected to the A11.7 and A11.8 pins of the connector 1 of the motherboard, and then respectively connected to the b13 and b14 pins of the connector 2 of the DUMMY card 1, and finally connected to the IO bundle of the BS chip of the DUMMY card 1, and the BS chip IO corresponding to the b13 and b14 pins of the connector 2 of the DUMMY card 1 can realize level transmission and reception, and finally achieve the purpose of open circuit test of the type to be tested 11.7 and the type to be tested 11.8;

[0081] Types 11.9 to 11.11 to be tested correspond to pins a11.9 to a11.11 of the CPU simulation board respectively. Pins a11.9 to a11.11 are connected together through the CPU simulation board. Pins a11.9 to a11.11 are connected to pins A11.9 to A11.11 of motherboard connector 1 respectively, and then connected to pins b15 to b17 of connector 2 of DUMMY card 1, and finally connected to the IO bundle of the BS chip of DUMMY card 1. The boundary scan transceiver test is completed between pins b15 to b17 (one pin is set to send, and the other two pins are set to receive), so that coverage test of types 11.9 to 11.11 to be tested can be achieved.

[0082] Type 13 to be tested includes type 13.1 to type 13.5, which correspond to pins a13.1 to a13.5 of the CPU simulation board respectively. On the simulation board, a13.1 and a13.2 are short-circuited, and a13.3 to a13.5 are also short-circuited. Pins a13.1 to a13.5 are connected to pins A13.1 to A13.5 of the mainboard respectively. On the test fixture, pins A13.1 to A13.5 of the mainboard are lowered and transferred to DUMMY card 1. Pins b18 to b22 of connector 2 are ultimately connected to the IO bundle of DUMMY card 1. On the one hand, data can be sent and received between the IOs of DUMMY card 1 corresponding to b18 and b19 to implement open circuit tests of types 13.1 to be tested and 13.2 to be tested. On the other hand, data can be sent and received between the IOs of DUMMY card 1 corresponding to b20 to b22 (where 1 IO sends and 2 IOs receive) to implement open circuit tests of types 13.3 to be tested and 13.5 to be tested.

[0083] Combination Figure 3 and Figure 6As shown, the type to be tested 11 is Figure 5 It is divided into test types 11.1 to 11.13, among which, test types 11.1 to 11.11 clearly show the design of the CPU simulation board of the IEEE 1149.1 protocol part. DUMMY card 1 complies with the BS chip reference model of the IEEE 1149.1 protocol: 10M25DAF484I7G. Test types 11.12 and 11.13 can also be short-circuited back to the path test with capacitors in series. Test type 11 is widely used and has the largest number of connections on the motherboard under test. Test type 11 is very important and flexible in the design of the simulation board.

[0084] The test type 12 is divided into test types 12.1 to 12.6. The CPU simulation board pins a12.1 and a12.2 corresponding to the test types 12.1 and 12.2 are connected to the CPU simulation board pins a11.12 and a11.13 corresponding to the test types 11.13 and 11.12, respectively. The CPU simulation board pins a12.1 and a12.2 are connected to one leg of the motherboard capacitors C12.1 and C12.2, respectively. The other legs of C12.1 and C12.2 are connected to the A12.1 and A12.2 pins of the motherboard connector 1, respectively, and then connected to the C3 and C4 pins of the DUMMY card 2 connector 3, and finally connected. To the IO bundle of boundary scan chip 2 of DUMMY card 2, in addition, pins a11.12 and a11.13 of the CPU simulation board are respectively connected to A11.12 and A11.13 of motherboard connector 1, and then connected to C1 and C2 pins of DUMMY card 2 connector, and finally connected to the IO bundle of DUMMY card 2 boundary scan chip, the IO corresponding to the C1 and C2 pins of DUMMY card 2 connector respectively forms a transceiver relationship with the IO corresponding to the C3 and C4 pins of DUMMY card 2 connector, thereby realizing the open circuit test of the test type 12.1 and the test type 12.2 and the test type 11.12 and the test type 11.13, and the test type 12.3 The simulation board pins a12.3 and a12.4 corresponding to the type to be tested 12.4 are short-circuited, the simulation board pins a12.3 and a12.4 are connected to one foot of the capacitors C12.3 and C12.4 respectively, the other foot of the capacitors C12.3 and C12.4 are connected to the A12.3 and A12.4 pins of the motherboard connector 1, and then connected to the C5 and C6 pins of the DUMMY card 2 connector 3 respectively, and finally connected to the BS chip IO bundle of the DUMMY card 2. The IO corresponding to the C5 and C6 pins of the DUMMY card 2 connector forms a sending and receiving relationship, thereby realizing the open circuit test of the types to be tested 12.3 and 12.4, and the types to be tested 12.5 and 12.4. .6, the simulation board pins a12.5 and a12.6 corresponding to the short circuit, the simulation board pins a12.5 and a12.6 are connected to one leg of the capacitors C12.5 and C12.6 respectively, the other leg of the capacitors C12.5 and C12.6 are connected to the A12.5 and A12.6 pins of the motherboard connector 1 respectively, and then connected to the C7 and C8 pins of the DUMMY card 2 connector 3 respectively, and finally connected to the BS chip IO bundle of the DUMMY card 2, the IO corresponding to the C7 and C8 pins of the DUMMY card 2 connector form a sending and receiving relationship, thereby realizing the open circuit test of the type 12.5 to be tested and the type 12.6 to be tested; this connection path test of the series capacitor is a test with IEEE 1149.6 protocol chip (reference model: SCAN15MB200TSQ / NOPB) DUMMY card 2 is completed. In actual application, the transmission and reception of this type of test are in the form of differential pairs and exist in pairs. Specifically, the transmission part is divided into the positive end of the transmission and the negative end of the transmission, which are represented by TX_P and TX_N respectively, and the receiving part is divided into the positive end of the reception and the negative end of the reception, which are represented by RX_P and RX_N respectively. Figure 6 The test types 12.3 and 12.4, as well as the test types 12.5 and 12.6 simulate this type of test. Since the signal transmission and reception are all handed over to the DUMMY card 2 end, the design of the transmission and reception direction is also very flexible.

[0085] The role of the test type 11 in the CPU simulation board is to assist the test of the test types 1 to 4. The test types 11 can also be short-circuited to achieve loop testing. The test type 11 can also participate in the test of the test type 12, which only increases the length of the line and does not affect the signal reception and transmission. In short, the design of the CPU simulation board is relatively flexible. The above open circuit fault test coverage is achieved through the CPU simulation board, and the short circuit fault design that is often overlooked must also be considered.

[0086] Combination Figure 6 and Figure 7 As shown, this block diagram simplifies Figure 6 , and added power control, programmable logic controller control, and boundary scan controller control content to form a comprehensive system block diagram. Among them, the functions of the programmable logic controller are: unified control of power supplies VA1 to VA5, and power control of the DUMMY card, the purpose is to ensure power-free operation during the docking process between the motherboard and the DUMMY card. The programmable logic controller also acts on the fixture motion control, the motherboard and DUMMY card docking control, and the boundary scan controller to achieve signal interaction. It also acts on the pressure control of the CPU simulation board. A series of GND pin points are selected on the motherboard, and the boundary scan test system is connected through the GND board. The common GND is realized, and the DUMMY card 1 and DUMMY card 2 are connected to form a cascade chain (daisy chain or serial chain, JTAG1 and JTAG2 can also be independently connected to the boundary scan controller), and finally connected to the boundary scan controller. Figure 6 All test types are implemented by manipulating the JTAG cascade chain.

[0087] Combination Figure 3 and 6 and Figure 7As shown in the figure, all open circuit tests of the tested types have been considered above, but the short circuit loop of the CPU simulation board itself will become a hiding place for the short circuit fault. In other words, when the short circuit of the CPU simulation board and the short circuit fault inside the motherboard exist at the same time, the test will still be PASS, and the short circuit fault inside the motherboard will not be detected (same Figure 3 The short-circuit fault described cannot be tested). To solve this problem, the following method is adopted based on the open-circuit fault: Step 1, put the mainboard into the fixture carrier, the fixture moves, the connector 1 of the mainboard is plugged into the connector 2 of DUMMY card 1 and the connector 3 of DUMMY card 2, and the simulation board is not pressed down temporarily to ensure that the types to be tested 1 to 13 are not short-circuited to the types to be tested; Step 2, control DUMMY card 1 and DUMMY card 2 to be powered on, while the pins VA1 to VA5 on the mainboard end are not powered; Step 3, boundary scan the cascade chain of DUMMY card 1 and DUMMY card 2 through the boundary scan controller Scan test, the test environment at this time is without CPU simulation board, the purpose is to do a comprehensive short-circuit scan test on the motherboard to ensure that in the absence of CPU simulation board, whether there is a short-circuit fault can be detected as much as possible; the content of the test is short-circuit fault association test (reference patent number: 2024114731468, a method and system for boundary scan test and effective positioning of short-circuit fault), which will not be elaborated here; in order to ensure the safety of the test, the IO corresponding to the test type 7 and the test type 10 does not participate in the spontaneous transmission and reception of the signal. Of course, if there are other test types and test types 7 and 10 that are short-circuited, there will also be a fault prompt. Step 4, control DUMMY card 1 and DUMMY card 2 to power off, press down the CPU simulation board, and then control DUMMY card 1 and DUMMY card 2 to power on, and at the same time control the VA1 to VA5 switches to close to ensure that the pin points VA1 to VA5 on the motherboard end are powered on. Step 5: Perform boundary scan test on the cascade chain of DUMMY card 1 and DUMMY card 2 through the boundary scan controller. The test environment at this time has a CPU simulation board, and the purpose is to conduct a comprehensive open circuit fault test on the motherboard; the content of the open circuit fault test includes: signal transmission and reception between IO, pull-up, pull-down, power supply, and GND level reading, and realize all types of open circuit fault tests to be tested. Step 6: After the test is completed, DUMMY card 1 and DUMMY card 2 are powered off, and the pin points VA1 to VA5 on the motherboard end are powered off, and the test is exited, waiting for the next motherboard test.

[0088] On the test fixture, the open-short circuit fault test is completed through the above test steps.

[0089] Considering from the perspective of fixture, combined with Figure 6As shown, connector 1 of the motherboard and connectors 2 and 3 of the DUMMY card in the block diagram refer to a general term for a type of connector. During the actual testing process, the motherboard has many connectors to be tested. Connector 1 of the motherboard includes: MCIO, PCIE, SLIMLINESAS, DDR, OCP, USB, RISER, etc. These connectors to be tested of the motherboard must be connected to connector 2 and connector 3 of the DUMMY card through an adapter card. The connectors of connector 2 and connector 3 may also include many connectors. Connector 2 and connector 3 represent the general term for adapters, which are usually a combination of multiple connectors and / or adapter cables, which are determined comprehensively based on docking requirements and design convenience.

[0090] like Figure 8 As shown in the figure, the BS chip IO ports of DUMMY card 1 are different IO ports, namely IO_i1 to IO_i8, combined with Figures 6 to 8 As shown, the short circuit of the CPU simulation board is Figure 6 , I won’t repeat the description here. Figure 6 The circled portion in is the portion of DUMMY card 1 that requires intervention testing, wherein the tests for test types 7 to 10 are the same as those for test types 1 to 4, respectively, and therefore test types 7 to 10 are omitted here.

[0091] For the BS chip of DUMMY card 1, its datesheet is analyzed. By burning the IO configuration program on the chip, the pull-up mode of the internal IO is disabled to ensure that the default state of IO_i1 to IO_i8 is high impedance. In the high impedance state, the level read by IO_i1 to IO_i8 is unknown. During the test, all 0 or all 1 can still be received. The pull-up, pull-down, power supply or GND levels of the test types 1 to 6 are read through IO_i1 to IO_i8, and false tests may still occur. This is because the read pull-up, pull-down power supply and GND states are all 1 or all 0, which may still be non-valid values ​​read in the high impedance state. The measured BS chip model is; 10M25DAF484I7G. The value of high impedance read is all 1, so the high level 1 of the pull-up and power supply of the test types 1, 2, and 7 is all false test, which is unacceptable during testing.

[0092] In order to achieve the purpose of effective testing of test types 1 to 6, it is necessary to connect a pull-up resistor to the power supply or a pull-down resistor to GND at the IO of the DUMMY card 1 end, as follows:

[0093] To achieve effective testing of the type 1 to be tested, the BS chip IO_i8 needs to detect the effective high level 1 from the pull-up resistor RA1 to the power supply V1. Therefore, a pull-down resistor Rb6 is connected to GND at the IO_i8 pin of the DUMMY card 1. Its effect is that when the type 1 to be tested is shorted to the entire connection network of the type 11.6 to be tested and an open circuit fault occurs, due to the effect of the parallel pull-down resistor Rb6 to GND, an effective low level 0 can be detected. When the type 1 to be tested is shorted to the entire connection network of the type 11.6 to be tested is normal, a high level 1 from the pull-up resistor RA1 to the power supply V1 can be detected. It is necessary to ensure that the detected high level 1 is valid and the following conditions must be met. Under normal circumstances, the condition for maintaining a high level is that the Rb6 voltage division is sufficient. By looking up the datesheet of BS chip 10M25DAF484I7G, we can get two parameters, one is IO level VCCIO, the other is high level minimum threshold VIH_min. To ensure that R65 can identify high level 1 under normal circumstances, it needs to satisfy the inequality: Rb6 / (RA1+Rb6)>VCCIO×VIH_min. By looking up the datesheet of BS chip model 10M25DAF484I7G, we know that when VCCIO=1.0V, VIH_min=0.65. Assuming that the pull-up resistor RA1 of type 1 to be tested is 2kΩ, we get: Rb6>3.714kΩ. If the pull-down resistor Rb6=10kΩ is removed, it can be achieved.

[0094] When the above conditions are met, an effective boundary scan test of the entire connection network of the type to be tested 1 shorted to the type to be tested 11.6 can be achieved; to achieve an effective test of the type to be tested 2, the BS chip IO_i7 needs to detect the effective high level 1 of the power supply V2, so a pull-down resistor Rb5 is connected to GND at the IO_i7 pin of the DUMMY card 1. Its effect is that when the entire connection network of the type to be tested 2 shorted to the type to be tested 11.5 has an open circuit fault, due to the effect of the parallel pull-down resistor Rb5 to GND, an effective low level 0 can be detected; when the entire connection network of the type to be tested 1 shorted to the type to be tested 11.5 is normal, the power supply V To achieve the effective high level 1 of 2, you only need to connect a pull-down resistor Rb5 to GND at the IO_i7 pin to complete the effective test of type 2 to be tested. The value of the pull-down resistor Rb5 is relatively flexible, such as 20kΩ. To achieve the effective test of type 3 to be tested, the BS chip IO_i6 needs to detect the effective low level 0 of GND. Therefore, a pull-up resistor Rb4 is connected to the power supply Vb3 at the IO_i6 pin of the DUMMY card 1. Its effect is that when the entire connection network of type 3 to be tested and type 11.4 to be tested is short-circuited and an open circuit fault occurs, due to the effect of the pull-up resistor Rb4 to the power supply Vb4, a valid high level 1 can be detected. When type 3 to be tested is When the connection network with the type to be tested 11.4 is normal, the effective low level 0 of GND can be detected. It is only necessary to connect a pull-up resistor Rb4 to the power supply Vb4 at the IO_i6 pin to complete the effective test of the type to be tested 3. The value of the pull-up resistor Rb4 is relatively flexible, such as 20kΩ. To achieve the effective test of the type to be tested 4, the BS chip IO_i5 needs to detect the effective high level 0 of the pull-down resistor RA2 to GND. Therefore, a pull-up resistor Rb3 is connected to the power supply Vb2 at the IO_i5 pin of the DUMMY card 1. Its effect is that when the type to be tested 4 is shorted to the entire connection network of the type to be tested 11.3 and an open circuit fault occurs, due to the parallel pull-up resistor The function of pulling resistor Rb3 to power supply Vb2 is to detect a valid high level 1. When the entire connection network of the type 4 to be tested is shorted to the type 11.3 to be tested, the low level 0 of the pull-down resistor RA2 to GND is normal. It is necessary to ensure that the detected high level 0 is valid and the following conditions must be met. Under normal circumstances, the condition for maintaining a low level is that the RA2 voltage divider is small enough. Looking up the datesheet of BS chip 10M25DAF484I7G can get another parameter, the low level maximum threshold VIL_max. To ensure that R65 can identify a high level 1 under normal circumstances, the inequality must be satisfied: RA2 / (RA2+Rb3) <VCCIO×VIL_max,

[0095] By consulting the datesheet of the BS chip model 10M25DAF484I7G, it is known that when VCCIO=1.0V, VIH_max=0.35. Assuming that the pull-down resistor RA2 of the type 4 to be tested is 10kΩ, it is obtained that: the pull-up resistor Rb3>18.571kΩ. If the pull-up resistor Rb3=50kΩ, it can be achieved.

[0096] When the above conditions are met, effective boundary scan testing of the entire connection network from type 4 to type 11.3 can be achieved;

[0097] Two tests are required for the test types 5 and 6 to achieve the purpose of testing as much as possible. One test is to test the direct connection path from IO_i1 to IO_i4 for the test type 5. The test method is to achieve correct level transmission and reception between the two IOs IO_i1 and IO_i4. For the test type 6, the direct connection path from IO_i2 to IO_i3 is required to be tested. The test method is to achieve correct level transmission and reception between the two IOs IO_i2 and IO_i3. Another test is to achieve as much as possible the pull-up resistor RA3 of the test type 5 to the power supply V3 and the pull-down resistor RA4 of the test type 6 to GND to achieve effective testing of the test type 5. The BS chip IO_i1 or IO_i4 can detect the effective high level 1 from the pull-up resistor RA3 to the power supply V3, so a pull-down resistor RA3 is connected to the IO_i1 pin of the DUMMY card 1. The resistor Rb1 is connected to GND. Its effect is that when the entire connection network of the type to be tested 5 is shorted to the type to be tested 11.2 and an open circuit fault occurs, due to the effect of the parallel pull-down resistor Rb1 to GND, a valid low level 0 can be detected. When the entire connection network of the type to be tested 5 is shorted to the type to be tested 11.1 is normal, a high level 1 from the pull-up resistor RA3 to the power supply V3 can be detected. It is necessary to ensure that the detected high level 1 is valid and the following conditions must be met. Under normal circumstances, the condition for maintaining a high level is that the Rb1 voltage is sufficiently divided, and the inequality must be satisfied: Rb1 / (RA3+Rb1)>VCCIO×VIH_min. When VCCIO=1.0V, assuming that the pull-up resistor RA3 of the type to be tested 5 is 47kΩ, the pull-down resistor Rb1>87.286kΩ is obtained. If the pull-down resistor Rb1=100kΩ, it can be achieved.

[0098] When the above conditions are met, an effective boundary scan test of the entire connection network from type 5 to type 11.2 can be achieved;

[0099] To achieve an effective test for the DUT type 6, the BS chip's IO_i2 or IO_i3 needs to detect a valid high level 0 of the pull-down resistor RA4 to GND. Therefore, a pull-up resistor Rb2 is connected to the power supply Vb1 at the IO_i2 pin of the DUMMY card 1. Its effect is that when there is an open-circuit fault in the entire connection network where the DUT type 6 is shorted to the DUT type 11.1, due to the action of the pull-up resistor Rb2 connected to the power supply Vb1, a valid high level 1 can be detected. When the entire connection network where the DUT type 6 is shorted to the DUT type 11.1 is normal, a low level 0 of the pull-down resistor RA4 to GND can be detected. To ensure the detected high level 0 is valid, the following conditions need to be met. Under normal circumstances, the condition for maintaining a low level is that the voltage division of RA4 is small enough, and the inequality needs to be satisfied: RA4 / (RA4 + Rb2) < VCCIO × VIL_max. When VCCIO = 1.0V and assuming the pull-down resistor RA4 of the DUT type 6 is 1kΩ, it is obtained that: the pull-up resistor Rb2 > 1.857kΩ. If the pull-up resistor Rb2 = 4.7kΩ is taken, it can be achieved.

[0100] After the above conditions are met, an effective boundary scan test for the entire connection network where the DUT type 6 is shorted to the DUT type 11.1 can be achieved.

[0101] The boundary scan test of a conventional main board depends relatively much on the CPU. The CPU needs to consider different supply voltages, and also needs to consider the power-on timing sequence. It also needs to control the mode pins to enter the boundary scan test state. In addition, the CPU is expensive and the test time is long. For the design of the CPU emulation board, adding pull-up and pull-down resistors at the IO of the DUMMY card 1 to interfere with the boundary scan test, and through the unified test of the DUMMY card 1, the test defects of the DUT types 1 to 4 are solved to achieve the purpose of being measurable. In addition, a comprehensive coverage test is carried out on the through-connection and the pull-up and pull-down resistors of the through-connection for the DUT types 5 and 6, avoiding the interference of the pull-up and pull-down resistors in the initial state of the CPU; the intervention means for the DUT types 1 to 6 to be measurable are not necessarily adding pull-up and pull-down resistors at the IO of the DUMMY card 1, and can also achieve the test purpose through means such as using an operational amplifier to enhance the driving ability or using a comparator to complete the level conversion, etc., and all can be completed through the DUMMY card 1, with flexible selectivity.

[0102] Combined with Figures 1 to 8As shown in the figure, the design of the CPU simulation board realizes that VA1 to VA5 are powered by the same power supply, keeps the IO level unified, and the power supply is the same, ensuring VCCIO=VA1=VA2=VA3=VA4=VA5. The test of the IEEE 1149.1 protocol part is assigned to DUMMY card 1. The unified IO level standard of DUMMY card 1 is completely determined by the boundary scan design end. In order to ensure the test safety and reduce power consumption, DUMMY card 1 can be tested with a lower IO level, such as: 1.0V, which is impossible for conventional CPU boundary scan tests; in addition, the test of the IEEE 1149.6 part is assigned to DUMMY card 2, which is completed by Figure 6 It can be seen that the IO levels of DUMMY card 2 and DUMMY card 1 are determined by the internal BS chip and are independently set without affecting each other.

[0103] In addition, regarding the cascade of DUMMY card 1 and DUMMY card 2, the BS chip model of DUMMY card 1 is selected as: 10M25DAF484I7G, and the BS chip model of DUMMY card 2 is selected as: SCAN15MB200TSQ / NOPB. According to the datesheet, the JTAG level of DUMMY card 1 and DUMMY card 2 is 3.3V (JTAG level and IO level are two levels), so the JTAG level can be unified to achieve cascade; when the JTAG level is inconsistent, it can also be achieved through external level conversion;

[0104] The CPU simulation board is a pure PCB board. After the docking is ready, the DUMMY card 1 is powered on within 1 second, and the boundary scan test state can be quickly entered, saving test time. In the actual application process, there are a large number of books of types 1 to 13 to be tested. On the simulation board, short-circuit design is performed according to the classification method of the present invention. The finally designed CPU simulation board will be a pure PCB board without components. Its pins are the same as those of conventional CPUs, which are BGA packages and can be pressed down like conventional CPUs. The design of the CPU simulation board is a brand-new boundary scan test mode of the motherboard to be tested, which solves the defects of conventional CPU tests and achieves a boundary scan test coverage effect that is better than that of conventional CPUs. It also solves the short-circuit fault test problem that is often overlooked, and has test reliability and fast test speed. There is no need to consider the power-on, power-on sequence and power-on time of the CPU. All signal transmission, reception and reading are completed through DUMMY. The test effect is completely controlled by the design end of the boundary scan test, with strong compatibility, high security and cost saving.

[0105] To achieve the above purpose, Fig. 9As shown, the present invention also provides a system for motherboard boundary scan testing, and the system is used to implement the described method for motherboard boundary scan testing; the system includes: a plug-in control unit, used to place the motherboard to be tested on a fixture carrier, and the fixture moves, and the first connector in the motherboard to be tested is respectively plugged with the second connector in the first simulation test card and the third connector in the second simulation test card; a test processing unit, used to perform a boundary scan test on the cascade chain of the first simulation test card and the second simulation test card through a set boundary scan controller.

[0106] The plug control unit further includes: a first determination module, used to determine whether each type to be tested is short-circuited, if so, execute the next step, otherwise, re-plug and re-determine until each type to be tested is short-circuited;

[0107] And / or, the test processing unit also includes: a first control module, used to control the first analog test card and the second analog test card to be in a powered-on state, and control the pin points connecting the mainboard to be tested and the power supply end to not be powered; a first test judgment module, used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determine whether there is a short circuit fault in the boundary scan test.

[0108] The test processing unit also includes: a second control module, used to control the first simulation test card and the second simulation test card to be in a power-off state, and then control the first simulation test card and the second simulation test card to be in a power-on state after pressing down the CPU simulation board, and at the same time, control the power supply of each pin point connecting the mainboard to be tested and the power supply end; a second test judgment module, used to perform a boundary scan test on the cascade chain of the first simulation test card and the second simulation test card through a set boundary scan controller, and determine whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

[0109] The system further includes: a third control module, which is used to control the first simulation test card and the second simulation test card to be in a power-off state, and to control each pin point connecting the mainboard to be tested and the power supply end to not be powered.

[0110] In the system solution embodiment of the present invention, method steps for motherboard boundary scan testing are involved, and the specific details have been described above. That is to say, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be repeated here.

[0111] To achieve the above purpose, Figure 7As shown, the present invention also provides a CPU simulation structure for motherboard boundary scan testing, the CPU simulation structure is used to implement a motherboard boundary scan testing method; the CPU simulation structure includes a motherboard to be tested, and a CPU simulation board arranged on the motherboard to be tested; the motherboard to be tested is electrically connected to a power control terminal through a pin point;

[0112] The CPU simulation structure also includes a programmable logic controller for controlling the operating status of each pin point of the power control terminal and acting on the pressure control of the CPU simulation board; the programmable logic controller also realizes signal interaction with the boundary scan controller set in the CPU simulation structure; a cascade chain consisting of a first simulation test card and a second simulation test card is also electrically connected between the mainboard to be tested and the boundary scan controller; a GND board for realizing a common ground for the boundary scan test system is also provided in the CPU simulation structure.

[0113] In the CPU simulation structure solution embodiment of the present invention, method steps for motherboard boundary scan testing are involved, and the specific details have been explained above. That is to say, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be repeated here.

[0114] The present invention places a mainboard to be tested on a fixture carrier board and activates the fixture, so that a first connector in the mainboard to be tested is plugged into a second connector in a first simulation test card and a third connector in a second simulation test card respectively; a boundary scan controller is provided to perform a boundary scan test on a cascade chain of the first simulation test card and the second simulation test card, and a system and a CPU simulation structure corresponding to the method can solve the defects of conventional CPU testing, achieve a boundary scan test coverage effect that is better than that of conventional CPUs, and solve the short-circuit fault test problem that is often neglected, with test reliability and fast test speed. Moreover, there is no need to consider the power-on, power-on sequence and power-on time of the CPU, and all signal transmission, reception and reading are completed through DUMMY. The test effect is completely controlled by the design end of the boundary scan test, with strong compatibility and high security.

[0115] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for motherboard boundary scan testing, characterized in that: The method comprises the steps of: The mainboard to be tested is placed on the fixture carrier board, and the fixture is activated, so that the first connector in the mainboard to be tested is plugged into the second connector in the first simulation test card and the third connector in the second simulation test card respectively; A boundary scan controller is provided to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card.

2. A method for motherboard boundary scan testing according to claim 1, characterized in that: The method further comprises placing the mainboard to be tested on the fixture carrier board, and operating the fixture, wherein the first connector in the mainboard to be tested is respectively plugged into the second connector in the first simulation test card and the third connector in the second simulation test card, and further comprising: Determine whether each type to be tested is short-circuited. If so, execute the next step. Otherwise, reconnect and determine again until each type to be tested is short-circuited.

3. A method for motherboard boundary scan testing according to claim 1, characterized in that: The step of performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a boundary scan controller is also as follows: Control the first simulation test card and the second simulation test card to be powered on, and control each pin point connecting the mainboard to be tested and the power supply end to be powered off; A boundary scan controller is provided to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, and determine whether there is a short circuit fault in the boundary scan test.

4. A method for motherboard boundary scan testing according to claim 1 or 3, characterized in that: The step of performing a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a boundary scan controller further includes: Control the first simulation test card and the second simulation test card to be in a power-off state, press down the CPU simulation board, and then control the first simulation test card and the second simulation test card to be in a power-on state, and at the same time, control the power supply of each pin point connected to the mainboard to be tested and the power supply end; A boundary scan controller is set up to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, and determine whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

5. A method for motherboard boundary scan testing according to claim 4, characterized in that: After the boundary scan controller is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card, the method further includes: The first simulation test card and the second simulation test card are controlled to be in a power-off state, and each pin point connecting the mainboard to be tested and the power supply end is controlled not to be powered.

6. A system for motherboard boundary scan testing, characterized in that: The system is used to implement a motherboard boundary scan test method as described in any one of claims 1 to 5; the system comprises: A plug-in control unit is used to place the mainboard to be tested on the fixture carrier board, and the fixture is activated, and the first connector in the mainboard to be tested is plugged with the second connector in the first simulation test card and the third connector in the second simulation test card respectively; The test processing unit is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller.

7. A system for motherboard boundary scan testing according to claim 6, characterized in that: The plug-in control unit further includes: The first determination module is used to determine whether each type to be tested is short-circuited. If so, the next step is executed; otherwise, the connection is reconnected and the determination is repeated until each type to be tested is short-circuited. And / or, the test processing unit further includes: A first control module, used for controlling the first simulation test card and the second simulation test card to be in a power-on state, and controlling each pin point connecting the mainboard to be tested and the power supply end to be powered off; The first test determination module is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determine whether there is a short circuit fault in the boundary scan test.

8. A system for motherboard boundary scan testing according to claim 6 or 7, characterized in that: The test processing unit further includes: A second control module is used to control the first simulation test card and the second simulation test card to be in a power-off state, and after pressing down the CPU simulation board, control the first simulation test card and the second simulation test card to be in a power-on state, and at the same time, control the power supply of each pin point connecting the mainboard to be tested and the power supply end; The second test determination module is used to perform a boundary scan test on the cascade chain of the first analog test card and the second analog test card through a set boundary scan controller, and determine whether there is an open circuit fault in the boundary scan test; wherein the open circuit fault test includes: signal reception or transmission, pull-up, pull-down, power supply and GND level reading between IO.

9. A motherboard boundary scan test system according to claim 8, characterized in that: The system further comprises: The third control module is used to control the first simulation test card and the second simulation test card to be in a power-off state, and control each pin point connecting the mainboard to be tested and the power supply end to not be powered.

10. A CPU simulation structure for motherboard boundary scan testing, characterized in that: The CPU simulation structure is used to implement a motherboard boundary scan test method as described in any one of claims 1 to 5; the CPU simulation structure includes a motherboard to be tested, and a CPU simulation board arranged on the motherboard to be tested; the motherboard to be tested is electrically connected to a power control terminal through a pin point; The CPU simulation structure also includes a programmable logic controller for controlling the operating state of each pin point of the power control terminal and acting on the pressure control of the CPU simulation board; the programmable logic controller also realizes signal interaction with the boundary scan controller set in the CPU simulation structure; A cascade chain consisting of a first analog test card and a second analog test card is also electrically connected between the mainboard to be tested and the boundary scan controller; The CPU simulation structure is also provided with a GND board for realizing a common ground for a boundary scan test system.

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