Digital LDO control circuit and electronic equipment

Abstract

The invention provides a digital LDO (Low Dropout Regulator) control circuit and electronic equipment, which are characterized in that a bidirectional shift register, a switch array, a feedback module and a control circuit are electrically connected in sequence, and the control circuit is coupled to the bidirectional shift register, so that the feedback module is used for monitoring the output voltage of the digital LDO circuit in real time; the control circuit judges whether the output voltage of the digital LDO circuit is within the output voltage range or not and controls the enabling and shifting direction of the bidirectional shifting register according to the judgment result so as to control the output state of the bidirectional shifting register, and the switch array controls the number of switches conducted in the switch array according to the output state of the bidirectional shifting register so as to control the output state of the bidirectional shifting register. Therefore, the output voltage of the digital LDO circuit is controlled.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a digital LDO control circuit and electronic equipment. Background Art

[0002] In recent years, digital LDO has been widely used in low-input, high-precision and high-efficiency power supply circuits due to its low-voltage operating characteristics, high precision, stable output, and process variability.

[0003] The comparator in the digital LDO has only two states: 0 or 1. In the stable state, the output of the accumulator of the traditional digital LDO will keep switching between two adjacent codes, resulting in limit loop oscillation (LCO), which introduces obvious ripple to the output and increases the power consumption of the system.

[0004] To solve this problem, a multi-loop, multi-precision control method or a hybrid LDO architecture method is generally used to suppress limit cycle oscillation. Figure 1 The medium, high and low three-precision multi-loop control scheme shown in the figure) improves the accuracy through multiple loops so that its output approaches the target value to achieve the goal of suppressing LCO. However, since both the coarse loop and the fine loop are implemented digitally, it is still affected by LCO and low PSR, so a very large output capacitor is required, the size of its power switch transistor will be multiplied, and the existence of LCO cannot be eliminated;

[0005] In a hybrid LDO architecture (such as Figure 2 As shown in the figure, the digital LDO system is changed into a system with dual LDO loops. Switching mode control is used to combine the advantages of analog and digital LDOs. Large signals are satisfied by the digital loop, and small signals are controlled by the analog loop. The SS gain and LS transient response are decoupled by switching from one controller to another using a voltage-based error signal (vreff-vreg). Since the digital loop is activated based on a large error in the output, even if a large output capacitor of the nF level is used, the regulator will suffer from a large droop in the output, and its quiescent current consumption is large, and the presence of the LCO cannot be eliminated.

[0006] Therefore, how to eliminate the limit cycle oscillation of the digital LDO while stabilizing the output of the digital LDO has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0007] The present invention provides a digital LDO control circuit and electronic equipment to solve the problem of stabilizing the output of the digital LDO while eliminating the limit cycle oscillation of the digital LDO.

[0008] According to a first aspect of the present invention, a digital LDO control circuit is provided, the digital LDO circuit comprising a bidirectional shift register, a switch array, a feedback module and a control circuit electrically connected in sequence, and the control circuit is coupled to the bidirectional shift register, wherein the switch array comprises N switches, wherein N is an integer greater than or equal to 1; wherein:

[0009] The feedback module is used to: monitor the output voltage of the digital LDO circuit in real time, and send the output voltage of the digital LDO circuit to the control circuit;

[0010] The control circuit is configured to: determine whether the output voltage of the digital LDO circuit is within the output voltage range, and control the enabling and shifting direction of the bidirectional shift register according to the determination result to control the output state of the bidirectional shift register;

[0011] The switch array is configured to control the number of switches turned on in the switch array according to the output state of the bidirectional shift register, so as to control the output voltage of the digital LDO circuit.

[0012] Optionally, the enabling and shifting direction of the bidirectional shift register are controlled according to the judgment result, specifically:

[0013] If the output voltage of the digital LDO circuit is within the output voltage range, latching the output state of the bidirectional shift register to lock the number of switches turned on in the switch array;

[0014] If the output voltage of the digital LDO circuit is less than the minimum voltage value in the output voltage range, shifting the bidirectional shift register in a first direction to increase the number of conductive switches in the switch array to control the final output voltage of the digital LDO circuit to be within the output voltage range;

[0015] If the output voltage of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the bidirectional shift register is shifted in a second direction to reduce the number of conductive switches in the switch array to control the final output voltage of the digital LDO circuit to be within the output voltage range.

[0016] Optionally, the control circuit includes a first comparator, a second comparator, a first AND gate, a second AND gate and a NOR gate;

[0017] The first input terminal of the first comparator receives a first reference voltage, the second input terminal of the first comparator receives the output voltage of the digital LDO circuit, the output terminal of the first comparator is coupled to the first input terminal of the first AND gate, and the output terminal of the first comparator is also coupled to the first input terminal of the second AND gate through a first inverter; the first input terminal of the second comparator receives a second reference voltage, the second input terminal of the second comparator receives the output voltage of the digital LDO circuit, the output terminal of the second comparator is coupled to the second input terminal of the first AND gate, and the output terminal of the second comparator is also coupled to the second input terminal of the second AND gate through a second inverter; the output terminal of the first AND gate is used to output a shift signal, the output terminal of the first AND gate is also coupled to the first input terminal of the NOR gate, the output terminal of the second AND gate is coupled to the second input terminal of the NOR gate, and the output terminal of the NOR gate is used to output a latch signal.

[0018] Optionally, the first reference voltage is a minimum voltage value in the output voltage range, and the second reference voltage is a maximum voltage value in the output voltage range.

[0019] Optionally, the bidirectional shift register comprises N shift register units connected in sequence, and the output state of the bidirectional shift register is represented by the output state of each shift register unit; wherein:

[0020] Each shift register unit is coupled to a switch to control the on or off of the corresponding switch; if the shift register unit outputs a first state, the corresponding switch is on; if the shift register unit outputs a second state, the corresponding switch is off.

[0021] Optionally, the enabling and shifting direction of the bidirectional shift register are controlled according to the judgment result, specifically:

[0022] If the output voltage of the digital LDO circuit is within the output voltage range, latching the output state of each shift register unit to lock the number of switches turned on in the switch array;

[0023] If the output voltage of the digital LDO circuit is less than the minimum voltage value in the output voltage range, the number of the shift register units outputting the first state is increased in sequence along the second direction until the final output voltage of the digital LDO circuit is within the output voltage range;

[0024] If the output voltage of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the number of the shift register units outputting the second state is increased in sequence in the first direction until the final output voltage of the digital LDO circuit is within the output voltage range.

[0025] Optionally, each shift register unit includes a first data selector, a second data selector and a D flip-flop;

[0026] The first input terminal of the first data selector is coupled to the output terminal of the D flip-flop corresponding to the subsequent shift register unit, the second input terminal of the first data selector is coupled to the output terminal of the D flip-flop corresponding to the previous shift register unit, the control terminal of the first data selector is coupled to the shift signal, and the output terminal of the first data selector is coupled to the first input terminal of the D flip-flop. The first input terminal of the second data selector is grounded, the second input terminal of the second data selector is coupled to a clock signal, the control terminal of the second data selector is coupled to the latch signal, the output terminal of the second data selector is coupled to the second input terminal of the D flip-flop, and the output terminal of the D flip-flop is coupled to the corresponding switch.

[0027] Optionally, the third terminal of the first comparator receives the clock signal, and the third input terminal of the second comparator receives the clock signal, so as to determine in real time whether the output voltage of the digital LDO circuit is within the output voltage range.

[0028] Optionally, the switch array is a PMOS tube switch array.

[0029] Optionally, the PMOS switch array includes N PMOS tubes, wherein the N PMOS tubes are connected in series and / or in parallel.

[0030] According to a second aspect of the present invention, an electronic device is provided, comprising the digital LDO control circuit provided by any one of the second aspect of the present invention.

[0031] The digital LDO control circuit and electronic device provided by the present invention use a bidirectional shift register, a switch array, a feedback module and a control circuit which are electrically connected in sequence, and the control circuit is coupled to the bidirectional shift register, so as to use the feedback module to monitor the output voltage of the digital LDO circuit in real time, the control circuit determines whether the output voltage of the digital LDO circuit is within the output voltage range, and controls the enabling and shifting direction of the bidirectional shift register according to the determination result to control the output state of the bidirectional shift register, and the switch array controls the number of switches turned on in the switch array according to the output state of the bidirectional shift register to control the output voltage of the digital LDO circuit; thus, the present invention can eliminate the limit cycle oscillation of the digital LDO and stabilize the output of the digital LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 This is a schematic diagram of the digital LDO control circuit structure in the prior art of the present invention. Figure 1 ;

[0034] Figure 2 This is a schematic diagram of the digital LDO control circuit structure in the prior art of the present invention. Figure 2 ;

[0035] Figure 3 Schematic diagram of the digital LDO control circuit structure in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a digital LDO control circuit in one embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of the control circuit structure in an embodiment of the present invention;

[0038] Figure 6 Schematic diagram of the structure of a bidirectional shift register in an embodiment of the present invention;

[0039] Figure 7 yes Figure 3 The waveform diagram of the digital LDO control circuit shown in Figure 1 ;

[0040] Figure 8 yes Figure 3 The waveform diagram of the digital LDO control circuit shown in Figure 2 ;

[0041] Fig. 9 yes Figure 1 The waveform diagram of the digital LDO control circuit shown;

[0042] Description of reference numerals:

[0043] 10- Bidirectional shift register;

[0044] 20- switch array;

[0045] 30-Feedback module;

[0046] 40-control circuit;

[0047] LDO_OUT - output voltage of the digital LDO circuit;

[0048] Rup - the first voltage dividing resistor;

[0049] Rdw- the second voltage dividing resistor;

[0050] 401 - a first comparator;

[0051] 402-second comparator;

[0052] 403-first inverter;

[0053] 404- second inverter;

[0054] 405-first AND gate;

[0055] 406-second AND gate;

[0056] 407-NOR gate;

[0057] Vref1-first reference voltage;

[0058] Vref2-second reference voltage;

[0059] SEL-shift signal;

[0060] EN_SR- latch signal;

[0061] RS-first direction shift signal;

[0062] LS-second direction shift signal;

[0063] EN-first latch signal;

[0064] LOCK-second latch signal;

[0065] 101- shift register unit;

[0066] 1011-first data selector;

[0067] 1012-second data selector;

[0068] 1013 - D flip-flop. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0072] In view of the fact that it is difficult to ensure that the output of the digital LDO is stable and the circuit structure is simple while eliminating the limit cycle oscillation of the digital LDO in the prior art, the present invention provides a digital LDO control circuit and an electronic device, which are electrically connected in sequence through a bidirectional shift register, a switch array, a feedback module and a control circuit, and the control circuit is coupled to the bidirectional shift register, so as to monitor the output voltage of the digital LDO circuit in real time by using the feedback module, the control circuit determines whether the output voltage of the digital LDO circuit is within the output voltage range, and controls the enabling and shifting direction of the bidirectional shift register according to the judgment result to control the output state of the bidirectional shift register, and the switch array controls the number of switches turned on in the switch array according to the output state of the bidirectional shift register to control the output voltage of the digital LDO circuit; thus, the present invention can eliminate the limit cycle oscillation of the digital LDO while stabilizing the output of the digital LDO.

[0073] Please refer to Figure 3 , an embodiment of the present invention provides a digital LDO control circuit 40, the digital LDO circuit comprises a bidirectional shift register 10, a switch array 20, a feedback module 30 and a control circuit 40 which are electrically connected in sequence, and the control circuit 40 is coupled to the bidirectional shift register 10, wherein the switch array 20 comprises N switches, wherein N is an integer greater than or equal to 1; wherein:

[0074] The feedback module 30 is used to: monitor the output voltage LDO_OUT of the digital LDO circuit in real time, and send the output voltage LDO_OUT of the digital LDO circuit to the control circuit 40;

[0075] The control circuit 40 is configured to: determine whether the output voltage LDO_OUT of the digital LDO circuit is within the output voltage range, and control the enabling and shifting direction of the bidirectional shift register 10 according to the determination result to control the output state of the bidirectional shift register 10;

[0076] The switch array 20 is configured to control the number of switches turned on in the switch array 20 according to the output state of the bidirectional shift register 10 , so as to control the output voltage LDO_OUT of the digital LDO circuit.

[0077] The control circuit 40 is configured to control the enabling and shifting direction of the bidirectional shift register 10 according to the judgment result, specifically:

[0078] If the output voltage LDO_OUT of the digital LDO circuit is within the output voltage range, the output state of the bidirectional shift register 10 is latched to lock the number of switches turned on in the switch array 20;

[0079] If the output voltage LDO_OUT of the digital LDO circuit is less than the minimum voltage value in the output voltage range, the bidirectional shift register 10 is shifted in a first direction to increase the number of turned-on switches in the switch array 20 to control the final output voltage of the digital LDO circuit to be within the output voltage range;

[0080] If the output voltage LDO_OUT of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the bidirectional shift register 10 is shifted in the second direction to reduce the number of turned-on switches in the switch array 20 to control the final output voltage of the digital LDO circuit to be within the output voltage range.

[0081] Therefore, the digital LDO control circuit 40 provided by the present invention can lock the number of switches turned on in the switch array 20 when the output voltage LDO_OUT of the digital LDO circuit meets the output voltage requirement, so that the output voltage LDO_OUT remains unchanged. Therefore, with respect to the digital LDO technology, the present invention can eliminate the limit cycle oscillation of the digital LDO and stabilize the output of the digital LDO.

[0082] In a preferred implementation, please refer to Figure 3 The digital LDO circuit also includes an output capacitor C0, a first end of the output capacitor C0 is coupled to the output end of the digital LDO circuit, and a second end thereof is grounded; wherein the output capacitor C0 is used to reduce the ripple of the output voltage LDO_OUT of the digital LDO circuit.

[0083] Regarding the feedback module 30, in one implementation, please refer to Figure 4 , the feedback module 30 includes a first voltage-dividing resistor Rup and a second voltage-dividing resistor Rdw;

[0084] The first end of the first voltage-dividing resistor Rup is coupled to the output end of the digital LDO circuit, the second end of the first voltage-dividing resistor Rup is respectively coupled to the first end of the second voltage-dividing resistor Rdw and the control circuit 40, and the second end of the second voltage-dividing resistor Rdw is grounded.

[0085] In this case, the voltage value of the second end of the first voltage-dividing resistor Rup can represent the output voltage LDO_OUT of the digital LDO circuit, and the control circuit 40 can judge whether the output voltage LDO_OUT of the digital LDO circuit is within the output voltage range according to the voltage value of the second end of the first voltage-dividing resistor Rup, and control the enabling and shifting direction of the bidirectional shift register 10 according to the judgment result to control the output state of the bidirectional shift register 10. Of course, the present invention does not limit the specific circuit structure of the feedback module 30, and the feedback module 30 can also sample the output voltage LDO_OUT of the digital LDO circuit through an operational amplifier, etc., and those skilled in the art can select a suitable sampling circuit as needed.

[0086] The control circuit 40 is now further described:

[0087] In one implementation, please refer to Figure 5 , the control circuit 40 includes a first comparator 401, a second comparator 402, a first AND gate 405, a second AND gate 406 and a NOR gate 407;

[0088] The first input terminal of the first comparator 401 receives the first reference voltage Vref1, the second input terminal of the first comparator 401 receives the output voltage LDO_OUT of the digital LDO circuit, and the output terminal of the first comparator 401 is coupled to the first input terminal of the first AND gate 405. The output terminal of the first comparator 401 is also coupled to the first input terminal of the second AND gate 406 through the first inverter 403; the first input terminal of the second comparator 402 receives the second reference voltage Vref2, the second input terminal of the second comparator 402 receives the output voltage LDO_OUT of the digital LDO circuit, and the output terminal of the second comparator 402 is coupled to the second input terminal of the first AND gate 405. The output terminal of the second comparator 402 is also coupled to the second input terminal of the second AND gate 406 through the second inverter 404; the output terminal of the first AND gate 405 is used to output the shift signal SEL, the output terminal of the first AND gate 405 is also coupled to the first input terminal of the NOR gate 407, the output terminal of the second AND gate 406 is coupled to the second input terminal of the NOR gate 407, and the output terminal of the NOR gate 407 is used to output the latch signal EN_SR.

[0089] Wherein, the shift signal SEL includes a first direction shift signal RS and a second direction shift signal LS; the latch signal EN_SR includes a first latch signal EN and a second latch signal LOCK;

[0090] The first direction shift signal RS is used by the control circuit 40 to control the bidirectional shift register 10 to shift in the first direction, the second direction shift signal LS is used by the control circuit 40 to control the bidirectional shift register 10 to shift in the second direction, the first latch signal LOCK is used to latch the output state of the bidirectional shift register 10, and the second latch signal EN is used to unlock the output state of the bidirectional shift register 10.

[0091] Of course, the first reference voltage Vref1 and the second reference voltage Vref2 can also be set according to the requirements of the circuit in actual applications and the minimum comparison accuracy of the comparator. In one example, the first reference voltage Vref1 is the minimum voltage value in the output voltage range, and the second reference voltage Vref2 is the maximum voltage value in the output voltage range.

[0092] In another example, the first reference voltage Vref1 may also be a preset output voltage of the digital LDO circuit, and the second reference voltage Vref2 is set according to actual circuit requirements and may be the minimum voltage value in the output voltage range or the maximum voltage value in the output voltage range.

[0093] In a specific implementation, please refer to Figure 5The positive input terminal of the first comparator 401 receives the first reference voltage Vref1, and the negative input terminal thereof receives the output voltage LDO_OUT of the digital LDO circuit.

[0094] In actual use, the bidirectional shift register 10 can be regarded as composed of a plurality of cascaded triggers. Based on the control circuit 40 described above, in one implementation mode, please refer to Figure 6 , the bidirectional shift register 10 comprises N shift register units 101 connected in sequence, and the output state of the bidirectional shift register 10 is represented by the output state of each shift register unit 101; wherein:

[0095] Each shift register unit 101 is coupled to a switch to control the on or off of the corresponding switch; if the shift register unit 101 outputs a first state, the corresponding switch is on; if the shift register unit 101 outputs a second state, the corresponding switch is off.

[0096] In this case, the control circuit 40 controls the enabling and shifting direction of the bidirectional shift register 10 according to the judgment result, specifically:

[0097] If the output voltage LDO_OUT of the digital LDO circuit is within the output voltage range, the output state of each shift register unit 101 is latched to lock the number of switches turned on in the switch array 20;

[0098] If the output voltage LDO_OUT of the digital LDO circuit is less than the minimum voltage value in the output voltage range, the number of the shift register units 101 outputting the first state is increased in sequence along the second direction until the final output voltage of the digital LDO circuit is within the output voltage range;

[0099] If the output voltage LDO_OUT of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the number of the shift register units 101 outputting the second state is increased in the first direction until the final output voltage of the digital LDO circuit is within the output voltage range.

[0100] To achieve that the output state of the bidirectional shift register 10 can be latched, in one implementation, please refer to Figure 7 , each shift register unit 101 includes a first data selector 1011, a second data selector 1012 and a D flip-flop 1013;

[0101] The first input terminal of the first data selector 1011 is coupled to the output terminal of the D flip-flop 1013 corresponding to the subsequent shift register unit 101, the second input terminal thereof is coupled to the output terminal of the D flip-flop 1013 corresponding to the previous shift register unit 101, the control terminal thereof is coupled to the shift signal SEL, and the output terminal thereof is coupled to the first input terminal of the D flip-flop 1013, the first input terminal of the second data selector 1012 is grounded, the second input terminal thereof is coupled to a clock signal CLK, the control terminal thereof is coupled to the latch signal EN_SR, the output terminal thereof is coupled to the second input terminal of the D flip-flop 1013, and the output terminal of the D flip-flop 1013 is coupled to the corresponding switch.

[0102] In one implementation, please refer to Figure 6 The D flip-flop 1013 also receives a reset signal CLR to reset the state of the shift register unit 101 when powered on.

[0103] In a specific example, the data in the bidirectional shift register 10 is defined as right shift when it is moved from a low-order trigger to a high-order trigger, and vice versa as left shift. Now, taking the first direction shift signal RS (i.e., the output logic of the first AND gate 405 is 1) used by the control circuit 40 to control the bidirectional shift register 10 to shift right, and taking the second direction shift signal LS (i.e., the output logic of the first AND gate 405 is 0) used by the control circuit 40 to control the bidirectional shift register 10 to shift left as an example, the bidirectional shift register 10 is described:

[0104] In actual use, when the first latch signal EN is received, the bidirectional shift register 10 controls its output state to shift right or left according to the first direction shift signal RS and the second direction shift signal LS. In one clock cycle, the bidirectional shift register 10 can only control the on or off of one switch. The output Q[0:n] of the bidirectional shift register 10 controls the number of switches M[0:n] turned on in the switch array 20. The control end of each switch in the switch array 20 is connected to the output end Q[0:n] of the bidirectional shift register 10.

[0105] The working principle of the shift register unit 101 is as follows: the shift register unit 101 provided by the present invention is composed of two two-choice data selectors and a D flip-flop as a basic unit. The working principle of the D flip-flop 1013 is as follows: the signal outputted from the output terminal Q of the D flip-flop 1013 depends on the states of the first input terminal and the second input terminal of the D flip-flop 1013 when the rising edge of the clock signal CLK arrives; and the first data selector 1011 and the second data selector 1012 both determine the shifting status of the bidirectional shift register 10 through the high and low levels of the input signals at the control terminals. The specific working principle is combined with Figure 5 and Figure 6 It can be described as follows: the second input terminal of the first shift register unit 101 and the first input terminal of the Nth shift register unit 101 are connected to the ground GND and the power supply voltage VDD respectively;

[0106] Whenever the bidirectional shift register 10 is shifted rightward by one bit (i.e., the output logic of the first AND gate 405 is 1), a shift register unit 101 with an output of 0 is added, thereby reducing a closed switch; whenever the bidirectional shift register 10 is shifted leftward by one bit (i.e., the output logic of the first AND gate 405 is 0), a shift register unit 101 with an output of 1 is added, thereby increasing a closed switch;

[0107] In one example, when powered on, the output of each shift register unit 101 is 1 (i.e., the signal output by the output terminal Q of the D flip-flop 1013), so that the switch corresponding to each shift register unit 101 is closed before the effective clock signal CLK arrives; when the first latch signal EN is received: if the bidirectional shift register 10 receives a right shift signal, when the first effective clock signal CLK arrives, the output terminal (Q1) of the first shift register unit 101 outputs 0, and the output terminals of the remaining shift register units 101 output 1; when the second effective clock signal CLK arrives, the output terminal (Q1) of the first shift register unit 101 and the output terminal (Q2) of the second shift register unit 101 output 0, and the output terminals of the remaining shift register units 101 output 1, and similarly, when the nth effective clock signal CLK arrives, the output of each shift register unit 101 is all 0;

[0108] In another example, when powered on, the output of each shift register unit 101 is 0 (i.e., the signal output by the output terminal Q of the D flip-flop 1013), so that the switch corresponding to each shift register unit 101 is disconnected before the effective clock signal CLK arrives; when the first latch signal EN is received: if the bidirectional shift register 10 receives a left shift signal, when the first effective clock signal CLK arrives, the output terminal (Qn) of the Nth shift register unit 101 outputs 1, and the output terminals of the remaining shift register units 101 output 0; when the second effective clock signal CLK arrives, the output terminal (Qn) of the Nth shift register unit 101 and the output terminal (Qn-1) of the N-1th shift register unit 101 output 1, and the output terminals of the remaining shift register units 101 output 0. Similarly, when the nth effective clock signal CLK arrives, the output of each shift register unit 101 is all 1;

[0109] When the second latch signal LOCK is received, the latch signal EN_SR will control the second data selector 1012 to output the ground signal GND, and the ground signal is a DC signal, so that the D flip-flop 1013 cannot control the signal outputted at its output terminal Q according to the clock signal CLK, thereby latching the output state of the bidirectional shift register 10.

[0110] In a specific implementation manner, the switch array 20 is a PMOS transistor switch array 20 .

[0111] In this case, the PMOS switch array 20 includes N PMOS transistors, wherein the N PMOS transistors are connected in series and / or in parallel.

[0112] Of course, the present invention does not limit the specific type of the switch, and the switch may also be an NMOS switch tube, etc. Those skilled in the art may adjust the specific structure of the circuit as needed.

[0113] In actual use, the control circuit 40 also monitors the output voltage LDO_OUT of the digital LDO circuit in real time based on the clock signal CLK. In one embodiment, the third end of the first comparator 401 receives the clock signal CLK, and the third input end of the second comparator 402 receives the clock signal CLK to determine in real time whether the output voltage LDO_OUT of the digital LDO circuit is within the output voltage range.

[0114] Now combined Figure 7-Figure 9 The waveform diagram shown compares the working effects of the digital LDO circuit of the present invention and the existing digital LDO circuit in actual work, wherein: Figure 7-Figure 8 for Figure 3 The working effect of the digital LDO circuit is as follows: Fig. 9 yes Figure 1 The working effect diagram of the existing digital LDO circuit is specifically described as follows:

[0115] PLUS, can be understood as load current,

[0116] LDO_OUT, which can be understood as the output voltage LDO_OUT of the digital LDO circuit;

[0117] EN_SR, can be understood as latch signal EN_SR;

[0118] SEL, which can be understood as a shift signal SEL;

[0119] CLK, can be logically a clock signal CLK;

[0120] DVDD can be understood as a reference voltage;

[0121] The load current is equivalent to the actual load of the subsequent circuit connected to the digital LDO circuit. When the actual load of the subsequent circuit connected to the digital LDO circuit changes dynamically, the output voltage LDO_OUT of the digital LDO circuit will also change accordingly. The digital LDO control circuit 40 can change the output voltage LDO_OUT of the digital LDO circuit according to the dynamic change of the load current to control the final output voltage of the digital LDO circuit within the output voltage range.

[0122] Please refer to Fig. 9 In the existing digital LDO circuit, when in a stable state, even if its reference voltage does not change, the output of its accumulator will keep switching between two adjacent codes, resulting in limit loop oscillation. The output voltage LDO_OUT of the digital LDO circuit has obvious ripples, and its voltage output is unstable. Moreover, this continuous switching state will increase the power consumption of the system.

[0123] In the digital LDO circuit provided by the present invention, please refer to Figure 7 , when the actual load of the subsequent circuit connected to the digital LDO circuit changes dynamically, the output voltage LDO_OUT of the digital LDO circuit changes less, and its voltage output is relatively stable;

[0124] Please continue to refer to Figure 8 , when the digital LDO circuit is in a stable state, its output voltage is relatively stable; when the control module controls the shift direction of the bidirectional shift register 10, the voltage output ripple of the digital LDO circuit is small, and its stability is good, and the output voltage is stable; when the second latch signal LOCK is received, the voltage output voltage value of the digital LDO circuit remains unchanged. Therefore, the present invention can eliminate the limit cycle oscillation of the digital LDO while stabilizing the output of the digital LDO, and the specific circuit of the control circuit 40 is simple. Furthermore, the power consumption of the digital LDO circuit system provided by the present invention is also low.

[0125] In addition, an embodiment of the present invention further provides an electronic device, comprising the above-mentioned digital LDO control circuit. As an example, the electronic device may be a charger, a single-chip microcomputer, and the like.

[0126] In summary, the present invention utilizes a bidirectional shift register, a switch array, a feedback module, and a control circuit that are electrically connected in sequence, and the control circuit is coupled to the bidirectional shift register, so as to utilize the feedback module to monitor the output voltage of the digital LDO circuit in real time. The control circuit determines whether the output voltage of the digital LDO circuit is within the output voltage range, and controls the enabling and shifting direction of the bidirectional shift register according to the determination result to control the output state of the bidirectional shift register. The switch array controls the number of switches turned on in the switch array according to the output state of the bidirectional shift register to control the output voltage of the digital LDO circuit.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital LDO control circuit, characterized in that: The digital LDO circuit includes a bidirectional shift register, a switch array, a feedback module and a control circuit which are electrically connected in sequence, and the control circuit is coupled to the bidirectional shift register, wherein the switch array includes N switches, wherein N is an integer greater than or equal to 1; wherein: The feedback module is used to: monitor the output voltage of the digital LDO circuit in real time, and send the output voltage of the digital LDO circuit to the control circuit; The control circuit is configured to: determine whether the output voltage of the digital LDO circuit is within the output voltage range, and control the enabling and shifting direction of the bidirectional shift register according to the determination result to control the output state of the bidirectional shift register; The switch array is configured to control the number of switches turned on in the switch array according to the output state of the bidirectional shift register, so as to control the output voltage of the digital LDO circuit.

2. The digital LDO control circuit according to claim 1, characterized in that: The enabling and shifting direction of the bidirectional shift register are controlled according to the judgment result, specifically: If the output voltage of the digital LDO circuit is within the output voltage range, latching the output state of the bidirectional shift register to lock the number of switches turned on in the switch array; If the output voltage of the digital LDO circuit is less than the minimum voltage value in the output voltage range, shifting the bidirectional shift register in a first direction to increase the number of conductive switches in the switch array to control the final output voltage of the digital LDO circuit to be within the output voltage range; If the output voltage of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the bidirectional shift register is shifted in a second direction to reduce the number of conductive switches in the switch array to control the final output voltage of the digital LDO circuit to be within the output voltage range.

3. The digital LDO control circuit according to claim 2, characterized in that: The control circuit includes a first comparator, a second comparator, a first AND gate, a second AND gate and a NOR gate; The first input terminal of the first comparator receives a first reference voltage, the second input terminal of the first comparator receives the output voltage of the digital LDO circuit, the output terminal of the first comparator is coupled to the first input terminal of the first AND gate, and the output terminal of the first comparator is also coupled to the first input terminal of the second AND gate through a first inverter; the first input terminal of the second comparator receives a second reference voltage, the second input terminal of the second comparator receives the output voltage of the digital LDO circuit, the output terminal of the second comparator is coupled to the second input terminal of the first AND gate, and the output terminal of the second comparator is also coupled to the second input terminal of the second AND gate through a second inverter; the output terminal of the first AND gate is used to output a shift signal, the output terminal of the first AND gate is also coupled to the first input terminal of the NOR gate, the output terminal of the second AND gate is coupled to the second input terminal of the NOR gate, and the output terminal of the NOR gate is used to output a latch signal.

4. The digital LDO control circuit according to claim 3, characterized in that: The first reference voltage is a minimum voltage value in the output voltage range, and the second reference voltage is a maximum voltage value in the output voltage range.

5. The digital LDO control circuit according to claim 3, characterized in that: The bidirectional shift register comprises N shift register units connected in sequence, and the output state of the bidirectional shift register is represented by the output state of each shift register unit; wherein: Each shift register unit is coupled to a switch to control the on or off of the corresponding switch; if the shift register unit outputs a first state, the corresponding switch is on; if the shift register unit outputs a second state, the corresponding switch is off.

6. The digital LDO control circuit according to claim 5, characterized in that: The enabling and shifting direction of the bidirectional shift register are controlled according to the judgment result, specifically: If the output voltage of the digital LDO circuit is within the output voltage range, latching the output state of each shift register unit to lock the number of switches turned on in the switch array; If the output voltage of the digital LDO circuit is less than the minimum voltage value in the output voltage range, the number of the shift register units outputting the first state is increased in sequence along the second direction until the final output voltage of the digital LDO circuit is within the output voltage range; If the output voltage of the digital LDO circuit is greater than the maximum voltage value in the output voltage range, the number of the shift register units outputting the second state is increased in sequence in the first direction until the final output voltage of the digital LDO circuit is within the output voltage range.

7. The digital LDO control circuit according to claim 6, characterized in that: Each shift register unit includes a first data selector, a second data selector and a D flip-flop; The first input terminal of the first data selector is coupled to the output terminal of the D flip-flop corresponding to the subsequent shift register unit, the second input terminal of the first data selector is coupled to the output terminal of the D flip-flop corresponding to the previous shift register unit, the control terminal of the first data selector is coupled to the shift signal, and the output terminal of the first data selector is coupled to the first input terminal of the D flip-flop. The first input terminal of the second data selector is grounded, the second input terminal of the second data selector is coupled to a clock signal, the control terminal of the second data selector is coupled to the latch signal, the output terminal of the second data selector is coupled to the second input terminal of the D flip-flop, and the output terminal of the D flip-flop is coupled to the corresponding switch.

8. The digital LDO control circuit according to claim 6, characterized in that: The third terminal of the first comparator receives the clock signal, and the third input terminal of the second comparator receives the clock signal, so as to determine in real time whether the output voltage of the digital LDO circuit is within the output voltage range.

9. The digital LDO control circuit according to claim 1, characterized in that: The switch array is a PMOS switch array.

10. The digital LDO control circuit according to claim 9, characterized in that: The PMOS switch array includes N PMOS transistors, wherein the N PMOS transistors are connected in series and / or in parallel.

11. An electronic device, characterized in that: The invention comprises the digital LDO control circuit as described in any one of claims 1 to 10.

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