Wafer feeding deviation correction method, device and equipment and storage medium

Abstract

The invention discloses a wafer feeding deviation correction method, device and equipment and a storage medium, and relates to the field of wafer detection. An image set of a target area of the wafer on a carrying table is obtained, the carrying table is provided with an auxiliary marking line used for alignment and correction, and the target area is a position area where the auxiliary marking line intersects with the wafer contour; determining the position of the wafer on the carrying table based on the image set, and generating actual attitude information of the wafer; and calculating correction data according to the actual attitude information and the standard attitude information, and controlling the movement of the carrier based on the correction data, so that the corrected actual attitude of the wafer is consistent with the standard attitude. According to the scheme, after deviation is generated during wafer feeding, a circle formula is constructed according to the wafer contour line in the image set, the wafer center and the actual posture information are determined, the posture and the wafer are synchronously adjusted through the posture adjusting mechanism, the wafer center coincides with the center of the stage in the initial state, and deviation correction is achieved.

Description

Technical Field

[0001] The present application relates to the field of wafer inspection, and in particular to a method, device, equipment and storage medium for correcting wafer loading deviation. Background Art

[0002] Wafer loading is a critical initial step in the entire process of chip manufacturing. Accurate loading can ensure the smooth implementation of a series of complex and high-precision processing techniques (such as photolithography, etching, coating, etc.) that follow, which is directly related to the final quality and yield of the chip. Wafer loading is also required in the process of wafer yield inspection based on visual inspection technology.

[0003] Although the equipment used for wafer loading and loading is constantly pursuing high precision in design and manufacturing, its precision still has a certain error range due to the current level of mechanical processing technology. In the process of grabbing and placing wafers, due to external factors such as slight air flow fluctuations in the production environment, slight vibrations caused by equipment operation, as well as factors such as its own structural vibration and joint wear, the wafer placement position may not be completely consistent with the expected target position, resulting in deviation.

[0004] The inventors discovered that in the process of micro-yield inspection of wafers based on visual inspection technology, an ultra-high-resolution camera is used for image acquisition. If the wafer is misaligned during loading, the captured image of the misaligned wafer will have a large pixel deviation from the image of the wafer in the correct position. The large pixel deviation will seriously affect the accuracy of the defect detection results. Summary of the invention

[0005] The present application provides a method, device, equipment and storage medium for correcting wafer loading deviation, which can accurately measure the deviation between the actual position of the wafer and the standard position, and perform effective adjustment and correction, thereby ensuring that the corrected wafer can be accurately in the specified position, laying a good foundation for the accuracy of the wafer defect detection results.

[0006] On the one hand, the present application provides a method for correcting wafer loading deviation, the method comprising:

[0007] Acquire an image set of a target area of ​​the wafer on a carrier, wherein the carrier is provided with auxiliary marking lines for alignment and correction, and the target area is a position area where the auxiliary marking lines intersect with the wafer contour line;

[0008] Determine the position of the wafer on the stage based on the image set, and generate actual posture information of the wafer;

[0009] According to the actual posture information and the standard posture information, correction data is calculated, and the movement of the stage is controlled based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

[0010] Specifically, the auxiliary marking lines are two perpendicular intersecting lines, and the intersection point coincides with the center point of the table surface of the carrier;

[0011] The image set includes images of the wafer notch and the four areas where the auxiliary marking lines intersect with the wafer outline.

[0012] Specifically, determining the position of the wafer on the stage based on the image set includes:

[0013] Establishing a stage coordinate system based on the two vertical auxiliary marking lines, and mapping all local wafer contour images in the image set to the stage coordinate system;

[0014] Performing circle fitting processing based on three of the local wafer contour images to obtain a complete fitting contour and a circle center of the wafer, and determining the actual center coordinates of the wafer in the stage coordinate system;

[0015] Based on the local wafer contour map with the notch, the actual notch coordinates of the wafer in the stage coordinate system are determined, and combined with the actual circle center coordinates, the posture of the wafer based on the stage coordinate system is determined.

[0016] Specifically, the actual posture information of the wafer is generated, including:

[0017] Based on a preset actual reference coordinate system, and according to the positional relationship between the stage and the actual reference coordinate system, determining a conversion relationship between the stage coordinate system and the actual reference coordinate system;

[0018] According to the conversion relationship, the posture of the wafer based on the stage coordinate system is converted into the posture of the wafer based on the actual reference coordinate system.

[0019] Specifically, the actual posture information is generated using the platform coordinate system as the actual reference coordinate system.

[0020] Specifically, the calculating and obtaining the correction data according to the actual posture information and the standard posture information includes:

[0021] Acquire the standard posture information of the wafer relative to the carrier in an ideal state; the standard posture information is the position posture when the center of the wafer coincides with the center of the carrier in an initialized state;

[0022] A groove line is connected between the wafer center and the groove point, and wafer correction vector data is calculated according to the groove line, the wafer center coordinates and the stage coordinate system.

[0023] Specifically, the wafer correction vector data includes a center offset value between the wafer center and the stage center, and an offset rotation angle formed by a wafer groove connecting line and a stage coordinate system;

[0024] The controlling the movement of the stage based on the correction data comprises:

[0025] Control the center of the stage to translate toward the center of the wafer by a distance equal to the center offset value;

[0026] The stage is controlled to rotate in the opposite direction of the wafer notch point by an offset rotation angle.

[0027] On the other hand, the present application provides a wafer loading deviation correction device, the device comprising:

[0028] Acquire an image set of a target area of ​​the wafer on a carrier, wherein the carrier is provided with auxiliary marking lines for alignment and correction, and the target area is a position area where the auxiliary marking lines intersect with the wafer contour line;

[0029] Determine the position of the wafer on the stage based on the image set, and generate actual posture information of the wafer;

[0030] According to the actual posture information and the standard posture information, correction data is calculated, and the movement of the stage is controlled based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

[0031] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the wafer loading deviation correction method described in the above aspects.

[0032] On the other hand, the present application provides a computer-readable storage medium, wherein the readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the wafer loading deviation correction method described in the above aspects.

[0033] The beneficial effects brought about by the technical solution provided in the embodiments of the present application include at least: when the wafer is loaded onto the carrier, the present application calculates the relative position relationship and the actual posture relationship between the wafer and the carrier according to the intersection of the wafer contour line and the auxiliary marking line of the carrier; by comparing with the annotated posture information of the wafer in the ideal state, the correction data is calculated, and then the carrier can be controlled to make targeted adjustments, and the posture adjustment mechanism is controlled to adjust the posture and wafer synchronously, so that the center of the wafer coincides with the center of the carrier in the initial state, thereby realizing deviation correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of wafer loading deviation correction provided in an embodiment of the present application;

[0035] Figure 2 is a flow chart of a wafer loading deviation correction method provided in an embodiment of the present application;

[0036] Figure 3 It is a schematic diagram of the state before and after loading on the carrier;

[0037] Figure 4 This is the corresponding detail picture of the wafer notch under tilted and normal viewing angles;

[0038] Figure 5 A schematic diagram of determining position deviation based on contour area is shown;

[0039] Figure 6 It is a schematic diagram of extracting point information based on auxiliary marking lines;

[0040] Figure 7 Schematic diagram of the camera field of view before and after deviation correction is shown;

[0041] Figure 8 The structure block diagram of the wafer loading deviation correction device is shown;

[0042] Fig. 9 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0044] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0045] Figure 1 1 is a schematic diagram of wafer loading deviation correction provided by an embodiment of the present application, including a detection platform 110, on which a posture adjustment mechanism 120 is arranged, and a carrier 130 is located at the top of the posture adjustment mechanism 120. The traditional defect detection scheme also needs to be equipped with a carrier, which is similar to the basic structure. Figure 1The structure of the intermediate stage is similar, but the difference is that the stage 130 of the present application is controlled by the posture adjustment mechanism 120, and can be raised and lowered and the displacement angle can be adjusted as needed, that is, it can be changed arbitrarily within the spatial range. The structure of the stage 130 is usually set to be circular, consistent with the shape of the wafer 140 to be tested. The deviation correction of the present application scheme is mainly achieved through the posture adjustment mechanism 120.

[0046] Figure 2 : is a flow chart of a wafer loading deviation correction method provided in an embodiment of the present application, comprising the following steps:

[0047] S1. Acquire an image set of a target area of ​​a wafer on a carrier, wherein auxiliary marking lines for alignment and correction are provided on the carrier, and the target area is a position area where the auxiliary marking lines intersect with the wafer contour line;

[0048] After the wafer is placed on the stage by the robotic arm, a camera directly above the stage or fixed at a specific position scans the state image of the wafer on the stage, which is called the wafer state diagram. The wafer state diagram shows the stage and the top surface of the wafer from a top-down perspective or a top-down perspective at a certain angle. Taking a circular stage as an example, theoretically the wafer should be clamped and placed in the center of the stage, but due to factors such as errors, the actual wafer cannot fall precisely to the center. Figure 3 The left side in the middle shows an image of the stage 310 before loading. In order to facilitate the subsequent determination of the stage deviation, an ideal area 320 can be simulated on the stage 310, that is, the ideal placement area of ​​the wafer contour line.

[0049] like Figure 3 In the wafer status diagram on the right side, the blue area is the wafer 340 that has been loaded and placed. From the figure, it can be seen that there is a position deviation between the contour lines of the wafer 340 area and the ideal area 320 (it is actually invisible to the naked eye and is only used to describe the deviation between the actual and ideal states). The present application performs wafer offset correction in this state. Figure 3 The offset correction in the figure is a schematic diagram of a microscopic scene. The offset value is in pixel size. To perform correction at the pixel size, a high-precision camera is needed to capture local images of the wafer and the stage, that is, a collection of images in the target area. The target area specifically refers to Figure 3The position area where the auxiliary marking line 330 intersects with the wafer outline line 340. Auxiliary marking lines 330 for alignment and correction are provided on the carrier 310, and the auxiliary marking lines can be engraved on the carrier, or lines formed by opening holes and filling markers. For example, the auxiliary marking lines are two vertically intersecting lines, and the intersection coincides with the center point of the table surface of the carrier. The wafer outline line 340 is preliminarily identified by the camera, and then the image of the target area is obtained by alignment shooting. In particular, when there are a large number of auxiliary marking lines 330, multiple intersections can be generated with the wafer outline line 340, so images of all intersection areas can be taken to form an image set. This image set is used for later wafer posture calculation.

[0050] S2, determining the position of the wafer on the stage based on the image set, and generating actual posture information of the wafer;

[0051] Calculating the actual wafer posture information is to determine the position of the wafer relative to the carrier. The ideal posture is that the center of the wafer coincides with the center of the carrier, and the wafer notch faces the target position. The wafer notch is set during the production process to locate the wafer position.

[0052] In some embodiments, in order to facilitate shooting and process flow, the wafer orientation photographed under a fixed camera angle should be fixed as much as possible. In traditional wafer layout, the motherboard image is mapped with the notch orientation, so when taking a panoramic photo, it is best to use the notch as the top or bottom as the reference when shooting, so that the captured image is not tilted. Figure 4 The following are the details of the wafer notch under tilted and normal viewing angles. The internal layout of the left image is actually tilted, which is not conducive to later data processing and defect recognition. Therefore, the angle is adjusted during this correction to avoid occupying computing resources for image processing during subsequent recognition. Figure 4 The right wafer notch is rotated to the bottom as a reference, then it can be determined Figure 3 The actual posture information of the wafer.

[0053] S3. According to the actual posture information and the standard posture information, correction data is calculated, and the movement of the stage is controlled based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

[0054] After determining the actual posture information, the correction data can be obtained based on the deviation from the standard posture information under the ideal state, and then the data can be sent to the posture adjustment mechanism 120 under the stage. The posture adjustment mechanism 120 will move the stage (with the wafer) as a whole, and the moving target is to move the wafer to the ideal area on the original stage. Note that this movement process controls the movement of the stage, and the relative position relationship between the wafer and the stage does not change. Instead, based on the spatial position relationship, the wafer is moved to the ideal area position of the wafer under the original spatial coordinates.

[0055] The moving process has a variety of control methods. For example, in some embodiments, before loading the wafer, the stage is controlled to initialize the position, the stage is moved into the target range of the camera angle of view, and the loading is performed within the fixed camera angle of view and the target range, for example, according to Figure 1 The lower support arm 150 located on the posture adjustment mechanism 120 can also be used as a reference to carry the wafer 150 up and down. The wafer state diagram is obtained by scanning with a camera device. The target range mentioned here is to move the stage into the center of the camera field of view, specifically, to coincide the center of the stage with the center of the camera field of view, which is the best ideal state. The calibration process can use a fixed camera viewing angle to determine the spatial position of the target area. When moving the stage and the wafer, the wafer and the stage are moved synchronously until the wafer contour is completely adjusted to the spatial position. Because the camera field of view is fixed, and the target area of ​​the stage in the initial state is actually understood as the center of the camera field of view, although the relative position of the stage and the wafer remains unchanged after correction, the wafer has actually completed the deflection correction. At this time, the center of the wafer coincides with the center of the initial stage, and the accuracy requirements of scanning and defect detection are met.

[0056] To summarize, when the wafer is loaded onto the carrier, the present application calculates the relative position relationship and actual posture relationship between the wafer and the carrier according to the intersection of the wafer contour line and the auxiliary marking line of the carrier; by comparing with the annotated posture information of the wafer in the ideal state, the correction data is calculated, and then the carrier can be controlled to make targeted adjustments, and the posture adjustment mechanism is controlled to adjust the posture and wafer synchronously, so that the center of the wafer coincides with the center of the carrier in the initial state, thereby realizing deviation correction.

[0057] The calculation of the actual wafer posture information needs to take into account the rotation angle of the wafer notch and the positional relationship with the ideal area, but it is not determined by the pixel accuracy of the panoramic wafer state map that it cannot be directly calculated. This application uses the collected local image set for offset calculation.

[0058] Because the center of the wafer cannot be obtained at this time and there is a lack of reference points for calculation, this step requires using the image set to calculate the coordinates of the center of the wafer, and then calculate the orientation of the wafer notch to determine the actual posture information of the wafer.

[0059] In a possible implementation, determining the position of the wafer on the stage based on the image set includes:

[0060] A. Establish a stage coordinate system based on two vertical auxiliary marking lines, and map all local auxiliary marking lines and local wafer contour images in the image set to the stage coordinate system;

[0061] Figure 5 This is a schematic diagram of mapping the stage coordinate system based on the local wafer contour map. Figure 5 The carrier contour line 510 in the figure is determined according to the auxiliary marking line 520. First, the carrier coordinate system is established according to the two vertical auxiliary marking lines, and then the carrier contour line 510 is simulated according to the carrier size (this step can be omitted). As for how to map the local wafer contour map into the coordinate system, the distance mapping method can be used as follows:

[0062] The auxiliary markings are strictly vertical coordinate systems. The camera is based on the auxiliary markings. Figure 1 If a local wafer profile image is taken in the target area, the camera travel and the distance between any two local wafer profile images can be accurately determined. Therefore, as long as the distance between each local wafer profile image is recorded, it can be mapped to the stage coordinate system.

[0063] B. Performing circle fitting processing based on three of the partial wafer contour images to obtain the complete fitting contour and circle center of the wafer, and determining the actual center coordinates of the wafer in the stage coordinate system;

[0064] Based on the three-point circle determination principle, any three partial wafer contour images are selected, and the circle fitting process can be performed according to the intersection of the wafer contour line and the auxiliary marking line, and then the actual center coordinates of the wafer are calculated. In particular, the actual center coordinates do not coincide with the center of the stage.

[0065] Figure 6 It is a wafer schematic diagram generated based on auxiliary markings and fitted wafer contour lines. In fact, the image set can contain four partial wafer contours, including one partial wafer contour with notch and three partial wafer contours without notch, or the wafer notch can also be photographed separately. When mapping with the partial wafer contour with notch, it is equivalent to directly mapping the orientation of the notch into the coordinate system, which simplifies the calculation process.

[0066] C. Based on the local wafer contour map with notch, determine the actual notch coordinates of the wafer in the stage coordinate system, and combine with the actual center coordinates to determine the posture of the wafer based on the stage coordinate system.

[0067] In some embodiments, because a three-dimensional coordinate system or other reference coordinate system independent of the stage may be used during the deflection correction, the actual posture information of the wafer needs to be further transformed. First, based on the preset actual reference coordinate system, the conversion relationship between the stage coordinate system and the actual reference coordinate system is determined according to the positional relationship between the stage and the actual reference coordinate system. Further, according to the conversion relationship, the posture of the wafer based on the stage coordinate system is converted to the posture of the wafer based on the actual reference coordinate system.

[0068] In actual operation, other methods can be used to avoid coordinate system transformation. The actual reference coordinate system posture can be set to be consistent with the initial position of the carrier during loading, that is, the established carrier coordinate system is the actual reference coordinate system. This application is explained using the carrier coordinate system as the actual reference coordinate system.

[0069] According to the actual posture information and the standard posture information, the process of calculating the correction data can be summarized as follows:

[0070] A. Obtain standard posture information of the wafer relative to the stage under ideal conditions;

[0071] The standard posture information described in this application is the position posture when the center of the wafer coincides with the center position of the download stage in the initialization state.

[0072] B. Connect the grooves of the wafer center and the groove points, and calculate the wafer correction vector data based on the groove connection line, the wafer center coordinates and the stage coordinate system.

[0073] See also Figure 6 As shown, the groove line formed by the wafer notch and the wafer center forms an angle α with the auxiliary marking line, which is the offset rotation angle. At the same time, the travel distance difference between the wafer center and the stage center is the wafer center offset value. Based on these two sets of data, the wafer correction vector data can be determined.

[0074] Controlling the movement of the stage based on the correction data includes controlling the stage center to translate toward the wafer center by a distance of a center offset value; and controlling the stage to rotate in the opposite direction of the wafer notch point by an offset rotation angle.

[0075] Figure 7The schematic diagram of the scene before and after the offset correction is shown. Before the correction, the center of the camera field of view coincides with the center of the stage by default. At this time, the center of the wafer is offset from the center of the field of view. During the correction stage, the computer equipment will control the center of the stage to translate toward the center of the wafer by a distance of the center offset value, and the angle will control the stage to rotate in the opposite direction of the wafer notch point by an angle deviation value. After the rotation, the line connecting the wafer notch and the center of the wafer is actually on the center line of the field of view, and the wafer is now in a straightened state; on the contrary, the center of the stage deviates from the center of the field of view. The above-mentioned offset correction can be used to pull the originally offset wafer back to the center of the camera field of view, so that the panoramic view scanned by this fully meets the angle and accuracy requirements.

[0076] Through the above-mentioned deviation correction, the originally offset wafer can be pulled back to the center of the camera's field of view, so that the scanned panoramic image fully meets the angle and accuracy requirements.

[0077] Figure 8 The structure block diagram of the wafer loading deviation correction device provided in the embodiment of the present application is shown, and the device includes:

[0078] An acquisition module 810 is used to acquire an image set of a target area of ​​a wafer on a carrier, wherein the carrier is provided with auxiliary markings for alignment and correction, and the target area is a position area where the auxiliary markings intersect with the wafer contour line;

[0079] A calculation module 820, configured to determine the position of the wafer on the stage based on the image set and generate actual posture information of the wafer;

[0080] The correction module 830 is used to calculate the correction data according to the actual posture information and the standard posture information, and control the movement of the stage based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

[0081] The wafer loading deviation correction device provided in the embodiment of the present application can be applied to the wafer loading deviation correction method provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0082] It should be noted that the wafer loading misalignment correction device provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the wafer loading misalignment correction device is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the wafer loading misalignment correction method provided in the above-mentioned method embodiment and the implementation method of the wafer loading misalignment correction device provided in this embodiment belong to the same concept. The specific implementation process of the wafer loading misalignment correction device provided in this embodiment is detailed in the above-mentioned method embodiment, which will not be repeated here.

[0083] Fig. 9 The block diagram of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various chips.

[0084] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0085] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0086] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.

[0087] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0088] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.

[0089] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0090] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0091] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0092] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A method for correcting wafer loading deviation, characterized in that: The method comprises: Acquire an image set of a target area of ​​the wafer on a carrier, wherein the carrier is provided with auxiliary marking lines for alignment and correction, and the target area is a position area where the auxiliary marking lines intersect with the wafer contour line; Determine the position of the wafer on the stage based on the image set, and generate actual posture information of the wafer; According to the actual posture information and the standard posture information, correction data is calculated, and the movement of the stage is controlled based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

2. The method according to claim 1, characterized in that The auxiliary marking lines are two perpendicular intersecting lines, and the intersection point coincides with the center point of the table surface of the carrier; The image set includes images of the wafer notch and the four areas where the auxiliary marking lines intersect with the wafer outline.

3. The method according to claim 2, characterized in that The step of determining the position of the wafer on the stage based on the image set comprises: Establishing a stage coordinate system based on the two vertical auxiliary marking lines, and mapping all local wafer contour images in the image set to the stage coordinate system; Performing circle fitting processing based on three of the local wafer contour images to obtain a complete fitting contour and a circle center of the wafer, and determining the actual center coordinates of the wafer in the stage coordinate system; Based on the local wafer contour map with the notch, the actual notch coordinates of the wafer in the stage coordinate system are determined, and combined with the actual circle center coordinates, the posture of the wafer based on the stage coordinate system is determined.

4. The method according to claim 3, characterized in that The actual posture information of the wafer is generated, including: Based on a preset actual reference coordinate system, and according to the positional relationship between the stage and the actual reference coordinate system, determining a conversion relationship between the stage coordinate system and the actual reference coordinate system; According to the conversion relationship, the posture of the wafer based on the stage coordinate system is converted into the posture of the wafer based on the actual reference coordinate system.

5. The method according to claim 3, characterized in that: The actual posture information is generated by taking the platform coordinate system as the actual reference coordinate system.

6. The method according to claim 5, characterized in that The step of calculating correction data according to the actual posture information and the standard posture information includes: Acquire the standard posture information of the wafer relative to the carrier in an ideal state; the standard posture information is the position posture when the center of the wafer coincides with the center of the carrier in an initialized state; A groove line is connected between the wafer center and the groove point, and wafer correction vector data is calculated according to the groove line, the wafer center coordinates and the stage coordinate system.

7. The method according to claim 6, characterized in that The wafer correction vector data includes a center offset value between the wafer center and the stage center, and an offset rotation angle formed by a wafer groove connection line and a stage coordinate system; The controlling the movement of the stage based on the correction data comprises: Control the center of the stage to translate toward the center of the wafer by a distance equal to the center offset value; The stage is controlled to rotate in the opposite direction of the wafer notch point by an offset rotation angle.

8. A wafer loading deviation correction device, characterized in that: The device comprises: An acquisition module is used to acquire an image set of a target area of ​​the wafer on the carrier, wherein the carrier is provided with auxiliary markings for alignment and correction, and the target area is a position area where the auxiliary markings intersect with the wafer contour line; A calculation module, used for determining the position of the wafer on the stage based on the image set and generating actual posture information of the wafer; The correction module is used to calculate the correction data according to the actual posture information and the standard posture information, and control the movement of the carrier based on the correction data so that the actual posture of the wafer after correction is consistent with the standard posture.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the wafer loading deviation correction method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the wafer loading deviation correction method as described in any one of claims 1 to 7.

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