Frequency dividing circuit

Abstract

The invention discloses a frequency dividing circuit which comprises an input module, a first delay module, a second delay module and a third delay module. The first delay module is used for responding to a first level state of the input module and outputting a first signal based on a level value of a positive output end of the input module; the second delay module is used for outputting a second signal based on the level value of the negative output end of the input module in response to a second level state of the input module; the third delay module is used for generating a first frequency multiplication signal based on the output signal of the positive output end of the input module and outputting a third signal based on the first frequency multiplication signal; wherein the ratio of the frequency of the first frequency multiplication signal to the frequency of the output signal of the positive output end of the input module is a preset integer. According to the frequency dividing circuit, the duty ratio of each output signal of the frequency dividing circuit can be different through different processing modes of each delay module on different output signals of the input module, so that the mismatching problem existing in high-speed and high-precision clock application of the frequency dividing circuit is solved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of circuit design technology, and more particularly to a frequency division circuit. Background Art

[0002] In the existing field of serializers or deserializers, a high-speed, high-precision clock control signal is required to realize the conversion between a high-speed serial signal and a low-speed parallel signal, and a frequency divider is a commonly used module for designing a clock control signal.

[0003] However, since the characteristics of the internal components of the circuit vary with factors such as process temperature and power supply, the clock control signal with a fixed duty cycle is prone to mismatch (i.e., the clock control signal is not synchronized), which can lead to data transmission errors, timing violations and other problems within the circuit.

[0004] Based on this, pulse width modulation (PWM) technology can be used to compensate for the mismatch of the clock control signal by adjusting the duty cycle of the clock control signal. However, in order to meet the requirements of high speed and high precision, the comparator used in pulse width modulation technology has high requirements, which makes circuit design very difficult.

[0005] Therefore, the mismatch problem existing in the existing frequency division circuit in high-speed and high-precision clock applications has become a problem that needs to be solved. Summary of the invention

[0006] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a frequency dividing circuit, which can process different output signals of the input module in different ways through each delay module, so that the duty cycle of each output signal of the frequency dividing circuit is different, thereby solving the mismatch problem of the frequency dividing circuit in high-speed and high-precision clock applications.

[0007] The circuit is as follows: According to one aspect of the present application, a frequency division circuit is provided, comprising: an input module, a first delay module, a second delay module and a third delay module. The control input terminal of the input module is connected to the control input terminal of the second delay module, the positive output terminal of the input module is connected to the input terminal of the third delay module, the input terminal of the first delay module is respectively connected to the data input terminal of the input module and the positive output terminal of the input module, and the data input terminal of the input module is connected to the negative output terminal of the first delay module; The first delay module is used for, in response to a first level state of the input module, outputting a first signal based on a level value of a positive output terminal of the input module; The second delay module is used for, in response to the second level state of the input module, outputting a second signal based on the level value of the negative output terminal of the input module; wherein the first level state is opposite to the second level state; The third delay module is used to generate a first frequency-doubled signal based on the output signal of the positive output terminal of the input module, and output a third signal based on the first frequency-doubled signal; wherein the ratio of the frequency of the first frequency-doubled signal to the frequency of the output signal of the positive output terminal of the input module is a preset integer.

[0008] In addition, the frequency division circuit of the present application may also have the following additional technical features: Preferably, the first delay module includes a first operator and a first trigger, the control input end of the input module is connected to the control input end of the first trigger, the input end of the first operator is respectively connected to the data input end of the input module and the positive output end of the input module, and the output end of the first operator is connected to the data input end of the first trigger; The first operator is used to determine the level value of the output terminal of the first operator based on the level value of the data input terminal of the input module and the level value of the positive output terminal of the input module; The first trigger is used to set the level value of the positive output terminal of the first trigger to the level value of the output terminal of the first operator in response to the first level state of the input module, and output a first signal based on the level value of the positive output terminal of the first trigger.

[0009] Preferably, the second delay module includes a first inverter, a second trigger and a second operator, the control input end of the input module is connected to the input end of the first inverter, the output end of the first inverter is connected to the control input end of the second trigger, the negative output end of the input module is connected to the data input end of the second trigger, and the input end of the second operator is respectively connected to the negative output end of the input module and the positive output end of the second trigger; The second trigger is used to set the level value of the positive output terminal of the second trigger to the level value of the negative output terminal of the input module in response to the second level state of the input module; The second operator is used to determine the level value of the output terminal of the second operator based on the level value of the positive output terminal of the second trigger and the level value of the negative output terminal of the input module, and output a second signal based on the level value of the output terminal of the second operator.

[0010] Preferably, the second delay module further includes a first frequency multiplication submodule and a third operator, the output end of the second operator is connected to the input end of the first frequency multiplication submodule and the first input end of the third operator respectively, and the output end of the first frequency multiplication submodule is connected to the second input end of the third operator; The first frequency multiplication submodule is used to output a second frequency multiplication signal based on the second signal; wherein the ratio of the frequency of the second frequency multiplication signal to the frequency of the second signal is a preset integer; The third operator is used to determine the level value of the output end of the third operator based on the second frequency-multiplied signal and the level value of the output end of the second operator, and output a fourth signal based on the level value of the output end of the third operator.

[0011] Preferably, the third delay module includes a fourth operator, a second inverter, a second frequency multiplication submodule and a fifth operator, the input end of the fourth operator is respectively connected to the positive output end of the input module and the output end of the second delay module, the output end of the fourth operator is connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the input end of the second frequency multiplication submodule and the first input end of the fifth operator, and the output end of the second frequency multiplication submodule is connected to the second input end of the fifth operator; The fourth operator is used to determine the level value of the output terminal of the fourth operator based on the level value of the positive output terminal of the input module and the level value of the output terminal of the second delay module; The second inverter is used to determine the level value of the output terminal of the second inverter based on the level value of the output terminal of the fourth operator, and output a fifth signal based on the level value of the output terminal of the second inverter; The second frequency multiplication submodule is used to generate a first frequency multiplication signal based on the output signal of the output terminal of the second inverter; wherein the ratio of the frequency of the first frequency multiplication signal to the frequency of the output signal of the output terminal of the second inverter is a preset integer; The fifth operator is used to determine the level value of the output terminal of the fifth operator based on the first frequency multiplication signal and the level value of the output terminal of the second inverter, and output the third signal based on the level value of the output terminal of the fifth operator.

[0012] Preferably, the third delay module further includes a third inverter, a sixth operator, a third frequency multiplication submodule and a seventh operator, the positive output end of the input module is connected to the input end of the third inverter, the input end of the sixth operator is respectively connected to the output end of the third inverter and the output end of the first delay module, the input end of the third frequency multiplication submodule is connected to the output end of the fourth operator, and the input end of the seventh operator is respectively connected to the output end of the third frequency multiplication submodule and the output end of the sixth operator; The third inverter is used to determine the level value of the output terminal of the third inverter based on the level value of the positive output terminal of the input module; The sixth operator is used to determine the level value of the output terminal of the sixth operator based on the level value of the output terminal of the third inverter and the level value of the output terminal of the first delay module; The third frequency multiplication submodule is used to output a third frequency multiplication signal based on the output signal of the output end of the fourth operator; wherein the ratio of the frequency of the third frequency multiplication signal to the frequency of the output signal of the output end of the fourth operator is a preset integer; The seventh operator is used to determine the level value of the output terminal of the seventh operator based on the third frequency-multiplied signal and the level value of the output terminal of the sixth operator, and output a sixth signal based on the level value of the output terminal of the seventh operator.

[0013] Preferably, the first frequency multiplication submodule, the second frequency multiplication submodule and the third frequency multiplication submodule respectively include an eighth operator, a delay submodule and a fourth trigger; the input end of the eighth operator is connected to the data input end of the fourth trigger and the negative output end of the fourth trigger, the output end of the eighth operator is connected to the input end of the delay submodule, and the output end of the delay submodule is connected to the control input end of the fourth trigger.

[0014] Preferably, the delay submodule comprises N inverters connected in series, wherein N is an odd number greater than 1.

[0015] Preferably, the input module includes a signal input terminal and a fifth trigger, the signal input terminal is respectively connected to the control input terminal of the fifth trigger, the control input terminal of the first delay module and the control input terminal of the second delay module, the positive output terminal of the fifth trigger is connected to the input terminal of the third delay module, the input terminal of the first delay module is respectively connected to the data input terminal of the fifth trigger and the positive output terminal of the fifth trigger, and the data input terminal of the fifth trigger is connected to the negative output terminal of the first delay module; The fifth trigger is used to set the level value of the positive output terminal of the fifth trigger to the level value of the negative output terminal of the first delay module based on the first level state of the signal input terminal.

[0016] Preferably, when the frequency of the signal output from the signal input terminal is 50 MHz, the frequencies of the first signal, the second signal and the third signal are 16.667 MHz.

[0017] The frequency division circuit provided in the embodiment of the present application can, on the one hand, use different delay modules to process different output signals of the input module in different ways, so that the duty cycle of each output signal of the frequency division circuit is different, thereby solving the mismatch problem of the frequency division circuit in high-speed and high-precision clock applications; on the other hand, compared with the prior art that uses pulse width modulation technology to compensate for the mismatch problem of the clock control signal, the present application can use digital logic modules to form a frequency division circuit, thereby simplifying the device structure inside the circuit and reducing the design difficulty of the frequency division circuit.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 A schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 2 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 3 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 4 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 5 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 6 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 7 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Figure 8 Another schematic diagram of a frequency division circuit provided in an embodiment of the present application; Fig. 9 A waveform diagram of a three-frequency output signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0021] It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.

[0022] First, the terms involved in this application are explained as follows: (1) Duty cycle: refers to the ratio of the high level duration in a pulse signal to the entire cycle time.

[0023] In the existing field of serializers or deserializers, a high-speed, high-precision clock control signal is required to realize the conversion between a high-speed serial signal and a low-speed parallel signal, and a frequency divider is a commonly used module for designing a clock control signal.

[0024] However, since the characteristics of the internal components of the circuit vary with factors such as process temperature and power supply, the clock control signal with a fixed duty cycle is prone to mismatch (i.e., the clock control signal is not synchronized), which can lead to data transmission errors, timing violations and other problems within the circuit.

[0025] Based on this, pulse width modulation technology can be used to compensate for the mismatch of the clock control signal by adjusting the duty cycle of the clock control signal. However, in order to meet the requirements of high speed and high precision, the comparator used in pulse width modulation technology has high requirements, which makes the circuit design very difficult.

[0026] Therefore, the mismatch problem existing in the existing frequency division circuit in high-speed and high-precision clock applications has become a problem that needs to be solved.

[0027] Based on this, the present application proposes a frequency division circuit, which can use different delay modules to process different output signals of the input module in different ways, so that the duty cycle of each output signal of the frequency division circuit is different, thereby solving the mismatch problem of the frequency division circuit in high-speed and high-precision clock applications.

[0028] Figure 1 is a schematic diagram of a frequency division circuit provided in an embodiment of the present application, such as Figure 1 As shown, the circuit includes: an input module 101, a first delay module 102, a second delay module 103 and a third delay module 104, the control input end of the input module 101 is connected to the control input end of the second delay module 103, the positive output end of the input module 101 is connected to the input end of the third delay module 104, the input end of the first delay module 102 is respectively connected to the data input end of the input module 101 and the positive output end of the input module 101, and the data input end of the input module 101 is connected to the negative output end of the first delay module 102.

[0029] Specifically, the first delay module 102 is used to respond to the first level state of the input module 101 and output a first signal based on the level value of the positive output terminal of the input module 101; the second delay module 103 is used to respond to the second level state of the input module 101 and output a second signal based on the level value of the negative output terminal of the input module 101; wherein the first level state is opposite to the second level state; the third delay module 104 is used to generate a first frequency-doubled signal based on the output signal of the positive output terminal of the input module 101, and output a third signal based on the first frequency-doubled signal; wherein the ratio of the frequency of the first frequency-doubled signal to the frequency of the output signal of the positive output terminal of the input module 101 is a preset integer.

[0030] In an embodiment of the present application, based on the connection status between different output ends of the input module 101 and different delay modules in the frequency division circuit, each delay module can perform different delay processing on different signals output by the input module 101, so that there is a difference in the duration of the high level in the output signal of the output end of each delay module, thereby enabling the output ends of different delay modules to generate clock signals with different duty cycles based on different level values.

[0031] In one possible implementation, the first level state of the input module 101 can be a state in which the output signal changes from a low level to a high level (i.e., a rising edge in the corresponding signal output waveform); the second level state of the input module 101 can be a state in which the output signal changes from a high level to a low level (i.e., a falling edge in the corresponding signal output waveform).

[0032] For example, Figure 2 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 2 As shown, the input module 101 includes a signal input terminal 1011 and a fifth trigger 1012, wherein the signal input terminal 1011 is respectively connected to the control input terminal of the fifth trigger 1012, the control input terminal of the first delay module 102 and the control input terminal of the second delay module 103, the positive output terminal of the fifth trigger 1012 is connected to the input terminal of the third delay module 104, the input terminal of the first delay module 102 is respectively connected to the data input terminal of the fifth trigger 1012 and the positive output terminal of the fifth trigger 1012, and the data input terminal of the fifth trigger 1012 is connected to the negative output terminal of the first delay module 102.

[0033] Specifically, when the input module 101 includes a signal input terminal 1011 and a fifth trigger 1012, the control input terminal of the input module 101 can be the output terminal of the signal input terminal 1011 (i.e., the input terminal of the clock signal input terminal for controlling data storage in the fifth trigger 1012), the data input terminal of the input module 101 can be the input terminal for storing data in the fifth trigger 1012, the positive output terminal of the input module 101 can be the output terminal for storing data in the fifth trigger 1012, and the negative output terminal of the input module 101 can be the non-output terminal for storing data output in the fifth trigger 1012; wherein, the clock signal input terminal for controlling data storage (i.e., the control input terminal), the input terminal for storing data (i.e., the data input terminal), the output terminal for storing data (i.e., the positive output terminal), and the non-output terminal for storing data output (i.e., the negative output terminal) of the fifth trigger 1012 can be respectively represented as the CLK terminal, the D terminal, the Q terminal, and the Q' terminal.

[0034] Exemplarily, the control input terminals of the fifth trigger 1012 , the first delay module 102 , and the second delay module 103 may be used to control the latching of data in the device or module.

[0035] Specifically, the data latch in the device or module can be a positive output terminal outputting the data of the data input terminal; for example, the level value of the positive output terminal can be set to the level value of the data input terminal.

[0036] Based on this, the fifth trigger 1012 can be used to respond to the first level state of the signal input terminal 1011, and output the data of its own data input terminal from its own output terminal (that is, set the level value of its own positive output terminal to the level value of the negative output terminal of the first delay module connected to its own data input terminal).

[0037] For example, the fifth flip-flop 1012 can be a data flip-flop (Data Flip-Flop, referred to as D flip-flop), and the data output by its negative output terminal can be the inverse data of the data output by its positive output terminal, that is, the Q' terminal level value of the fifth flip-flop 1012 can be the inverse level value of the Q terminal level value.

[0038] Exemplarily, the duty cycle of the signal output by the signal input terminal 1011 may be, for example, 50%.

[0039] The frequency division circuit provided in the embodiment of the present application can, on the one hand, use different delay modules to process different output signals of the input module in different ways, so that the duty cycle of each output signal of the frequency division circuit is different, thereby solving the mismatch problem of the frequency division circuit in high-speed and high-precision clock applications; on the other hand, compared with the prior art that uses pulse width modulation technology to compensate for the mismatch problem of the clock control signal, the present application can use digital logic modules to form a frequency division circuit, thereby simplifying the device structure inside the circuit and reducing the design difficulty of the frequency division circuit.

[0040] In another embodiment of the present application, the specific structure of the first delay module 102 is also introduced. For example, Figure 3 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 3 As shown, the first delay module 102 specifically includes a first operator 1021 and a first trigger 1022; wherein, the control input end of the input module 101 is connected to the control input end of the first trigger 1022, the input end of the first operator 1021 is respectively connected to the data input end of the input module 101 and the positive output end of the input module 101, and the output end of the first operator 1021 is connected to the data input end of the first trigger 1022.

[0041] Specifically, the first operator 1021 is used to determine the level value of the output terminal of the first operator 1021 based on the level value of the data input terminal of the input module 101 and the level value of the positive output terminal of the input module 101; the first trigger 1022 is used to respond to the first level state of the input module 101, set the level value of the positive output terminal of the first trigger 1022 to the level value of the output terminal of the first operator 1021, and output a first signal based on the level value of the positive output terminal of the first trigger 1022.

[0042] Exemplary, reference Figure 3 When the first delay module 102 includes a first operator 1021 and a first trigger 1022, the input end of the first delay module 102 may include the first input end, the second input end and the control input end of the first trigger 1022 of the first operator 1021, the output end of the first delay module 102 may be the positive output end of the first trigger 1022, and the negative output end of the first delay module 102 may be the negative output end of the first trigger 1022; wherein the control input end, the data input end, the positive output end and the negative output end of the first trigger 1022 may be represented as the CLK end, the D end, the Q end and the Q' end, respectively.

[0043] Exemplarily, similar to the fifth flip-flop 1012 , the control input terminal, data input terminal, positive output terminal, and negative output terminal of the first flip-flop 1022 may also be represented by a CLK terminal, a D terminal, a Q terminal, and a Q′ terminal.

[0044] Exemplarily, the first operator 1021 may be an AND operator (i.e., an AND operator). When the input module 101 includes the signal input terminal 1011 and the fifth flip-flop 1012, the input terminal of the first operator 1021 may be connected to the D terminal and the Q terminal of the fifth flip-flop 1012, respectively, and the level value of its own output terminal is determined based on the level value of the D terminal and the level value of the Q terminal of the fifth flip-flop 1012.

[0045] Exemplarily, the CLK terminal of the first trigger 1022 can set the level value of the Q terminal to the level value of the D terminal in response to the first level state of the input module 101 (specifically, the state in which the signal output by the signal input terminal 1011 changes from a low level to a high level), and the D terminal of the first trigger 1022 is the output terminal of the first operator 1021. Therefore, the first trigger 1022 can set the level value of the Q terminal to the level value of the output terminal of the first operator 1021, and output the first signal based on the level value of the Q terminal.

[0046] Exemplary, reference Figure 3 In the frequency dividing circuit shown, taking the signal input terminal 1011 outputting a signal with a duty cycle of 50% and a frequency of 50 MHz as an example, the generation process of the first signal outputted from the Q terminal of the first trigger 1022 is specifically described as follows.

[0047] First, the reset terminal Reset in the fifth trigger 1012 and the first trigger 1022 can be used to set the Q terminal of each trigger to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal in the fifth trigger 1012 and the first trigger 1022 is 0, and the level value of the Q' terminal is 1.

[0048] Based on this, the initial level value of the D terminal of the fifth trigger 1012 is 1, and the initial level value of the D terminal of the first trigger 1022 is 0.

[0049] When the output signal of the signal input terminal 1011 is in the first first level state (that is, when the output signal reaches the first rising edge from the initial state of 0), the fifth trigger 1012 and the first trigger 1022 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the fifth trigger 1012 sets the level value of the Q terminal to 1, and the first trigger 1022 sets the level value of the Q terminal to 0. At this time, the level values ​​of the Q' terminal of the fifth trigger 1012 and the first trigger 1022 are 0 and 1 respectively.

[0050] Before the output signal of the signal input terminal 1011 reaches the second first level state (i.e., before the output signal reaches the second rising edge), the D-terminal level value of the fifth trigger 1012 is set to 1 by the Q'-terminal level value of the first trigger 1022, and the D-terminal level value of the first trigger 1022 is set to 1.

[0051] When the output signal of the signal input terminal 1011 is in the second first level state (that is, when the output signal reaches the second rising edge), the fifth trigger 1012 and the first trigger 1022 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the fifth trigger 1012 sets the level value of the Q terminal to 1, and the first trigger 1022 sets the level value of the Q terminal to 1. At this time, the level values ​​of the Q' terminal of the fifth trigger 1012 and the first trigger 1022 are 0 and 0 respectively.

[0052] Before the output signal of the signal input terminal 1011 reaches the first level state for the third time (i.e., before the output signal reaches the third rising edge), the D-terminal level value of the fifth trigger 1012 is set to 0 by the Q'-terminal level value of the first trigger 1022, and the D-terminal level value of the first trigger 1022 is set to 0.

[0053] When the output signal of the signal input terminal 1011 is in the first level state for the third time (that is, when the output signal reaches the third rising edge), the fifth trigger 1012 and the first trigger 1022 respond to the first level state, and respectively set the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the fifth trigger 1012 sets the level value of the Q terminal to 0, and the first trigger 1022 sets the level value of the Q terminal to 0. At this time, the level values ​​of the Q' terminal of the fifth trigger 1012 and the first trigger 1022 are 1 and 1 respectively.

[0054] Before the output signal of the signal input terminal 1011 is in the first level state for the fourth time (i.e., before the output signal reaches the fourth rising edge), the level value of the D terminal of the fifth trigger 1012 is set to 1 by the level value of the Q' terminal of the first trigger 1022, and the level value of the D terminal of the first trigger 1022 is set to 0; wherein, before the output signal reaches the fourth rising edge, the level values ​​of the ports of the fifth trigger 1012 and the first trigger 1022 are restored to the initial set values.

[0055] It can be known that after every three cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the Q terminal of the fifth trigger 1012 first experiences a high level of two cycles of the output signal, and then experiences a low level of one cycle of the output signal; and the Q terminal of the first trigger 1022 first experiences a low level of one cycle of the output signal, and then experiences a high level of one cycle of the output signal, and finally experiences a low level of one cycle of the output signal; then when the signal input terminal 101 continues to output the signal, the Q terminals of the fifth trigger 1012 and the first trigger 1022 both repeat the above-mentioned level change state.

[0056] Based on this, the duty cycle of the first signal outputted from the Q terminal of the first trigger 1022 is 4 / 12.

[0057] In another embodiment of the present application, the specific structure of the second delay module 103 is also introduced. For example, Figure 4 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 4 As shown, the second delay module 103 specifically includes a first inverter 1031, a second trigger 1032 and a second operator 1033, wherein the control input terminal of the input module 101 is connected to the input terminal of the first inverter 1031, the output terminal of the first inverter 1031 is connected to the control input terminal of the second trigger 1032, the negative output terminal of the input module 101 is connected to the data input terminal of the second trigger 1032, and the input terminal of the second operator 1033 is respectively connected to the negative output terminal of the input module 101 and the positive output terminal of the second trigger 1032.

[0058] Specifically, the second trigger 1032 is used to set the level value of the positive output terminal of the second trigger 1032 to the level value of the negative output terminal of the input module 101 in response to the second level state of the input module 101; the second operator 1033 is used to determine the level value of the output terminal of the second operator 1033 based on the level value of the positive output terminal of the second trigger 1032 and the level value of the negative output terminal of the input module 101, and output a second signal based on the level value of the output terminal of the second operator 1033.

[0059] Exemplarily, the first inverter 1031 may be used to receive a first level state of an output signal of the input module 101 and invert the first level state to a second level state, so that the second delay module 103 outputs a second signal in response to the second level state.

[0060] Specifically, when the input module 101 includes the signal input terminal 1011 and the fifth trigger 1012, the signal input terminal 1011 can be connected to the input terminal of the first inverter 1031, so that the first inverter 1031 inverts the first level state of the signal input terminal 1011 to the second level state.

[0061] Exemplarily, similar to the fifth flip-flop 1012 , the control input terminal, data input terminal, positive output terminal and negative output terminal of the second flip-flop 1032 may also be represented by the CLK terminal, D terminal, Q terminal and Q′ terminal.

[0062] Specifically, the CLK terminal of the second flip-flop 1032 can set the level value of its Q terminal to the level value of the Q′ terminal of the fifth flip-flop 1012 in response to the inversion signal of the first inverter 1031 (ie, the second level state of the signal input terminal 1011 ).

[0063] Exemplarily, the second operator 1033 may be an OR operator (i.e., an OR operator). When the input module 101 includes the fifth trigger 1012, the input end of the second operator 1033 may be connected to the Q' end of the fifth trigger 1012 and the Q end of the second trigger 1032, respectively, and the level value of its own output end is determined based on the level value of the Q' end of the fifth trigger 1012 and the Q end of the second trigger 1032, and the second signal is output based on the level value of its own output end.

[0064] Exemplary, reference Figure 4 In the frequency dividing circuit shown, taking the signal input terminal 1011 outputting a signal with a duty cycle of 50% and a frequency of 50 MHz as an example, the generation process of the second signal outputted from the output terminal of the second operator 1033 is specifically described as follows.

[0065] First, the reset terminal Reset of the second flip-flop 1032 can be used to set the Q terminal of the second flip-flop 1032 to a low level and the Q′ terminal to a high level, that is, the level value of the Q terminal of the second flip-flop 1032 is 0, and the level value of the Q′ terminal is 1.

[0066] Based on the specific process that the Q terminal of the fifth trigger 1012 first experiences a high level of two cycles of the output signal and then experiences a low level of one cycle length of the output signal every three cycles of the output signal at the signal input terminal 1011 with a frequency of 50 MHz: when the output signal of the signal input terminal 1011 is in the second level state for the first time (that is, when the output signal reaches the first falling edge from the initial state of 0), the second trigger 1032 sets the level value of the Q terminal to the level value of the Q' terminal of the fifth trigger 1012 in response to the second level state, that is, the second trigger 1032 sets the level value of the Q terminal to 0.

[0067] When the output signal of the signal input terminal 1011 is in the second level state for the second time (that is, when the output signal reaches the second falling edge), the second trigger 1032 sets the level value of the Q terminal to the level value of the Q' terminal of the fifth trigger 1012 in response to the second level state, that is, the second trigger 1032 sets the level value of the Q terminal to 0.

[0068] When the output signal of the signal input terminal 1011 is in the second level state for the third time (that is, when the output signal reaches the third falling edge), the second trigger 1032 sets the level value of the Q terminal to the level value of the Q' terminal of the fifth trigger 1012 in response to the second level state, that is, the second trigger 1032 sets the level value of the Q terminal to 1.

[0069] When the output signal of the signal input terminal 1011 is in the second level state for the fourth time (i.e., when the output signal reaches the fourth falling edge), the second trigger 1032 sets the level value of the Q terminal to the level value of the Q' terminal of the fifth trigger 1012 in response to the second level state, that is, the second trigger 1032 sets the level value of the Q terminal to 0.

[0070] It can be known that after every three cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the Q terminal of the second trigger 1032 first experiences a low level of the length of two cycles of the output signal, and then experiences a high level of the length of one cycle of the output signal; wherein, the length of one cycle of the output signal of the signal input terminal 1011 is the time from one falling edge to the next falling edge.

[0071] Based on this, when the second operator 1033 uses the Q-terminal level value of the second trigger 1032 and the Q'-terminal level value of the fifth trigger 1012 to determine the level value of its own output terminal, when the output signal of the signal input terminal 1011 is between the first and third first level states (that is, when the output signal is between the first rising edge and the third rising edge), the Q-terminal level value of the second trigger 1032 and the Q'-terminal level value of the fifth trigger 1012 are both 0, and therefore, the level value of the output terminal of the second operator 1033 is also 0 in this stage.

[0072] When the output signal of the signal input terminal 1011 is between the third first level state and the third second level state (that is, when the output signal is between the third rising edge and the third falling edge), the level value of the Q terminal of the second trigger 1032 is 0, and the level value of the Q' terminal of the fifth trigger 1012 is 1, therefore, the level value of the output terminal of the second operator 1033 is 1 in this stage.

[0073] When the output signal of the signal input terminal 1011 is between the third second level state and the fourth first level state (that is, when the output signal is between the third falling edge and the fourth rising edge), the level value of the Q terminal of the second trigger 1032 is 1, and the level value of the Q' terminal of the fifth trigger 1012 is 1, therefore, the level value of the output terminal of the second operator 1033 is also 1 in this stage.

[0074] When the output signal of the signal input terminal 1011 is between the fourth first level state and the fourth second level state (that is, when the output signal is between the fourth rising edge and the fourth falling edge), the level value of the Q end of the second trigger 1032 is 1, and the level value of the Q' end of the fifth trigger 1012 is 0. Therefore, the level value of the output end of the second operator 1033 is also 1 in this stage.

[0075] When the output signal of the signal input terminal 1011 is in the fourth second level state (that is, when the output signal reaches the fourth falling edge), the level value of the Q' terminal of the fifth trigger 1012 is 0, and the second trigger 1032 sets the level value of its own Q terminal to 0 in response to the second level state. Therefore, the level value of the output terminal of the second operator 1033 is 0.

[0076] It can be known that after every three rising edge cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the output terminal of the second operator 1033 first experiences a low level with a length of 1.5 cycles of the output signal, and then experiences a high level with a length of 1.5 cycles of the output signal; then when the signal input terminal 1011 continues to output the signal, the output terminal of the second operator 1033 repeats the above level change state.

[0077] Based on this, the duty cycle of the second signal outputted from the output terminal of the second operator 1033 is 6 / 12.

[0078] In another embodiment of the present application, other components of the second delay module 103 are also introduced. For example, Figure 5 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 5 As shown, the second delay module 103 also includes a first frequency multiplication submodule 1034 and a third operator 1035, wherein the output end of the second operator 1033 is respectively connected to the input end of the first frequency multiplication submodule 1034 and the first input end of the third operator 1035, and the output end of the first frequency multiplication submodule 1034 is connected to the second input end of the third operator 1035.

[0079] Specifically, the first frequency multiplication submodule 1034 is used to output a second frequency multiplication signal based on the second signal, wherein the ratio of the frequency of the second frequency multiplication signal to the frequency of the second signal is a preset integer; the third operator 1035 is used to determine the level value of the output end of the third operator 1035 based on the second frequency multiplication signal and the level value of the output end of the second operator 1033, and output the fourth signal based on the level value of the output end of the third operator 1035. For example, the third operator 1035 can be an AND operator (i.e., an AND operator).

[0080] For example, Figure 6 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 6 As shown, the first frequency multiplication submodule 1034 may include an eighth operator 601, a delay submodule 602 and a fourth trigger 603; wherein the first input terminal and the second input terminal of the eighth operator 601 are respectively connected to the data input terminal of the fourth trigger 603 and the negative output terminal of the fourth trigger 603, the third input terminal of the eighth operator 601 is the input terminal of the first frequency multiplication submodule 1034, the output terminal of the eighth operator 601 is connected to the input terminal of the delay submodule 603, and the output terminal of the delay submodule 603 is connected to the control input terminal of the fourth trigger 603.

[0081] Exemplarily, the eighth operator 601 may be an exclusive OR operator (ie, an XOR operator).

[0082] Exemplarily, similar to the fifth flip-flop 1012 , the control input terminal, data input terminal, positive output terminal and negative output terminal of the fourth flip-flop 603 may also be represented by the CLK terminal, D terminal, Q terminal and Q′ terminal.

[0083] Specifically, refer to Figure 6 , the output end of the second operator 1033 is the third input end of the eighth operator 601, and the output end of the first frequency multiplication submodule 1034 is specifically the output end of the delay submodule 602. For example, the delay submodule 602 includes N inverters connected in series, wherein the delay submodule 602 can be an odd number greater than 1.

[0084] It should be noted that the delay submodule 602 included in the first frequency multiplication submodule 1034 may also be referred to as an inverter odd-numbered series sequence (INV_ODD_SEQ), and the number of inverter series sequences included in the inverter odd-numbered series sequence may be 1045.

[0085] Exemplary, reference Figure 6In the frequency division circuit shown, the output of the second operator 1033 is used as the input of the first frequency multiplication submodule 1034. Taking the signal duty cycle of the signal output from the signal input terminal 1011 as 50% and the frequency as 50 MHz as an example, the generation process of the fourth signal output from the output terminal of the third operator 1035 is specifically described as follows.

[0086] First, the reset terminal Reset of the fourth trigger 603 can be used to set the Q terminal of the fourth trigger 603 to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal of the fourth trigger 603 is 0, and the level value of the Q' terminal is 1; the delay value of the delay submodule 602 can be equal to one half of the high level duration time within the unit period of the input signal of the first frequency doubling submodule 1034. For example, when the frequency division circuit is a three-frequency division circuit, the delay value of the delay submodule 602 can be equal to three quarters of the period of the output signal of the signal input terminal 1011.

[0087] Based on the initial state of the input signal of the first frequency multiplication submodule 1034 (i.e., the signal input at one end of the eighth operator 601) being 0 and the level value of the Q' end of the fourth trigger 603, the level value of the initial state of the output end of the eighth operator 601 is 1; based on this, the level value of the initial state of the output end of the delay submodule 602 is 0, and the level value of the initial state of the data input end of the fourth trigger 603 is 1.

[0088] When the input signal of the first frequency multiplication submodule 1034 is in the first first level state (ie, when the input signal reaches the first rising edge from the initial state of 0), the level values ​​of the two input terminals of the eighth operator 601 are both 1, and the level value of the output terminal is 0.

[0089] After a delay of half the duration of the high level within the unit period of the input signal of the first frequency doubling submodule 1034, the level value of the output end of the delay submodule 602 is set to 1; then, the CLK end of the fourth trigger 603 responds to the first level state, and sets the level value of the Q end to the level value of the D end at the previous moment, that is, the fourth trigger 603 sets the level value of the Q end to 1, and the level value of the Q' end of the fourth trigger 603 is 0 at this time; based on this, the state of the input signal of the first frequency doubling submodule 1034 is still 1, and the level value of the output end of the eighth operator 601 is 1.

[0090] After a delay of half the high level duration in the unit cycle of the input signal of the first frequency multiplication submodule 1034, the level state of the CLK terminal of the fourth trigger 603 jumps to 0. At this time, the input signal of the first frequency multiplication submodule 1034 reaches a falling edge.

[0091] When the input signal of the first frequency multiplication submodule 1034 is in the first second level state (ie, when the input signal reaches the first falling edge), the level values ​​of the two input terminals of the eighth operator 601 are both 0, and the level value of the output terminal is 0.

[0092] After a delay of half the duration of the high level within the unit period of the input signal of the first frequency doubling submodule 1034, the level value of the output end of the delay submodule 602 is set to 1; then, the CLK end of the fourth trigger 603 responds to the first level state, and sets the level value of the Q end to the level value of the D end at the previous moment, that is, the fourth trigger 603 sets the level value of the Q end to 0, and at this time the level value of the Q' end of the fourth trigger 603 is 1; based on this, the state of the input signal of the first frequency doubling submodule 1034 is still 0, and the level value of the output end of the eighth operator 601 is 1.

[0093] After a delay of half the duration of the high level within the unit cycle of the input signal of the first frequency multiplication submodule 1034, the level state of the CLK terminal of the fourth trigger 603 jumps to 0. At this time, the input signal of the first frequency multiplication submodule 1034 also reaches the next rising edge, and the above process is repeated.

[0094] It can be known that, after every three rising edge cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the output terminal of the first frequency multiplication submodule 1034 (i.e., the first input terminal of the third operator 1035) first experiences a low level for 0.75 cycles of the output signal, then experiences a high level for 0.75 cycles of the output signal, then experiences a low level for 0.75 cycles of the output signal, and finally experiences a high level for 0.75 cycles of the output signal.

[0095] Therefore, based on the fact that every time the output signal of the signal input terminal 1011 with a frequency of 50 MHz passes through three cycles, the output terminal of the second operator 1033 (i.e., the second input terminal of the third operator 1035) first experiences a low level for 1.5 cycles of the output signal, and then experiences a high level for 1.5 cycles of the output signal, and the output terminal of the third operator 1035 first experiences a low level for 0.75 cycles of the output signal, and then experiences a high level for 0.75 cycles of the output signal, and finally experiences a low level for 1.5 cycles of the output signal; then when the signal input terminal 1011 continues to output the signal, the output terminal of the third operator 1035 repeats the above-mentioned level change state.

[0096] Based on this, the duty cycle of the fourth signal outputted from the output terminal of the third operator 1035 is 3 / 12.

[0097] In another embodiment of the present application, the specific structure of the third delay module 104 is also introduced. For example, Figure 7 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 7 As shown, the third delay module 104 includes a fourth operator 1041, a second inverter 1042, a second frequency multiplication submodule 1043 and a fifth operator 1044, wherein the input end of the fourth operator 1041 is respectively connected to the positive output end of the input module 101 and the output end of the second delay module 103, the output end of the fourth operator 1041 is connected to the input end of the second inverter 1042, the output end of the second inverter 1042 is respectively connected to the input end of the second frequency multiplication submodule 1043 and the first input end of the fifth operator 1044, and the output end of the second frequency multiplication submodule 1043 is connected to the second input end of the fifth operator 1044.

[0098] Specifically, the fourth operator 1041 is used to determine the level value of the output end of the fourth operator 1041 based on the level value of the positive output end of the input module 101 and the level value of the output end of the second delay module 103; the second inverter 1042 is used to determine the level value of the output end of the second inverter 1042 based on the level value of the output end of the fourth operator 1041, and output the fifth signal based on the level value of the output end of the second inverter 1042; the second frequency doubling submodule 1043 is used to generate a first frequency doubling signal based on the output signal of the output end of the second inverter 1042; wherein the ratio of the frequency of the first frequency doubling signal to the frequency of the output signal of the output end of the second inverter 1042 is a preset integer; the fifth operator 1044 is used to determine the level value of the output end of the fifth operator 1044 based on the first frequency doubling signal and the level value of the output end of the second inverter 1042, and output the third signal based on the level value of the output end of the fifth operator 1044.

[0099] Exemplarily, the fourth operator 1041 may be an OR operator (ie, an OR operator); and the fifth operator 1044 may be an AND operator (ie, an AND operator).

[0100] Exemplarily, similar to the first frequency multiplication submodule 1034, the second frequency multiplication submodule 1043 may also include an eighth operator 701, a delay submodule 702 and a fourth trigger 703, wherein the first input terminal and the second input terminal of the eighth operator 701 are respectively connected to the data input terminal of the fourth trigger 703 and the negative output terminal of the fourth trigger 703, the third input terminal of the eighth operator 701 is the input terminal of the second frequency multiplication submodule 1043, the output terminal of the eighth operator 701 is connected to the input terminal of the delay submodule 703, and the output terminal of the delay submodule 703 is connected to the control input terminal of the fourth trigger 703.

[0101] Specifically, refer to Figure 7 , the output end of the second inverter 1042 is the third input end of the eighth operator 701, and the output end of the second frequency multiplication submodule 1043 is specifically the output end of the delay submodule 702. For example, the delay submodule 702 includes N inverters connected in series, wherein the delay submodule 702 can be an odd number greater than 1.

[0102] It should be noted that the delay submodule 702 included in the second frequency multiplication submodule 1043 may also be referred to as an inverter odd-numbered series sequence (INV_ODD_SEQ), and the number of inverter series sequences included in the inverter odd-numbered series sequence may be 349.

[0103] Exemplarily, based on the input module 101 including a signal input terminal 1011 and a fifth trigger 1012, and the second delay module 103 including a first inverter 1031, a second trigger 1032 and a second operator 1033, the input terminal of the fourth operator 1041 can be respectively connected to the Q terminal of the fifth trigger 1012 in the input module 101 and the Q terminal of the second trigger 1032 in the second delay module 103.

[0104] Based on this, every time the output signal of the signal input terminal 1011 with a frequency of 50 MHz passes through three cycles, the Q terminal of the fifth trigger 1012 first experiences a high level of two cycle lengths of the output signal, and then experiences a low level of one cycle length of the output signal, and the Q terminal of the second trigger 1032 first experiences a high level of 0.5 cycle length of the output signal, and then experiences a low level of 2 cycle lengths of the output signal, and finally experiences a high level of 0.5 cycle length of the output signal. It can be known that the output terminal of the fourth operator 1041 first experiences a high level of 2 cycle lengths of the output signal, and then experiences a low level of 0.5 cycle length of the output signal, and finally experiences a low level of 0.5 cycle length of the output signal.

[0105] Therefore, the duty cycle of the fifth signal outputted from the output terminal of the second inverter 1042 is 2 / 12.

[0106] Exemplary, reference Figure 7 The frequency dividing circuit shown, combined with the duty cycle of the fifth signal output from the output end of the second inverter 1042 being 2 / 12, the generation process of the third signal output from the output end of the fifth operator 1044 is specifically described as follows.

[0107] First, the reset terminal Reset of the fourth trigger 703 can be used to set the Q terminal of the fourth trigger 703 to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal of the fourth trigger 703 is 0, and the level value of the Q' terminal is 1; the delay value of the delay submodule 702 can be equal to one half of the high level duration time within a unit period of the input signal of the second frequency doubling submodule 1043. For example, when the frequency division circuit is a three-frequency division circuit, the delay value of the delay submodule 702 can be equal to one quarter of the period of the output signal of the signal input terminal 1011.

[0108] Based on the initial state of the input signal of the second frequency multiplication submodule 1043 (i.e., the signal input at one end of the eighth operator 701) being 0 and the level value of the Q' end of the fourth trigger 703, the level value of the initial state of the output end of the eighth operator 701 is 1; based on this, the level value of the initial state of the output end of the delay submodule 702 is 0, and the level value of the initial state of the data input end of the fourth trigger 703 is 1.

[0109] When the input signal of the second frequency multiplication submodule 1043 is in the first first level state (ie, when the input signal reaches the first rising edge from the initial state of 0), the level values ​​of the two input terminals of the eighth operator 701 are both 1, and the level value of the output terminal is 0.

[0110] After a delay of half the duration of the high level within the unit period of the input signal of the second frequency doubling submodule 1043, the level value of the output end of the delay submodule 702 is set to 1; then, the CLK end of the fourth trigger 703 responds to the first level state, and sets the level value of the Q end to the level value of the D end at the previous moment, that is, the fourth trigger 703 sets the level value of the Q end to 1, and the level value of the Q' end of the fourth trigger 703 is 0 at this time; based on this, the state of the input signal of the second frequency doubling submodule 1043 is still 1, and the level value of the output end of the eighth operator 701 is 1.

[0111] After a delay of half the high level duration in the unit cycle of the input signal of the second frequency multiplication submodule 1043, the level state of the CLK terminal of the fourth trigger 703 jumps to 0. At this time, the input signal of the second frequency multiplication submodule 1043 reaches a falling edge.

[0112] When the input signal of the second frequency multiplication submodule 1043 is in the first second level state (ie, when the input signal reaches the first falling edge), the level values ​​of the two input terminals of the eighth operator 701 are both 0, and the level value of the output terminal is 0.

[0113] After a delay of half the duration of the high level within the unit period of the input signal of the second frequency doubling submodule 1043, the level value of the output end of the delay submodule 702 is set to 1; then, the CLK end of the fourth trigger 703 responds to the first level state, and sets the level value of the Q end to the level value of the D end at the previous moment, that is, the fourth trigger 703 sets the level value of the Q end to 0, and the level value of the Q' end of the fourth trigger 703 is 1 at this time; based on this, the state of the input signal of the second frequency doubling submodule 1043 is still 0, and the level value of the output end of the eighth operator 701 is 1.

[0114] After a delay of half the duration of the high level within the unit cycle of the input signal of the second frequency multiplication submodule 1043, the level state of the CLK terminal of the fourth trigger 703 jumps to 0. At this time, the input signal of the second frequency multiplication submodule 1043 has experienced one-third of the low level, and the level state of each signal remains unchanged for the next two-thirds of the time.

[0115] It can be known that, after every three rising edge cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the output terminal of the second frequency multiplication submodule 1043 (i.e., the first input terminal of the fifth operator 1044) first experiences a low level for 0.25 cycle length of the output signal, then experiences a high level for 0.25 cycle length of the output signal, then experiences a low level for 0.25 cycle length of the output signal, then experiences a high level for 0.25 cycle length of the output signal, and finally experiences a high level for 2 cycle lengths of the output signal.

[0116] Therefore, in combination with the above-mentioned output signal of the signal input terminal 1011 with a frequency of 50 MHz, every time after three cycles, the output terminal of the second inverter 1042 (i.e., the second input terminal of the fifth operator 1044) first experiences a high level for 0.5 cycles of the output signal, and then experiences a low level for 2.5 cycles of the output signal; the output terminal of the fifth operator 1044 first experiences a low level for 0.25 cycles of the output signal, and then experiences a high level for 0.25 cycles of the output signal, and finally experiences a low level for 2.5 cycles of the output signal; then when the signal input terminal 1011 continues to output the signal, the output terminal of the fifth operator 1044 repeats the above-mentioned level change state.

[0117] Based on this, the duty cycle of the third signal outputted from the output terminal of the fifth operator 1044 is 1 / 12.

[0118] In another embodiment of the present application, other components of the third delay module 104 are also introduced. For example, Figure 8 is another schematic diagram of the frequency division circuit provided in the embodiment of the present application, such as Figure 8As shown, the third delay module 104 also includes a third inverter 1045, a sixth operator 1046, a third frequency multiplication sub-module 1047 and a seventh operator 1048, the positive output end of the input module 101 is connected to the input end of the third inverter 1045, the input end of the sixth operator 1046 is respectively connected to the output end of the third inverter 1045 and the output end of the first delay module 102, the input end of the third frequency multiplication sub-module 1047 is connected to the output end of the fourth operator 1041, and the input end of the seventh operator 1048 is respectively connected to the output end of the third frequency multiplication sub-module 1047 and the output end of the sixth operator 1046.

[0119] Specifically, the third inverter 1045 is used to determine the level value of the output end of the third inverter 1045 based on the level value of the positive output end of the input module 101; the sixth operator 1046 is used to determine the level value of the output end of the sixth operator 1046 based on the level value of the output end of the third inverter 1045 and the level value of the output end of the first delay module 102; the third frequency multiplication submodule 1047 is used to output a third frequency multiplication signal based on the output signal of the output end of the fourth operator 1041; wherein the ratio of the frequency of the third frequency multiplication signal to the frequency of the output signal of the output end of the fourth operator 1041 is a preset integer; the seventh operator 1048 is used to determine the level value of the output end of the seventh operator 1048 based on the third frequency multiplication signal and the level value of the output end of the sixth operator 1046, and output the sixth signal based on the level value of the output end of the seventh operator 1048.

[0120] Exemplarily, the sixth operator 1046 may be an OR operator (ie, an OR operator); and the seventh operator 1048 may be an AND operator (ie, an AND operator).

[0121] Exemplarily, similar to the first frequency multiplication submodule 1034, the third frequency multiplication submodule 1047 may also include an eighth operator 801, a delay submodule 802 and a fourth trigger 803, wherein the first input terminal and the second input terminal of the eighth operator 801 are respectively connected to the data input terminal of the fourth trigger 803 and the negative output terminal of the fourth trigger 803, the third input terminal of the eighth operator 801 is the input terminal of the third frequency multiplication submodule 1047, the output terminal of the eighth operator 701 is connected to the input terminal of the delay submodule 703, and the output terminal of the delay submodule 703 is connected to the control input terminal of the fourth trigger 703.

[0122] Specifically, refer to Figure 8, the output end of the fourth operator 1041 is the third input end of the eighth operator 801, and the output end of the third frequency multiplication submodule 1047 is specifically the output end of the delay submodule 802. For example, the delay submodule 802 includes N inverters connected in series, wherein the delay submodule 802 can be an odd number greater than 1.

[0123] It should be noted that the delay submodule 802 included in the third frequency multiplication submodule 1047 may also be referred to as an inverter odd-numbered series sequence (INV_ODD_SEQ), and the number of inverter series sequences included in the inverter odd-numbered series sequence may be 1741.

[0124] Exemplarily, based on the input module 101 including the signal input terminal 1011 and the fifth trigger 1012, and the first delay module 102 including the first operator 1021 and the first trigger 1022, the input terminal of the third inverter 1045 can be connected to the Q terminal of the fifth trigger 1012, and the input terminal of the sixth operator 1046 can be connected to the output terminal of the third inverter 1045 and the Q terminal of the first trigger 1022, respectively.

[0125] Based on this, every time the output signal of the signal input terminal 1011 with a frequency of 50 MHz passes through three cycles, the Q terminal of the fifth trigger 1012 first experiences a high level for the length of two cycles of the output signal, and then experiences a low level for the length of one cycle of the output signal. It can be known that the output terminal of the third inverter 1045 first experiences a low level for the length of two cycles of the output signal, and then experiences a high level for the length of one cycle of the output signal.

[0126] In combination with the fact that every time the output signal of the signal input terminal 1011 with a frequency of 50 MHz passes through three cycles, the Q terminal of the first trigger 1022 first experiences a low level of the length of the cycle of the output signal, then experiences a high level of the length of the cycle of the output signal, and finally experiences a low level of the length of the cycle of the output signal. It can be known that the output terminal of the sixth operator 1046 first experiences a low level of the length of the cycle of the output signal, and then experiences a high level of the length of two cycles of the output signal.

[0127] Exemplary, reference Figure 8 The frequency dividing circuit shown, combined with the duty cycle of the signal output from the output end of the fourth operator 1041 being 10 / 12, the generation process of the sixth signal output from the output end of the seventh operator 1048 is specifically described as follows.

[0128] First, the reset terminal Reset of the fourth trigger 803 can be used to set the Q terminal of the fourth trigger 803 to a low level and the Q' terminal to a high level, that is, the level value of the Q terminal of the fourth trigger 803 is 0, and the level value of the Q' terminal is 1; the delay value of the delay submodule 802 can be equal to one-half of the high level duration time within a unit period of the input signal of the third frequency multiplication submodule 1047. For example, when the frequency division circuit is a three-frequency division circuit, the delay value of the delay submodule 802 can be equal to one-fourths of the period of the output signal of the signal input terminal 1011.

[0129] Based on the initial state of the input signal of the third frequency multiplication sub-module 1047 (i.e., the signal input at one end of the eighth operator 801) being 0 and the level value of the Q' end of the fourth trigger 803, the level value of the initial state of the output end of the eighth operator 801 is 1; based on this, the level value of the initial state of the output end of the delay sub-module 802 is 0, and the level value of the initial state of the data input end of the fourth trigger 803 is 1.

[0130] When the input signal of the third frequency multiplication submodule 1047 is in the first first level state (ie, when the input signal reaches the first rising edge from the initial state of 0), the level values ​​of the two input terminals of the eighth operator 801 are both 1, and the level value of the output terminal is 0.

[0131] After a delay of half the duration of the high level within the unit period of the input signal of the third frequency multiplication submodule 1047, the level value of the output end of the delay submodule 802 is set to 1; then, the CLK end of the fourth trigger 803 responds to the first level state, and sets the level value of the Q end to the level value of the D end at the previous moment, that is, the fourth trigger 803 sets the level value of the Q end to 1, and the level value of the Q' end of the fourth trigger 803 is 0 at this time; based on this, the state of the input signal of the third frequency multiplication submodule 1047 is still 1, and the level value of the output end of the eighth operator 801 is 1.

[0132] After a delay of half the high level duration in the unit cycle of the input signal of the third frequency multiplication submodule 1047, the level state of the CLK terminal of the fourth trigger 803 jumps to 0. At this time, the input signal of the third frequency multiplication submodule 1047 reaches the falling edge.

[0133] When the input signal of the third frequency multiplication submodule 1047 is in the first second level state (ie, when the input signal reaches the first falling edge), the level values ​​of the two input terminals of the eighth operator 801 are both 0, and the level value of the output terminal is 0.

[0134] It should be noted that since the low-level maintenance time of the input signal of the third frequency multiplication sub-module 1047 is less than half of the high-level duration time of the input signal of the third frequency multiplication sub-module 1047 within a unit period, the second rising edge of the input signal of the third frequency multiplication sub-module 1047 arrives before the level value of the output end of the delay sub-module 802 is set to 1. At this time, the output end of the eighth operator 801 is set to 1, and at the same time, the signal is transmitted to the CLK end of the fourth trigger 803 through the delay sub-module 802.

[0135] Specifically, the level value of the output terminal of the delay submodule 802 jumps from 0 to 1 at 1.25 cycles of the output signal of the signal input terminal 1011 after the first falling edge of the input signal of the third frequency multiplication submodule 1047 arrives. Based on this, the CLK terminal of the fourth trigger 803 responds to the first level state and sets the level value of the Q terminal to the level value of the D terminal at the previous moment, that is, the fourth trigger 803 sets the level value of the Q terminal to 0, and at this time, the level value of the Q' terminal of the fourth trigger 803 is 1; then, the level value of the output terminal of the eighth operator 801 is 0.

[0136] After another 0.5 cycle of the output signal of the signal input terminal 1011, under the influence of the second rising edge of the third frequency multiplication submodule 1047, the level value of the output terminal of the delay submodule 802 is set to 0. At this time, the level values ​​of the input terminal and the output terminal of the eighth operator 801 remain unchanged.

[0137] After another 0.75 cycles of the output signal of the signal input terminal 1011, under the influence of the first falling edge of the third frequency multiplication sub-module 1047, the output change of the output terminal of the eighth operator 801 sets the level value of the CLK terminal of the delay sub-module 802 to 1 to form a rising edge, thereby setting the Q terminal of the fourth trigger 803 to 1, setting the Q' terminal of the fourth trigger 803 to 0, and setting the output terminal of the eighth operator 801 to 1.

[0138] After a delay of half the duration of the high level in the unit period of the input signal of the third frequency multiplication submodule 1047 , the level state of the CLK terminal of the fourth trigger 803 jumps to 0, thereby forming a periodic cycle.

[0139] It can be known that, after every three rising edge cycles of the output signal of the signal input terminal 1011 with a frequency of 50 MHz, the output terminal of the third frequency multiplication submodule 1047 (i.e., the first input terminal of the seventh operator 1048) first experiences a low level for 0.25 of the cycle length of the output signal, then experiences a high level for 0.5 of the cycle length of the output signal, and then experiences a low level for 0.75 of the cycle length of the output signal, and then experiences a high level for 1.25 of the cycle length of the output signal, and finally experiences a low level for 0.25 of the cycle length of the output signal.

[0140] Therefore, in combination with the above-mentioned output signal of the signal input terminal 1011 with a frequency of 50 MHz, every time after three cycles, the output terminal of the sixth operator 1046 (i.e., the second input terminal of the seventh operator 1048) first experiences a low level for the length of one cycle of the output signal, and then experiences a high level for the length of two cycles of the output signal; the output terminal of the seventh operator 1048 first experiences a low level for the length of 1.5 cycles of the output signal, and then experiences a high level for the length of 1.25 cycles of the output signal, and finally experiences a low level for the length of 0.25 cycles of the output signal; then when the signal input terminal 1011 continues to output the signal, the output terminal of the seventh operator 1048 repeats the above-mentioned level change state.

[0141] Based on this, the duty cycle of the sixth signal outputted from the output terminal of the seventh operator 1048 is 5 / 12.

[0142] In another embodiment of the present application, a waveform diagram of the output signal of the frequency division circuit is also provided. Exemplarily, when the frequency of the output signal of the signal input terminal 1011 is 50 MHz, the frequencies of the first signal, the second signal, the third signal, the fourth signal, the fifth signal and the sixth signal can be 16.667 MHz, that is, the frequency division circuit provided in the embodiment of the present application is a three-frequency division circuit.

[0143] Specifically, Fig. 9 is a waveform diagram of a three-frequency output signal provided in an embodiment of the present application, such as Fig. 9 As shown, waveform a can be used to represent the waveform diagram of the signal output from the signal input terminal 1011; waveform b can be used to represent the waveform diagram of the third signal output from the output terminal of the fifth operator 1044, that is, it can be used to represent a 3-frequency divided signal with a duty cycle of 1 / 12; waveform c can be used to represent the waveform diagram of the fifth signal output from the output terminal of the second inverter 1042, that is, it can be used to represent a 3-frequency divided signal with a duty cycle of 2 / 12; waveform d can be used to represent the fourth signal output from the output terminal of the third operator 1035, That is, it can be used to represent a 3-frequency divided signal with a duty cycle of 3 / 12; waveform e can be used to represent the first signal output from the Q end of the first trigger 1022, that is, it can be used to represent a 3-frequency divided signal with a duty cycle of 4 / 12; waveform f can be used to represent the sixth signal output from the output end of the seventh operator 1048, that is, it can be used to represent a 3-frequency divided signal with a duty cycle of 5 / 12; waveform g can be used to represent the second signal output from the output end of the second operator 1033, that is, it can be used to represent a 3-frequency divided signal with a duty cycle of 6 / 12.

[0144] In the embodiment of the present application, by combining and connecting different computing devices inside the circuit, the duty cycle of the circuit output signal can be expanded, thereby reducing the circuit design cost and expanding the application scope of the frequency division circuit.

[0145] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A frequency division circuit, characterized in that: It includes an input module, a first delay module, a second delay module and a third delay module, The control input end of the input module is connected to the control input end of the second delay module, the positive output end of the input module is connected to the input end of the third delay module, the input end of the first delay module is connected to the data input end of the input module and the positive output end of the input module respectively, and the data input end of the input module is connected to the negative output end of the first delay module; The first delay module is used for, in response to a first level state of the input module, outputting a first signal based on a level value of a positive output terminal of the input module; The second delay module is used to output a second signal based on the level value of the negative output terminal of the input module in response to the second level state of the input module; wherein the first level state is opposite to the second level state; The third delay module is used to generate a first frequency-doubled signal based on the output signal of the positive output end of the input module, and output a third signal based on the first frequency-doubled signal; wherein the ratio of the frequency of the first frequency-doubled signal to the frequency of the output signal of the positive output end of the input module is a preset integer.

2. The frequency division circuit according to claim 1, characterized in that: The first delay module includes a first operator and a first trigger, the control input end of the input module is connected to the control input end of the first trigger, the input end of the first operator is respectively connected to the data input end of the input module and the positive output end of the input module, and the output end of the first operator is connected to the data input end of the first trigger; The first operator is used to determine the level value of the output terminal of the first operator based on the level value of the data input terminal of the input module and the level value of the positive output terminal of the input module; The first trigger is used to set the level value of the positive output terminal of the first trigger to the level value of the output terminal of the first operator in response to the first level state of the input module, and output a first signal based on the level value of the positive output terminal of the first trigger.

3. The frequency division circuit according to claim 1, characterized in that: The second delay module includes a first inverter, a second trigger and a second operator, the control input end of the input module is connected to the input end of the first inverter, the output end of the first inverter is connected to the control input end of the second trigger, the negative output end of the input module is connected to the data input end of the second trigger, and the input end of the second operator is respectively connected to the negative output end of the input module and the positive output end of the second trigger; The second trigger is used to set the level value of the positive output terminal of the second trigger to the level value of the negative output terminal of the input module in response to the second level state of the input module; The second operator is used to determine the level value of the output end of the second operator based on the level value of the positive output end of the second trigger and the level value of the negative output end of the input module, and output a second signal based on the level value of the output end of the second operator.

4. The frequency division circuit according to claim 3, characterized in that: The second delay module further includes a first frequency multiplication submodule and a third operator, the output end of the second operator is respectively connected to the input end of the first frequency multiplication submodule and the first input end of the third operator, and the output end of the first frequency multiplication submodule is connected to the second input end of the third operator; The first frequency multiplication submodule is used to output a second frequency multiplication signal based on the second signal; wherein the ratio of the frequency of the second frequency multiplication signal to the frequency of the second signal is a preset integer; The third operator is used to determine the level value of the output end of the third operator based on the second frequency-multiplied signal and the level value of the output end of the second operator, and output a fourth signal based on the level value of the output end of the third operator.

5. The frequency division circuit according to claim 1, characterized in that: The third delay module includes a fourth operator, a second inverter, a second frequency multiplication submodule and a fifth operator, the input end of the fourth operator is respectively connected to the positive output end of the input module and the output end of the second delay module, the output end of the fourth operator is connected to the input end of the second inverter, the output end of the second inverter is respectively connected to the input end of the second frequency multiplication submodule and the first input end of the fifth operator, and the output end of the second frequency multiplication submodule is connected to the second input end of the fifth operator; The fourth operator is used to determine the level value of the output end of the fourth operator based on the level value of the positive output end of the input module and the level value of the output end of the second delay module; The second inverter is used to determine the level value of the output terminal of the second inverter based on the level value of the output terminal of the fourth operator, and output a fifth signal based on the level value of the output terminal of the second inverter; The second frequency multiplication submodule is used to generate a first frequency multiplication signal based on the output signal of the output terminal of the second inverter; wherein the ratio of the frequency of the first frequency multiplication signal to the frequency of the output signal of the output terminal of the second inverter is a preset integer; The fifth operator is used to determine the level value of the output end of the fifth operator based on the level value of the first frequency-multiplied signal and the output end of the second inverter, and output a third signal based on the level value of the output end of the fifth operator.

6. The frequency division circuit according to claim 5, characterized in that: The third delay module also includes a third inverter, a sixth operator, a third frequency multiplication submodule and a seventh operator, the positive output end of the input module is connected to the input end of the third inverter, the input end of the sixth operator is respectively connected to the output end of the third inverter and the output end of the first delay module, the input end of the third frequency multiplication submodule is connected to the output end of the fourth operator, and the input end of the seventh operator is respectively connected to the output end of the third frequency multiplication submodule and the output end of the sixth operator; The third inverter is used to determine the level value of the output terminal of the third inverter based on the level value of the positive output terminal of the input module; The sixth operator is used to determine the level value of the output end of the sixth operator based on the level value of the output end of the third inverter and the level value of the output end of the first delay module; The third frequency multiplication submodule is used to output a third frequency multiplication signal based on the output signal of the output end of the fourth operator; wherein the ratio of the frequency of the third frequency multiplication signal to the frequency of the output signal of the output end of the fourth operator is a preset integer; The seventh operator is used to determine the level value of the output end of the seventh operator based on the third frequency-multiplied signal and the level value of the output end of the sixth operator, and output a sixth signal based on the level value of the output end of the seventh operator.

7. The frequency division circuit according to any one of claims 4 to 6, characterized in that: The first frequency multiplication submodule, the second frequency multiplication submodule and the third frequency multiplication submodule respectively include an eighth operator, a delay submodule and a fourth trigger; the input end of the eighth operator is connected to the data input end of the fourth trigger and the negative output end of the fourth trigger, the output end of the eighth operator is connected to the input end of the delay submodule, and the output end of the delay submodule is connected to the control input end of the fourth trigger.

8. The frequency division circuit according to claim 7, characterized in that: The delay submodule includes N inverters connected in series, wherein N is an odd number greater than 1.

9. The frequency division circuit according to claim 1, characterized in that: The input module includes a signal input terminal and a fifth trigger, the signal input terminal is respectively connected to the control input terminal of the fifth trigger, the control input terminal of the first delay module and the control input terminal of the second delay module, the positive output terminal of the fifth trigger is connected to the input terminal of the third delay module, the input terminal of the first delay module is respectively connected to the data input terminal of the fifth trigger and the positive output terminal of the fifth trigger, and the data input terminal of the fifth trigger is connected to the negative output terminal of the first delay module; The fifth trigger is used for setting the level value of the positive output terminal of the fifth trigger to the level value of the negative output terminal of the first delay module in response to the first level state of the signal input terminal.

10. The frequency division circuit according to claim 9, characterized in that: When the frequency of the signal output from the signal input terminal is 50 MHz, the frequencies of the first signal, the second signal, and the third signal are 16.667 MHz.

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