Pixel circuit and image sensor

Abstract

The invention relates to a pixel circuit and an image sensor. A pixel circuit including a transistor, a barrier layer, and an output circuit is disclosed. The transistor includes a first doped region and a second doped region disposed on opposite sides of a channel of the transistor proximate a first surface of a semiconductor substrate such that photocarriers generated inside the semiconductor substrate in response to incident light flow into one of the first and second doped regions. The barrier layer is disposed between the other of the first and second doped regions and a second surface of the semiconductor substrate opposite the first surface. The barrier layer is configured to block the photocarriers from directly flowing into the other of the first doped region and the second doped region. The output circuit outputs an image signal according to a voltage signal output from the transistor.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and an image sensor operating in a solar cell mode. Background Art

[0002] In image sensors, it is desirable to increase the dynamic range. For this purpose, image sensors operating in solar cell mode using the logarithmic characteristics of diodes are known, and the dynamic range can be increased.

[0003] US serial number 20210084243A1 describes an example of a configuration of an image sensor operating in a solar cell mode. Note that logarithmic characteristics are also called diode characteristics or exponential function characteristics, and a mode using these characteristics is called a solar cell mode.

[0004] If light is incident on a pixel of an image sensor, carriers (electrons or holes) are generated by the light. The generated carriers move to the pn junction and recombine at the crystal defects on its surface, and the photovoltage generated at the output of the pixel is determined by the recombination speed of the carriers. In addition, the recombination speed is related to the energy level of the crystal defects and the number of crystal defects.

[0005] On the other hand, crystal defects on the pn junction surface vary greatly depending on the manufacturing method. Therefore, a change occurs in the VI curve, which indicates the relationship between the photovoltage generated from the pixel and the photocurrent caused by the movement of carriers in the pixel, and the output from the pixel will vary. In an image sensor in which pixels are arranged two-dimensionally, such a change in each of the pixels acts as a fixed pattern noise. In addition, as the number of pixels decreases, the change tends to increase, and thus the problem is exacerbated when obtaining a high-resolution image. Summary of the invention

[0006] One aspect of the present disclosure provides a pixel circuit of an image sensor, the pixel circuit comprising a phototransistor, a blocking layer, and an output circuit. The phototransistor includes a source and a drain, which are disposed on opposite sides of a channel near a first surface (e.g., a front surface) of a semiconductor substrate, so that photocarriers generated inside the semiconductor substrate due to incident light flow into one region of the source and the drain. The phototransistor outputs a voltage signal from the one region of the source and the drain. The blocking layer is disposed below another region of the drain and the source, and away from the far side of the surface portion of the channel formed near the first surface. The blocking layer may be disposed between the other region of the drain and the source and a second surface (e.g., a back surface) of the semiconductor substrate, wherein the second surface is opposite to the first surface. The blocking layer blocks the photocarriers from directly flowing into the other region of the drain or the source. The output circuit outputs an image signal according to the voltage signal output from the phototransistor. The phototransistor allows a subthreshold current to flow between the source and the drain while the phototransistor operates in a pinched state wherein photocarriers travel through a bulk channel region of the channel at a location away from the first surface of the semiconductor substrate.

[0007] Another aspect of the present disclosure provides a pixel circuit of an image sensor, the pixel circuit comprising a photodiode, a transistor, a blocking layer and an output circuit. The transistor includes a gate electrode, a first doped region and a second doped region. The first doped region and the second doped region are disposed on opposite sides of a channel of the transistor near a first surface of a semiconductor substrate, so that photocarriers generated inside the semiconductor substrate in response to incident light flow into the second doped region. The transistor is coupled to output a voltage signal from the first doped region, wherein the voltage signal is generated in response to the amount of photocarriers generated. The blocking layer is disposed in the semiconductor substrate between the second doped region and a second surface of the semiconductor substrate opposite to the first surface. The blocking layer operates to block the photocarriers from flowing directly into the second doped region.

[0008] In some embodiments, the photodiode is disposed on a first semiconductor substrate and the transistor is disposed or otherwise fabricated on a second semiconductor substrate, wherein the first semiconductor substrate is bonded or otherwise coupled to the second semiconductor substrate. In some embodiments, the blocking layer and the output circuit may be disposed on the first semiconductor substrate. In other embodiments, the blocking layer may be omitted from the first semiconductor substrate.

[0009] Each of the first doped region and the second doped region has a first conductivity type opposite to a second conductivity type of the barrier layer. The first conductivity type may be an N type, and the second conductivity type may be a P type.

[0010] A further aspect of the present disclosure provides a pixel circuit of an image sensor, the pixel circuit comprising a photodiode, a pinch transistor and an output circuit. The photodiode is formed in a p-type doped germanium (Ge) region. The photodiode has a pn junction sensitive to infrared rays and is configured to generate photocarriers in response to incident light. The pinch transistor is formed on a silicon (Si) substrate, and the pinch transistor is configured to electrically couple the photodiode to the output circuit. The pinch transistor includes a source and a drain, which are disposed on opposite sides of a channel near a first surface of the Si substrate, so that photocarriers from the photodiode are received in one region of the source and the drain. The output circuit is disposed on the Si substrate, and is coupled to output an image signal according to a voltage signal output from the one region of the source and the drain of the pinch transistor. The one region of the pinch transistor is configured to generate the voltage signal based on the amount of photocarriers generated. The pinch-off transistor allows the flow of a subthreshold current in a pinch-off state, wherein photocarriers pass through a bulk channel region of the channel at a location away from the surface of the Si substrate.

[0011] In some embodiments, the p-type Ge region is coupled or otherwise adjusted to have a negative voltage relative to a voltage of the Si substrate (eg, a ground reference voltage).

[0012] In some embodiments, the blocking layer is disposed in the Si substrate between the drain and a second surface of the Si substrate opposite to the first surface. The blocking layer operates to block the photocarriers from flowing directly into the drain.

[0013] It should be understood that if no photoelectric conversion occurs within the silicon substrate, the blocking layer may be omitted. For example, in embodiments where the photodiode is formed on a SiGe substrate bonded to the Si substrate on which the pinch transistor is formed via a bonding scheme (e.g., an oxide bonding or a hybrid bonding scheme), in such embodiments, the blocking layer may be omitted from the silicon substrate.

[0014] Furthermore, another aspect of the present disclosure relates to an image sensor using the above-mentioned pixel circuit.

[0015] In yet another aspect of the present disclosure, an image sensor is provided that includes one or more pixel circuits described above that are arranged to form a pixel array.

[0016] According to the present disclosure, an image sensor operating in a solar cell mode can be obtained, and variations in the pixel circuit can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all examples of components must be labeled to avoid obscuring the drawings where appropriate. The drawings are not necessarily drawn to scale, emphasis instead being placed on illustrating the principles being described.

[0018] Figure 1 is a view illustrating a configuration of a pixel circuit of an image sensor according to an embodiment of the present disclosure.

[0019] Figure 2 is a schematic diagram illustrating the configuration of a phototransistor according to an embodiment of the present disclosure.

[0020] Figure 3A is a graph for describing a photocurrent in a photodiode in a solar cell mode according to an embodiment of the present disclosure.

[0021] Figure 3B is a diagram illustrating VI characteristics of a photodiode in a solar cell mode according to an embodiment of the present disclosure.

[0022] Figure 4 2 is a diagram illustrating VI characteristics of a phototransistor and a photodiode according to an embodiment of the present disclosure.

[0023] Figure 5 The configuration of an example of an integrating circuit using a p-channel FET according to an embodiment of the present disclosure is described.

[0024] Figure 6 is a timing diagram illustrating the operation of a phototransistor, an integration circuit, and an output circuit according to an embodiment of the present disclosure.

[0025] Figure 7 2 is an explanatory diagram illustrating the potential of each portion of a phototransistor and a p-channel transistor according to an embodiment of the present disclosure.

[0026] Figure 8 The configuration of an example of an integrating circuit using n-channel FETs according to an embodiment of the present disclosure is described.

[0027] Fig. 9 A modification of the phototransistor according to the embodiment of the present disclosure is described.

[0028] Fig.10 is an operation timing diagram of a modified phototransistor according to an embodiment of the present disclosure.

[0029] Fig.11 is a cross-sectional view illustrating a configuration in which a germanium (Ge) substrate and a silicon substrate including a pinch-off transistor are separately provided according to an embodiment of the present disclosure.

[0030] Fig. 12A A configuration in which a Ge photodiode is embedded in an n-type diffusion layer coupled to a source electrode of a pinch transistor according to an embodiment of the present disclosure is described.

[0031] Fig. 12B A configuration in which a Ge photodiode is formed in an upper portion of an n-type diffusion layer according to an embodiment of the present disclosure is described.

[0032] Fig. 12C A configuration in which a Ge photodiode is disposed on the rear surface side of a silicon substrate according to an embodiment of the present disclosure is described.

[0033] Fig.13 is a block diagram showing the structure of an image sensor according to an embodiment of the present disclosure.

[0034] Throughout the multiple views of the drawings, corresponding reference symbols indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. In addition, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate a more unimpeded viewing of these different embodiments of the present invention. DETAILED DESCRIPTION

[0035] Various examples are described herein involving an imaging sensor having a pixel array including a plurality of pixel circuits, each of which has a phototransistor operating in a solar cell mode. In various examples, such a phototransistor biased to operate in a clamped state has the same meaning as a clamped transistor and is interchangeable. Hereinafter, the present invention describes providing reduced image lag. In the following description, many specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details, or using other methods, components, materials, etc. In other examples, in order to avoid making certain aspects unclear, well-known structures, materials, or operations are not shown or described in detail.

[0036] The term "comprises, comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process or method comprising a series of steps includes not only those steps, but may also include other steps that are not explicitly listed or inherent to such a process or method. Similarly, in the absence of more constraints, one or more devices or subsystems or elements or structures or components beginning with "including ... one" do not exclude the presence of other devices or other subsystems or other elements or other structures or other components or additional devices or additional subsystems or additional elements or additional structures or additional components. As used herein, when preceding a list of elements, expressions such as "at least one of" modify the entire list of elements without modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0037] Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification is not necessarily referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0038] For ease of description, spatially relative terms such as "below", "below", "above", "down", "above", "up", "top", "bottom", "left", "right", "center", "middle" and the like may be used herein to describe the relationship of one element or feature to another (or some) element or feature as illustrated in the figure. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figure. For example, if the device in the figure is rotated or flipped, then the element described as being "below" or "below" or "below" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, the exemplary terms "below" and "down" can cover both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there can also be one or more intervening elements.

[0039] It should be understood that the term "semiconductor substrate" throughout the present disclosure may correspond to a portion or the entirety of a semiconductor wafer (eg, a silicon wafer).

[0040] Throughout this specification, several terms are used. These terms have their ordinary meaning in the fields from which they are derived, unless explicitly defined herein or the context of their use clearly indicates otherwise. It should be noted that component names and symbols can be used interchangeably throughout this document (e.g., Si and silicon); however, both have the same meaning.

[0041] (Pixel circuit configuration)

[0042] Figure 1 1 is a diagram illustrating a configuration of a pixel circuit of an image sensor according to an embodiment of the present disclosure. The pixel circuit 1 may be included in a plurality of pixel circuits in a pixel array of the image sensor. In various examples, the pixel array is a two-dimensional (2D) array including a plurality of pixel circuits 1, which are arranged in rows and columns to acquire image data of a person, place, scene, object, etc., which can then be used to present an image of the person, place, scene, object, etc.

[0043] The pixel circuit 1 may include a phototransistor 10, an integration circuit 12 and an output circuit 14. Figure 1 In an embodiment of the invention, the phototransistor 10 is configured as an n-channel field effect transistor (FET) disposed on a semiconductor substrate. In addition, photocarriers (e.g., electrons) generated by the incidence of light enter the source S of the phototransistor 10 from a pn junction formed in the semiconductor substrate, and the source voltage decreases relative to the amount of light incident on the phototransistor 10. In the same or different embodiments, a pn junction may be formed between the source S of the phototransistor 10 and a substrate region of the semiconductor substrate surrounding the source S of the phototransistor 10. The drain D of the phototransistor 10 may be electrically coupled to a voltage source Vbias to receive a bias voltage. Note that in the figure, the voltage generated at the source S due to the introduction of one or more electrons is illustrated as a voltage signal. Note that, as will be described later, the phototransistor 10 is configured to operate in a clamped state, for example, during an integration or exposure period of a pixel circuit, and a subthreshold current flows to a body channel region within a channel of the phototransistor 10, which is not a depletion region, and thus a logarithmic characteristic is obtained in the source S in response to the number of electrons introduced into the source S by incidence of light. In other words, the phototransistor 10 operates in a solar cell mode (also referred to as a photovoltaic mode).

[0044] The source S of the phototransistor 10 is electrically connected to an integration circuit 12 to output an image signal based on a photocurrent (or the amount of photocarriers) generated in response to the incident light received. The integration circuit 12 integrates the output from the source S of the phototransistor 10 for a certain period of time and outputs a stable voltage. The integration circuit 12 is electrically connected to an output circuit 14. The output circuit 14 may include a source follower transistor 14a and a row selection transistor 14b. The output of the integration circuit 12 is electrically connected to the gate of the source follower transistor 14a for signal amplification. The source follower transistor 14a may be an n-channel FET, wherein its drain is electrically connected to a power supply having a specified or predefined potential, and its source is electrically connected to the drain of the row selection transistor 14b. In some embodiments, the source of the source follower transistor 14a and the drain of the row selection transistor 14b may be formed as a common junction region. The row selection transistor 14b may be an n-channel FET, wherein its drain is connected to an output line 18 (e.g., a readout bit line) arranged in the column direction of the pixel array.

[0045] Therefore, when the row selection transistor 14b is turned on by, for example, a row selection signal, a current corresponding to the gate potential of the source follower transistor 14a flows into the source follower transistor 14a, and the corresponding image signal is output to the output line 18. In an embodiment, the row selection signal is supplied to the gate of the row selection transistor 14b, and by causing the row selection signal to become an H level at a prescribed timing to turn on the row selection transistor 14b, the image signal corresponding to the amount of light received by the pixel that has been integrated by the integration circuit 12 is output to the output line 18 for signal readout.

[0046] [Configuration of phototransistor]

[0047] Figure 2 1 is a partial cross-sectional schematic diagram illustrating the configuration of a single phototransistor 10 in a pixel circuit that may be included in a plurality of pixel circuits in a pixel array of an image sensor. The phototransistor 10 is a metal oxide semiconductor field effect transistor (MOSFET). The phototransistor 10 includes a gate electrode 116, a gate oxide film 118, a drain 102, a source 104, and a barrier layer 108. It should be understood that certain elements may be omitted or not labeled (e.g., contacts to the gate electrode 116, optical elements such as color filters, microlenses, and metal layers for signal routing, other portions of the pixel circuitry, such as Figure 5 and Figure 8 ), so as to avoid obscuring certain aspects of the present disclosure.

[0048] The phototransistor 10 is disposed on a semiconductor substrate 100. In the illustrated example, the semiconductor substrate 100 is a semiconductor substrate doped with p-type impurities, which may be referred to as a p-type doped semiconductor substrate and may be represented as p-sub, however in other examples, the semiconductor substrate 100 may be an n-type doped semiconductor substrate. It should be understood that the semiconductor substrate 100 may be a silicon substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from a III-V group compound, other suitable semiconductor materials or alloys, combinations thereof, bulk substrates thereof, or wafers thereof. It should be understood that the semiconductor substrate 100 may also be an epitaxial substrate. More specifically, the semiconductor substrate 100 may correspond to any semiconductor material or combination of materials that may be doped or otherwise configured as a plurality of pixel circuits of a pixel array comprising an image sensor. In one embodiment, the semiconductor substrate 100 is formed of intrinsic or extrinsic silicon having regions that are sufficiently doped to form a plurality of phototransistors 10. It should be further understood that in some embodiments, the semiconductor substrate 100 may have at least a semiconductor layer epitaxially grown thereon (e.g., formed via epitaxial techniques). In such embodiments, the phototransistor 10 is formed in the semiconductor layer. The semiconductor substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a. In the same or different embodiments, the first surface 100a may be referred to as a non-illuminated surface of the semiconductor substrate 100, and the second surface 100b may be referred to as an illuminated surface of the semiconductor substrate 100.

[0049] In some embodiments, the semiconductor substrate 100 may include a semiconductor layer, such as an epitaxial layer grown on the semiconductor substrate 100. In such embodiments, the drain 102, the source 104, and the barrier layer 108 may be formed in the epitaxial layer via ion implantation or otherwise disposed in the epitaxial layer on the semiconductor substrate 100. The first surface 100a may then be referred to as a surface of the epitaxial layer opposite to the second surface 100b.

[0050] The gate electrode 116 is disposed near the first surface 100a of the semiconductor substrate 100. In the illustrated embodiment, a gate oxide is disposed between the gate electrode 116 and the first surface 100a of the semiconductor substrate 100. On the first surface 100a of the p-type semiconductor substrate 100, the source 104 and the drain 102 are formed at a prescribed distance via photolithography and ion implantation processes. The gate electrode 116 is configured to couple the source 104 to the drain 102.

[0051] The source 104 and the drain 102 are disposed in the semiconductor substrate 100, for example, by ion implantation. Each of the source 104 and the drain 102 may be a doped region having a conductivity type opposite to that of the semiconductor substrate 100. In some embodiments, the source 104 and the drain 102 are semiconductor regions doped with a high concentration of n-type impurities in the semiconductor substrate 100. Each of the source 104 and the drain 102 may be referred to as an n+ doped region. The region between the source 104 and the drain 102 is a channel 106 formed under the gate electrode 116 in the semiconductor substrate 100.

[0052] The blocking layer 108 is a doped region in the semiconductor substrate 100, and the blocking layer 108 has a conductivity type different from the conductivity type of each of the source 104 and the drain 102. The blocking layer 108 may have the same conductivity type as the semiconductor substrate 100. In various examples, the blocking layer 108 is a region of the semiconductor substrate 100 doped with a high concentration of p-type impurities. The blocking layer 108 may have an impurity concentration that is at least one order of magnitude or magnitude higher than the impurity concentration of the semiconductor substrate 100. In some embodiments, the impurity concentration of the blocking layer 108 may be configured to be the same as the impurity concentration of the drain 102. In some embodiments, the impurity concentration of the blocking layer 108 may be configured to be higher than the impurity concentration of the drain 102.

[0053] The blocking layer 108 may be disposed between the drain 102 and the second surface 100b of the semiconductor substrate 100. The blocking layer 108 may span a spatial region in the semiconductor substrate 100 that is located i) below the drain 102 and ii) between the drain and the source 104. In an embodiment, the blocking layer 108 may be disposed below the drain 102 and the channel 106 so that when the phototransistor 10 is operated in a pinched state, one or more photocarriers 120 (e.g., electrons) generated from the source 104 flow through the bulk channel region 106B of the channel 106 into the drain 102 and are absorbed by the drain 102, as illustrated by the example path 121, rather than flowing directly to the drain 102. That is, the blocking layer 108 is operable to block photocarriers 120 (e.g., electrons) from flowing directly to the drain 102, wherein the photocarriers 120 (e.g., electrons) are generated in response to incident light 20 received incident on the detection region of the phototransistor 10 through the second surface 100b of the semiconductor substrate 100. In one example, the blocking layer 108 is operable to form a junction isolation with the drain 102, thereby providing electrical isolation between the drain 102 and the region of the semiconductor substrate 100 between the blocking layer 108 and the second surface 100b within the detection region of the phototransistor 10. In an embodiment, the body channel region 106B of the channel 106 of the phototransistor 10 is a non-depleted body channel region in the semiconductor substrate 100, which is located away from the first surface 100a and between the pinch-off region 106P of the channel 106 and the blocking layer 108 in the semiconductor substrate 100.

[0054] In example operation, during an integration or exposure period, the gate electrode 116 is coupled to receive a gate voltage of zero or ground reference voltage, and the drain 102 is coupled to constantly receive a bias voltage greater than the gate voltage, so that the phototransistor 10 operates in a pinched state. In the pinched state, a body channel region 106B formed in the region of the channel 106 is formed to operably couple the source 104 and the drain 102, such that a flow of a subthreshold current (or an off leakage current) between the source 104 and the drain 102 allows photocarriers 120 to flow from the source 104 to the drain 102 through the body channel region 106B without recombination in the source 104, wherein the flow of the subthreshold current (or the off leakage current) between the source 104 and the drain 102 is exponentially related to the number of one or more photocarriers (e.g., photocarriers 120) generated in the source.

[0055] In some embodiments, the barrier layer 108 has a second region width W greater than the drain 102. D The first area width W BL. The blocking layer 108 may be disposed at a depth D1 that is less than a junction depth JD1 of the drain 102. The blocking layer 108 may have a junction depth JD2 that is greater than the junction depth JD1. The depth difference between the junction depth JD2 and the depth D1 provides a regional thickness in a depth direction for the blocking layer 108. In some embodiments, the blocking layer 108 overlaps a portion of the drain 102 in a substrate thickness or depth direction. In some embodiments, the blocking layer 108 is formed to cover the drain 102 and the lower side region of the channel 106. In some embodiments, the blocking layer 108 may be arranged to extend laterally and directly contact an edge of the source 104 to ensure that the generated one or more photocarriers 120 (e.g., electrons) flow from the source 104 to the drain 102 through the body channel region 106B of the channel 106 of the phototransistor 10. In the semiconductor substrate 100, a region of the phototransistor 10 is isolated from a region adjacent to the phototransistor 10 by a pixel isolation portion 110.

[0056] The source contact 114 is disposed on the first surface 100a directly contacting the upper surface 104US of the source 104 to electrically connect the source 104. The source contact 114 can electrically connect the source 104 to the amplifier of the integration circuit 12. The drain contact 112 is disposed on the first surface 100a and contacts the upper surface 102US of the drain 102 to electrically connect the drain 102 to a bias voltage (e.g., provided by a voltage source Vbias).

[0057] In the example described above, the semiconductor substrate 100 is a p-type silicon substrate (marked as p-sub in the figure). The pixel isolation portion 110 may be formed of an insulating material (e.g., silicon oxide). In some embodiments, each of the pixel isolation portions 110 is a trench isolation structure. The pixel isolation portions 110 may be interconnected to form a grid of a plurality of pixel regions defining a pixel circuit within a pixel array for an image sensor. The phototransistor 10 is disposed in a corresponding one of the plurality of pixel regions. Each of the pixel isolation portions 110 may extend from the second surface 110b to a depth in the semiconductor substrate 100 that is less than the thickness of the semiconductor substrate 100. The thickness of the semiconductor substrate may be in the range of 3 microns to 7 microns. One or more layers including a surface passivation layer, an anti-reflective coating, a processing protection layer (e.g., an oxide-based stress buffer layer) a color filter layer, and a microlens may be formed on the second surface 100b.

[0058] The source contact 114 and the drain contact 112 are formed of a metal such as tungsten, copper or aluminum. The gate electrode 116 is formed of polysilicon, a silicide material or a metal. A gate oxide film 118 is disposed between the gate electrode 116 and the first surface 100a of the semiconductor substrate 100. The gate oxide film 118 may have a thickness in a depth direction ranging from 20 angstroms to 80 angstroms.

[0059] In the illustrated embodiment, the p-type semiconductor substrate 100 is connected to a prescribed low voltage power source (eg, ground) to which holes generated by the incidence of light flow.

[0060] [Photodiode in solar cell mode]

[0061] Figure 3A is a diagram for describing the photocurrent in a photodiode in a solar cell mode. The photodiode includes an n-type doped region 32 and a p-type doped region 34. The n-type doped region 32 is surrounded by the p-type doped region 34, wherein the outer periphery of the n-type doped region 32 and the p-type doped region 34 forms a pn junction of the photodiode. The photodiode is configured to operate in a solar cell or photovoltaic mode. In this way, photocarriers (in this example, electrons) generated inside the photodiode recombine with holes located on the surface of or near the n-region represented by "x" in the figure, thereby causing photocurrent to flow.

[0062] The VI characteristic of a photodiode can be expressed as follows

[0063]

[0064] Where I is the output current, q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, V is the generated signal voltage at the source 104, and N is denoted as the emission coefficient.

[0065] In addition, the emission coefficient N is determined according to the density and state of surface defects of the semiconductor substrate 100, but the state of the surface defects varies depending on the photodiode manufacturing process. It has been observed that the emission coefficient N may have a deviation in the range from 1 to 2.

[0066] Figure 3B is a diagram illustrating the VI characteristics of a photodiode in solar cell mode. In the figure, the horizontal or x-axis represents the cathode node voltage or n-type doped region 32 (where the left side is in the + or positive direction and the right side is in the - or negative direction), and the vertical or y-axis represents the amount of photocurrent. In this way, a slight current flows in the opposite direction until the cathode node voltage reaches 0, and the current is 0 when the voltage is 0. Thereafter, as the cathode node voltage drops below 0, the photocurrent increases exponentially. At this point, the VI characteristics of the photodiode change depending on the value of N.

[0067] (Phototransistor in solar cell mode)

[0068] Figure 4is a graph illustrating the VI characteristics of the phototransistor 10 and the photodiode. The pinched state of the phototransistor 10 is a state in which the gate voltage is sufficiently low (e.g., lower than the bias voltage to the drain 102), and the characteristics are similar to those of a photodiode operating in a state of a high source voltage, but the drain current begins to flow before the source voltage reaches 0 V, the current is 0 amperes when the source voltage is between 0.1 and 0.2 V, and thereafter the drain current increases exponentially as the source voltage becomes increasingly negative. In other words, the phototransistor 10 in the pinched state operates in a solar cell mode, similar to a photodiode in which a pn junction is formed between the source 104 of the phototransistor 10 and the semiconductor substrate 100, as shown in FIG. Figure 2 As described in .

[0069] Return to reference Figure 2 , which illustrates the movement of photocarriers (in this example, electrons) when operating in the solar cell mode. In this way, in response to the amount of incident light 20 received, electrons generated by photoelectric conversion in the semiconductor substrate 100 flow into the source 104 of the phototransistor 10. In addition, the electrons flow into the drain 102 through the non-depleted body channel region separated from the pinch interface. In other words, the subthreshold current or the off-leakage current flows through the body channel region 106B. Note that, as previously described, the presence of the blocking layer 108 blocks the electrons generated inside the semiconductor substrate 100 from flowing directly into the drain 102.

[0070] In addition, if Figure 4 As explained in FIG. 1 , when the emission coefficient N=1, the subthreshold current of the phototransistor 10 in the pinched state does not change or varies. The output variation is considered to be suppressed because the subthreshold current is independent of carrier recombination due to surface defects.

[0071] At this point, when the diffusion length L of photocarriers (in this case, electrons) in the non-depleted body channel region is longer than the distance between the source 104 and the drain 102 , the photocarriers flow into the drain 102 through the non-depleted body channel region.

[0072] The diffusion length L is approximately 1 μm to 100 μm, depending on the crystallinity of the body channel region in the semiconductor substrate 100. Since it is sufficiently longer than the length between the miniaturized source (e.g., source 104) and the drain (e.g., drain 102), the subthreshold current does not disappear in the body channel region (e.g., body channel region 106B). On the other hand, when the lateral distance between the source (e.g., source 104) and the drain (e.g., drain 102) is shorter than the depth of the body channel (e.g., channel 106), the emission coefficient N becomes greater than 1 due to the short channel effect, resulting in a change in the VI characteristics. In the present embodiment, the phototransistor 10 is configured so that an appropriate distance is obtained between the source (e.g., source 104) and the drain (e.g., drain 102).

[0073] (Integrating circuit 12)

[0074] Figure 5 An example circuit system configuration of an integration circuit 12 using a p-channel FET is illustrated. The integration circuit 12 includes a p-channel transistor 122, a switch transistor 124, and an integration capacitor 126. The source of the p-channel transistor 122 is connected to a power supply PSI. The source of the switch transistor 124 is connected to the drain of the p-channel transistor 122. The integration capacitor 126 is connected to the drain of the switch transistor 124. In an embodiment, both the p-channel transistor 122 and the switch transistor 124 are p-channel FETs.

[0075] The gate of the p-channel transistor 122 is connected to the source of the phototransistor 10, and allows the flow of current according to the source voltage of the output phototransistor 10. In other words, a current corresponding to the amount of incident light 20 incident on the phototransistor 10 flows from the p-channel transistor 122. The signal SW_sig is supplied to the gate of the switching transistor 124. The signal SW_sig may be configured and output by a control circuit (not illustrated) in the image sensor. When the voltage of the integration capacitor 126 is read out, the signal SW_sig may be operatively turned off.

[0076] (Pixel Circuit Operation)

[0077] Figure 6 is a timing diagram illustrating an exemplary operation of a pixel circuit. Figure 2 and Figure 7 refer to Figure 6 . Figure 7 Diagrams are shown illustrating exemplary potential configurations for each portion of a phototransistor and a p-channel transistor according to an embodiment of the present disclosure.

[0078] like Figure 6, the drain 102 (labeled D in the figure) of the phototransistor 10 can be set to a constant positive bias voltage. For example, a constant voltage of 0.4V is applied to the drain 102 through the drain contact 112. It should be understood that, as illustrated by the dotted line in the figure, the drain 102 can also be set to 0.4V only during the reset period, and is set to 0.8V in some embodiments.

[0079] The gate electrode 116 (labeled as G in the figure) is biased by a control signal that turns the phototransistor 10 on to a high level in a reset period before the integration of the amount of incident light (e.g., incident light 20) begins (e.g., before time t0). Using this configuration, the source 104 is first reset to the same voltage as the drain 102 (e.g., 0.4V). In addition, the control voltage applied to the gate electrode 116 (labeled as G in the figure) via the control signal is set to a negative voltage level (e.g., -1V or other negative voltage levels that turn off the phototransistor 10 depending on the associated electrical characteristics of the phototransistor 10). Using this configuration, the phototransistor 10 is completely turned off and enters a pinch-off state. It should be understood that the voltage level of the control signal applied to the gate electrode 116 and the bias voltage applied to the drain 102 can be configured to other suitable voltage levels that provide a flow of a subthreshold current for an electron movement path from the source 104 to the drain 106 during the integration period when the phototransistor 10 operates in the pinch-off state.

[0080] In the clamped state, in response to light (eg, incident on the phototransistor 10 (eg, through the second surface 100 b of the semiconductor substrate 100 or an illumination surface) (eg, Figure 2 The electrons generated by the incident light 20) enter the source region from the pn junction, causing the source voltage at the source 104 to drop. Figure 7 As illustrated on the left side of , the introduction of electrons into the source 104 results in a change in the voltage source and the generation of a corresponding voltage signal Sig, and the potential drops from a preset voltage (eg, 0.4 V).

[0081] Here, depending on the operational needs, the drain 102 as illustrated may be configured to be 0.4V (or 0.8V), causing electrons to move from the lower voltage source 104 toward the drain 102. This movement of electrons is a subthreshold current or an off leakage current, and is the current described above that changes exponentially depending on the amount of photocarriers 120 generated in response to the incident light 20. For this reason, the source voltage changes logarithmically with respect to the movement of electrons generated by the photoelectric conversion.

[0082] The gate of the p-channel transistor 122 is connected to the source 104 of the phototransistor 10 .

[0083] Next, the integration operation will be described. Figure 6and 7 The timing in the four stages from (i) to (iv) is explained, and thus each stage will be described.

[0084] (i) In operation, the power supply PSI of the integration circuit 12 is configured to briefly become an H level (e.g., 2 V) during a reset period (e.g., before time t0). At this time, the phototransistor 10 is pulsed on via a control signal at the gate electrode 116 (marked as G in the figure), so that the source of the phototransistor 10 is at 0.4 V, which is the same voltage as the drain 102. Then, the p-channel transistor 122 is configured to be turned on, and the potential of the channel and its source also becomes high at a voltage of 2 V. In other words, holes are supplied from the drain of the p-channel transistor 122 to the source of the p-channel transistor 122 to which the integration capacitor 126 is connected. In addition, since the signal SW_sig is at an L level and the switch transistor 124 is also turned on, the integration capacitor 126 is set to the voltage level (e.g., 2 V) supplied by the power supply PSI.

[0085] (ii) Next, after time t0, the power supply PSI returns to 0 V, which causes the drain of the p-channel transistor 122 to return to 0 V, the source voltage of the source of the p-channel transistor 122 becomes a voltage corresponding to the gate voltage, and the corresponding holes from the source of the p-channel transistor 122 return to the drain of the p-channel transistor 122.

[0086] In other words, the fill and overflow operation of the drain of the p-channel transistor 122 causes the voltage of the integrating capacitor 126 to be set to a voltage corresponding to the source voltage of the phototransistor 10 (eg, the voltage at the source 104 ).

[0087] (iii) The source voltage of the phototransistor 10 (e.g., voltage signal Sig) decreases logarithmically from 0.4 V with respect to the amount of incident light due to the influx of photocarriers and subthreshold current during the integration period (i.e., between time t0 and t1). In the illustrated embodiment, the voltage change at the source 104 of the phototransistor 10 corresponds to Figure 6 In addition, the source voltage of the p-channel transistor 122 changes according to the source voltage of the phototransistor 10, and its current is integrated by the integration capacitor 126. Therefore, the voltage of the integration capacitor 126 decreases corresponding to the voltage change in the voltage signal Sig.

[0088] (iv) After a prescribed integration period has elapsed, the signal SW_sig becomes an H level, and the switch transistor 124 is turned off. In addition, the row selection signal SEL that becomes an H level turns on the row selection transistor 14b, and outputs an output signal (e.g., an image signal) according to the voltage of the integration capacitor 126 from the output line 18. In this way, an output signal corresponding to the amount of incident light on the detection or sensing area of ​​the phototransistor 10 of the corresponding pixel is obtained. It should be understood that the control signal applied to the gate electrode 116 of the phototransistor 10, the voltage applied to the drain 102, the signal SW_sig to the switch transistor 124, and the voltage level of the power supply PSI can be configured by a control circuit included in the image sensor (not illustrated), wherein the control circuit is coupled to the phototransistor 10 and the integration circuit 12.

[0089] In this way, in the present embodiment, by operating the phototransistor 10 in the clamped state, the phototransistor 10 is configured to operate in the solar cell mode. Therefore, the dynamic range can be expanded.

[0090] In addition, the integration circuit 12 is coupled between the source 104 of the phototransistor 10 and the source follower transistor 14a, as shown in FIG. Figure 1 As described in . Therefore, a signal change in response to the amount of incident light on the phototransistor 10 operating in the solar cell mode is integrated and output. For this reason, flickering that occurs when capturing an LED or the like can be suppressed.

[0091] It should be appreciated that in the examples described above, an n-channel FET is used in the phototransistor 10 and a p-channel FET is used in the integrating circuit, but in other embodiments, using a p-channel FET in the phototransistor and an n-channel FET in the integrating circuit 12 is possible.

[0092] (Other Examples of Integrator Circuits)

[0093] Figure 8 The configuration of another example of the integration circuit 82 using an n-channel FET is described. The integration circuit 82 includes an n-channel transistor 832, an integration capacitor 834 connected to the drain 832D of the n-channel transistor 832, a reset transistor 836 connected in parallel with the integration capacitor 834, and a reset power supply 838 coupled between the reset transistor 836 and the ground GND. The n-channel transistor 832 is configured as a diode-connected n-channel transistor with its gate 832G electrically connected to its drain 832D. Both the n-channel transistor 832 and the reset transistor 836 are n-channel FETs. The reset transistor 836 is coupled to receive a signal RESET and is configured to charge and discharge when receiving the signal RESET.

[0094] At the reset timing, the reset transistor 836 is turned on (eg, coupled to receive the signal RESET having a high voltage level), and the integration capacitor 834 is charged to the voltage of the reset power supply 838 (eg, 2V).

[0095] The source 832S of the n-channel transistor 832 may be connected to the source 104 of the phototransistor 10, for example, via the source contact 112, and allows the flow of current according to the source voltage of the phototransistor 10. In other words, a current corresponding to the amount of incident light on the phototransistor 10 flows from the integration capacitor 834 to the source 104 of the phototransistor 10, and is integrated in the negative direction in the integration capacitor 634. Therefore, a current similar to Figure 5 The voltage of the integrating capacitor 126 in the circuit.

[0096] (Modification of Phototransistor 10)

[0097] Fig. 9 The illustration shows a partial cross-sectional view of an alternative configuration of a phototransistor 90. Phototransistor 90 is a modification of phototransistor 10 and may include the same or similar features, elements, etc. as phototransistor 10. Fig. 9 In the embodiment illustrated in , the phototransistor 90 does not include a gate electrode. Instead, a surface blocking layer 918 is provided in a surface portion of the channel 906. That is, the phototransistor 90 includes a drain 902, a source 904, a surface blocking layer 918, and a blocking layer 908. The surface blocking layer 918 is disposed between the drain 902 and the source 904 near the first surface 900a, preventing the generated photocarriers from moving toward the first surface 900a. In one embodiment, the surface blocking layer 918 is doped to generate an electric field that pushes one or more generated photocarriers (e.g., electrons) away from the surface portion of the channel 906 near the first surface 900a.

[0098] The phototransistor 90 is disposed on a semiconductor substrate 900, which may be an example of the semiconductor substrate 100. The semiconductor substrate 900 may be a silicon substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from a III-V compound, other suitable semiconductor materials or alloys, combinations thereof, a bulk substrate thereof, or a wafer thereof. In some embodiments, the semiconductor substrate 900 may also be formed as an epitaxial substrate. In some embodiments, the semiconductor substrate 900 may be a substrate having at least a semiconductor layer epitaxially grown thereon, wherein the phototransistor 10 is formed therein. In an embodiment, the semiconductor substrate 900 may include at least one semiconductor layer, such as a doped epitaxial layer. In the illustrated embodiment, a drain 902, a source 904, and a barrier layer 908 are formed or otherwise disposed in the semiconductor layer. The semiconductor substrate 900 may have a first surface 900a and a second surface 900b opposite the first surface 900b.

[0099] Source 904 and drain 902 may each be an example of source 104 and drain 102, respectively. In an embodiment, source 904 and drain 902 are doped regions formed via ion implantation or otherwise disposed in semiconductor substrate 900, each having a conductivity type opposite to semiconductor substrate 900. In an example, source 904 and drain 902 are doped regions doped with a high concentration of n-type impurities. Barrier layer 908 is an example of barrier layer 108.

[0100] The barrier layer 908 is a doped region having a conductivity type opposite to each of the source 904 and the drain 902. In one embodiment, the barrier layer 908 is a region of the semiconductor substrate 900 doped with a high concentration of p-type impurities. The barrier layer 908 is disposed between the drain 902 and the second surface 900b.

[0101] The phototransistor 90 is configured to operate in a clamped state during an exposure or integration period, so that in operation, one or more photocarriers (e.g., electrons) generated in the semiconductor substrate 900 in response to light incident on the phototransistor 90 through the second surface 900b flow from the source 904 through the body channel region of the channel 906 into the drain 902 via a subthreshold current. The body channel region of the channel 906 is configured to be formed between the surface blocking layer 918 and the blocking layer 908. The blocking layer 908 is configured to prevent one or more photocarriers (e.g., electrons) generated in the semiconductor substrate 900 from directly entering the drain 902 and being absorbed by the drain 902. That is, the blocking layer 908 can be operable to prevent one or more photocarriers (e.g., electrons) generated in the semiconductor substrate 900 from entering the drain 902 without passing through the source 904 in a manner similar to the blocking layer 108.

[0102] Furthermore, a bias power source Vbis that causes the voltage at the source 904 to swing in the opposite direction is connected to the source contact 114 through a bias capacitor Cb.

[0103] Fig.10 is an exemplary operational timing diagram of the phototransistor 90 based on the modification according to the teachings of the present disclosure. Figure 2 In the phototransistor 10 of FIG. 1 , the initial source voltage at the beginning of light sensing is reset to the drain voltage by briefly turning on the gate. Fig. 9 There is no gate electrode in the present modification of , so the charge is injected into the source 904 by a fill and overflow operation from the drain 902 , as indicated by the arrows between the source 904 and the drain 902 .

[0104] In the illustrated embodiment, the bias power supply Vbis is first configured to change from an H level (e.g., 0.8 V) to an L level (e.g., 0 V), and the source 904 is set to an L level (e.g., 0 V) ​​by the bias capacitor Cb. In this state, a negative voltage (e.g., -0.4 V) is applied to the drain 902.

[0105] In this way, in a state where the source 904 is at a higher voltage than the drain 902 of the phototransistor 90, current flows from the source 902 to the drain 902, thereby injecting electrons from the drain 902 to the source 904. Therefore, the voltage at the source 904 is the same as the voltage at the drain 902 (for example, the voltage at the source 906 is also -0.4 V).

[0106] Next, after returning the voltage of the drain 902 to a positive voltage (eg, 0.4 V), the voltage of the bias capacitor Cb is returned to an H level (eg, 0.8 V). Using this configuration, in an embodiment, the source voltage of the source 904 can be raised by 0.8 V from -0.4 V and set to 0.4 V.

[0107] In this way, both the source 904 and the drain 902 are reset to a preset or predetermined reset voltage, such as 0.4 V, to obtain an initial state after a reset period prior to an integration or exposure period. Such an operation of setting the source voltage of the source 904 by setting the drain voltage of the drain 902 is referred to as a drain fill and overflow mode.

[0108] Thereafter, electrons flow into the source in response to incident light, and a portion of the electrons flow to the drain as a subthreshold current. Thus, the amount of incident light can be detected in a manner similar to the example described above.

[0109] (Example Using Germanium (Ge) Substrate)

[0110] Fig.11 An example cross-sectional view illustrating a pixel structure according to the teachings of the present disclosure is shown. Fig.11 In the example illustrated in , the pixel includes a silicon substrate 1100 (a first semiconductor substrate) and a germanium (Ge) substrate 1130 (a second semiconductor substrate). The silicon substrate 1100 may be an example of the semiconductor substrate 100, and has a first surface 1100a and a second surface 1100b opposite to the first surface 1100a. The germanium (Ge) substrate 1130 has a first substrate surface 1130a and a second substrate surface 1130b opposite to the first substrate surface 1130a. The silicon substrate 1100 is bonded to the germanium (Ge) substrate 1130 via a suitable bonding scheme (e.g., oxide bonding, hybrid bonding, etc.). In some embodiments, the silicon substrate 1100 is bonded to the germanium (Ge) substrate 1130 using a face-to-face (FF) bonding scheme on a pixel level basis. In some embodiments, a silicon germanium (SiGe) substrate may be used instead of the Ge substrate 1130, depending on the imaging application. It should be understood that certain elements may be omitted or unlabeled (e.g., contacts with the gate electrode 116, optical elements such as color filters, microlenses, and metal layers for signal routing between the silicon substrate 1100 and the Ge substrate 1130, etc.) to avoid obfuscation of certain aspects of the present embodiment provided in accordance with the teachings of the present disclosure.

[0111] The germanium (Ge) substrate 1130 includes an n-type doped region 1132 formed or otherwise disposed in the germanium substrate 1130 near the second substrate surface 1130b. The n-type doped region 1132 is a doped region of the Ge substrate 1130. The silicon substrate 1100 includes the pinch-off transistor 1120. In various examples, the silicon substrate 1100 may be an epitaxial substrate. In various examples, the silicon substrate 1100 may include a semiconductor layer (e.g., an epitaxially grown silicon layer on which the pinch-off transistor 1120 is formed). The germanium (Ge) substrate 1130 may be a substrate having a semiconductor layer (e.g., an epitaxially grown Ge layer in which the n-type doped region 1132 is formed). The pinch-off transistor 1120 includes a drain 1102, a source 1104, a gate electrode 116, and an optional barrier layer 1108 disposed in the silicon substrate 1100. In various examples, pinch-off transistor 1120 can be configured to operate in a pinch-off state similar to the pinch-off state of phototransistor 10 .

[0112] The Ge substrate 1130 is represented as a germanium substrate (p-Ge-sub) as a p-type Ge region, and an n-type doped region (n-Ge) 1132 is disposed in a surface portion on one side thereof (e.g., near the second substrate surface 1130b). For example, the n-type region 1132 is formed in each pixel by ion implantation. In an embodiment, a single photodiode 1134 is a pn junction formed by a single n-type region 1132 and a corresponding portion of the Ge substrate 1130. The photodiode 1134 is capable of detecting infrared light (e.g., light having a wavelength in a range from 850 nm to 3000 nm). The n-type region 1132 may be disposed corresponding to the position arrangement of the pinch transistor 1120 on the silicon substrate 1100. The Ge substrate 1130 is connected to a power supply 1136 and is set to an appropriate voltage. In addition, a wiring 1138 electrically connects the n-type region 1132 of the Ge substrate 1130 and to the source 1104 of the pinch transistor 1120.

[0113] In an exemplary embodiment, the n-type region 1132 of the Ge substrate 1130 and the source 1104 of the pinch transistor 1120 are electrically connected through a metal pad 1140 and a wiring 1138 via a pixel-level hybrid bonding method, so that photocarriers generated and accumulated in the n-type region 1132 are transferred to the source 1102 and then move to the drain 1102 via a subthreshold current through the body channel region of the channel 1106.

[0114] When light 1160 is incident on the Ge substrate 1130 , holes and electrons are generated. The holes flow to the power source 1136 , and the electrons flow into the n-type region 1132 .

[0115] In the silicon substrate 1100, a pinch transistor 1120 is provided for each pixel included in the pixel array of the image sensor. The silicon substrate 1100 is of p-type, and the phototransistor 1120 is a MOSFET similar to the phototransistor 10. In the surface portion of the silicon substrate 1100, a first n+ doped region for a source 1104 and a second n+ doped region for a drain 1102 are formed to be a specified distance apart, and the region therebetween is a channel 1106 configured for coupling the source 1104 to the drain 1102 during operation of the pinch transistor 1120.

[0116] The blocking layer 1108 may be formed of a p-type doped region arranged to cover the drain 1102 and the lower side of the channel 1106 in the silicon substrate 1100. Inside the silicon substrate 1100, the region of the phototransistor 1120 is isolated from the region of the pinching transistor 1120 of the adjacent pixel by the corresponding pixel isolation portion 110.

[0117] The source contact 114 is connected to the surface of the source 1104, and the gate electrode 1116 is disposed close to the surface of the channel 106 through the gate oxide film 1118. In addition, the wiring 1138 and the source contact 114 are connected to form a charge transfer path from the n-type region 1132 of the Ge substrate 1130 to the source 1104 of the pinch transistor 1120.

[0118] The incident light causes the photocarriers (electrons) generated during the photoelectric conversion operation in the Ge substrate 1130 to flow through the wiring 1138 and the non-depleted body channel region of the phototransistor 1120 to the drain 1102. When the pinched transistor 1120 is configured to operate in the pinched state and the drain 1102 is appropriately biased via the drain contact 112, the non-depleted body channel region of the pinched transistor 1120 is formed between (i) the drain 1104 and the source 1104 and (ii) the pinched region of the channel 1106 and the barrier layer 1108.

[0119] In this case, the incident light (e.g., light 1160) generally contains infrared rays in the near infrared, infrared, short-wave infrared, and far infrared ranges, and by using the Ge substrate 1130, efficient photoelectric conversion is performed. In addition, it should be understood that since Ge and Si have different physical constants, such as band gaps, adjustment of the voltages of the Ge substrate 1130 and the silicon substrate 1110 is necessary. Therefore, the voltage of the Ge substrate 1130 is adjusted to a voltage more negative than the voltage of the silicon substrate 1100 (e.g., zero volts or a ground reference voltage) by the power supply 1136. When a large negative voltage is applied to the Ge substrate 1130, the photocurrent flows more easily, but the dark current in the Ge substrate increases. Therefore, it is preferred that the Ge substrate 1130 be adjusted to be highly sensitive to incident light with a small dark current. For the power supply 1136, in an example, it is considered appropriate to provide a voltage in the range of approximately -0.2V to -0.5V according to the teachings of the present disclosure. However, it should be understood that this range of voltage values ​​may only apply to situations where there are few crystal defects, and in reality, there is the possibility that the values ​​may deviate greatly or even be positive voltages.

[0120] When such a photodiode 1134 and a pinch transistor 1120 are used, a signal (e.g., an image signal) can be output from an output circuit (e.g., output circuit 14) through an integration circuit (e.g., integration circuit 12) coupled to the source 1104, and these circuits can have the same implementation as described above.

[0121] Although in the illustrated embodiment, the silicon substrate 110 includes the blocking layer 1108, it should be understood that the blocking layer can be omitted when the photodiode and the transistor are formed on different substrates. That is, the blocking layer can be optional, as represented by the dashed box. For example, in the illustrated embodiment, the photodiode 1134 is disposed on the Ge substrate 1130, and the pinch-off transistor 1120 is disposed on the silicon substrate 1100, so that photoelectric conversion does not occur within the silicon substrate 110. In such embodiments, the blocking layer 1108 can be omitted from the silicon substrate 1100.

[0122] (Ge photodiode is formed inside the substrate)

[0123] exist Fig.11 In the embodiment, the Ge substrate 1130 and the Si substrate 1100 are formed separately and bonded together in a stacked manner, but another possibility is to form a heterojunction of Si and Ge and form a Ge-based photodiode 1134 and a Si-based phototransistor 1120 in a single substrate.

[0124] Fig. 12A A configuration of a pixel having a pinch transistor for sensing infrared light (eg, light having a wavelength in a range from 850 nm to 3000 nm) in accordance with the teachings of the present disclosure is illustrated. Fig. 12A A configuration is illustrated in which a Ge photodiode 1234A is embedded or otherwise disposed in an n-type doped diffusion layer 1250 coupled to the source 1204 of the pinch transistor 1220. The n-type doped diffusion layer 1250 may be a silicon doped region disposed within a semiconductor substrate 1200 (e.g., a p-type doped silicon substrate, an epitaxial substrate, etc.), wherein the semiconductor substrate 1200 has a first surface 1200a and a second surface 1200b opposite the first surface 1200a. The Ge photodiode 1234A may include a pn junction formed by a Ge p-type region Ge(p) and a Ge n-type region Ge(n). The pn junction formed by the Ge p-type region Ge(p) and the Ge n-type region Ge(n) is within the n-type doped diffusion layer 1250. The Ge photodiode 1234A is disposed proximate to the first surface 1200a of the semiconductor substrate 1200.

[0125] The pinch transistor 1220 includes a drain 1202, a source 1204, a gate electrode 1216, and a barrier layer 1208 formed in the semiconductor substrate 1200. The pinch transistor 1220 is disposed near the first surface 1200a of the semiconductor substrate 1200. The pinch transistor 1220 may include a drain 1202, a source 1204, a gate electrode 1216, and a barrier layer 1208. It should be understood that the drain 1202, the source 1204, the gate electrode 1216, and the barrier layer 1208 may be formed with Figure 2The drain 102, source 104, gate electrode 116 and barrier layer 108 of the phototransistor 10 of the embodiment are configured in a similar manner. The barrier layer 1208 is disposed in the semiconductor substrate 120, covering the drain 1202 and the lower side region of the channel 1206. The drain 1202 and the source 1204 having opposite conductivity types as the barrier layer are heavily doped regions, for example, N+ doped regions. The drain 1202 is coupled to constantly receive a bias voltage. In an embodiment, the source 1204 is configured to extend and partially embed in the n-type doped diffusion layer 1250 to be electrically coupled to the Ge photodiode 1234A.

[0126] In operation, during the integration or exposure period of the pixel, the pinch transistor 1220 is configured to operate in a pinched state. That is, the drain 1202 is coupled to constantly receive a bias voltage greater than the voltage applied to the gate electrode 1216 (e.g., a zero or ground reference voltage). In such operation, photocarriers are transferred from the Ge photodiode 1234A in the semiconductor substrate 1200 to the source 1104 in response to incident light (e.g., light 1240) incident on the second surface 1200b and accumulated in the n-type region 1132, and then moved to the drain 1102 via the flow of a subthreshold current through the bulk channel region of the channel 1206.

[0127] Fig. 12B Another example configuration of a pixel having a pinch-off transistor for sensing infrared light in accordance with the teachings of the present disclosure is illustrated. Fig. 12B Similar to Fig. 12A , where the position of the Ge photodiode 1234B is different. Fig. 12B A configuration is described in which a Ge photodiode 1234B is formed in an upper portion of an n-type doped diffusion layer 1250. The Ge photodiode 1234B may be coupled to the source 1204 of the pinch transistor 1220 through the n-type doped diffusion layer 1250. The Ge photodiode 1234B is formed on the first surface 1200a of the semiconductor substrate 1200. In one example, the Ge photodiode 1234B may be formed by a Ge in-situ doped epitaxial layer grown on the first surface 1200a of the semiconductor substrate 1200.

[0128] Fig. 12C Another example configuration of a pixel having a pinch-off transistor for sensing infrared light in accordance with the teachings of the present disclosure is illustrated. Fig. 12CA configuration is described in which a Ge photodiode 1234C is bonded to the second surface 1200b (e.g., the rear surface side) of the semiconductor substrate 1200. The Ge photodiode 1234C may be coupled to the source 1204 of the pinch transistor 1220 through the n-type doped diffusion layer 1250. In one example, the Ge photodiode 1234C may be formed in another substrate (e.g., a germanium substrate or a silicon germanium substrate) and bonded to the second surface 1200b of the semiconductor substrate 1200.

[0129] A pixel having such a configuration using a pinch transistor 1220 similar to the phototransistor 10 may also be expected to have a similar Fig.10 operation.

[0130] [Image sensor]

[0131] Fig.13 1 is a block diagram showing the structure of an image sensor according to an embodiment of the present disclosure. The image sensor 1300 of this example configuration includes a pixel array 1310 having a plurality of pixels P, a readout circuit system 1314, and a function logic 1316. Each pixel P includes a pixel circuit corresponding to Figure 1 , Figure 2 , Fig.11 and Figures 12A to 12C The configuration described in , wherein according to an embodiment of the present disclosure Figure 6 , Figure 7 and Fig.10 The operation is further described in .

[0132] Pixel array 1310 is a two-dimensional array in which pixels P are arranged in rows and columns. In some embodiments, each pixel P may employ a phototransistor (e.g., phototransistor 10). In some embodiments, each pixel P may employ a pinch transistor (e.g., pinch transistor 1120 or pinch transistor 1220) coupled to a Si-based photodiode or a Ge-based photodiode to generate a corresponding image signal in response to incident light sensed or otherwise detected as described above.

[0133] Image sensor 1300 is a simplified schematic diagram showing a pixel array 1310 having a plurality of pixels P, each including at least one of the photodiodes disposed within a corresponding pixel area in pixel array 1310 .

[0134] Each pixel P may have a color filter on a light incident side, and light of a specific color having passed through the color filter is incident on the pixel P.

[0135] The control circuit system 1312 controls the operation of the pixel array 1310 (e.g., during the pre-, post-, and in-situ stages of image and / or video acquisition). For example, the control circuit system 1312 controls the exposure period of each pixel P, the output of the image signal of each pixel P, etc. The control circuit system 1312 can control the operation of the phototransistor (or pinch transistor) used in each pixel according to the operation of the image sensor 1300. The control circuit system 1312 can be implemented as hardware logic (e.g., a dedicated integrator circuit, a field programmable gate array, a system on a chip, etc.), software / firmware logic executed on a general-purpose microcontroller or microprocessor, or a combination of both hardware and software / firmware.

[0136] The readout circuit system 1314 individually reads out the image signal of each pixel P, A / D converts the read signal to obtain digital data, and supplies the digital data to the function logic 1316. For example, the readout circuit system 1314 reads or otherwise samples analog signals (e.g., reads out voltage signals generated by each of a plurality of pixels) from individual pixels in the pixel array 1310 in response to incident light to generate image signals for capturing image frames, etc., and may include amplification circuit systems, analog / digital (ADC) circuit systems, image buffers, etc. In the illustrated embodiment, the readout circuit system 1314 is separate from the control circuit 1312, but in other embodiments, the readout circuit system 1314 may be included in the control circuit system 1312.

[0137] Function logic 1316 is coupled to readout circuit system 1314 to receive image data to demosaic the image data and generate one or more image frames. In an example embodiment, function logic 1316 applies processing to the data from each pixel P (e.g., applying post-image effects such as cropping, rotation, removing red eye, adjusting brightness, adjusting contrast, etc.) to obtain a video signal for screen display and outputs the obtained video signal. The video signal is supplied to a display or other electronic device, and the image acquired by image sensor 1300 can be displayed on the display.

[0138] The above description of the illustrated examples of the present invention (including the content described in the Abstract) is not intended to be exhaustive or limit the present invention to the precise form disclosed. As will be appreciated by those skilled in the relevant art, although specific examples of the present invention are described herein for illustrative purposes, various modifications are possible within the scope of the present invention.

[0139] In light of the above detailed description, these modifications may be made to the present invention. The terms used in the appended claims should not be interpreted as limiting the present invention to the specific examples disclosed in the specification. Rather, the scope of the present invention will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. A pixel circuit of an image sensor, the pixel circuit comprising: a transistor comprising a first doped region and a second doped region, the first and second doped regions being disposed on opposite sides of a channel of the transistor near a first surface of a semiconductor substrate, such that photocarriers generated inside the semiconductor substrate in response to incident light flow into the second doped region, and the first doped region is coupled to output a voltage signal; a blocking layer disposed in the semiconductor substrate between the second doped region and a second surface of the semiconductor substrate opposite to the first surface, the blocking layer blocking the photocarriers from directly flowing into the second doped region; and an output circuit coupled to the transistor and configured to output an image signal according to the voltage signal, The transistor is configured to allow subthreshold current to flow between the first doped region and the second doped region while operating in a pinched state, wherein photocarriers are configured to pass through a body channel region of the channel located at a position away from the first surface of the semiconductor substrate. 2 . The pixel circuit according to claim 1 , wherein the barrier layer has a conductivity type opposite to a conductivity type of the second doped region. 3 . The pixel circuit of claim 1 , wherein the blocking layer is disposed such that the channel of the transistor is between a gate electrode of the transistor and the blocking layer. 4 . The pixel circuit of claim 1 , wherein the barrier layer at least partially overlaps the second doped region and extends laterally to directly contact the first doped region.

5. The pixel circuit of claim 1 , further comprising a gate electrode disposed to couple the first doped region to the second doped region, wherein the second doped region is constantly coupled to receive a bias voltage, and the gate electrode is coupled to receive a control voltage that is less than the bias voltage. 6 . The pixel circuit of claim 5 , wherein the transistor is a phototransistor comprising an n-channel field effect transistor, and the first doped region is a source of the phototransistor, and the second doped region is a drain of the phototransistor.

7. A pixel circuit according to claim 5, wherein the photocarriers are generated inside a pn junction formed between the first doped region and a substrate region of the semiconductor substrate surrounding the first doped region, and the transistor is configured so that the photocarriers flow from the first doped region through the body channel region into the second doped region. 8 . The pixel circuit of claim 1 , wherein the subthreshold current varies logarithmically with the number of photocarriers generated in response to incident light.

9. The pixel circuit according to claim 1, wherein the transistor comprises: a surface barrier layer disposed between the channel and the first surface and between the first doped region and the second doped region, the surface barrier layer having a conductivity type opposite to a conductivity type of each of the first doped region and the second doped region; and A bias capacitor is coupled between the first doped region and a bias power supply.

10. The pixel circuit according to claim 1, wherein the integration circuit comprises: a p-channel transistor having a gate coupled to the first doped region of the transistor, and an integrating capacitor coupled to the source of the p-channel transistor.

11. The pixel circuit according to claim 1, wherein the integration circuit comprises: an n-channel transistor, the drain and gate of which are connected to each other, and the source of the n-channel transistor is coupled to the first doped region of the transistor, and An integrating capacitor and a reset transistor are coupled to the drain of the n-channel transistor.

12. The pixel circuit according to claim 1, further comprising: A pn junction in the semiconductor substrate is coupled to the first doped region, the pn junction comprising a p-type doped germanium region and an n-type doped Ge region, the pn junction being configured to sense light wavelengths greater than or equal to 850 nanometers and generate photocarriers in response to incident light. 13 . The pixel circuit of claim 12 , further comprising an n-type doped diffusion layer disposed in the semiconductor substrate, the n-type doped diffusion layer coupled to the first doped region, wherein the pn junction is in the n-type doped diffusion region.

14. The pixel circuit of claim 1, wherein the output circuit comprises an integration circuit coupled to receive the voltage signal output from the transistor and integrate the voltage signal to generate the image signal.

15. An image sensor comprising a plurality of pixel circuits, each of the plurality of pixel circuits comprising: a photodiode comprising a p-type doped germanium region and an n-type doped Ge region, the photodiode having a pn junction sensitive to infrared light and generating photocarriers in response to incident light; a pinch transistor disposed in the first semiconductor substrate, the pinch transistor being electrically coupled to the photodiode, and the pinch transistor comprising: a source and a drain disposed on both sides of the channel near the first surface of the first semiconductor substrate so that photocarriers from the photodiode are received in one region of the source and the drain; and an output circuit disposed on the first semiconductor substrate and outputting an image signal based on a voltage signal output from the one region of the source and the drain of the pinch transistor, The pinch-off transistor allows a subthreshold current to flow in a pinch-off state, wherein photocarriers pass through a bulk channel region of the channel in the first semiconductor substrate at a location away from the first surface of the first semiconductor substrate. 16 . The image sensor of claim 15 , wherein the p-type doped Ge region is coupled to a negative voltage relative to a voltage of the first semiconductor substrate.

17. The image sensor according to claim 15, further comprising a second semiconductor substrate, wherein the photodiode included in each of the pixel circuits is disposed on the second semiconductor substrate, and the second semiconductor substrate is bonded to the first semiconductor substrate having the clamping transistor so that the photodiode is coupled to the clamping transistor.

18. The image sensor of claim 17, each of the plurality of pixel circuits further comprising: A blocking layer is disposed between the source and a second surface of the first semiconductor substrate, wherein the second surface is opposite to the first surface, wherein the blocking layer has a conductivity type opposite to the conductivity type of each of the source and the drain, and the blocking layer is configured to block the photocarriers from directly flowing into another region of the source and the drain.

19. The image sensor according to claim 17, wherein the first semiconductor substrate is a silicon substrate, and the second semiconductor substrate is a p-type doped Ge substrate, wherein the p-type doped Ge region of the photodiode is the p-type doped Ge substrate, and the n-type doped Ge region is a doped region disposed in the p-type doped Ge substrate.

20. The image sensor of claim 15, each of the plurality of pixel circuits further comprising an epitaxial layer disposed on the first semiconductor substrate, wherein the photodiode is disposed in the epitaxial layer coupled to the pinch transistor through the one region of the source and the drain.

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