A method for optimizing surface passivation of tunnel oxide passivated cells

Abstract

The application provides a surface passivation treatment method for optimizing a tunneling oxide passivation battery, which comprises the following steps: in a BOE cleaning step, placing an annealed silicon wafer into a mixed solution of a tank cleaning device, cleaning the silicon wafer in the mixed solution for more than 120s, taking out the silicon wafer and cleaning the silicon wafer with sufficient DIW, then placing the silicon wafer into an acid solution, taking out the silicon wafer and cleaning the silicon wafer with a large amount of DIW, and bubbling in the cleaning process, and finally passivating the surface of the silicon wafer by using an (NH4)2S solution; and in a reflection reduction film manufacturing step, the reflection reduction film is divided into three layers for preparation. The application utilizes sulfur passivation of the P-type emitter of the battery, assists accumulation of negative charges of aluminum oxide to enhance the field passivation effect, passivates the silicon surface dangling bond, releases the process window reduction caused by the accumulation of [H] source for hydrogen passivation in the preparation process of silicon nitride, and reduces the performance attenuation caused by the escape of [H] in the long-term use of the battery assembly.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of TOPCon cell production, in particular, it shows a surface passivation treatment method for optimizing tunneling oxide passivation cells. BACKGROUND

[0002] At present, after years of development of solar cells, considering the cell efficiency and manufacturing cost, TOPCon (Tunnel Oxide Passivated Contact Solar Cell, tunnel oxide passivated solar cell) has a higher market share year by year due to its excellent surface passivation, high conversion efficiency and relatively low cost. At present, TOPCon cell is undoubtedly the market mainstream. TOPCon technology is a kind of technology that prepares an ultra-thin tunneling oxide layer (SiOx) on the back surface of the cell and grows a heavily doped polysilicon layer (Poly-Si) on its surface, which forms a passivation contact structure together. The non-conductive but extremely thin tunneling oxide layer can make high-concentration majority carriers (multi-carriers) pass through in the form of quantum tunneling, but will block minority carriers; the heavily doped Poly can change the energy band position of silicon, making it become a P-type / N-type semiconductor, blocking electrons / holes. Therefore, TOPCon cells have high passivation ability and conversion efficiency, which makes TOPCon cells the first choice for large-scale production.

[0003] However, the poly layer belongs to parasitic light absorption for light absorption, which does not contribute to photocurrent (Isc). At present, TOPCon cells are only prepared on the back surface. If this structure is prepared on the front surface as the light absorption surface, the parasitic light absorption of the poly layer will greatly reduce the Isc, thereby reducing the cell efficiency. The surface of a silicon crystal can reduce the surface state density by depositing or growing a passivation layer on the surface of the cell, thereby reducing the surface recombination rate. Therefore, the front surface of the current n-TOPCon cell does not prepare a TOPCon structure, but selects a p+ emitter / aluminum oxide / silicon nitride passivation structure.

[0004] At present, an aluminum oxide film layer is prepared on the front surface of the n-TOPCon cell as a passivation layer. Since the front surface of a general n-type cell is generally a positive electrode (P-type emitter), aluminum oxide has a large number of (1.3-2.0×10 13 cm -2 ) fixed negative charges, which can produce a strong field passivation effect, passivating the P-type emitter. Therefore, atomic layer deposition of an aluminum oxide film on the passivated P-type emitter has good passivation effect.

[0005] However, there are a large number of silicon dangling bonds between the p+ emitter / aluminum oxide that have not been passivated (such as Figure OneThe current method is to add elemental [H] in the subsequent silicon nitride preparation, activate the elemental [H] in the sintering process, and combine the elemental [H] with the silicon surface dangling bond to passivate the interface.

[0006] The hydrogen passivation elemental [H] is derived from the reaction gas ammonia and silane in the preparation of silicon nitride, and is transported to the p+ emitter / Al2O3 interface to complete passivation during the sintering of the prepared metal electrode. The transport of [H] is realized due to the concentration gradient difference, but in the system of interface / [H] containing layer / external environment, the content of [H] in the external environment is obviously the lowest, and a large amount of [H] escapes to the external environment. Therefore, in order to ensure the hydrogen passivation effect, more [H] needs to be stored in the silicon nitride film layer, which will affect the performance of the silicon nitride film layer, and in the long-term use process after the battery is prepared into a module, due to the small volume of [H] relative to silicon atoms, [H] is easily detached from the interface under the action of external energy and continuously escapes over time.

[0007] Although the [H] stored in the silicon nitride film layer can be supplemented, the content of [H] is decreasing overall, resulting in continuous attenuation of the battery efficiency and module power. SUMMARY

[0008] The purpose of the present application is to overcome the shortcomings of the prior art, and provide a surface passivation treatment method for optimizing tunneling oxidation passivation battery, which passivates the interface by using sulfur element before preparing the aluminum oxide film layer.

[0009] Based on this, the present application discloses a surface passivation treatment method for optimizing tunneling oxidation passivation battery, and the preparation method of the tunneling oxidation passivation battery mainly includes the following steps: cleaning and texturing, boron diffusion, removing glass layer and plating, alkali polishing, preparing TOPCon structure on the back, annealing, BOE cleaning, front side aluminum oxide passivation, anti-reflection film making, and screen printing.

[0010] In the BOE cleaning step: first, the annealed silicon wafer is placed in a mixed solution in a slot cleaning device, the mixed solution is NaOH, H2O2 and DIW with a volume ratio of 1:8:120, and the silicon wafer is cleaned in the mixed solution for more than 120s, then the silicon wafer is taken out and cleaned with sufficient DIW, then the silicon wafer is placed in an acid solution, the acid solution is HF, HCl and DIW with a volume ratio of 3:1:12, the silicon wafer is taken out and cleaned with a large amount of DIW, and bubbling is performed during the cleaning, and finally the surface of the silicon wafer is passivated by using (NH4)2S solution.

[0011] In the antireflection film manufacturing step: the antireflection film is prepared in three layers, the first layer of antireflection film has a thickness of 15-20 nm, the preparation temperature is not more than 240°C, the second layer of antireflection film has a thickness of 15-20 nm, the preparation temperature is not more than 350°C, and the third layer of antireflection film has a thickness of 40-50 nm, the preparation temperature is 480-500°C.

[0012] Preferably, the temperature of the (NH4)2S solution is 25-30°C when passivating the surface of the silicon wafer. Since (NH4)2S is easily dissolved in cold water but is easily decomposed in hot water, the temperature of the (NH4)2S solution needs to be controlled close to room temperature.

[0013] Preferably, the concentration of the (NH4)2S solution is 18-20 wt%. Since the (NH4)2S aqueous solution is alkaline, a too high concentration of the (NH4)2S solution will have a risk of corroding the pyramid suede structure, so the concentration of the (NH4)2S solution needs to be controlled not too high.

[0014] Preferably, the cleaning time of the (NH4)2S solution is 250-300 s when passivating the surface of the silicon wafer. Since sulfur passivation is a supplement to hydrogen passivation and AlO passivation, it does not need to be completely passivated, and since the (NH4)2S aqueous solution will corrode the silicon substrate, the passivation cleaning time should not be too long.

[0015] Preferably, after the silicon wafer is completely cleaned with a large amount of DIW, the surface of the silicon wafer is dried with nitrogen at 50°C. This is to prevent the sulfur passivation structure from being damaged and the surface of the silicon wafer from being oxidized.

[0016] Preferably, the temperature of the mixed solution is 45°C when cleaning the silicon wafer in the mixed solution. The temperature needs to be appropriate mainly to clean the organic impurities on the surface of the silicon wafer.

[0017] Compared with the prior art, the present application has the beneficial effects that: the P-type emitter of the sulfur passivated battery assists the accumulation of negative charges of aluminum oxide to enhance the field passivation effect; the silicon surface dangling bonds are passivated to release the process window reduction caused by the accumulation of [H] source in the preparation process of silicon nitride for hydrogen passivation; and the performance decay caused by the escape of [H] in the long-term use of the battery assembly is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a schematic diagram showing that a large number of silicon dangling bonds between the p+ emitter and aluminum oxide are not passivated;

[0019] Figure 2 is a schematic diagram showing that a covalent bond of a hydrogen atom is connected to a silicon dangling bond for passivation;

[0020] Figure 3 is a schematic diagram showing that two covalent bonds of a sulfur atom are connected to two silicon dangling bonds for passivation;

[0021] Figure 4 is a PL diagram showing a conventional process Base line (BL) sample;

[0022] Figure 5 is a PL diagram showing a sample prepared by an embodiment of the present application;

[0023] Figure 6 is a graph showing battery efficiency comparison data of an embodiment of the present application and a conventional process Base line. DETAILED DESCRIPTION

[0024] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that the advantages and features of the present application can be more easily understood by those skilled in the art and the scope of protection of the present application can be more clearly defined.

[0025] The present application proposes a surface passivation treatment method for optimizing tunneling oxide passivation batteries, mainly using sulfur element to passivate the interface before preparing the aluminum oxide film layer.

[0026] The unit cell of monocrystalline silicon is mainly composed of a set of face-centered cubic lattices formed by atoms at the corners of the cube and face centers, and another set of face-centered cubic lattices formed by atoms at the body diagonal, so it can be considered that the silicon crystal is composed of two sets of face-centered cubic lattices with a quarter length displacement along the body diagonal. This unit cell is called a cubic unit cell with a diamond structure, and each silicon atom has four covalent bonds, i.e., each silicon atom needs to be connected to four atoms to avoid dangling bonds. The two-dimensional planar structure of monocrystalline silicon can be represented by Figure One Simple identification, in the body region, silicon atoms are closely connected and there are no dangling bonds, and at the interface, there are dangling bonds, [H] has one covalent bond that can be connected to the silicon dangling bond to passivate (as shown in Figure 2 ), and the sulfur atom has two covalent bonds that can be connected to two silicon dangling bonds to passivate (as shown in Figure 3 ).

[0027] And the sulfur atom is in group VII element 16, which has strong oxidizing property, and the sulfided surface helps the negative charge accumulation of the aluminum oxide passivation layer, which can better passivate the P-type emitter and improve the battery efficiency.

[0028] Embodiment:

[0029] A surface passivation treatment method for optimizing tunneling oxide passivation batteries, comprising the following preparation steps:

[0030] (1) Cleaning and texturing: select n-type c-Si silicon wafer and perform texturing treatment to remove the surface cutting damage layer and form a textured surface structure on the surface to reduce light loss.

[0031] Specifically, the silicon wafer is placed in a NaOH alkaline solution, the temperature of the NaOH solution is preferably set to about 65°C, the volume ratio of NaOH and DIW is 1:150, and after texturing, the silicon wafer is cleaned with DIW and dried for removal.

[0032] (2) Boron diffusion: After cleaning after texturing, the silicon wafer is placed in a boron diffusion tube for boron diffusion. The diffusion is divided into four steps: pre-oxidation, deposition, promotion, and post-oxidation. Compared with the traditional process, the process time is reduced, and the diffusion concentration is reduced.

[0033] Specifically, the deposition time is 90-120s, the promotion time is 350-400s, and the sheet resistance of the silicon wafer after diffusion is about 150Ω / □.

[0034] (3) Remove glass layer and plating: Use chain single-sided HF equipment to remove back BSG, the volume ratio of HF and DIW in the machine is 1:10.

[0035] (4) Alkaline polishing: Place the silicon wafer in an alkaline polishing tank. After alkaline polishing, clean the surface of the silicon wafer with HCl+HF solution.

[0036] (5) Back surface preparation of TOPCon structure: Based on PVD / PECVD / LPCVD technology, TOPCon structure is prepared on the back surface. First, an ultra-thin tunneling oxide layer is prepared, and then a doped amorphous silicon layer is prepared.

[0037] (6) Annealing: High-temperature annealing is performed at a temperature of 850°C for 2000s to activate the dopant atoms.

[0038] (7) BOE cleaning: First, place the annealed silicon wafer in a mixed solution in a tank cleaning device, the mixed solution is NaOH, H2O2, and DIW with a volume ratio of 1:8:120, the temperature of the mixed solution is set to 45°C, and the cleaning time in the mixed solution is more than 120s. Here, it is to clean the organic impurities on the surface of the silicon wafer. Take out the silicon wafer and clean it with plenty of DIW. Then, place the silicon wafer in an acid solution, the acid solution is HF, HCl, and DIW with a volume ratio of 3:1:12, to remove the oxide on the surface of the silicon wafer and reduce the residual metal ions. Since SiO reacts with HF to generate H2SiF6, H2SiF6 and hydrolysis products will adhere to the surface of the silicon wafer. In order to prevent the subsequent sulfur passivation step from being disturbed, the removed silicon wafer is completely cleaned with a large amount of DIW, and bubbling is performed during cleaning. After complete cleaning, the surface of the silicon wafer is passivated with (NH4)2S solution.

[0039] Since (NH4)2S is easily soluble in cold water but easily decomposed in hot water, the temperature of the (NH4)2S solution needs to be controlled close to room temperature, preferably, the temperature of the (NH4)2S solution is 25-30°C.

[0040] Since the aqueous (NH4)2S solution is alkaline, its concentration is too high, which will corrode the pyramid velvet structure of gold, so the concentration of (NH4)2S solution should not be too high, preferably, the concentration of (NH4)2S solution is 18-20wt%.

[0041] Since sulfur passivation is used as a supplement to hydrogen passivation and AlO passivation, it does not need to be completely passivated, and since the aqueous (NH4)2S solution will corrode the silicon substrate, the passivation cleaning time should not be too long. Preferably, the cleaning time of (NH4)2S solution is 250-300s.

[0042] In order to prevent the sulfur passivation structure from being destroyed and prevent the surface of the silicon wafer from being oxidized, after the silicon wafer is completely cleaned with a large amount of DIW, the surface of the silicon wafer is dried with nitrogen at 50°C.

[0043] (8) Front surface aluminum oxide passivation: an aluminum oxide passivation layer is prepared on the front surface of the silicon wafer using an atomic layer deposition device (ALD).

[0044] (9) Anti-reflective film preparation: silicon nitride (SiNx) anti-reflective film is prepared on the front and back surfaces of the silicon wafer based on plasma enhanced chemical deposition (PECVD), reducing light reflection.

[0045] Since the Si-S-Si bond after sulfur passivation is easily destroyed by high temperature, the ALD-deposited aluminum oxide passivation layer is only a few nanometers thick and cannot provide sufficient protection, so the SiNx anti-reflective film preparation stage is divided into multiple steps. In the initial stage of leak detection, purging, etc., the temperature should not exceed 200°C.

[0046] Specifically, the anti-reflective film is prepared in three layers, the first layer of anti-reflective film has a thickness of 15-20nm, the preparation temperature does not exceed 240°C, the second layer of anti-reflective film has a thickness of 15-20nm, the preparation temperature does not exceed 350°C, and the third layer of anti-reflective film has a thickness of 40-50nm, the preparation temperature is 480-500°C.

[0047] And the sulfur atom is element 16 in group VII, compared to the atomic size and unit cell structure of element silicon, which is element 14 in group IV, the sulfur element is larger, and then the ALD-deposited aluminum oxide passivation layer and the SiNx anti-reflective layer covered in different temperature zones, the S element is wrapped on the surface of the silicon cell and cannot escape and lose, in the subsequent preparation, even if the Si-S-Si bond is broken, the S element is still retained, and after the temperature decreases, it is recombined with the surface Si element to form a Si-S-Si bond.

[0048] (10) Screen printing: metal paste is applied to the front and back surfaces of the cell using a screen printing device, and high-temperature processing is performed in a sintering furnace to prepare metal grid lines, allowing the metal material to combine with silicon to form an alloy, guiding photo-generated carriers out of the cell, and completing the preparation of the cell.

[0049] The present application can better passivate the P-type emitter and improve the battery efficiency by optimizing the surface passivation step of the tunneling oxide passivation battery, and the sulfided surface helps the aluminum oxide passivation layer to accumulate negative charges.

[0050] After testing, the passivation ability of the sample battery prepared by the present application is obviously improved, the Voc of the prepared battery is about 1-2 mV, and the final efficiency of the battery is about 0.1% higher than that of the conventional TOPCon battery.

[0051] As shown in Figure 4 , 5 , 6, compared with the conventional process Base line (BL) sample, the PL brightness of the sample treated by the sulfur passivation process of the present application is about 2.92% higher, and the passivation performance is obviously improved.

[0052] The above only describes some embodiments of the present application. Those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. An optimized surface passivation treatment method for tunneling oxide passivation solar cells, the preparation method of which mainly includes the following steps: cleaning and texturing, boron diffusion, removal of glass layer and winding plating, alkaline polishing, preparation of TOPCon structure on the back side, annealing, BOE cleaning, alumina passivation on the front side, antireflective film preparation, and screen printing, characterized in that: In the BOE cleaning process: First, the annealed silicon wafer is placed in a mixed solution of a tank cleaning device. The mixed solution is NaOH, H2O2 and DIW in a volume ratio of 1:8:

120. The wafer is cleaned in the mixed solution for more than 120 seconds. The wafer is then removed and cleaned with a sufficient amount of DIW. After that, the wafer is placed in an acid solution of HF, HCl and DIW in a volume ratio of 3:1:

12. The wafer is then removed and completely cleaned with a large amount of DIW, with bubbling during the cleaning process. Finally, the surface of the wafer is passivated using (NH4)2S solution. In the fabrication process of the antireflective coating: the antireflective coating is prepared in three layers. The first layer of the antireflective coating has a thickness of 15-20 nm and is prepared at a temperature not exceeding 240℃. The second layer of the antireflective coating has a thickness of 15-20 nm and is prepared at a temperature not exceeding 350℃. The third layer of the antireflective coating has a thickness of 40-50 nm and is prepared at a temperature of 480-500℃.

2. The surface passivation treatment method for an optimized tunneling oxide passivation battery according to claim 1, characterized in that, When passivating the surface of the silicon wafer, the temperature of the (NH4)2S solution is 25-30°C.

3. The surface passivation treatment method for an optimized tunneling oxide passivation battery according to claim 1, characterized in that, The concentration of the (NH4)2S solution is 18–20 wt%.

4. The surface passivation treatment method for an optimized tunneling oxide passivation battery according to claim 1, characterized in that, When passivating the surface of a silicon wafer, the cleaning time of the (NH4)2S solution is 250-300 s.

5. The surface passivation treatment method for an optimized tunneling oxide passivation battery according to claim 1, characterized in that, After thoroughly cleaning the silicon wafer with a large amount of DIW, the surface of the silicon wafer is dried with nitrogen gas at 50°C.

6. The surface passivation treatment method for an optimized tunneling oxide passivation battery according to claim 1, characterized in that, When cleaning silicon wafers in a mixed solution, the temperature of the mixed solution is 45°C.

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