Chip fault prediction method and device, equipment and storage medium

Abstract

The invention relates to a chip fault prediction method and device, equipment and a storage medium, and the method comprises the following steps: carrying out the feature extraction of preprocessed electrical operation data, and obtaining electrical operation extraction feature data; constructing an electrical operation state network of the target chip based on the electrical operation extraction feature data; performing node state prediction on the target chip based on the electrical operation state network to obtain a node state prediction result; if the node state prediction result is that the target chip has a fault, performing fault positioning on the target chip based on the node state prediction result to obtain a fault position of the target chip; and performing fault path propagation analysis on the target chip based on the fault position to obtain a fault propagation path, and formulating a corresponding fault response measure based on the fault position and the fault propagation path, thereby solving the technical problem that a traditional fault detection method mainly depends on postmortem inspection.

Description

Technical Field

[0001] The present invention relates to the field of chip failure technology, and in particular to a chip failure prediction method, device, equipment and storage medium. Background Art

[0002] With the rapid development of electronic technology, integrated circuits (ICs) have become an indispensable part of modern science and technology and are widely used in many fields such as computers, communication equipment, and consumer electronics. However, with the increasing complexity of chip design and the increase in integration, the failure rate of chips during production and use has also increased, which not only affects the quality of the product, but also increases the risk of maintenance costs and customer dissatisfaction. Traditional fault detection methods mainly rely on post-inspection, that is, taking measures only after the fault occurs. This passive approach often fails to solve the problem in a timely and effective manner.

[0003] At present, the demand for preventive maintenance of chip failures is growing, especially in mission-critical systems, where any minor failure may lead to serious consequences. Therefore, it is particularly important to develop intelligent systems that can predict and prevent failures in advance. Although existing fault prediction technologies have made some progress, they still face many challenges in terms of accuracy, real-time and adaptability. For example, some methods require a large amount of historical data to train the model, which may be difficult to obtain; some methods are insufficient in recognizing nonlinear and dynamically changing fault patterns, resulting in low prediction accuracy.

[0004] In response to the above problems, a new chip fault prediction method is proposed. This method collects the electrical operation data of the chip, processes it and extracts features using advanced data analysis technology, and builds a model that can reflect the actual working status of the chip. Furthermore, an efficient node state prediction algorithm is used to analyze the model to achieve early warning of potential faults. This method can not only effectively improve the accuracy and timeliness of fault prediction, but also provide an important basis for subsequent fault location and fault path propagation analysis, thereby laying the foundation for the formulation of scientific and reasonable fault response strategies. This method is expected to overcome the limitations of existing technologies and provide a more solid guarantee for the reliability and safety of chips. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip fault prediction method, device, equipment and storage medium, which solves the technical problem that traditional fault detection methods mainly rely on post-inspection.

[0006] To achieve the above object, the present invention provides a chip fault prediction method, comprising the following steps: Collecting electrical operation data of the target chip, and preprocessing the electrical operation data to obtain preprocessed electrical operation data; Performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data; Building an electrical operation state network of a target chip based on the electrical operation extraction feature data; By using a node state prediction algorithm, a node state prediction is performed on the target chip based on the electrical operation state network to obtain a node state prediction result; If the node state prediction result indicates that the target chip is faulty, locating the fault of the target chip based on the node state prediction result to obtain the fault position of the target chip; Based on the fault location, a fault path propagation analysis is performed on the target chip to obtain a fault propagation path, and corresponding fault coping measures are formulated based on the fault location and the fault propagation path.

[0007] Further, the collecting electrical operation data of the target chip and preprocessing the electrical operation data to obtain preprocessed electrical operation data includes: Collecting electrical data of the target chip through a preset multimodal sensor to obtain original operation data; removing noise from the original operation data to obtain electrical operation data; Regularizing the electrical operation data by using a fractal dimension analysis method to obtain regularized operation data; Using a preset blind source separation algorithm to separate the data types of the running regularized data to obtain independent source data; Reorganizing the independent source data to obtain reorganized operation data; The reorganized operating data is mapped using a preset nonlinear technology to obtain nonlinear mapping data, and the nonlinear mapping data is used as preprocessing operating data; wherein the preprocessing operating data includes voltage operating data, current operating data and power operating data.

[0008] Furthermore, the extracting features of the pre-processed electrical operation data to obtain electrical operation extracted feature data includes: Performing time series analysis on the pre-processed electrical operation data to obtain electrical time series characteristics; Performing frequency domain analysis on the electrical timing characteristics by using Fourier transform to obtain electrical frequency domain characteristics; Performing statistical feature extraction on the electrical frequency domain features to obtain electrical statistical feature data; Performing electrical correlation analysis on the electrical timing characteristics based on the electrical statistical characteristic data to obtain electrical correlation characteristic data; wherein the electrical correlation characteristic data is used to capture the relationship and dependency between different electrical parameters; Feature extraction is performed on the electrical correlation feature data to obtain electrical operation extraction feature data; wherein the electrical operation extraction feature data is used to describe the correlation, coupling degree or causal relationship between different electrical timing features.

[0009] Furthermore, constructing an electrical operation status network of a target chip based on the electrical operation extraction feature data includes: Acquire a structural diagram of the target chip and components in the structural diagram corresponding to the electrical operation extraction feature data from a database; Based on the structure diagram and the elements corresponding to the electrical operation extracted feature data, the electrical operation extracted feature data is subjected to graph structure processing to obtain an electrical operation diagram; wherein the electrical operation diagram includes nodes and edges, the nodes are elements in the target chip structure diagram, and the edges are connection relationships between elements in the target chip structure diagram; The electrical operation diagram is divided into sub-graphs by a preset spectral clustering algorithm to obtain a plurality of sub-graphs; wherein each of the sub-graphs represents a functional module in the target chip; Constructing a corresponding electrical operation matrix based on each of the subgraphs respectively; wherein the electrical operation matrix includes rows, columns and elements; the rows represent the position identifiers of each component, the columns represent the components corresponding to the electrical operation extracted feature data, and the elements represent the electrical operation extracted feature data; Combining the electrical operation matrices to obtain a combined matrix; Performing graph reconstruction processing on the structure graph based on the combination matrix to obtain an initial electrical operation state network; The initial electrical operation state network is visualized to obtain a visualized electrical operation state network, and the visualized electrical operation state network is used as the electrical operation state network of the target chip.

[0010] Furthermore, the node state prediction algorithm is used to predict the node state of the target chip based on the electrical operation state network to obtain a node state prediction result, including: Input the electrical operation status network into a preset graph neural network algorithm; wherein the node status prediction algorithm includes a convolution module, a multi-head attention mechanism module, a time series modeling module, a feature fusion module, an adaptive pooling module and a prediction module; Performing a deep graph convolution operation on the electrical operation status network through the convolution module to obtain an initial node feature vector; Performing a multi-head attention mechanism calculation on the initial node feature vector through the multi-head attention mechanism module to obtain a node weighted feature vector; Performing time series modeling on the node weighted feature vector through the time series modeling module to obtain a node time series feature vector; Performing feature fusion on the node time series feature vectors through the feature fusion module to obtain a node fusion feature vector; The node fusion feature vector is dimensionally adjusted by the adaptive pooling module to obtain a node state representation vector; The prediction module predicts the node state of the target chip based on the node state representation vector to obtain a node state prediction result.

[0011] Further, locating the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip includes: Using the node status prediction results, status screening is performed on nodes in the electrical operation status network to obtain suspected fault nodes; Using a graph diffusion algorithm, locally diffuse the electrical operation status network based on the suspected fault node to obtain a diffusion node set; Using a community detection algorithm, the target chip is divided into communities based on the diffusion node set to obtain a community division result; Based on the community division result, importance scoring is performed on the nodes of the target chip to obtain an importance scoring result; According to the importance scoring result, the node with the highest score is selected as the candidate fault node; The fault position of the target chip is located based on the candidate fault nodes and the node state prediction result to obtain the fault position of the target chip.

[0012] Further, performing fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path includes: By using a preset spatial autocorrelation analysis method, a neighborhood analysis is performed on the fault location to identify hot spots around the fault location and obtain a fault impact area; By using a preset community detection algorithm, the fault affected area is divided into functional modules to obtain a modular fault network; Modeling the time series data of the modular fault network to analyze the changing trend of the fault location over time and obtain the fault evolution path; Performing causal relationship mining on the fault evolution path to obtain a causal link graph; A multi-agent system is used to simulate the propagation process of the fault location inside the target chip based on the causal link diagram to obtain the fault propagation path.

[0013] The present invention also provides a chip fault prediction device, comprising: An acquisition module, used for acquiring electrical operation data of a target chip, and preprocessing the electrical operation data to obtain preprocessed electrical operation data; An extraction module, used for performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data; A construction module, used for constructing an electrical operation state network of a target chip based on the electrical operation extraction feature data; A prediction module, configured to perform node state prediction on the target chip based on the electrical operation state network by using a node state prediction algorithm to obtain a node state prediction result; A positioning module, configured to locate the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip if the node status prediction result indicates that the target chip is faulty; The analysis module is used to perform fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path, and formulate corresponding fault response measures based on the fault location and the fault propagation path.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0016] The chip fault prediction method provided by the present invention comprises the following steps: extracting features from the pre-processed electrical operation data to obtain electrical operation extraction feature data; constructing an electrical operation status network of a target chip based on the electrical operation extraction feature data; predicting the node status of the target chip based on the electrical operation status network to obtain a node status prediction result; if the node status prediction result is that the target chip has a fault, locating the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip; performing fault path propagation analysis on the target chip based on the fault position to obtain a fault propagation path, and formulating corresponding fault response measures based on the fault position and the fault propagation path, thereby solving the technical problem that the traditional fault detection method mainly relies on post-inspection, and realizing that once it is predicted that the chip may have a fault, the method can accurately locate the fault based on the node status prediction result and determine the specific fault location. This precise fault location helps to quickly find the problem and speed up the repair. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the steps of a chip fault prediction method in one embodiment of the present invention; Figure 2 is a structural block diagram of a chip fault prediction device in one embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 It is a schematic diagram of the steps of a chip fault prediction method in one embodiment of the present invention; An embodiment of the present invention provides a chip fault prediction method, comprising the following steps: Step S1, collecting electrical operation data of a target chip, and preprocessing the electrical operation data to obtain preprocessed electrical operation data.

[0021] Specifically, in the above-mentioned step of "collecting the electrical operation data of the target chip, and preprocessing the electrical operation data to obtain the preprocessed electrical operation data", it is first necessary to use high-precision data acquisition equipment, such as current and voltage sensors or dedicated integrated circuit test instruments, to collect various electrical parameters of the target chip during operation, such as current, voltage, temperature and other information. These data reflect the performance of the chip under different working conditions and are an important basis for evaluating the health of the chip. Next, in order to ensure the effectiveness and accuracy of subsequent processing, the collected raw data must be preprocessed. The preprocessing process usually includes operations such as noise removal, filling missing values, standardization or normalization, the purpose of which is to eliminate outliers and interference factors in the data, making the data cleaner and neater for further analysis. For example, in a complex communication device, due to the influence of environmental factors, random noise may be mixed into the collected data. At this time, filtering technology can be used to eliminate this part of the noise, and interpolation methods can be used to fill in the missing data caused by sensor failures and other reasons. Through such preprocessing, more reliable and representative electrical operation data can be obtained, laying a solid foundation for subsequent feature extraction and state network construction.

[0022] Step S2, performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data.

[0023] Specifically, after completing the collection of electrical operation data of the target chip and preprocessing, the next key step is to extract features from the preprocessed electrical operation data to obtain electrical operation extraction feature data. This process is mainly to mine important features that can reflect the operating status of the chip from a large amount of data, which are crucial for subsequent fault prediction. Feature extraction can be achieved through a variety of algorithms, such as Fourier transform, wavelet transform, or feature selection methods in machine learning. These technologies can help us identify periodic components, frequency domain characteristics, and nonlinear characteristics in the data, which are important indicators for evaluating the health of the chip. Taking Fourier transform as an example, it can convert signals in the time domain into representations in the frequency domain, so as to help us observe the changes in signal strength at certain specific frequencies, which is very useful for detecting whether there are abnormal vibrations or other unstable factors inside the chip. In the machine learning method, by constructing a feature matrix and applying algorithms such as principal component analysis (PCA) and support vector machine (SVM), the most representative feature combination can be screened out from multi-dimensional data to further improve the accuracy of fault prediction. For example, in a high-performance computing server, by monitoring the electrical operation data of the core processor on the server motherboard for a long time, we can use the above feature extraction technology to identify key features associated with processor overheating, power supply abnormalities, etc. from massive data streams, thereby providing strong support for subsequent fault prediction and diagnosis. In this way, through effective feature extraction, we can not only significantly reduce the dimension of the data and reduce the computing burden, but also significantly improve the efficiency and accuracy of fault prediction.

[0024] Step S3: constructing an electrical operation status network of the target chip based on the electrical operation extraction feature data.

[0025] Specifically, after the feature extraction of the pre-processed electrical operation data is completed, the next step is to build the electrical operation state network of the target chip based on the extracted feature data of the electrical operation. This process aims to use the extracted features to establish a model that can fully reflect the chip operation state, so as to facilitate further analysis and prediction. Specifically, building the electrical operation state network involves selecting appropriate modeling methods, which can be determined according to the characteristics of the feature data and the expected application scenarios. For example, a graph model in graph theory can be used to regard each chip component as a node in the graph, and the connections between the nodes represent the interactions or dependencies between them. In addition, machine learning models such as neural networks and decision trees can also be used to build state networks. These models can automatically learn and capture the complex relationships between feature data, so as to more accurately simulate the actual operation of the chip. Taking neural networks as an example, we can use the extracted feature data as the nodes of the input layer, and finally output a result that can characterize the chip operation state through learning and adjustment of the hidden layer. In this process, the neural network will continuously optimize the weights according to the training data so that the model can better fit the actual operation state. For example, in the application scenario of high-performance computing servers, by monitoring the electrical operation data of the core processor on the server motherboard for a long time and using the above method to build an electrical operation status network, we can more intuitively understand the operating characteristics of the processor under different load conditions. In this way, when the network model training is completed, it can not only reflect the current operating status of the chip, but also be used to predict possible future faults and provide a scientific basis for taking preventive measures. The electrical operation status network constructed in this way can not only enhance the accuracy of fault prediction, but also provide a solid foundation for fault location and fault path propagation analysis.

[0026] Step S4, using a node state prediction algorithm, based on the electrical operation state network, performs node state prediction on the target chip to obtain a node state prediction result.

[0027] Specifically, after the electrical operation status network of the target chip is constructed, the next key step is to use the node state prediction algorithm to predict the node state of the target chip based on the electrical operation status network to obtain the node state prediction result. The core of this process is to use the algorithm to analyze the state of each node in the network and predict their changing trends in the future. The selection of the node state prediction algorithm needs to consider multiple factors, including the prediction accuracy, computational efficiency and adaptability to different types of faults of the algorithm. Common prediction algorithms include time series analysis, support vector machine, deep learning model, etc. These methods can predict future situations based on existing data patterns. Taking the long short-term memory network (LSTM) in deep learning as an example, it can process time series data well and capture time dependencies, which is very suitable for predicting the state changes of each node inside the chip. First, the node feature data in the constructed electrical operation status network is input into the LSTM model. The model establishes an internal time dependency model by learning the change law of these data over time. Then, the trained model is used to predict the node state at a certain point in the future. For example, in the application scenario of high-performance computing servers, by analyzing the historical operating data of the core processor and its related circuit nodes on the server motherboard, the LSTM model can predict which nodes may have problems such as overheating and excessive current under specific workload conditions. Through such predictions, system administrators can take measures in advance, such as adjusting workload distribution and strengthening heat dissipation, to avoid potential failures. In addition, the node status prediction results can also provide important reference information for subsequent fault location and fault path propagation analysis, helping technicians to find the root cause of the fault more quickly and develop effective response strategies. In short, analyzing the electrical operation status network through the node status prediction algorithm can not only improve the accuracy of fault prediction, but also provide strong support for maintaining the stable operation of the system.

[0028] Step S5: If the node status prediction result indicates that the target chip is faulty, the fault location of the target chip is performed based on the node status prediction result to obtain the fault position of the target chip.

[0029] Specifically, when the node state prediction result shows that the target chip has a fault, it is necessary to locate the fault of the target chip based on the node state prediction result to determine the specific location of the fault. This process is to further analyze and identify which specific nodes or areas have problems based on the existing prediction results. The accuracy of fault location directly affects the efficiency and effect of subsequent maintenance work, so it is crucial to choose a suitable method. Common methods include physical model-based fault diagnosis, rule-based expert systems, and machine learning-based technologies. These methods can make a comprehensive judgment based on the node state prediction results in the electrical operation status network, combined with the design principles and operation characteristics of the chip. For example, in the application scenario of a high-performance computing server, it is assumed that the LSTM model predicts that a power supply module of a core processor may have an abnormal increase in current in the future, which may be caused by aging or damage of a component inside the module. In this case, the physical model-based fault diagnosis method can be further used to verify the prediction results in combination with the design parameters and working principles of the power supply module. At the same time, the pre-established fault knowledge base can also be called to find the fault mode that matches the prediction result, so as to accurately locate the specific fault location, such as a capacitor or resistor. In addition, with the help of visualization tools, the prediction results and fault location information can be intuitively displayed to help engineers quickly understand and handle faults. This method can not only improve the accuracy of fault location, but also shorten the troubleshooting time and ensure the stable operation of the system. In general, fault location based on node status prediction results provides strong technical support for efficiently and accurately solving chip faults.

[0030] Step S6, performing fault path propagation analysis on the target chip based on the fault location to obtain a fault propagation path, and formulating corresponding fault coping measures based on the fault location and the fault propagation path.

[0031] Specifically, after determining the fault location of the target chip, it is necessary to perform a fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path. The purpose of this analysis is to understand how the fault gradually spreads along the connection path inside the chip from the initial location, so as to predict other areas that the fault may affect. Fault path propagation analysis usually involves the use of simulation software or specialized algorithms. These tools can simulate the propagation process of the fault inside the chip and help engineers identify all nodes or circuit parts that may be affected by the fault. For example, in the application scenario of a high-performance computing server, if the power supply module of a core processor is found to be faulty through fault location, then it is necessary to perform a fault path propagation analysis on the power supply module. Circuit simulation software can be used to input the known fault location and the circuit topology of the chip, and run the simulation program to simulate the flow path of the current under the fault state. By analyzing the simulation results, it can be clearly seen how the fault current starts from the power supply module and gradually affects other parts of the processor along the power supply line, and may even extend to the memory controller or other peripherals connected to it. This detailed fault propagation path analysis provides a scientific basis for formulating effective fault response measures. Based on the information of the fault location and fault propagation path, more accurate and efficient fault response measures can be formulated. For example, if the fault propagation path shows that the fault may affect the cache module of the processor, then this part can be monitored in advance, and measures such as redundant switching or reducing the operating frequency can be taken if necessary to prevent the fault from further deteriorating. At the same time, the optimal maintenance path can be planned according to the fault propagation path, and the key nodes most affected can be repaired first to ensure that the system can resume normal operation as soon as possible. In this way, not only can the scope of the fault be effectively controlled, the maintenance time and cost can be reduced, but also the overall performance and stability of the system can be protected to the maximum extent. In short, fault path propagation analysis is an important part of fault management, which provides important guidance and support for fault prevention and repair.

[0032] In a specific embodiment, the collecting electrical operation data of the target chip and preprocessing the electrical operation data to obtain preprocessed electrical operation data includes: Collecting electrical data of the target chip through a preset multimodal sensor to obtain original operation data; removing noise from the original operation data to obtain electrical operation data; Regularizing the electrical operation data by using a fractal dimension analysis method to obtain regularized operation data; Using a preset blind source separation algorithm to separate the data types of the running regularized data to obtain independent source data; Reorganizing the independent source data to obtain reorganized operation data; The reorganized operating data is mapped using a preset nonlinear technology to obtain nonlinear mapping data, and the nonlinear mapping data is used as preprocessing operating data; wherein the preprocessing operating data includes voltage operating data, current operating data and power operating data.

[0033] Specifically, when implementing the step of "collecting the electrical operation data of the target chip, and preprocessing the electrical operation data to obtain the preprocessed electrical operation data", it is first necessary to collect the electrical data of the target chip through a preset multimodal sensor to obtain the original operation data. The multimodal sensor here refers to a sensor that can measure multiple electrical parameters at the same time, such as a current sensor, a voltage sensor, a temperature sensor, etc. These sensors can be installed at key locations of the chip, such as the power input terminal, the signal transmission line, the heat sink, etc., to ensure that the various electrical parameters of the chip during operation can be fully and accurately obtained. For example, in the application scenario of a high-performance computing server, these multimodal sensors can be deployed in the core processor and its peripheral circuits on the server motherboard to monitor the changes in the current, voltage, temperature, etc. of the processor under different workloads in real time. After completing the data collection, it is necessary to remove the noise from the original operation data to obtain the electrical operation data. Noise removal is a very critical step in data preprocessing, because the data collected in the actual environment is often affected by various external interferences, such as electromagnetic interference, power supply fluctuations, etc. These interferences will cause a large amount of noise in the data, affecting the accuracy of subsequent analysis. Common noise removal methods include low-pass filtering, high-pass filtering, band-pass filtering, etc. These methods can effectively filter out high-frequency noise or low-frequency drift and retain useful signal components. For example, in a high-performance computing server, a digital filter can be used to remove data noise caused by electromagnetic interference to ensure the authenticity and accuracy of signals such as current and voltage. After removing the noise, the electrical operation data needs to be regularized by a fractal dimension analysis method to obtain regularized operation data. Fractal dimension analysis is a mathematical method used to quantify the complexity and irregularity of data. By calculating the fractal dimension of data, the inherent structural characteristics of the data can be revealed, which helps to discover patterns and laws in the data. In chip fault prediction, fractal dimension analysis can help identify abnormal points and mutations in the data, thereby providing clues for subsequent fault detection. For example, in a high-performance computing server, by performing fractal dimension analysis on the current data of the processor, the irregularity of current changes in certain time periods can be found, which may be caused by instability or failure of the internal circuit. Next, the data types of the regularized operation data are separated using a preset blind source separation algorithm to obtain independent source data. Blind source separation algorithm is a signal processing technology that can separate independent source signals from mixed signals without knowing the source signals. In chip fault prediction, blind source separation algorithm can be used to separate different electrical parameter signals, such as current, voltage, temperature, etc. These signals are often mixed together during the actual acquisition process. By separating independent source signals, the change trend of each electrical parameter can be observed more clearly, providing purer data for subsequent feature extraction and fault prediction.For example, in a high-performance computing server, an independent component analysis (ICA) algorithm can be used to separate the mixed current and voltage data into independent current signals and voltage signals for analysis. The independent source data is reorganized to obtain reorganized operating data. The purpose of data reorganization is to reorganize the separated independent source data into a form suitable for subsequent processing. In chip fault prediction, data reorganization can include operations such as data rearrangement, merging, and segmentation to ensure the consistency and integrity of the data format. For example, in a high-performance computing server, the separated current signal and voltage signal can be rearranged in chronological order to form a new time series data set, which is convenient for subsequent time series analysis and prediction. Finally, the reorganized operating data is mapped using a preset nonlinear technology to obtain nonlinear mapping data, and the nonlinear mapping data is used as preprocessing operating data. Nonlinear technology is a method for processing nonlinear relationships, which can map data from one space to another space to reveal the nonlinear characteristics implicit in the data. In chip fault prediction, nonlinear technology can help discover nonlinear patterns and complex relationships in data and improve the accuracy of fault prediction. For example, in high-performance computing servers, nonlinear dimensionality reduction techniques such as kernel principal component analysis (KPCA) can be used to map the reorganized current and voltage data into a high-dimensional feature space, thereby better capturing the nonlinear characteristics in the data. Through such nonlinear mapping, the final pre-processed operation data not only includes voltage operation data, current operation data, and power operation data, but also can more accurately reflect the operating characteristics of the chip under different working conditions, providing high-quality data support for subsequent feature extraction and fault prediction.

[0034] In a specific embodiment, the step of extracting features from the pre-processed electrical operation data to obtain electrical operation extracted feature data includes: Performing time series analysis on the pre-processed electrical operation data to obtain electrical time series characteristics; Performing frequency domain analysis on the electrical timing characteristics by using Fourier transform to obtain electrical frequency domain characteristics; Performing statistical feature extraction on the electrical frequency domain features to obtain electrical statistical feature data; Performing electrical correlation analysis on the electrical timing characteristics based on the electrical statistical characteristic data to obtain electrical correlation characteristic data; wherein the electrical correlation characteristic data is used to capture the relationship and dependency between different electrical parameters; Feature extraction is performed on the electrical correlation feature data to obtain electrical operation extraction feature data; wherein the electrical operation extraction feature data is used to describe the correlation, coupling degree or causal relationship between different electrical timing features.

[0035] Specifically, in the process of extracting features from the pre-processed electrical operation data, it is first necessary to perform time series analysis on the pre-processed electrical operation data to obtain electrical time series features. Time series analysis is to reveal the dynamic characteristics and periodic behavior in the data by studying the law of data change over time. In the application scenario of high-performance computing servers, the change trends of these electrical parameters in different time periods can be identified by performing time series analysis on the pre-processed operation data such as current, voltage, and power. For example, the current change pattern of the processor under high load and low load conditions can be analyzed using methods such as the moving average method and the autoregressive moving average model (ARIMA) to understand its operating characteristics under different working conditions. After completing the time series analysis, it is necessary to perform frequency domain analysis on the electrical time series features using Fourier transform to obtain electrical frequency domain features. Fourier transform is a mathematical tool that converts time domain signals into frequency domain signals. Through Fourier transform, time series data can be decomposed into sinusoidal wave components of different frequencies, thereby revealing periodic features in the data. In a high-performance computing server, by performing Fourier transform on the timing characteristics of current and voltage, the amplitude and phase information of these signals at different frequencies can be identified, which is very useful for detecting abnormal conditions such as harmonic distortion and noise interference inside the chip. For example, if an abnormally high amplitude is found at a certain frequency, this may indicate that there is a periodic interference source inside the chip. After obtaining the electrical frequency domain characteristics, it is necessary to perform statistical feature extraction on the electrical frequency domain characteristics to obtain electrical statistical feature data. Statistical feature extraction is to extract representative statistics from frequency domain characteristics, such as mean, variance, kurtosis, skewness, etc. These statistics can reflect the central tendency, discrete degree and distribution form of the data. In a high-performance computing server, the mean and variance of the frequency domain characteristics of current and voltage can be calculated to understand the basic statistical characteristics of these signals in the frequency domain. For example, if it is found that the frequency domain variance of the current increases significantly within a certain period of time, this may mean that the chip has experienced a large current fluctuation during this period of time, and the cause needs to be further investigated. Based on the electrical statistical feature data, it is then necessary to perform electrical correlation analysis on the electrical timing characteristics to obtain electrical correlation feature data. The purpose of electrical correlation analysis is to study the relationship and dependence between different electrical parameters. Through correlation analysis, the correlation, coupling or causal relationship between electrical parameters can be found. In high-performance computing servers, correlation coefficients, mutual information, Granger causality tests and other methods can be used to analyze the correlation between parameters such as current, voltage, and power. For example, by calculating the correlation coefficient between current and voltage, it can be determined whether there is a linear relationship between the two; through mutual information analysis, the degree of nonlinear dependence between current and temperature can be understood; through Granger causality tests, it can be determined whether current changes will cause voltage changes. Finally, feature extraction is performed on the electrical correlation feature data to obtain electrical operation extraction feature data.This process aims to extract features from electrical correlation feature data that can fully describe the correlation, coupling or causal relationship between different electrical timing features. In high-performance computing servers, methods such as principal component analysis (PCA) and independent component analysis (ICA) can be used to reduce the dimension and select features of electrical correlation feature data to extract the most representative features. For example, PCA can reduce the dimension of multiple related electrical parameters to a few principal components, which can retain the variation information of the original data to the greatest extent; ICA can separate the independent components between different electrical parameters and reveal the nonlinear relationship between them. The final electrical operation extraction feature data can not only fully reflect the electrical characteristics of the chip under different working conditions, but also provide an important basis for subsequent fault prediction and diagnosis. Through this series of feature extraction steps, the accuracy and reliability of fault prediction can be significantly improved, providing a strong guarantee for the stable operation of high-performance computing servers.

[0036] In a specific embodiment, the step of constructing an electrical operation state network of a target chip based on the electrical operation extraction feature data includes: Acquire a structural diagram of the target chip and components in the structural diagram corresponding to the electrical operation extraction feature data from a database; Based on the structure diagram and the elements corresponding to the electrical operation extracted feature data, the electrical operation extracted feature data is subjected to graph structure processing to obtain an electrical operation diagram; wherein the electrical operation diagram includes nodes and edges, the nodes are elements in the target chip structure diagram, and the edges are connection relationships between elements in the target chip structure diagram; The electrical operation diagram is divided into sub-graphs by a preset spectral clustering algorithm to obtain a plurality of sub-graphs; wherein each of the sub-graphs represents a functional module in the target chip; Constructing a corresponding electrical operation matrix based on each of the subgraphs respectively; wherein the electrical operation matrix includes rows, columns and elements; the rows represent the position identifiers of each component, the columns represent the components corresponding to the electrical operation extracted feature data, and the elements represent the electrical operation extracted feature data; Combining the electrical operation matrices to obtain a combined matrix; Performing graph reconstruction processing on the structure graph based on the combination matrix to obtain an initial electrical operation state network; The initial electrical operation state network is visualized to obtain a visualized electrical operation state network, and the visualized electrical operation state network is used as the electrical operation state network of the target chip.

[0037] Specifically, in the process of constructing the electrical operation status network of the target chip based on the electrical operation extraction feature data, it is first necessary to obtain the structure diagram of the target chip and the components corresponding to the electrical operation extraction feature data in the structure diagram from the database. This step is to ensure that the subsequent graph structuring processing can accurately reflect the physical structure and electrical characteristics inside the chip. In the application scenario of high-performance computing servers, the detailed structure diagram of the core processor and its surrounding circuits, including the location, type and connection relationship of each component, can be obtained by accessing the database provided by the chip manufacturer. At the same time, it is also necessary to match these structural information with the electrical operation feature data extracted previously to find the specific components corresponding to the feature data. For example, if the feature data contains a current anomaly at a certain frequency, it is necessary to determine which specific capacitor or resistor component the current anomaly at this frequency is associated with. After obtaining the structure diagram of the target chip and the corresponding component information, it is necessary to perform graph structuring processing on the electrical operation extraction feature data based on the structure diagram and the components corresponding to the electrical operation extraction feature data to obtain an electrical operation diagram. The purpose of graph structuring processing is to convert the electrical operation feature data into a graph form to facilitate subsequent analysis and processing. In a high-performance computing server, each element in the structure diagram can be used as a node, and the connection relationship between the elements can be used as an edge to construct a graph model. In this graph model, the node represents a specific element, and the edge represents the electrical connection relationship between the elements. For example, the power input terminal of the processor can be used as a node, and the connection line between the power input terminal and the processor can be used as an edge, so that a preliminary electrical operation diagram is formed. After completing the graph structure processing, it is necessary to divide the electrical operation diagram into subgraphs using a preset spectral clustering algorithm to obtain multiple subgraphs. The spectral clustering algorithm is a graph-based clustering method. By calculating the eigenvectors of the Laplace matrix of the graph, the nodes in the graph can be divided into multiple subgraphs, and each subgraph represents a functional module in the target chip. In a high-performance computing server, the spectral clustering algorithm can be used to divide the processor and its surrounding circuits into different functional modules, such as a power management module, a data processing module, a signal transmission module, etc. Through subgraph division, the operating status of each functional module inside the chip can be better understood, providing support for subsequent fault prediction and diagnosis. After obtaining multiple subgraphs, it is necessary to construct a corresponding electrical operation matrix based on each of the subgraphs. The electrical operation matrix is ​​a two-dimensional array, in which the rows represent the position identification of each component, the columns represent the components corresponding to the electrical operation extracted feature data, and the elements represent the electrical operation extracted feature data. In a high-performance computing server, an electrical operation matrix can be constructed for each sub-graph, in which the rows of the matrix represent the positions of each component in the sub-graph, the columns represent the electrical operation feature data corresponding to these components, and the elements are the specific feature values.For example, in the electrical operation matrix of the power management module, the row can represent the position of components such as the power input terminal and the voltage regulator, the column can represent the characteristic data such as the current and voltage of these components, and the element is the specific current value or voltage value. The electrical operation matrices are combined to obtain a combined matrix. The purpose of the combined matrix is ​​to integrate the electrical operation matrices of each sub-graph into a complete matrix for subsequent overall analysis. In a high-performance computing server, the electrical operation matrices of each sub-graph such as the power management module, the data processing module, and the signal transmission module can be arranged in a certain order to form a large combined matrix. This combined matrix not only contains the electrical operation characteristic data of each sub-graph, but also retains the relative position relationship between each sub-graph, which provides a basis for subsequent graph reconstruction processing. The structure graph is reconstructed based on the combined matrix to obtain an initial electrical operation state network. The purpose of the graph reconstruction processing is to reorganize the information in the combined matrix into a graph form to form a network model that can fully reflect the chip operation state. In a high-performance computing server, the sub-graphs in the combined matrix can be recombined into a complete electrical operation state network through graph reconstruction processing. This network model not only includes the position and connection relationship of each component, but also includes the electrical operation characteristic data of each component, which can fully reflect the operation of the chip under different working conditions. Finally, the initial electrical operation state network is visualized to obtain a visualized electrical operation state network, and the visualized electrical operation state network is used as the electrical operation state network of the target chip. The purpose of visualization is to display the complex electrical operation state network in a graphical form, which is convenient for engineers to intuitively understand and analyze. In high-performance computing servers, professional visualization tools can be used to display each node, edge and characteristic data in the initial electrical operation state network in the form of a graph. For example, different components can be represented by nodes of different colors, the connection strength between components can be represented by edges of different thicknesses, and specific characteristic data values ​​can be displayed by labels. Through such visualization, engineers can see at a glance the operation of the chip under different working conditions, providing an intuitive basis for fault prediction and diagnosis. Through this series of steps, not only can the electrical operation extraction characteristic data be combined with the physical structure of the chip to construct a network model that fully reflects the chip operation state, but also can provide strong support for subsequent fault prediction and diagnosis. In the application scenario of high-performance computing servers, this method based on the electrical operation status network can significantly improve the accuracy and efficiency of fault prediction and ensure the stable operation of the system.

[0038] In a specific embodiment, the node state prediction algorithm is used to predict the node state of the target chip based on the electrical operation state network to obtain the node state prediction result, including: Input the electrical operation status network into a preset graph neural network algorithm; wherein the node status prediction algorithm includes a convolution module, a multi-head attention mechanism module, a time series modeling module, a feature fusion module, an adaptive pooling module and a prediction module; Performing a deep graph convolution operation on the electrical operation status network through the convolution module to obtain an initial node feature vector; Performing a multi-head attention mechanism calculation on the initial node feature vector through the multi-head attention mechanism module to obtain a node weighted feature vector; Performing time series modeling on the node weighted feature vector through the time series modeling module to obtain a node time series feature vector; Performing feature fusion on the node time series feature vectors through the feature fusion module to obtain a node fusion feature vector; The node fusion feature vector is dimensionally adjusted by the adaptive pooling module to obtain a node state representation vector; The prediction module predicts the node state of the target chip based on the node state representation vector to obtain a node state prediction result.

[0039] Specifically, in the process of predicting the node state of the target chip based on the electrical operation state network through the node state prediction algorithm, the electrical operation state network needs to be first input into the preset graph neural network algorithm. The node state prediction algorithm used here includes a convolution module, a multi-head attention mechanism module, a time series modeling module, a feature fusion module, an adaptive pooling module and a prediction module. This series of modules work together to achieve accurate prediction of the node state of the target chip through multi-stage processing. In the application scenario of high-performance computing servers, it is assumed that we have built an electrical operation state network that fully reflects the operating state of the core processor and its surrounding circuits. This network not only contains the position and connection relationship of each component, but also contains the electrical operation feature data of each component. In order to predict the future state of these nodes, we input this electrical operation state network into the preset graph neural network algorithm. First, the electrical operation state network is subjected to a deep graph convolution operation through the convolution module to obtain an initial node feature vector. Graph convolution operation is a method of performing convolution on graph structure data, which can capture local structural information between nodes. In a high-performance computing server, the feature information of each node and its neighboring nodes can be extracted through a graph convolution operation to form an initial node feature vector. For example, for a power input node of a processor, the graph convolution operation can extract the feature information of the power input terminal and its connected voltage regulator, capacitor and other components to form an initial feature vector containing this information. Next, the multi-head attention mechanism module performs a multi-head attention mechanism calculation on the initial node feature vector to obtain a node weighted feature vector. The multi-head attention mechanism is a method that can capture complex dependencies between nodes. Through multiple attention heads, different aspects of the node can be focused on at the same time. In a high-performance computing server, the importance of each node in different contexts can be calculated through a multi-head attention mechanism to form a node weighted feature vector. For example, for a power input node of a processor, the multi-head attention mechanism can calculate the importance of the power input terminal under different workloads to form a weighted feature vector to better reflect the dynamic characteristics of the node. Then, the node weighted feature vector is subjected to time series modeling by the time series modeling module to obtain a node time series feature vector. The purpose of time series modeling is to capture the law of changes in node features over time. In high-performance computing servers, time series modeling methods such as long short-term memory networks (LSTM) or gated recurrent units (GRU) can be used to analyze the changing trend of node weighted feature vectors over time and form node time series feature vectors. For example, for the power input node of the processor, time series modeling can capture the current changing trend of the power input terminal in different time periods and form a time series feature vector that reflects the dynamic behavior of the node.Next, the feature fusion module performs feature fusion on the node time series feature vector to obtain a node fusion feature vector. The purpose of feature fusion is to combine feature information from different sources to form a richer feature representation. In a high-performance computing server, the node time series feature vector can be fused with other feature vectors (such as static features, environmental features, etc.) through methods such as feature splicing and feature weighted summation to form a node fusion feature vector. For example, for the power input node of the processor, the time series feature vector can be fused with the temperature feature vector, the load feature vector, etc. to form a comprehensive feature vector that more comprehensively reflects the operating status of the node. Subsequently, the node fusion feature vector is dimensionally adjusted through the adaptive pooling module to obtain a node state representation vector. Adaptive pooling is a method that can dynamically adjust the dimension of feature vectors, and can compress feature vectors to a fixed dimension according to the requirements of the task. In a high-performance computing server, the node fusion feature vector can be compressed to a fixed-length vector through adaptive pooling to form a node state representation vector. For example, for the power input node of the processor, adaptive pooling can compress the fusion feature vector to a 128-dimensional vector to facilitate subsequent prediction processing. Finally, the prediction module predicts the node state of the target chip based on the node state representation vector to obtain the node state prediction result. The purpose of the prediction module is to predict the state of the node at a certain point in the future based on the node state representation vector. In high-performance computing servers, classification or regression models such as fully connected neural networks and support vector machines (SVMs) can be used to predict the current, voltage and other states of the node at a certain point in the future based on the node state representation vector. For example, for the power input node of the processor, the prediction module can predict the current value of the power input terminal at the next time point. If the prediction result exceeds the normal range, measures can be taken in advance to avoid potential failures. Through this series of steps, not only can the structural information and feature information in the electrical operation status network be fully utilized, but also the deep-level features of the node can be gradually extracted through multi-stage processing, and finally the node state of the target chip can be accurately predicted. In the application scenario of high-performance computing servers, this node state prediction method based on graph neural networks can significantly improve the accuracy and efficiency of fault prediction and ensure the stable operation of the system.

[0040] In a specific embodiment, the step of locating the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip includes: Using the node status prediction results, status screening is performed on nodes in the electrical operation status network to obtain suspected fault nodes; Using a graph diffusion algorithm, locally diffuse the electrical operation status network based on the suspected fault node to obtain a diffusion node set; Using a community detection algorithm, the target chip is divided into communities based on the diffusion node set to obtain a community division result; Based on the community division result, importance scoring is performed on the nodes of the target chip to obtain an importance scoring result; According to the importance scoring result, the node with the highest score is selected as the candidate fault node; The fault position of the target chip is located based on the candidate fault nodes and the node state prediction result to obtain the fault position of the target chip.

[0041] Specifically, in the process of locating the fault of the target chip based on the node state prediction result, it is first necessary to screen the nodes in the electrical operation state network based on the node state prediction result to obtain suspected fault nodes. The purpose of this process is to screen out those nodes with abnormal states from a large number of nodes as the focus of subsequent analysis. In the application scenario of high-performance computing servers, it is assumed that we have obtained the state prediction results of each node through the graph neural network algorithm. These results may include the predicted values ​​of the current, voltage, temperature and other parameters of the node. By setting a threshold, those nodes whose predicted values ​​exceed the normal range can be screened out and marked as suspected fault nodes. For example, if the current prediction value of a node is significantly higher than the normal range, then this node can be marked as a suspected fault node. After completing the state screening, it is necessary to use the graph diffusion algorithm to locally diffuse the electrical operation state network based on the suspected fault nodes to obtain a set of diffusion nodes. The graph diffusion algorithm is a method of propagating information in graph structured data. By starting from the suspected fault node and gradually diffusing to its neighboring nodes, other nodes associated with the suspected fault node can be found. In a high-performance computing server, a graph diffusion algorithm can be used to gradually diffuse from a node marked as a suspected fault to nodes directly or indirectly connected to it, forming a diffusion node set. For example, assuming that the power input node of the processor is marked as a suspected fault node, then the graph diffusion algorithm can be used to include the voltage regulator, capacitor and other nodes directly connected to the power input, as well as other nodes indirectly connected through these nodes, into the diffusion node set. After obtaining the diffusion node set, it is necessary to use a community detection algorithm to perform community division on the target chip based on the diffusion node set to obtain a community division result. The community detection algorithm is a method for dividing the nodes in a graph into several closely connected subgraphs. Through community division, the nodes in the diffusion node set can be divided into several functional modules or subsystems. In a high-performance computing server, the community detection algorithm can be used to divide the nodes in the diffusion node set into different functional modules such as a power management module, a data processing module, and a signal transmission module. For example, assuming that the diffusion node set contains nodes such as a power input terminal, a voltage regulator, and a capacitor, these nodes can be divided into a power management module through the community detection algorithm. Based on the community division results, it is necessary to perform importance scoring on the nodes of the target chip to obtain importance scoring results. The purpose of importance scoring is to evaluate the importance of each node in the community, so as to find the node that is most likely to be the source of the fault. In high-performance computing servers, the importance of nodes can be scored by calculating indicators such as the centrality, betweenness centrality, and closeness centrality of the nodes. For example, the betweenness centrality of each node can be calculated. Nodes with higher betweenness centrality are usually bridge nodes connecting different subsystems. Failures of these nodes may affect the normal operation of the entire system.According to the importance scoring result, the node with the highest score is selected as the candidate fault node. In a high-performance computing server, the nodes with the highest importance score can be used as candidate fault nodes, and these nodes are most likely to be the source of the fault. For example, assuming that in the power management module, the betweenness centrality of a capacitor node is the highest, then this capacitor node can be selected as a candidate fault node. Finally, the fault position of the target chip is located based on the candidate fault node and the node state prediction result to obtain the fault position of the target chip. The purpose of fault location positioning is to determine the specific location of the fault and provide a basis for subsequent fault processing. In a high-performance computing server, the location of the fault can be further confirmed by comparing the state prediction results of the candidate fault node with the state prediction results of other nodes. For example, if the current prediction value of the candidate fault node is significantly higher than that of other nodes, and the betweenness centrality of the node is the highest, then it can be determined that the node is the specific location of the fault. Through this series of steps, not only can the suspected fault nodes be quickly screened out from a large number of nodes, but also the fault range can be gradually narrowed through methods such as graph diffusion algorithm, community detection algorithm and importance scoring, and finally the specific location of the fault can be accurately located. In the application scenario of high-performance computing servers, this fault location method based on node status prediction results can significantly improve the accuracy and efficiency of fault location and ensure the stable operation of the system.

[0042] In a specific embodiment, performing fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path includes: By using a preset spatial autocorrelation analysis method, a neighborhood analysis is performed on the fault location to identify hot spots around the fault location and obtain a fault impact area; By using a preset community detection algorithm, the fault affected area is divided into functional modules to obtain a modular fault network; Modeling the time series data of the modular fault network to analyze the changing trend of the fault location over time and obtain the fault evolution path; Performing causal relationship mining on the fault evolution path to obtain a causal link graph; A multi-agent system is used to simulate the propagation process of the fault location inside the target chip based on the causal link diagram to obtain the fault propagation path.

[0043] Specifically, in the process of performing fault path propagation analysis on the target chip based on the fault location, it is first necessary to perform neighborhood analysis on the fault location through a preset spatial autocorrelation analysis method to identify hot spots around the fault location and obtain the fault impact area. Spatial autocorrelation analysis is a statistical method used to detect aggregation and correlation in spatial data. In the application scenario of a high-performance computing server, it is assumed that we have determined that a certain capacitor node is the specific location of the fault through the previous steps. Next, the nodes around the fault location can be analyzed by the spatial autocorrelation analysis method to identify which nodes are affected by the fault and form a fault impact area. For example, methods such as Moran's I or Getis-Ord General G can be used to calculate the autocorrelation of state characteristics (such as current, voltage, etc.) of nodes near the fault location, thereby identifying hot spots. These hot spots are usually manifested as a group of adjacent nodes whose state characteristic values ​​are significantly higher or lower than the normal range. After completing the neighborhood analysis, it is necessary to divide the fault impact area into functional modules through a preset community detection algorithm to obtain a modular fault network. The community detection algorithm is a method for dividing the nodes in a graph into several closely connected subgraphs. Through community division, the nodes in the fault impact area can be divided into different functional modules. In a high-performance computing server, the community detection algorithm can be used to divide the nodes in the fault impact area into different functional modules such as a power management module, a data processing module, and a signal transmission module. For example, assuming that the fault impact area includes nodes such as a power input terminal, a voltage regulator, and a capacitor, these nodes can be divided into a power management module through the community detection algorithm. The time series data of the modular fault network is modeled to analyze the changing trend of the fault location over time and obtain the fault evolution path. The purpose of time series data modeling is to predict the development direction of the fault by analyzing the changing trend of the fault location over time. In a high-performance computing server, the changing trend of the state characteristics of each node in the modular fault network over time can be analyzed by time series modeling methods such as long short-term memory network (LSTM) and autoregressive integrated moving average model (ARIMA). For example, the LSTM model can be used to input the time series data of the current, voltage, etc. of each node in the modular fault network to predict the state change trend of these nodes in the future, thereby obtaining the fault evolution path. This step can help us understand how the fault gradually spreads over time and provide a basis for subsequent fault propagation analysis. The fault evolution path is subjected to causal mining to obtain a causal link diagram. The purpose of causal mining is to reveal the inherent mechanism of fault propagation by analyzing the causal relationship in the fault evolution path. In high-performance computing servers, causal inference methods such as Granger causality test and Bayesian network can be used to analyze the causal relationship between nodes in the fault evolution path.For example, Granger causality test can be used to analyze whether the current change at the power input terminal causes the voltage fluctuation of the regulator, thereby forming a causal link graph. This causal link graph not only shows the path of fault propagation, but also reveals the causal relationship between each node, providing important reference information for fault propagation analysis. Finally, a multi-agent system is used to simulate the propagation process of the fault location inside the target chip based on the causal link graph to obtain the fault propagation path. A multi-agent system is a method to simulate the behavior of a complex system through the interaction of multiple autonomous agents. In a high-performance computing server, a multi-agent system can be used to simulate the propagation process of the fault location inside the target chip based on a causal link graph. For example, an agent can be set for each node, and these agents interact according to the relationship in the causal link graph to simulate the process of the fault gradually propagating from the initial position to other nodes. Through the simulation of the multi-agent system, a detailed fault propagation path can be generated to show how the fault gradually spreads from the initial position to the entire chip. This step can not only help us understand the specific process of fault propagation, but also provide a scientific basis for the formulation of fault prevention and response measures. Through this series of steps, we can not only analyze the impact range and propagation path of the fault step by step based on the fault location, but also reveal the internal mechanism of fault propagation through time series modeling and causal relationship mining. In the application scenario of high-performance computing servers, this fault path propagation analysis method based on fault location can significantly improve the accuracy and efficiency of fault analysis and ensure the stable operation of the system. Through these methods, we can better prevent and respond to potential faults and improve the reliability and security of the system.

[0044] The above describes the fault prediction method of the chip in the embodiment of the present invention. The following describes the fault prediction system of the chip in the embodiment of the present invention. Figure 2 , an embodiment of a chip fault prediction system in an embodiment of the present invention includes: The acquisition module 21 is used to acquire the electrical operation data of the target chip and pre-process the electrical operation data to obtain pre-processed electrical operation data; An extraction module 22, used for performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data; A construction module 23, configured to construct an electrical operation state network of a target chip based on the electrical operation extraction feature data; A prediction module 24, configured to perform node state prediction on the target chip based on the electrical operation state network by using a node state prediction algorithm to obtain a node state prediction result; A positioning module 25 is used for locating the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip if the node status prediction result indicates that the target chip is faulty; The analysis module 26 is used to perform a fault path propagation analysis on the target chip based on the fault location to obtain a fault propagation path, and formulate corresponding fault coping measures based on the fault location and the fault propagation path.

[0045] In this embodiment, for the specific implementation of each unit in the above system embodiment, please refer to the above method embodiment, which will not be repeated here.

[0046] Reference Figure 3 The present invention also provides a computer device in an embodiment, wherein the internal structure of the computer device can be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0047] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0048] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0049] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0050] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0051] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip failure prediction method, characterized in that: The following steps are involved: Collecting electrical operation data of the target chip, and preprocessing the electrical operation data to obtain preprocessed electrical operation data; Performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data; Building an electrical operation state network of a target chip based on the electrical operation extraction feature data; By using a node state prediction algorithm, a node state prediction is performed on the target chip based on the electrical operation state network to obtain a node state prediction result; If the node state prediction result indicates that the target chip is faulty, locating the fault of the target chip based on the node state prediction result to obtain the fault position of the target chip; Based on the fault location, a fault path propagation analysis is performed on the target chip to obtain a fault propagation path, and corresponding fault coping measures are formulated based on the fault location and the fault propagation path.

2. The chip failure prediction method according to claim 1, characterized in that: The collecting electrical operation data of the target chip and preprocessing the electrical operation data to obtain preprocessed electrical operation data includes: Collecting electrical data of the target chip through a preset multimodal sensor to obtain original operation data; removing noise from the original operation data to obtain electrical operation data; Regularizing the electrical operation data by using a fractal dimension analysis method to obtain regularized operation data; Using a preset blind source separation algorithm to separate the data types of the running regularized data to obtain independent source data; Reorganizing the independent source data to obtain reorganized operation data; The reorganized operating data is mapped using a preset nonlinear technology to obtain nonlinear mapping data, and the nonlinear mapping data is used as preprocessing operating data; wherein the preprocessing operating data includes voltage operating data, current operating data and power operating data.

3. The chip failure prediction method according to claim 1, characterized in that: The step of extracting features from the pre-processed electrical operation data to obtain electrical operation extracted feature data includes: Performing time series analysis on the pre-processed electrical operation data to obtain electrical time series characteristics; Performing frequency domain analysis on the electrical timing characteristics by using Fourier transform to obtain electrical frequency domain characteristics; Performing statistical feature extraction on the electrical frequency domain features to obtain electrical statistical feature data; Performing electrical correlation analysis on the electrical timing characteristics based on the electrical statistical characteristic data to obtain electrical correlation characteristic data; wherein the electrical correlation characteristic data is used to capture the relationship and dependency between different electrical parameters; Feature extraction is performed on the electrical correlation feature data to obtain electrical operation extraction feature data; wherein the electrical operation extraction feature data is used to describe the correlation, coupling degree or causal relationship between different electrical timing features.

4. The chip failure prediction method according to claim 1, characterized in that: The step of constructing an electrical operation state network of a target chip based on the electrical operation extraction feature data comprises: Acquire a structural diagram of the target chip and components in the structural diagram corresponding to the electrical operation extraction feature data from a database; Based on the structure diagram and the elements corresponding to the electrical operation extracted feature data, the electrical operation extracted feature data is subjected to graph structure processing to obtain an electrical operation diagram; wherein the electrical operation diagram includes nodes and edges, the nodes are elements in the target chip structure diagram, and the edges are connection relationships between elements in the target chip structure diagram; The electrical operation diagram is divided into sub-graphs by a preset spectral clustering algorithm to obtain a plurality of sub-graphs; wherein each of the sub-graphs represents a functional module in the target chip; Constructing a corresponding electrical operation matrix based on each of the subgraphs respectively; wherein the electrical operation matrix includes rows, columns and elements; the rows represent the position identifiers of each component, the columns represent the components corresponding to the electrical operation extracted feature data, and the elements represent the electrical operation extracted feature data; Combining the electrical operation matrices to obtain a combined matrix; Performing graph reconstruction processing on the structure graph based on the combination matrix to obtain an initial electrical operation state network; The initial electrical operation state network is visualized to obtain a visualized electrical operation state network, and the visualized electrical operation state network is used as the electrical operation state network of the target chip.

5. The chip failure prediction method according to claim 1, characterized in that: The node state prediction algorithm is used to predict the node state of the target chip based on the electrical operation state network to obtain a node state prediction result, including: Input the electrical operation status network into a preset graph neural network algorithm; wherein the node status prediction algorithm includes a convolution module, a multi-head attention mechanism module, a time series modeling module, a feature fusion module, an adaptive pooling module and a prediction module; Performing a deep graph convolution operation on the electrical operation status network through the convolution module to obtain an initial node feature vector; Performing a multi-head attention mechanism calculation on the initial node feature vector through the multi-head attention mechanism module to obtain a node weighted feature vector; Performing time series modeling on the node weighted feature vector through the time series modeling module to obtain a node time series feature vector; Performing feature fusion on the node time series feature vectors through the feature fusion module to obtain a node fusion feature vector; The node fusion feature vector is dimensionally adjusted by the adaptive pooling module to obtain a node state representation vector; The prediction module predicts the node state of the target chip based on the node state representation vector to obtain a node state prediction result.

6. The chip failure prediction method according to claim 1, characterized in that: The performing fault location on the target chip based on the node status prediction result to obtain the fault position of the target chip includes: Using the node status prediction results, status screening is performed on nodes in the electrical operation status network to obtain suspected fault nodes; Using a graph diffusion algorithm, locally diffuse the electrical operation status network based on the suspected fault node to obtain a diffusion node set; Using a community detection algorithm, the target chip is divided into communities based on the diffusion node set to obtain a community division result; Based on the community division result, importance scoring is performed on the nodes of the target chip to obtain an importance scoring result; According to the importance scoring result, the node with the highest score is selected as the candidate fault node; The fault position of the target chip is located based on the candidate fault nodes and the node state prediction result to obtain the fault position of the target chip.

7. The chip failure prediction method according to claim 1, characterized in that: The performing fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path includes: By using a preset spatial autocorrelation analysis method, a neighborhood analysis is performed on the fault location to identify hot spots around the fault location and obtain a fault impact area; By using a preset community detection algorithm, the fault affected area is divided into functional modules to obtain a modular fault network; Modeling the time series data of the modular fault network to analyze the changing trend of the fault location over time and obtain the fault evolution path; Performing causal relationship mining on the fault evolution path to obtain a causal link graph; A multi-agent system is used to simulate the propagation process of the fault location inside the target chip based on the causal link diagram to obtain the fault propagation path.

8. A chip failure prediction device, characterized in that: include: An acquisition module, used for acquiring electrical operation data of a target chip, and preprocessing the electrical operation data to obtain preprocessed electrical operation data; An extraction module, used for performing feature extraction on the pre-processed electrical operation data to obtain electrical operation extracted feature data; A construction module, used for constructing an electrical operation state network of a target chip based on the electrical operation extraction feature data; A prediction module, configured to perform node state prediction on the target chip based on the electrical operation state network by using a node state prediction algorithm to obtain a node state prediction result; A positioning module, configured to locate the fault of the target chip based on the node status prediction result to obtain the fault position of the target chip if the node status prediction result indicates that the target chip is faulty; The analysis module is used to perform fault path propagation analysis on the target chip based on the fault location to obtain the fault propagation path, and formulate corresponding fault response measures based on the fault location and the fault propagation path.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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