Advanced back-end wire automatic process control system for intelligent chip factory

Abstract

The invention discloses an advanced back-end wire automatic process control system for an intelligent chip factory, and relates to the technical field of chips. The system comprises an insulating layer deposition part, an insulating layer chemical mechanical grinding part, an anti-reflection coating and photoresist coating part, a photoetching part, an etching part, a barrier layer deposition part, an electroplating part, an electroplating layer chemical mechanical grinding part and a cobalt cap layer atomic layer deposition part, virtual measurement is used for predicting parameters of all the parts, process control is assisted, and the manufacturing process is optimized. And the accuracy of automatic process control is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an advanced back-end wire automatic process control system for an intelligent chip factory. Background Art

[0002] The automatic process control in related technologies does not use advanced virtual measurement systems, resulting in prediction data with large errors, causing inaccurate automatic process control. Some are only calculated based on SPC (Statistic Process Control) data without real-time data, resulting in deviations due to insufficient sampling and measurement data. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose an advanced back-end wire automatic process control system for an intelligent chip factory, the system comprising: an insulating layer deposition component, used to perform insulating layer deposition on the wafer according to the insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing component, used to perform insulating layer chemical mechanical polishing on the wafer after deposition according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating component, used to perform anti-reflective coating and photoresist coating on the wafer after chemical mechanical polishing of the insulating layer according to the insulating layer deposition thickness after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography component, used to perform photolithography on the wafer after anti-reflective coating and photoresist coating; an etching component A component is used to etch the wafer after photolithography according to the thickness of the anti-reflective coating and photoresist after coating determined by virtual measurement, the thickness of the insulating layer deposited after grinding determined by virtual measurement, and the etching parameters determined by virtual measurement; a barrier layer deposition component is used to deposit a barrier layer on the etched wafer according to the deposition parameters of the barrier layer determined by virtual measurement; an electroplating component is used to electroplate the wafer after the barrier layer is deposited according to the electroplating parameters determined by virtual measurement; an electroplating layer chemical mechanical polishing component is used to perform electroplating layer chemical mechanical polishing on the electroplated wafer according to the electroplating layer thickness determined by virtual measurement, the electroplating layer grinding thickness determined by virtual measurement, and the key size after etching determined by virtual measurement; a cobalt cap layer atomic layer deposition component is used to perform cobalt cap layer atomic layer deposition on the wafer after the electroplating layer is chemically mechanically polished to obtain the chip corresponding to the wafer.

[0004] To achieve the above-mentioned purpose, the first embodiment of the present application proposes an advanced back-end wire automatic process control system for an intelligent chip factory, the system comprising: an insulating layer deposition component, used to perform insulating layer deposition on a wafer according to the insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing component, used to perform insulating layer chemical mechanical polishing on the deposited wafer according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating component, used to perform anti-reflective coating and photoresist coating on the wafer after the insulating layer chemical mechanical polishing according to the insulating layer deposition thickness after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography component, used to perform photolithography on the wafer after the anti-reflective coating and photoresist coating; An etching component is used to etch the wafer after photolithography according to the thickness of the anti-reflective coating and photoresist after coating determined by virtual measurement, the thickness of the insulating layer deposited after grinding determined by virtual measurement, and the etching parameters determined by virtual measurement; a barrier layer deposition component is used to deposit a barrier layer on the etched wafer according to the deposition parameters of the barrier layer determined by virtual measurement; an electroplating component is used to electroplate the wafer after the barrier layer is deposited according to the electroplating parameters determined by virtual measurement; an electroplating layer chemical mechanical polishing component is used to perform electroplating layer chemical mechanical polishing on the electroplated wafer according to the electroplating layer thickness determined by virtual measurement, the electroplating layer grinding thickness determined by virtual measurement, and the key size after etching determined by virtual measurement; a cobalt cap layer atomic layer deposition component is used to perform cobalt cap layer atomic layer deposition on the wafer after the electroplating layer is chemically mechanically polished to obtain the chip corresponding to the wafer.

[0005] According to one embodiment of the present application, a deposition correspondence is determined according to operating parameters of an insulating layer deposition component and a preset virtual measurement AI model, and insulating layer deposition parameters are determined according to a target insulating layer deposition thickness and the insulating layer deposition correspondence, wherein the insulating layer deposition parameters include an insulating layer deposition time and an insulating layer deposition rate, and the insulating layer deposition correspondence is used to characterize the correspondence between the insulating layer deposition time, the insulating layer deposition rate and the insulating layer deposition thickness; the insulating layer deposition thickness is determined according to the insulating layer deposition time and the insulating layer deposition rate.

[0006] According to one embodiment of the present application, the insulating layer chemical mechanical polishing correspondence is determined according to the operating parameters of the insulating layer chemical mechanical polishing components and a preset virtual measurement AI model, and the insulating layer chemical mechanical polishing parameters are determined according to the target insulating layer chemical mechanical polishing thickness and the insulating layer chemical mechanical polishing correspondence, wherein the insulating layer chemical mechanical polishing parameters include the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate, and the insulating layer chemical mechanical polishing correspondence is used to characterize the correspondence between the insulating layer chemical mechanical polishing time, the insulating layer chemical mechanical polishing rate and the insulating layer chemical mechanical polishing thickness; the insulating layer deposition thickness after polishing is determined according to the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate.

[0007] According to one embodiment of the present application, a coating correspondence is determined based on the operating parameters of the anti-reflective coating and photoresist coating components and a preset virtual measurement AI model, and the anti-reflective coating and photoresist coating parameters are determined based on the target coating thickness and the coating correspondence, wherein the anti-reflective coating and photoresist coating parameters include coating time and coating rate, and the coating correspondence is used to characterize the correspondence between coating time, coating rate and coating thickness; the coating thickness is determined based on the coating time and coating rate.

[0008] According to one embodiment of the present application, the etching correspondence is determined according to the operating parameters of the etching component and a preset virtual measurement AI model, and the etching parameters are determined according to the target etching critical dimension and the etching correspondence, wherein the etching parameters include etching time and etching rate, and the etching correspondence is used to characterize the correspondence between the etching time, etching rate and the critical dimension after etching; the critical dimension after etching is determined according to the etching time and etching rate.

[0009] According to one embodiment of the present application, a barrier layer deposition correspondence is determined according to operating parameters of a barrier layer deposition component and a preset virtual measurement AI model, and barrier layer deposition parameters are determined according to a target barrier layer deposition thickness and the barrier layer deposition correspondence, wherein the barrier layer deposition parameters include a barrier layer deposition time and a barrier layer deposition rate, and the barrier layer deposition correspondence is used to characterize the correspondence between the barrier layer deposition time, the barrier layer deposition rate and the barrier layer deposition thickness; the barrier layer deposition thickness is determined according to the barrier layer deposition time and the barrier layer deposition rate.

[0010] According to one embodiment of the present application, the electroplating correspondence is determined according to the operating parameters of the electroplating component and a preset virtual measurement AI model, and the electroplating parameters are determined according to the target electroplating layer thickness and the electroplating correspondence, wherein the electroplating parameters include the electroplating time and the electroplating rate, and the electroplating correspondence is used to characterize the correspondence between the electroplating time, the electroplating rate and the electroplating layer thickness; the electroplating layer thickness is determined according to the electroplating time and the electroplating rate.

[0011] According to one embodiment of the present application, the chemical mechanical polishing correspondence of the electroplating layer is determined according to the operating parameters of the chemical mechanical polishing components of the electroplating layer and the preset virtual measurement AI model, and the chemical mechanical polishing parameters of the electroplating layer are determined according to the target chemical mechanical polishing thickness of the electroplating layer and the chemical mechanical polishing correspondence of the electroplating layer, wherein the chemical mechanical polishing parameters of the electroplating layer include the chemical mechanical polishing time of the electroplating layer and the chemical mechanical polishing rate of the electroplating layer, and the chemical mechanical polishing correspondence of the electroplating layer is used to characterize the correspondence between the chemical mechanical polishing time of the electroplating layer, the chemical mechanical polishing rate of the electroplating layer and the chemical mechanical polishing thickness of the electroplating layer; the chemical mechanical polishing thickness of the electroplating layer is determined according to the chemical mechanical polishing time and the chemical mechanical polishing rate of the electroplating layer.

[0012] According to an embodiment of the present application, integrated layout and / or mask design is performed according to the critical dimension after etching.

[0013] According to an embodiment of the present application, the insulating layer deposition parameters of the insulating layer deposition component are adjusted according to the insulating layer deposition thickness after grinding determined by virtual measurement and the insulating layer grinding thickness determined by virtual measurement.

[0014] According to the advanced back-end wire automatic process control system of the intelligent chip factory of the embodiment of the present application, the system includes: an insulating layer deposition component, which is used to perform insulating layer deposition on the wafer according to the insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing component, which is used to perform insulating layer chemical mechanical polishing on the wafer after deposition according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating component, which is used to perform anti-reflective coating and photoresist coating on the wafer after the insulating layer chemical mechanical polishing according to the insulating layer deposition thickness after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography component, which is used to perform photolithography on the wafer after the anti-reflective coating and photoresist coating; an etching component, which is used to perform etching on the wafer after the anti-reflective coating and photoresist coating; According to the thickness of the anti-reflective coating and photoresist after coating determined by virtual measurement, the thickness of the insulating layer deposited after grinding determined by virtual measurement, and the etching parameters determined by virtual measurement, the wafer after photolithography is etched; a barrier layer deposition component is used to deposit a barrier layer on the etched wafer according to the deposition parameters of the barrier layer determined by virtual measurement; an electroplating component is used to electroplate the wafer after the barrier layer is deposited according to the electroplating parameters determined by virtual measurement; an electroplating layer chemical mechanical polishing component is used to perform electroplating layer chemical mechanical polishing on the electroplated wafer according to the thickness of the electroplating layer determined by virtual measurement, the grinding thickness of the electroplating layer determined by virtual measurement, and the key dimensions after etching determined by virtual measurement; a cobalt cap layer atomic layer deposition component is used to perform cobalt cap layer atomic layer deposition on the wafer after chemical mechanical grinding of the electroplating layer, so as to obtain the chip corresponding to the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the structure of an advanced back-end wire automatic process control system of a smart chip factory according to some embodiments of the present application. DETAILED DESCRIPTION

[0016] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0017] The following describes in detail the advanced back-end wire automatic process control system for a smart chip factory according to an embodiment of the present application with reference to the accompanying drawings.

[0018] In some embodiments, monitoring data and online monitoring data are acquired and stored in an SPC database according to a preset corresponding position, and the offline monitoring data and online monitoring data in the SPC database are offset and calibrated according to the performance change trend of the measurement tool to obtain first calibration data, and then the first calibration data is filtered to obtain SPC data. Process tool sensor data and measurement tool sensor data are acquired and stored in an FDC database according to a preset corresponding position, and the process tool sensor data and the measurement tool sensor data are offset and calibrated according to the performance change trend of the process tool sensor and the performance change trend of the measurement tool sensor to obtain second calibration data, and then the second calibration data is filtered to obtain FDC data. Use SPC data and FDC data to train the preset virtual measurement AI (Artificial Intelligence) model. During use, the process tool operating parameters can be input into the preset virtual measurement AI model to predict the virtual measurement auxiliary data, and the offline monitoring data and online monitoring data that have not been corrected and filtered can be used as non-virtual measurement auxiliary data. Both the virtual measurement auxiliary data and the non-virtual measurement auxiliary data are stored in the SPC database. APC (AutoProcess Control) and RMS (Recipe Management System) will control the process tools according to the virtual measurement auxiliary data and non-virtual measurement auxiliary data in the SPC database, and then control the smart chip factory.

[0019] In the chip production process, such as insulating layer deposition, insulating layer chemical mechanical polishing, anti-reflective coating and photoresist coating, photolithography, etching, barrier layer deposition, electroplating, electroplating layer chemical mechanical polishing and cobalt cap layer atomic layer deposition, the present application uses the above-mentioned preset virtual measurement AI model to predict various process parameters, that is, uses an advanced virtual measurement system to assist process control, thereby improving the accuracy of automatic process control.

[0020] Reference Figure 1 The advanced back-end wire automatic process control system 1 of the intelligent chip factory includes: an insulating layer deposition component 11, which is used to perform insulating layer deposition on the wafer according to the insulating layer deposition parameters determined by virtual measurement; an insulating layer chemical mechanical polishing component 12, which is used to perform insulating layer chemical mechanical polishing on the wafer after deposition according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; an anti-reflective coating and photoresist coating component 13, which is used to perform anti-reflective coating and photoresist coating on the wafer after the insulating layer chemical mechanical polishing according to the insulating layer deposition thickness after polishing determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; a photolithography component 14, which is used to perform photolithography on the wafer after the anti-reflective coating and photoresist coating; an etching component 15, which is used to perform etching on the wafer after the anti-reflective coating and photoresist coating according to the virtual measurement. The wafer after photolithography is etched according to the thickness of the anti-reflective coating and photoresist after coating determined by virtual measurement, the thickness of the insulating layer deposited after grinding determined by virtual measurement, and the etching parameters determined by virtual measurement; the barrier layer deposition component 16 is used to deposit the barrier layer on the etched wafer according to the deposition parameters of the barrier layer determined by virtual measurement; the electroplating component 17 is used to electroplate the wafer after the barrier layer deposition according to the electroplating parameters determined by virtual measurement; the electroplating layer chemical mechanical grinding component 18 is used to perform electroplating layer chemical mechanical grinding on the electroplated wafer according to the thickness of the electroplating layer determined by virtual measurement, the grinding thickness of the electroplating layer determined by virtual measurement, and the key size after etching determined by virtual measurement; the cobalt cap layer atomic layer deposition component 19 is used to perform cobalt cap layer atomic layer deposition on the wafer after the electroplating layer chemical mechanical grinding, so as to obtain the chip corresponding to the wafer.

[0021] Specifically, before the insulating layer deposition part 11 performs the insulating layer deposition operation on each product wafer, it is necessary to use virtual measurement to predict the insulating layer deposition parameters, that is, to predict the insulating layer deposition time and the insulating layer deposition rate when the insulating layer deposition part 11 is to deposit the target insulating layer deposition thickness, and then the insulating layer deposition part 11 performs insulating layer deposition according to the insulating layer deposition time and the insulating layer deposition rate, wherein the insulating layer can be a silicon dioxide layer.

[0022] Before the insulating layer chemical mechanical polishing component 12 performs chemical mechanical polishing of the insulating layer on the deposited wafer, it is necessary to use virtual measurement to predict the insulating layer chemical mechanical polishing parameters, that is, to predict the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate when the insulating layer chemical mechanical polishing component 12 is to polish the target insulating layer chemical mechanical polishing thickness, wherein the target insulating layer chemical mechanical polishing thickness needs to be determined based on the insulating layer deposition thickness determined by the virtual measurement and the insulating layer deposition thickness before grinding, which can to a certain extent prevent the insulating layer chemical mechanical polishing component 12 from grinding the insulating layer too much and damaging the wafer, and the insulating layer deposition thickness before grinding can be obtained based on the sensor detection set on the insulating layer chemical mechanical polishing component 12, and then the insulating layer chemical mechanical polishing component 12 performs the insulating layer chemical mechanical polishing according to the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate.

[0023] Before the anti-reflective coating and photoresist coating part 13 performs anti-reflective coating and photoresist coating on the wafer after chemical mechanical grinding of the insulating layer, it is necessary to use virtual measurement to predict the anti-reflective coating and photoresist coating parameters, that is, to predict the coating time and coating rate when the anti-reflective coating and photoresist coating part 13 is to coat the target coating thickness, wherein the deposition thickness of the insulating layer after grinding will affect the optical coefficient, and then affect the thickness of the anti-reflective coating and photoresist, so it is necessary to determine the target coating thickness according to the deposition thickness of the insulating layer after grinding, and then the anti-reflective coating and photoresist coating part 13 performs coating according to the coating time and coating rate.

[0024] The photolithography component 14 is used to perform photolithography on the wafer coated with the anti-reflective coating and the photoresist, for example, to perform deep multiple exposure.

[0025] Before the etching component 15 etches the wafer after photolithography, it is necessary to use virtual measurement to predict the etching parameters, that is, to predict the etching time and etching rate when the etching component 15 etches the target etching critical dimension, wherein the target etching critical dimension includes the etching depth, and the etching depth needs to be determined based on the thickness of the anti-reflective coating and photoresist after coating and the thickness of the insulating layer deposition after grinding. To a certain extent, it can avoid the etching depth being too deep and damaging the wafer. Then the etching component 15 etches according to the etching time and etching rate.

[0026] Before the barrier layer deposition component 16 deposits a barrier layer on the etched wafer, it is necessary to use virtual measurement to predict the barrier layer deposition parameters, that is, to predict the barrier layer deposition time and barrier layer deposition rate when the barrier layer deposition component 16 is to deposit the target barrier layer deposition thickness. Then the barrier layer deposition component 16 performs barrier layer deposition according to the barrier layer deposition time and barrier layer deposition rate, for example, cobalt atomic layer deposition.

[0027] Before the electroplating component 17 electroplates the wafer after the barrier layer is deposited, it is necessary to use virtual measurement to predict the electroplating parameters, that is, to predict the plating time and plating rate when the electroplating component 17 is to plate the target plating layer thickness, and then the electroplating component 17 performs electroplating according to the plating time and plating rate, such as electroplating copper.

[0028] Before the electroplated wafer is subjected to electroplating chemical mechanical polishing by the electroplating layer chemical mechanical polishing component 18, it is necessary to use virtual measurement to predict the electroplating layer chemical mechanical polishing parameters, that is, to predict the electroplating layer chemical mechanical polishing time and the electroplating layer chemical mechanical polishing rate when the electroplating layer chemical mechanical polishing component 18 is required to polish the target electroplating layer chemical mechanical polishing thickness. The target electroplating layer chemical mechanical polishing thickness needs to be determined according to the electroplating layer thickness, which can avoid the electroplating layer chemical mechanical polishing component 18 from grinding the electroplating layer too much and damaging the wafer to a certain extent. The target electroplating layer chemical mechanical polishing thickness also needs to be determined according to the key dimensions after etching. The key dimensions after etching include the line density. The higher the line density, the thicker the electroplating layer will be. Therefore, the target electroplating layer chemical mechanical polishing thickness should be increased at locations with high line density, which can avoid uneven electroplating layer after chemical mechanical polishing to a certain extent. Then the electroplating layer chemical mechanical polishing component 18 performs grinding according to the electroplating layer chemical mechanical polishing time and the electroplating layer chemical mechanical polishing rate.

[0029] Before the cobalt cap layer atomic layer deposition component 19 performs cobalt cap layer atomic layer deposition on the wafer after chemical mechanical grinding of the electroplating layer, it is necessary to use virtual measurement to predict the cobalt cap layer atomic layer deposition parameters, that is, to predict the cobalt cap layer atomic layer deposition time and deposition rate when the cobalt cap layer atomic layer deposition component 19 is going to deposit the target cobalt cap layer atomic layer thickness. The cobalt cap layer atomic layer deposition component 19 performs deposition according to the cobalt cap layer atomic layer deposition time and deposition rate to obtain the chip corresponding to the wafer.

[0030] In this way, the accuracy of automatic process control is improved.

[0031] In some embodiments, the deposition correspondence is determined according to the operating parameters of the insulating layer deposition component 11 and a preset virtual measurement AI model, and the insulating layer deposition parameters are determined according to the target insulating layer deposition thickness and the insulating layer deposition correspondence, wherein the insulating layer deposition parameters include the insulating layer deposition time and the insulating layer deposition rate, and the insulating layer deposition correspondence is used to characterize the correspondence between the insulating layer deposition time, the insulating layer deposition rate and the insulating layer deposition thickness; the insulating layer deposition thickness is determined according to the insulating layer deposition time and the insulating layer deposition rate.

[0032] Specifically, the operating parameters of the insulating layer deposition component 11 (which can be obtained according to the built-in sensor detection of the insulating layer deposition component 11) are input into the preset virtual measurement AI model to predict the correspondence between the insulating layer deposition time, the insulating layer deposition rate and the insulating layer deposition thickness, and then the insulating layer deposition time and the insulating layer deposition rate of the insulating layer deposition component 11 are determined according to the target insulating layer deposition thickness and the above correspondence, and the insulating layer deposition time and the insulating layer deposition rate are stored in the SPC database. APC and RMS control the insulating layer deposition component 11 to perform insulating layer deposition according to the insulating layer deposition time and the insulating layer deposition rate in the SPC database.

[0033] In some embodiments, the insulating layer chemical mechanical polishing correspondence is determined according to the operating parameters of the insulating layer chemical mechanical polishing component 12 and a preset virtual measurement AI model, and the insulating layer chemical mechanical polishing parameters are determined according to the target insulating layer chemical mechanical polishing thickness and the insulating layer chemical mechanical polishing correspondence, wherein the insulating layer chemical mechanical polishing parameters include the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate, and the insulating layer chemical mechanical polishing correspondence is used to characterize the correspondence between the insulating layer chemical mechanical polishing time, the insulating layer chemical mechanical polishing rate and the insulating layer chemical mechanical polishing thickness; the insulating layer deposition thickness after polishing is determined according to the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate.

[0034] Specifically, the operating parameters of the insulating layer chemical mechanical polishing component 12 (which can be obtained based on the built-in sensor detection of the insulating layer chemical mechanical polishing component 12) are input into the preset virtual measurement AI model to predict the corresponding relationship between the insulating layer chemical mechanical polishing time, the insulating layer chemical mechanical polishing rate and the insulating layer chemical mechanical polishing thickness, and then the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate are determined based on the above-mentioned target insulating layer chemical mechanical polishing thickness and the above-mentioned corresponding relationship, and the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate are stored in the SPC database, and APC and RMS control the insulating layer chemical mechanical polishing component 12 for polishing based on the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate in the SPC database.

[0035] In some embodiments, a coating correspondence is determined based on the operating parameters of the anti-reflective coating and photoresist coating component 13 and a preset virtual measurement AI model, and the anti-reflective coating and photoresist coating parameters are determined based on the target coating thickness and the coating correspondence, wherein the anti-reflective coating and photoresist coating parameters include coating time and coating rate, and the coating correspondence is used to characterize the correspondence between coating time, coating rate and coating thickness; the coating thickness is determined based on the coating time and coating rate.

[0036] Specifically, the operating parameters of the anti-reflective coating and photoresist coating component 13 (which can be obtained based on the built-in sensor detection of the anti-reflective coating and photoresist coating component 13) are input into the preset virtual measurement AI model to predict the correspondence between the coating time, coating rate and coating thickness, and then the coating time and coating rate are determined based on the target coating thickness and the above correspondence, and the coating time and coating rate are stored in the SPC database. APC and RMS control the coating of the anti-reflective coating and photoresist coating component 13 based on the coating time and coating rate in the SPC database.

[0037] In some embodiments, the etching correspondence is determined according to the operating parameters of the etching component 15 and a preset virtual measurement AI model, and the etching parameters are determined according to the target etching critical dimension and the etching correspondence, wherein the etching parameters include etching time and etching rate, and the etching correspondence is used to characterize the correspondence between the etching time, etching rate and the critical dimension after etching; the critical dimension after etching is determined according to the etching time and etching rate.

[0038] Specifically, the operating parameters of the etching component 15 (which can be obtained through detection by sensors built into the etching component 15) are input into a preset virtual measurement AI model to predict the correspondence between the etching time, etching rate and the key dimension after etching (such as etching depth). Then, the etching time and etching rate are determined based on the target etching key dimension and the above correspondence, and the etching time and etching rate are stored in the SPC database. APC and RMS control the etching component 15 to etch according to the etching time and etching rate in the SPC database.

[0039] In some embodiments, the barrier layer deposition correspondence is determined according to the operating parameters of the barrier layer deposition component 16 and a preset virtual measurement AI model, and the barrier layer deposition parameters are determined according to the target barrier layer deposition thickness and the barrier layer deposition correspondence, wherein the barrier layer deposition parameters include the barrier layer deposition time and the barrier layer deposition rate, and the barrier layer deposition correspondence is used to characterize the correspondence between the barrier layer deposition time, the barrier layer deposition rate and the barrier layer deposition thickness; the barrier layer deposition thickness is determined according to the barrier layer deposition time and the barrier layer deposition rate.

[0040] Specifically, the operating parameters of the barrier layer deposition component 16 (which can be obtained based on the built-in sensor detection of the barrier layer deposition component 16) are input into the preset virtual measurement AI model to predict the corresponding relationship among the barrier layer deposition time, the barrier layer deposition rate and the barrier layer deposition thickness, and then the barrier layer deposition time and the barrier layer deposition rate are determined based on the target barrier layer deposition thickness and the above corresponding relationship, and the barrier layer deposition time and the barrier layer deposition rate are stored in the SPC database. APC and RMS control the barrier layer deposition component 16 for deposition based on the barrier layer deposition time and the barrier layer deposition rate in the SPC database.

[0041] In some embodiments, the electroplating correspondence is determined according to the operating parameters of the electroplating component 17 and a preset virtual measurement AI model, and the electroplating parameters are determined according to the target electroplating layer thickness and the electroplating correspondence, wherein the electroplating parameters include the electroplating time and the electroplating rate, and the electroplating correspondence is used to characterize the correspondence between the electroplating time, the electroplating rate and the electroplating layer thickness; the electroplating layer thickness is determined according to the electroplating time and the electroplating rate.

[0042] Specifically, the operating parameters of the electroplating component 17 (which can be obtained through detection by sensors built into the electroplating component 17) are input into a preset virtual measurement AI model to predict the correspondence between the electroplating time, electroplating rate and electroplating layer thickness, and then the electroplating time and electroplating rate are determined based on the target electroplating layer thickness and the above correspondence, and the electroplating time and electroplating rate are stored in the SPC database. APC and RMS control the electroplating component 17 for electroplating based on the electroplating time and electroplating rate in the SPC database.

[0043] In some embodiments, the chemical mechanical polishing correspondence of the electroplating layer is determined according to the operating parameters of the electroplating layer chemical mechanical polishing component 18 and the preset virtual measurement AI model, and the chemical mechanical polishing parameters of the electroplating layer are determined according to the target chemical mechanical polishing thickness of the electroplating layer and the chemical mechanical polishing correspondence of the electroplating layer, wherein the chemical mechanical polishing parameters of the electroplating layer include the chemical mechanical polishing time of the electroplating layer and the chemical mechanical polishing rate of the electroplating layer, and the chemical mechanical polishing correspondence of the electroplating layer is used to characterize the correspondence between the chemical mechanical polishing time of the electroplating layer, the chemical mechanical polishing rate of the electroplating layer and the chemical mechanical polishing thickness of the electroplating layer; the chemical mechanical polishing thickness of the electroplating layer is determined according to the chemical mechanical polishing time and the chemical mechanical polishing rate of the electroplating layer.

[0044] Specifically, the operating parameters of the electroplating layer chemical mechanical polishing component 18 (which can be obtained based on the built-in sensor detection of the electroplating layer chemical mechanical polishing component 18) are input into the preset virtual measurement AI model to predict the correspondence between the electroplating layer chemical mechanical polishing time, the electroplating layer chemical mechanical polishing rate and the electroplating layer chemical mechanical polishing thickness, and then the electroplating layer chemical mechanical polishing time and the electroplating layer chemical mechanical polishing rate are determined according to the target electroplating layer chemical mechanical polishing thickness and the above correspondence, and the electroplating layer chemical mechanical polishing time and the electroplating layer chemical mechanical polishing rate are stored in the SPC database, and APC and RMS control the electroplating layer chemical mechanical polishing component 18 for polishing according to the electroplating layer chemical mechanical polishing time and the electroplating layer chemical mechanical polishing rate in the SPC database.

[0045] In some embodiments, integrated layout and / or mask design is performed according to the critical dimensions after etching.

[0046] Specifically, the critical dimensions after etching include line density. The higher the line density, the lower the etching rate. In order to maintain the same etching rate, it is necessary to re-perform integrated layout, mask design, or integrated layout and mask design based on the critical dimensions after etching.

[0047] In some embodiments, the insulating layer deposition parameters of the insulating layer deposition component 11 are adjusted according to the insulating layer deposition thickness after grinding determined by virtual measurement and the insulating layer grinding thickness determined by virtual measurement.

[0048] Specifically, due to the aging of the grinding sheet during the grinding process, the grinding thickness of the insulating layer will become thinner and thinner, and the target grinding thickness cannot be achieved after adjusting the grinding time and the grinding rate. Therefore, it is also necessary to feed back the insulation layer deposition thickness after grinding determined by the virtual measurement and the insulation layer grinding thickness determined by the virtual measurement to the insulation layer deposition component 11 to adjust the insulation layer deposition parameters, such as reducing the insulation layer deposition time or the insulation layer deposition rate, so as to reduce the thickness of the insulation layer deposition.

[0049] In summary, the virtual measurement system is used to predict the parameters of each component in real time and provide them to the automatic process control system for precise regulation. According to the process integration requirements, fast and effective data is provided to relevant upstream and downstream process sites so that the automatic process control system can make precise adjustments and promptly correct the process parameters for the next chip. The process can also be shut down in time to reduce the impact of the incident.

[0050] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0051] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0052] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0054] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0055] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An advanced back-end wire automatic process control system for a smart chip factory, characterized in that: The system comprises: An insulating layer deposition component, used for performing insulating layer deposition on the wafer according to the insulating layer deposition parameters determined by virtual measurement; An insulating layer chemical mechanical polishing component, used to perform chemical mechanical polishing of the insulating layer on the wafer after deposition according to the insulating layer deposition thickness determined by virtual measurement, the insulating layer deposition thickness before polishing, and the insulating layer chemical mechanical polishing parameters determined by virtual measurement; An anti-reflective coating and photoresist coating component, used for coating the wafer after chemical mechanical grinding of the insulating layer with an anti-reflective coating and a photoresist according to the insulating layer deposition thickness after grinding determined by virtual measurement and the anti-reflective coating and photoresist coating parameters determined by virtual measurement; A photolithography component, used for performing photolithography on the wafer coated with an anti-reflective coating and a photoresist; An etching component, used for etching the wafer after photolithography according to the thickness of the anti-reflective coating and the photoresist after coating determined by virtual measurement, the thickness of the insulating layer deposited after grinding determined by the virtual measurement, and the etching parameters determined by the virtual measurement; A barrier layer deposition component, used for depositing a barrier layer on the etched wafer according to the deposition parameters of the barrier layer determined by virtual measurement; An electroplating component, used for electroplating the wafer after the barrier layer is deposited according to the electroplating parameters determined by virtual measurement; The electroplating layer chemical mechanical polishing component is used to perform chemical mechanical polishing of the electroplating layer on the wafer after electroplating according to the electroplating layer thickness determined by virtual measurement, the electroplating layer polishing thickness determined by virtual measurement, and the key size after etching determined by virtual measurement; The cobalt cap layer atomic layer deposition component is used to perform cobalt cap layer atomic layer deposition on the wafer after chemical mechanical grinding of the electroplating layer to obtain the chip corresponding to the wafer.

2. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1 is characterized in that: Determine a deposition correspondence according to operating parameters of an insulating layer deposition component and a preset virtual measurement AI model, and determine the insulating layer deposition parameters according to a target insulating layer deposition thickness and the insulating layer deposition correspondence, wherein the insulating layer deposition parameters include an insulating layer deposition time and an insulating layer deposition rate, and the insulating layer deposition correspondence is used to characterize a correspondence between the insulating layer deposition time, the insulating layer deposition rate, and the insulating layer deposition thickness; The insulating layer deposition thickness is determined according to the insulating layer deposition time and the insulating layer deposition rate.

3. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1 is characterized in that: Determine the insulating layer chemical mechanical polishing correspondence relationship according to the operating parameters of the insulating layer chemical mechanical polishing component and the preset virtual measurement AI model, and determine the insulating layer chemical mechanical polishing parameters according to the target insulating layer chemical mechanical polishing thickness and the insulating layer chemical mechanical polishing correspondence relationship, wherein the insulating layer chemical mechanical polishing parameters include the insulating layer chemical mechanical polishing time and the insulating layer chemical mechanical polishing rate, and the insulating layer chemical mechanical polishing correspondence relationship is used to characterize the correspondence between the insulating layer chemical mechanical polishing time, the insulating layer chemical mechanical polishing rate and the insulating layer chemical mechanical polishing thickness; The deposition thickness of the insulating layer after grinding is determined according to the chemical mechanical grinding time of the insulating layer and the chemical mechanical grinding rate of the insulating layer.

4. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1 is characterized in that: Determine a coating correspondence relationship according to operating parameters of an anti-reflective coating and a photoresist coating component and a preset virtual measurement AI model, and determine the anti-reflective coating and photoresist coating parameters according to a target coating thickness and the coating correspondence relationship, wherein the anti-reflective coating and photoresist coating parameters include a coating time and a coating rate, and the coating correspondence relationship is used to characterize the correspondence between the coating time, the coating rate, and the coating thickness; The coating thickness is determined according to the coating time and the coating rate.

5. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1 is characterized in that: Determine an etching correspondence according to the operating parameters of the etching component and a preset virtual measurement AI model, and determine the etching parameters according to the target etching critical dimension and the etching correspondence, wherein the etching parameters include etching time and etching rate, and the etching correspondence is used to characterize the correspondence between etching time, etching rate and critical dimension after etching; The critical dimension after etching is determined according to the etching time and the etching rate.

6. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1, characterized in that: Determine the barrier layer deposition correspondence relationship according to the operating parameters of the barrier layer deposition component and the preset virtual measurement AI model, and determine the barrier layer deposition parameters according to the target barrier layer deposition thickness and the barrier layer deposition correspondence relationship, wherein the barrier layer deposition parameters include barrier layer deposition time and barrier layer deposition rate, and the barrier layer deposition correspondence relationship is used to characterize the correspondence between the barrier layer deposition time, the barrier layer deposition rate and the barrier layer deposition thickness; The barrier layer deposition thickness is determined according to the barrier layer deposition time and the barrier layer deposition rate.

7. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1, characterized in that: Determine the electroplating correspondence according to the operating parameters of the electroplating component and the preset virtual measurement AI model, and determine the electroplating parameters according to the target electroplating layer thickness and the electroplating correspondence, wherein the electroplating parameters include the electroplating time and the electroplating rate, and the electroplating correspondence is used to characterize the correspondence between the electroplating time, the electroplating rate and the electroplating layer thickness; The thickness of the electroplating layer is determined according to the electroplating time and the electroplating rate.

8. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1 is characterized in that: Determine the chemical mechanical polishing correspondence of the electroplating layer according to the operating parameters of the electroplating layer chemical mechanical polishing component and the preset virtual measurement AI model, and determine the chemical mechanical polishing parameters of the electroplating layer according to the target chemical mechanical polishing thickness of the electroplating layer and the chemical mechanical polishing correspondence of the electroplating layer, wherein the chemical mechanical polishing parameters of the electroplating layer include the chemical mechanical polishing time of the electroplating layer and the chemical mechanical polishing rate of the electroplating layer, and the chemical mechanical polishing correspondence of the electroplating layer is used to characterize the correspondence between the chemical mechanical polishing time of the electroplating layer, the chemical mechanical polishing rate of the electroplating layer and the chemical mechanical polishing thickness of the electroplating layer; The chemical mechanical polishing thickness of the electroplating layer is determined according to the chemical mechanical polishing time of the electroplating layer and the chemical mechanical polishing rate of the electroplating layer.

9. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1, characterized in that: Perform integrated layout and / or mask design based on the critical dimensions after etching.

10. The advanced back-end wire automatic process control system for a smart chip factory according to claim 1, characterized in that: The insulating layer deposition parameters of the insulating layer deposition component are adjusted according to the insulating layer deposition thickness after grinding determined by the virtual measurement and the insulating layer grinding thickness determined by the virtual measurement.

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