Broadband sampling circuit and method with staggered sampling frequencies, and communication equipment
Through a wide-band sampling circuit with interlaced sampling frequencies, multiple analog-to-digital converters are used to sample in parallel and integrate data, the problems of high sampling costs, high power consumption and high design difficulty in the prior art are solved, and wider frequency band coverage and lower sampling costs are achieved.
Patent Information
- Application Number
- CN202411602684.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-03-11
AI Technical Summary
The existing wide-band sampling methods have problems such as high sampling cost and power consumption, high design difficulty and low sampling capability.
A wide-band sampling circuit with interleaved sampling frequencies is proposed. Multiple analog-to-digital converters are driven to sample in parallel at different sampling frequencies through a clock driving circuit, and the sampling data is integrated through a dual multiplexer and a multiplexed logic circuit to output a digital analog signal covering the complete frequency band of the radio frequency signal.
It effectively reduces the equipment sampling cost, power consumption and design difficulty, improves sampling capabilities, expands the frequency band coverage of the sampler, and completes the coverage of the entire working frequency band.
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Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of communication equipment, and in particular to a wide-band sampling circuit and method with staggered sampling frequencies, and a communication equipment. Background Art
[0002] The operating frequency range is an important indicator of communication radio equipment. In the context of software radio, the communication system has higher and higher requirements for the coverage of the operating frequency band of communication radio equipment. To meet this requirement, the position of the sampler in the communication radio equipment is getting closer and closer to the antenna port. For example, in the communication radio equipment with direct RF sampling architecture and zero intermediate frequency architecture, the sampler is placed before the frequency converter, and only the RF amplification channel is retained between the sampler and the antenna port. The sampler is close to the antenna port, which greatly reduces the limitation of the RF analog channel on the coverage of the operating frequency band, but also greatly increases the frequency band coverage requirements of the front-end sampler. Therefore, the wide-band sampling method can cover a wider operating frequency band, which is very suitable for the use of wide-band communication radio equipment.
[0003] At present, a common method for wide-band sampling is to use a higher sampling frequency to cover a wider operating frequency band. According to the bandpass sampling law, the sampling frequency of the sampler should be no less than twice the bandwidth of the operating frequency band. The operating frequency band bandwidth of wide-band communication radio equipment under software radio requirements is often above GHz, which requires that the sampling frequency of the wide-band sampler of the traditional method should be above 2GHz. However, using a high-sampling-frequency ADC to achieve wide-band sampling will cost a lot, which will not only increase the cost and power consumption of communication radio equipment, but also greatly increase the design difficulty of data interface, clock design and digital signal processing. At the same time, since the carrier bandwidth of communication radio equipment is relatively small, the sampling frequency required in the end is not high, so the benefit of this cost is very low. Summary of the invention
[0004] In order to solve the problems of high equipment sampling cost and power consumption, high design difficulty and low sampling capability in the above-mentioned existing wide-band sampling methods, the present invention proposes a wide-band sampling circuit, method and communication device with staggered sampling frequency, which effectively reduce the equipment sampling cost, power consumption and design difficulty and improve the sampling capability.
[0005] In order to achieve the above technical effects, the technical solution of the present invention is as follows:
[0006] A wide-band sampling circuit with staggered sampling frequencies comprises a first analog-to-digital converter ADC0, a second analog-to-digital converter ADC1, a clock driving circuit clk_drv, a dual-channel multiplexer MUX and a multiplexing logic circuit MUX_Logic; the output end of the clock driving circuit clk_drv is respectively connected to the input ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 for sampling radio frequency signals, the output ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 are respectively connected to the first input end and the second input end of the dual-channel multiplexer MUX, the output end of the multiplexing logic circuit MUX_Logic is connected to the third input end of the dual-channel multiplexer MUX, and the output end of the dual-channel multiplexer MUX outputs a digitized analog signal covering the complete frequency band of the radio frequency signal.
[0007] Preferably, the input end of the clock driving circuit clk_drv receives the input reference clock signal refclk, and the output end of the clock driving circuit clk_drv outputs the first sampling clock signal clk0 to the input end of the first analog-to-digital converter ADC0, and outputs the second sampling clock signal clk1 to the input end of the second analog-to-digital converter ADC1.
[0008] Preferably, the first sampling frequency of the first sampling clock signal clk0 is Fs0, and the calculation expression of the first sampling frequency Fs0 is as follows:
[0009] Fs0=n0×Rs (1)
[0010] Wherein, n0 represents a positive integer, and Rs represents the baseband signal symbol rate.
[0011] Preferably, the second sampling frequency of the second sampling clock signal clk1 is Fs1, and the calculation expression of the second sampling frequency Fs1 is as follows:
[0012] Fs1=n1×Rs (2)
[0013] Wherein, n1 represents a positive integer, and Rs represents the baseband signal symbol rate.
[0014] Preferably, the input end of the first analog-to-digital converter ADC0 receives the input first sampling clock signal clk0, samples the radio frequency signal RF using the first sampling frequency Fs0, and outputs the first digitized analog sampling data data0; wherein the first frequency band of the sampled radio frequency signal is covered by Frq0(m), and the calculation expression of Frq0(m) is as follows:
[0015]
[0016] Where m represents a positive integer, BW represents the physical bandwidth of the modulation signal, and the calculation expression of BW is as follows:
[0017] BW=Rs×(1+α) (4)
[0018] Wherein, α represents the baseband signal modulation roll-off coefficient.
[0019] Preferably, the input end of the second analog-to-digital converter ADC1 receives the input second sampling clock signal clk1, samples the radio frequency signal RF using the second sampling frequency Fs1, and outputs the second digitized analog sampling data data1; wherein the second frequency band of the sampled radio frequency signal is covered by Frq1(m), and the calculation expression of Frq1(m) is as follows:
[0020]
[0021] Wherein, m represents a positive integer, and BW represents the physical bandwidth of the modulated signal.
[0022] Preferably, the first sampling frequency Fs0 of the first analog-to-digital converter ADC0 and the second sampling frequency Fs1 of the second analog-to-digital converter ADC1 satisfy the following relationship:
[0023]
[0024] Substituting formula (4) into formulas (6) and (7) and rearranging them, we obtain the following relationship:
[0025] (m+1)×n0-m×n1>2×(1+α) (8)
[0026] (m+1)×(n1-n0)>2×(1+α) (9).
[0027] Preferably, the multiplexing logic circuit MUX_Logic generates a selection signal sel according to the carrier frequency frq_carry and inputs it into the dual-channel multiplexer MUX, and uses the selection signal sel to control the dual-channel multiplexer MUX to combine the first digitized analog sampling data data0 output by the first analog-to-digital converter ADC0 and the second digitized analog sampling data data1 output by the second analog-to-digital converter ADC1, and outputs the digitized analog signal covering the complete frequency band of the radio frequency signal.
[0028] The present invention also proposes a wide-band sampling method with staggered sampling frequencies, comprising the following steps:
[0029] S1. Input the reference clock signal refclk to the clock driving circuit clk_drv, the clock driving circuit clk_drv converts the reference clock signal refclk into a first sampling clock signal clk0 and a second sampling clock signal clk1, the first sampling clock signal clk0 is input to the first analog-to-digital converter ADC0, and the second sampling clock signal clk1 is input to the second analog-to-digital converter ADC1;
[0030] S2. The first analog-to-digital converter ADC0 receives the first sampling clock signal clk0, samples the input RF signal using the first sampling frequency, and outputs the first digitized analog sampling data to the dual-channel multiplexer MUX;
[0031] S3. The second analog-to-digital converter ADC1 receives the second sampling clock signal clk1, samples the RF signal using a second sampling frequency, and outputs second digitized analog sampling data to the dual-channel multiplexer MUX;
[0032] S4. The dual-channel multiplexer MUX receives the first digitized analog sampling data and the second digitized analog sampling data, and under the drive of the multiplexing logic circuit MUX_Logic, selects to output a digitized analog signal covering the complete frequency band of the radio frequency signal.
[0033] The present invention also provides a communication device, comprising the wide-band sampling circuit with staggered sampling frequencies as described above.
[0034] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0035] The present invention proposes a wide-band sampling circuit, method and communication device with staggered sampling frequencies. First, a clock driving circuit clk_drv is used to drive a first analog-to-digital converter ADC0 and a second analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 perform parallel sampling on a radio frequency signal at different sampling frequencies. Then, the sampled data is passed through a dual-channel multiplexer MUX. Under the drive of a multiplexing logic circuit MUX_Logic, the sampled data is integrated, and a digital analog signal covering the complete frequency band of the radio frequency signal is selected for output, thereby expanding the frequency band coverage of the sampler and completing the coverage of the entire working frequency band. Further, wide-band sampling is achieved through the cooperation of the first analog-to-digital converter ADC0, the second analog-to-digital converter ADC1, the clock driving circuit clk_drv, the dual-channel multiplexer MUX and the multiplexing logic circuit MUX_Logic, thereby effectively reducing the sampling cost, power consumption and design difficulty of the equipment and improving the sampling capability. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 A structural diagram of a wide-band sampling circuit with staggered sampling frequencies proposed in an embodiment of the present invention;
[0037] Figure 2 A schematic diagram showing wide frequency band coverage proposed in an embodiment of the present invention;
[0038] Figure 3 A flowchart of a wide-band sampling method with staggered sampling frequencies proposed in an embodiment of the present invention is shown;
[0039] Figure 4 It is a block diagram showing the structure of the communication device proposed in the embodiment of the present invention. DETAILED DESCRIPTION
[0040] The drawings are for illustrative purposes only and should not be construed as limiting the present patent;
[0041] It is understandable to those skilled in the art that some well-known contents may be omitted in the drawings;
[0042] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.
[0043] Example 1
[0044] In order to illustrate the basic principle and process of this wide-band sampling, the following parameters are first defined: RF signal frequency range, start frequency is Fstart, end frequency is Fstop, baseband signal symbol rate is Rs, baseband signal modulation roll-off factor is α, and modulation signal physical bandwidth is BW;
[0045] like Figure 1 As shown, a wide-band sampling circuit with staggered sampling frequencies includes a first analog-to-digital converter ADC0, a second analog-to-digital converter ADC1, a clock driving circuit clk_drv, a dual-channel multiplexer MUX and a multiplexing logic circuit MUX_Logic; the output end of the clock driving circuit clk_drv is respectively connected to the input ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 for sampling radio frequency signals, the output ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 are respectively connected to the first input end and the second input end of the dual-channel multiplexer MUX, the output end of the multiplexing logic circuit MUX_Logic is connected to the third input end of the dual-channel multiplexer MUX, and the output end of the dual-channel multiplexer MUX outputs a digitized analog signal covering the complete frequency band of the radio frequency signal.
[0046] The circuit principle is as follows: the radio frequency signal RF enters two parallel ADC0 and ADC1 at the same time. The radio frequency signal RF entering ADC0 and ADC1 is sampled as the first digital analog sampling data data0 and the second digital analog sampling data data1 at sampling frequencies of Fs0 and Fs1 respectively. Then the two data0 and data1 are selected and output by the dual-channel multiplexer MUX to obtain the digital analog signal data_out. The radio frequency signal RF is a sampled wide-band radio frequency signal, data0 and data1 are digital analog signals with discontinuous frequency bands, and data_out is a digital analog signal covering the complete frequency band of the RF signal.
[0047] The input end of the clock driving circuit clk_drv receives the input reference clock signal refclk, and the output end of the clock driving circuit clk_drv outputs the first sampling clock signal clk0 to the input end of the first analog-to-digital converter ADC0, and outputs the second sampling clock signal clk1 to the input end of the second analog-to-digital converter ADC1; the first sampling clock signal clk0 and the second sampling clock signal clk1 are two homologous clock signals;
[0048] The first sampling frequency of the first sampling clock signal clk0 is Fs0. The calculation expression of the first sampling frequency Fs0 is as follows:
[0049] Fs0=n0×Rs (1)
[0050] Wherein, n0 represents a positive integer, and Rs represents the baseband signal symbol rate.
[0051] The second sampling frequency of the second sampling clock signal clk1 is Fs1, and the calculation expression of the second sampling frequency Fs1 is as follows:
[0052] Fs1=n1×Rs (2)
[0053] Wherein, n1 represents a positive integer; Fs0 is set to be less than Fs1;
[0054] The input end of the first analog-to-digital converter ADC0 receives the input first sampling clock signal clk0, samples the radio frequency signal RF using the first sampling frequency Fs0, and outputs the first digital analog sampling data data0; wherein the first frequency band of the sampled radio frequency signal is covered by Frq0(m), and the calculation expression of Frq0(m) is as follows:
[0055]
[0056] Where m represents a positive integer, BW represents the physical bandwidth of the modulation signal, and the calculation expression of BW is as follows:
[0057] BW=Rs×(1+α) (4)
[0058] Wherein, α represents the baseband signal modulation roll-off coefficient.
[0059] The input end of the second analog-to-digital converter ADC1 receives the input second sampling clock signal clk1, samples the radio frequency signal RF using the second sampling frequency Fs1, and outputs the second digital analog sampling data data1; wherein the second frequency band of the sampled radio frequency signal is covered by Frq1(m), and the calculation expression of Frq1(m) is as follows:
[0060]
[0061] The first sampling frequency Fs0 of the first analog-to-digital converter ADC0 and the second sampling frequency Fs1 of the second analog-to-digital converter ADC1 satisfy the following relationship:
[0062]
[0063] Substituting formula (4) into formulas (6) and (7) and rearranging them, we obtain the following relationship:
[0064] (m+1)×n0-m×n1>2×(1+α) (8)
[0065] (m+1)×(n1-n0)>2×(1+α) (9)
[0066] To achieve staggered frequency band coverage, the values of n1 and n0 are as follows:
[0067] (1) From formula (9), we can get that the minimum difference between n1 and n0 is 2.
[0068] (2) From the above calculation, it can be seen that the smaller the difference between n1 and n0 is, the more times the interleaving can be performed, and the wider the frequency band that can be covered after the interleaving. However, when the sampling frequency is very low, if the difference is too small, it is easy to cause frequency difference interference between the two clocks. Therefore, n1 and n0 should be determined in combination with the actual sampling frequency and formula (9).
[0069] (3) When formula (8) is satisfied, the values of n1 and n2 should be as small as possible, so that the sampling clock frequency can be reduced as much as possible;
[0070] When parameters such as n0, n1, and m satisfy formulas (8) to (9), the frequency band coverage Frq0(m) and Frq1(m) of ADC0 and ADC1 are cross-continuous.
[0071] The multiplexing logic circuit MUX_Logic generates a selection signal sel according to the carrier frequency frq_carry and inputs it into the dual-channel multiplexer MUX. The selection signal sel is used to control the dual-channel multiplexer MUX to combine the first digitized analog sampling data data0 output by the first analog-to-digital converter ADC0 and the second digitized analog sampling data data1 output by the second analog-to-digital converter ADC1, such as cutting and integrating data0 and data1; and outputs the digitized analog signal covering the complete frequency band of the radio frequency signal, so that the digitized analog signal meets the frequency band coverage requirements. Finally, according to the frequency band width to be covered, appropriate parameters are selected to complete the coverage of the wide frequency band.
[0072] The first digital analog sampling data data0 output by ADC0 and the second digital analog sampling data data1 output by ADC1 are combined to complete the coverage of the complete frequency band of the RF signal, see Figure 2 , including:
[0073] (1) When frq_carry satisfies the Frq0(m) condition in formula (3), sel controls MUX to make data_out = data0;
[0074] (2) When frq_carry does not satisfy the Frq0(m) condition in formula (3), but satisfies the Frq1(m) condition in formula (5), sel controls MUX to make data_out = data1;
[0075] (3) When frq_carry is less than Frq0(1), sel controls MUX to make data_out = data1.
[0076] In actual use, the combination method of the first digital analog sampling data data0 output by ADC0 and the second digital analog sampling data data1 output by ADC1 is not limited to the above method. Generally, there may be other methods. The essence is to cut and integrate the sampling data of ADC0 and ADC1.
[0077] In this embodiment, the clock driving circuit clk_drv is first used to drive the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 perform parallel sampling of the radio frequency signal at different sampling frequencies, and then the sampled data is integrated through the dual-channel multiplexer MUX, and the digital analog signal covering the complete frequency band of the radio frequency signal is selected and output, thereby expanding the frequency band coverage of the sampler and completing the coverage of the entire working frequency band; further, the first analog-to-digital converter ADC0, the second analog-to-digital converter ADC1, the clock driving circuit clk_drv, the dual-channel multiplexer MUX and the multiplexing logic circuit MUX_Logic are used to realize wide-band sampling, effectively reducing the sampling cost, power consumption and design difficulty of the equipment, and improving the sampling capability. In addition, a dual ADC with staggered sampling frequencies is used to oversample the signals below the Nyquist frequency in the working frequency band, and undersample the signals above the Nyquist frequency, and then the sampled data is integrated through the dual-channel multiplexer, thereby completing the coverage of the entire working frequency band.
[0078] Example 2
[0079] This embodiment is to further illustrate the sampling effect achieved by a wide-band sampling circuit with staggered sampling frequencies described in the above embodiment. The physical layer signal parameters are defined as follows:
[0080] The baseband signal symbol rate is Rs = 15MHz;
[0081] The baseband signal modulation roll-off factor is α = 0.3;
[0082] From formula (4), it can be concluded that the physical bandwidth of the modulated signal BW = BW × (1 + α) = 20 MHz;
[0083] According to the n1 and n0 value selection principles described in the above embodiment, it is calculated according to Table 1 below that when n1 is 28, n0 is 26, and m is 1 to 11, the frequency band coverage requirement can be met.
[0084] Table 1 Parameter calculation table
[0085]
[0086]
[0087] According to formula (1) and formula (2), Fs1 = 420Msps, Fs0 = 390Msps, and the frequency band coverage is shown in Table 2. In the table, when m = 0, it means that the part below the Nyquist frequency in the working frequency band is covered, and when m = 1 to 11, it means that the part above the Nyquist frequency is covered.
[0088] Table 1 Interleaved frequency band table
[0089]
[0090]
[0091] After integration by the dual-channel multiplexer MUX, the frequency band coverage of the output digitized analog signal is shown in the following table.
[0092] Table 3 Frequency band coverage
[0093] Band 1 ADC1 sampling frequency Band 2 ADC0 sampling frequency [30,205) 420 [205,380) 420 [380,400) 390 [400,575) 420 [575,595) 390 [595,770) 420 [770,790) 390 [790,965) 420 [965,985) 390 [985,1160) 420 [1160,1180) 390 [1180,1355) 420 [1355,1375) 390 [1375,1550) 420 [1550,1570) 390 [1570,1745) 420 [1745,1765) 390 [1765,1940) 420 [1940,1960) 390 [1960,2135) 420 [2135,2155) 390 [2155,2330) 420 [2330,2510) 390
[0094] It can be seen from the data in Table 3 that the wide-band sampling method with staggered sampling frequency uses a sampling frequency of no more than 420Msps to cover the operating frequency band of 30MHz to 2500MHz. However, using traditional single ADC sampling, the sampling frequency should be (2500-30)×2=4940Msps or more. This embodiment reduces the sampling frequency covering the operating frequency band of 30MHz to 2500MHz from 4940Msps to 420Msps, greatly reducing the requirements of the sampling frequency for the frequency band coverage, and also provides a parameterized design process, which can simply and quickly complete the parameter design through measurement.
[0095] Example 3
[0096] See also Figure 3 The present embodiment provides a wide-band sampling method with staggered sampling frequencies, comprising the following steps:
[0097] S1. Input the reference clock signal refclk to the clock driving circuit clk_drv, the clock driving circuit clk_drv converts the reference clock signal refclk into a first sampling clock signal clk0 and a second sampling clock signal clk1, the first sampling clock signal clk0 is input to the first analog-to-digital converter ADC0, and the second sampling clock signal clk1 is input to the second analog-to-digital converter ADC1;
[0098] S2. The first analog-to-digital converter ADC0 receives the first sampling clock signal clk0, samples the input RF signal using the first sampling frequency, and outputs the first digitized analog sampling data to the dual-channel multiplexer MUX;
[0099] S3. The second analog-to-digital converter ADC1 receives the second sampling clock signal clk1, samples the RF signal using a second sampling frequency, and outputs second digitized analog sampling data to the dual-channel multiplexer MUX;
[0100] S4. The dual-channel multiplexer MUX receives the first digitized analog sampling data and the second digitized analog sampling data, and under the drive of the multiplexing logic circuit MUX_Logic, selects to output a digitized analog signal covering the complete frequency band of the radio frequency signal.
[0101] In this embodiment, the clock driving circuit clk_drv is first used to drive the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 perform parallel sampling of the radio frequency signal at different sampling frequencies, and then the sampled data are integrated through the dual-channel multiplexer MUX and driven by the multiplexing logic circuit MUX_Logic, and the digital analog signal covering the complete frequency band of the radio frequency signal is selected for output, thereby expanding the frequency band coverage of the sampler and completing the coverage of the entire working frequency band; further, wide-band sampling is achieved through the cooperation of the first analog-to-digital converter ADC0, the second analog-to-digital converter ADC1, the clock driving circuit clk_drv, the dual-channel multiplexer MUX and the multiplexing logic circuit MUX_Logic, effectively reducing the sampling cost, power consumption and design difficulty of the equipment, and improving the sampling capability.
[0102] Example 4
[0103] See also Figure 4 A communication device is proposed, comprising a wide-band sampling circuit with staggered sampling frequencies as described in the above embodiment, the circuit comprising a first analog-to-digital converter ADC0, a second analog-to-digital converter ADC1, a clock driving circuit clk_drv, a dual-channel multiplexer MUX and a multiplexing logic circuit MUX_Logic; the output end of the clock driving circuit clk_drv is respectively connected to the input ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 for sampling radio frequency signals, the output ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 are respectively connected to the first input end and the second input end of the dual-channel multiplexer MUX, the output end of the multiplexing logic circuit MUX_Logic is connected to the third input end of the dual-channel multiplexer MUX, and the output end of the dual-channel multiplexer MUX outputs a digitized analog signal covering the complete frequency band of the radio frequency signal.
[0104] In this embodiment, the clock driving circuit clk_drv is first used to drive the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 perform parallel sampling of the radio frequency signal at different sampling frequencies, and then the sampled data are integrated through the dual-channel multiplexer MUX and driven by the multiplexing logic circuit MUX_Logic, and the digital analog signal covering the complete frequency band of the radio frequency signal is selected for output, thereby expanding the frequency band coverage of the sampler and completing the coverage of the entire working frequency band; further, wide-band sampling is achieved through the cooperation of the first analog-to-digital converter ADC0, the second analog-to-digital converter ADC1, the clock driving circuit clk_drv, the dual-channel multiplexer MUX and the multiplexing logic circuit MUX_Logic, effectively reducing the sampling cost, power consumption and design difficulty of the equipment, and improving the sampling capability.
[0105] Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.
Claims
1. A wide-band sampling circuit with staggered sampling frequencies, characterized in that: It includes a first analog-to-digital converter ADC0, a second analog-to-digital converter ADC1, a clock driving circuit clk_drv, a dual-channel multiplexer MUX and a multiplexing logic circuit MUX_Logic; the output end of the clock driving circuit clk_drv is respectively connected to the input ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 for sampling radio frequency signals, the output ends of the first analog-to-digital converter ADC0 and the second analog-to-digital converter ADC1 are respectively connected to the first input end and the second input end of the dual-channel multiplexer MUX, the output end of the multiplexing logic circuit MUX_Logic is connected to the third input end of the dual-channel multiplexer MUX, and the output end of the dual-channel multiplexer MUX outputs a digitized analog signal covering the complete frequency band of the radio frequency signal.
2. The wide-band sampling circuit with staggered sampling frequency according to claim 1, characterized in that: The input end of the clock driving circuit clk_drv receives the input reference clock signal refclk, and the output end of the clock driving circuit clk_drv outputs the first sampling clock signal clk0 to the input end of the first analog-to-digital converter ADC0, and outputs the second sampling clock signal clk1 to the input end of the second analog-to-digital converter ADC1.
3. The wide-band sampling circuit with staggered sampling frequency according to claim 2, characterized in that: The first sampling frequency of the first sampling clock signal clk0 is Fs0. The calculation expression of the first sampling frequency Fs0 is as follows: Fs0=n0×Rs (1) Wherein, n0 represents a positive integer, and Rs represents the baseband signal symbol rate.
4. The wide-band sampling circuit with staggered sampling frequency according to claim 2, characterized in that: The second sampling frequency of the second sampling clock signal clk1 is Fs1, and the calculation expression of the second sampling frequency Fs1 is as follows: Fs1=n1×Rs (2) Wherein, n1 represents a positive integer, and Rs represents the baseband signal symbol rate.
5. The wide-band sampling circuit with staggered sampling frequency according to claim 3 or 4, characterized in that: The input end of the first analog-to-digital converter ADC0 receives the input first sampling clock signal clk0, samples the radio frequency signal RF using the first sampling frequency Fs0, and outputs the first digital analog sampling data data0; The first frequency band of the sampled RF signal is covered as Frq0(m), and the calculation expression of Frq0(m) is as follows: Where m represents a positive integer, BW represents the physical bandwidth of the modulation signal, and the calculation expression of BW is as follows: BW=Rs×(1+α) (4) Wherein, α represents the baseband signal modulation roll-off coefficient.
6. The wide-band sampling circuit with staggered sampling frequency according to claim 3 or 4, characterized in that: The input end of the second analog-to-digital converter ADC1 receives the input second sampling clock signal clk1, samples the radio frequency signal RF using the second sampling frequency Fs1, and outputs the second digital analog sampling data data1; wherein the second frequency band of the sampled radio frequency signal is covered by Frq1(m), and the calculation expression of Frq1(m) is as follows: Wherein, m represents a positive integer, and BW represents the physical bandwidth of the modulated signal.
7. The wide-band sampling circuit with staggered sampling frequency according to claim 5, characterized in that: The first sampling frequency Fs0 of the first analog-to-digital converter ADC0 and the second sampling frequency Fs1 of the second analog-to-digital converter ADC1 satisfy the following relationship: Substituting formula (4) into formulas (6) and (7) and rearranging them, we obtain the following relationship: (m+1)×n0-m×n1>2×(1+α) (8) (m+1)×(n1-n0)>2×(1+α) (9).
8. The wide-band sampling circuit with staggered sampling frequencies according to claim 7, characterized in that: The multiplexing logic circuit MUX_Logic generates a selection signal sel according to the carrier frequency frq_carry and inputs it into the dual-channel multiplexer MUX. The selection signal sel is used to control the dual-channel multiplexer MUX to combine the first digitized analog sampling data data0 output by the first analog-to-digital converter ADC0 and the second digitized analog sampling data data1 output by the second analog-to-digital converter ADC1, and outputs the digitized analog signal covering the complete frequency band of the radio frequency signal.
9. A wide-band sampling method with staggered sampling frequencies, characterized in that: The following steps are involved: S1. Input the reference clock signal refclk to the clock driving circuit clk_drv, the clock driving circuit clk_drv converts the reference clock signal refclk into a first sampling clock signal clk0 and a second sampling clock signal clk1, the first sampling clock signal clk0 is input to the first analog-to-digital converter ADC0, and the second sampling clock signal clk1 is input to the second analog-to-digital converter ADC1; S2. The first analog-to-digital converter ADC0 receives the first sampling clock signal clk0, samples the input RF signal using the first sampling frequency, and outputs the first digitized analog sampling data to the dual-channel multiplexer MUX; S3. The second analog-to-digital converter ADC1 receives the second sampling clock signal clk1, samples the RF signal using a second sampling frequency, and outputs second digitized analog sampling data to the dual-channel multiplexer MUX; S4. The dual-channel multiplexer MUX receives the first digitized analog sampling data and the second digitized analog sampling data, and under the drive of the multiplexing logic circuit MUX_Logic, selects to output a digitized analog signal covering the complete frequency band of the radio frequency signal.
10. A communication device, characterized in that: It comprises a wide-band sampling circuit with staggered sampling frequencies as described in claims 1-8.