Back-end analysis method for chip failure
Through SPICE simulation and nanoprobe technology, the key devices that cause chip failure are accurately positioned and confirmed, solving the difficulty of determining device problems in the prior art, and improving production efficiency and success rate.
Patent Information
- Application Number
- CN202411705241.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-03-14
AI Technical Summary
In the prior art, when dealing with chip failure, it is difficult to accurately determine the critical devices that cause failure, resulting in increased production costs and time costs.
The problematic device is initially determined through SPICE simulation, and then the nanoprobes of the FIB or SEM device are isolated or added with new devices for subsequent analysis and testing to confirm the root cause of the problem.
Improve the accuracy and efficiency of determining the problematic devices, significantly increase the success rate of next chip production, and save time and cost.
Smart Images
Figure CN119623389A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of chip technology, and in particular relates to a back-end analysis method for chip failure. Background Art
[0002] The gap between the model and the manufactured silicon wafer will lead to a decrease in product yield or functional failure. The traditional method is to identify the problematic device by gradually adjusting the model parameters and design simulation, including: Identify the problem: locate the suspected device through model parameter adjustment and design simulation; Silicon wafer adjustment: adjust the silicon wafer for the identified problem. Analysis and inspection: use new silicon wafers to perform product yield analysis or silicon wafer function inspection.
[0003] Current circuit design, especially analog circuit design, is based on SPICE simulation, which verifies whether the chip to be produced meets various functional requirements through simulation results. Therefore, the accuracy of the SPICE model is closely related to whether the final chip can pass functional verification and the yield of the chip. However, the SPICE model often deviates from the actual device performance. Here is a practical example:
[0004] Figure 1 The threshold voltage simulation value (solid line) and test value (dotted line) of the pmos are shown in FIG. There is a large deviation between the test value and the simulation value when Vb=0. This error leads to Figure 2 of actual product failures. Figure 2 The horizontal axis in the middle represents the ambient temperature, and the vertical axis represents the temperature monitored and output by the chip minus the ambient temperature. That is, the error of the temperature monitor in monitoring the external ambient temperature. Because this is a temperature detector, the simulation value is expected, that is, the smaller the chip output changes with temperature, the better. The error given by the simulation value (maximum, minimum, typical value) is about 0.2 degrees. However, the maximum error of the actual chip test is 4 degrees, which cannot meet the use requirements. That is, after the chip is produced, because the actual chip data changes too much and does not meet the design requirements, the chip fails, and the key components need to be found and corrected.
[0005] based on Figure 3 The existing route shown (solid black line) finds that after the product fails, it is roughly estimated through SPICE simulation that it is caused by the pmos performance, but it cannot be completely confirmed. The only way is to modify the model, simulate again, and then tape out production again. If the estimation is wrong, it will increase the time cost and production cost. Therefore, this proposal wants to provide a method, that is, on the failed chip, after roughly estimating the root cause of the failure through SPICE simulation, some methods are used on the chip again to determine the root cause of the chip failure. In this way, based on SPICE simulation and test analysis of actual chips, it is possible to more confidently identify the problematic device and greatly increase the success rate of the next tape out.
[0006] Traditional methods mainly focus on how to use different methods for general verification. The core of the invention described in this question focuses on solving silicon device performance problems caused by SPICE model accuracy problems, and improving the actual performance of the device on the silicon wafer through tuning. Summary of the invention
[0007] The purpose of the present invention is to solve the deficiencies of the prior art and provide a back-end analysis method and system for chip failure.
[0008] A back-end analysis method for chip failure, the technical solution adopted to solve its technical problems is as follows:
[0009] Step 1: When a device on the failed chip has been identified as a key device for chip failure through SPICE simulation, use a nanoprobe of a FIB or SEM device to isolate the key device or add a new device at the endpoint of the key device for subsequent analysis.
[0010] Step 2: After adding the new device, if the corresponding threshold voltage or other performance is the same as expected, directly test the chip connected with the new device. If the chip works as expected, it means that the chip failure is caused by this device, and it can be corrected in the next version of production.
[0011] Furthermore, the confirmation of the key component causing chip failure in step 1 means that the probability of the key component causing chip failure is greater than a set threshold, and the general threshold value is 80%.
[0012] Furthermore, the method of adding a new device described in step 1 includes:
[0013] Method 1: When the key device provides insufficient voltage or current, causing the chip to fail, the new device added is a controllable voltage source / current source;
[0014] Method 2: When the current provided by the key device is too large and causes the chip to fail, a controlled resistor is added to the source and drain ends of the key device to reduce the excessive source and drain current in the failed circuit.
[0015] Method 3: Use the same key components to replace the original problematic components, including the same key components in independent packages;
[0016] Method 4: When the suspected key device is a MOSFET, the performance of the key device is changed by changing the substrate voltage of the MOSFET, thereby verifying that the chip failure is caused by the difference between the performance and the SPICE simulation result.
[0017] Furthermore, method 3 in step 1 specifically includes the following two situations:
[0018] 3-1. Directly replace the original problematic device that caused the chip failure with a spare identical key device;
[0019] 3-2. Isolate the key components on the original chip, and then reconnect a new identical key component through nanoprobes.
[0020] Furthermore, step 2 is specifically implemented as follows:
[0021] If method 3 in step 1 is inconvenient to implement, the key device can only be regulated by changing the substrate voltage through method 4, and the specific implementation is as follows:
[0022] ① Obtain the normal working chip status through SPICE simulation, and the corresponding relationship between the voltage of each terminal of the key device and time. The terminal voltage includes Vs, Vg and Vd; that is, at a certain moment, the values of Vd, Vs, Vg and Vb are stored in a PWL file A;
[0023] ② Through the test of a single key device or SPICE simulation, the relationship between the change of the threshold voltage Vth and the voltages Vb, Vs, Vd, and Vg can be obtained; based on the PWL file A, and through a code program or a calculation formula in Excel, the value of the threshold voltage Vth at each moment can be calculated through the content recorded in the file PWLA, and the difference in the threshold voltage that needs to be adjusted is known, so the value of Vb required at the current moment can be calculated, and finally the PWL file B is obtained;
[0024] ③ In the actual chip test, PWL file B is applied to the key device, and the threshold voltage or other performance of the key device will change with the chip test. Verify whether the chip works normally under the action of PWL file B. If normal, it means that the problem is with the key device.
[0025] Furthermore, the code program or the calculation formula in Excel is used to implement the process as follows:
[0026] (1) Define the threshold voltage Vth: Id = 1e -7 The value of Vg at this time.
[0027] (2) Multiple simulations are performed on the key device. The values of Vg, Vd and Vb are different in each simulation, and a threshold voltage Vth can be obtained in each simulation.
[0028] (3) After multiple simulations are completed, the threshold voltage Vth = f(Vg, Vd, Vb) is obtained, that is, the relationship between Vth and Vg, Vd, and Vb.
[0029] (4) Vg, Vd and Vb at each moment are described in PWL file A, so Vth at each moment can be obtained through step (3).
[0030] (5) In the test, the difference delta_Vth that needs to be adjusted for the threshold voltage Vth is already known; continue to use the formula Vth=f(Vg, Vd, Vb) obtained in step (3), and while keeping Vg and Vd unchanged, we can get Vth+delta_Vth=f(Vg, Vd, Vb_new) to get a new Vb value.
[0031] (6) In PWL file B, record the Vb_new calculated at each moment, that is, the new Vb value; using PWL file B can control the Vth of the key device to change from Vth to Vth+delta_Vth at a certain moment.
[0032] Furthermore, if it is a controlled voltage source or current source, a PWL file B can also be obtained. PWL file B describes the relationship between the voltage source / current source changing with time.
[0033] Furthermore, the present invention also provides a corresponding connection device, which is a connection device for a nanoprobe and a chip. One end of the device is used to connect the probe, and the other end can directly plug and unplug an external device, thereby realizing the connection of one or more external devices to the original chip through a nanoprobe.
[0034] Furthermore, the connection device is also provided with a register for storing the PWL file B.
[0035] Beneficial effects of the present invention:
[0036] 1. SPICE simulation can roughly identify the problematic device. By adding some components and retesting the failed chip, the problematic device can be confirmed again. This ensures the certainty of the root cause of the problem and completely eliminates the problem in the next tape-out production.
[0037] 2. Use the custom file B to control the performance of external devices, adjust the devices in the chip that no longer meet the performance expectations to match the performance, and test again to see if the chip works properly. If it works properly, it means that the problematic device has been found.
[0038] 3. If the key component problem is not clear, the problem still exists in the second tape-out production, causing time delay and increased product cost. The present invention further clarifies the key component causing the problem by adding more test simulation links.
[0039] In summary, if this patent is not used, the chip will be produced again after the cause is estimated, and then the chip will be tested after it leaves the factory. The probability of the chip working normally is 80%. The cause needs to be eliminated many times. Each elimination requires 1 month of redesign time and 2 months of chip re-production time. The additional cost varies depending on the chip process, ranging from 100,000 to several million. After using this patent, the estimated cause is not only verified in simulation, but also verified by hardware testing. After re-production, the probability of chip success is 99%. It saves 3 months and huge financial expenses. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 A schematic diagram of the threshold voltage simulation value and test value of the pmos device of the present invention;
[0041] Figure 2 The dotted line is the test value in the present invention and the curve of chip output changing with temperature;
[0042] Figure 3 It is a flow chart of the present invention. DETAILED DESCRIPTION
[0043] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0044] like Figure 1-3 As shown, a back-end analysis method for chip failure, the technical solution adopted to solve its technical problems is as follows:
[0045] Step 1: When a device on the failed chip has been identified as the key device of chip failure through SPICE simulation, use the nanoprobe (a particularly thin probe) of FIB or SEM equipment to isolate the key device or add a new device at the endpoint of the key device (such as the source, drain, gate or substrate end of the pmos of the problem device) for subsequent analysis.
[0046] The confirmation of the key component causing chip failure means that the probability of the key component causing chip failure is greater than a set threshold, and the threshold is generally set to 80%.
[0047] Furthermore, the added new device is:
[0048] Method 1: When the key device provides insufficient voltage or current, causing the chip to fail, the new device added is a controllable voltage source / current source;
[0049] Method 2: When the current provided by the key device is too large and causes the chip to fail, a controlled resistor is added to the source and drain ends of the key device to reduce the excessive source and drain current in the failed circuit.
[0050] Method 3: Use the same key component (possibly in a separate package) to replace the original problematic component.
[0051] 3-1. Directly replace the original problematic device that caused the chip failure with a spare identical key device;
[0052] 3-2. Isolate the key device on the original chip, and then reconnect a new key device through the nanoprobe.
[0053] For example, if the threshold voltage of the original pmos is suspected to have changed, the original pmos is directly isolated and a new pmos is reconnected through the nanoprobe. For the convenience of connection, the pmos is a packaged independent pmos, and its threshold reaches the new threshold voltage by changing the length and width of the device. Through the new pmos, it can be verified whether the chip is caused by the old pmos.
[0054] Method 4: When the suspected key device is MOSFET (including PMOS and MMOS), the performance of the key device, such as the threshold voltage, is changed by changing the substrate voltage of the MOSFET, thereby verifying that the chip failure is caused by the difference between the threshold voltage and the SPICE simulation results.
[0055] Step 2: In step 1, a device can be added to the original chip through the nanoprobe, or the suspected key device can be changed by changing the substrate voltage. However, step 1 does not describe how large and how much performance the device needs to be added, and how much the substrate voltage needs to be changed, so as to complete the entire analysis work and determine that the key device is the component that causes the chip failure. Step 2 will describe this method.
[0056] If method 3 is used in step 1, that is, a same key device is used, but its threshold voltage or other performance is the same as expected (the threshold voltage of the original device is offset from the simulation value, so the actual chip test is different from the expected value). Directly test the chip after connecting the same new device. If the chip works as expected, it means that the chip failure is caused by this device, and it can be corrected in the next version of production.
[0057] If method 3 in step 1 is not convenient to implement, for example, there is no suitable identical device, it can only be implemented by other methods, such as changing the substrate voltage through method 4 to control the key device, such as MOSFET.
[0058] For example: Figure 1As shown in the figure, the threshold voltage Vth (the figure is the Id-Vg curve, which is the change law of the drain current and the gate voltage. The threshold voltage Vth can be defined as Vg when Id = 1e-7) can be adjusted with the change of Vb (i.e., substrate voltage). Therefore, in the verification process of the failure circuit, it is necessary to know when to adjust Vb. Vb is related to the terminal voltage (Vs, Vg and Vd) of the key device at every moment in the failure test. The specific implementation method is:
[0059] ① Through SPICE simulation, the chip status of normal operation is obtained, and the corresponding relationship between the voltage of each terminal (Vs, Vg and Vd) of the key device and time, that is, the value of Vd, Vs, Vg, Vb at a certain moment. They are stored in a PWL file (which can be named A file). The content of the file is shown in Table 1 below:
[0060] Table 1
[0061] time Vd Vs Vg Vb 1 second 0 0 1 0 ... ... ... ... ... 10 seconds 1 0.5 1.5 0
[0062] Further, the PWL file is explained as follows:
[0063] In circuit simulation software such as LTspice, PWL (Piece-wise linear) is a piecewise linear voltage source that can describe the required voltage source waveform by setting the voltage value corresponding to the time. This method can directly set the coordinate points with time as the horizontal axis and voltage as the vertical axis in the voltage source, or it can be described by importing a file. If you need to set the period or number of cycles, you can do so through specific instructions.
[0064] ②Through Figure 1 It can be seen that by testing a single key device or SPICE simulation, the relationship between the change of Vth and Vb, Vs, Vd, and Vg can be obtained. Based on the PWL file A obtained earlier, and through a code program or a calculation formula in Excel, the value of the threshold voltage Vth at each moment can be calculated through the content recorded in file A. At the same time, the value of the threshold voltage error that needs to be changed is known, so the value of Vb required at the current moment can be calculated, and finally the PWL file B is obtained. The content example is shown in Table 2 below:
[0065] Table 2
[0066] time Vb 1 second 0.3 ... ... 10 seconds 0.5
[0067] The calculation process in Excel is as follows:
[0068] (1) Define the value of Vg (abscissa) when the threshold voltage Vth is Id=1e-7 (ordinate).
[0069] (2) Multiple simulations are performed on the device, with different values of Vg, Vd and Vb in each simulation, and a threshold voltage Vth can be obtained in each simulation.
[0070] (3) After multiple simulations are completed, Vth = f(Vg, Vd, Vb) is obtained, that is, the relationship between Vth and Vg, Vd, Vb.
[0071] Among them, f() is an existing function, and the specific formula is as follows:
[0072]
[0073] Among them, K1, K2, K3 are parameters; T0 represents room temperature, T represents current temperature, L is the channel length of the key device; V th Represents the threshold voltage, V b Indicates the voltage Vb in the file.
[0074] (4) In PWL file A, Vg, Vd, and Vb at each moment are described, so Vth at each moment can be obtained through step (3).
[0075] (5) In the test, the difference delta_Vth that needs to be adjusted for the threshold voltage Vth is already known; continue to use the formula Vth=f(Vg, Vd, Vb) obtained in step (3), and while keeping Vg and Vd unchanged, we can get Vth+delta_Vth=f(Vg, Vd, Vb_new) to get a new Vb value.
[0076] (6) In PWL file B, record the Vb_new calculated at each moment, i.e., the new Vb value;
[0077] By using PWL file B, the Vth of key components can be controlled to change from Vth to Vth+delta_Vth at a certain moment.
[0078] Furthermore, if it is a controlled voltage source or current source, a PWL file B can be obtained similarly, which contains the relationship between the voltage source / current source and time.
[0079] ③ In the actual chip test, file B is applied to the key device, and the threshold voltage or other performance of the key device will change with the chip test (the threshold voltage on the chip does not meet expectations, and by changing Vb, the threshold voltage will meet expectations). Verify whether the chip works normally under the action of file B. If normal, it means that the problem is with the key device.
[0080] Furthermore, the present invention also provides a connection device, which is a connection device for connecting a nanoprobe to a chip, one end of which is used to connect the probe, and the other end can directly plug and unplug external devices. Furthermore, the device can realize connecting one or more external devices to the original chip through a nanoprobe, which is convenient for connection.
[0081] Furthermore, the connection device is also provided with a register for storing the PWL file B.
[0082] Furthermore, the connecting device is also provided with a microprocessor, which is connected to the probe of the chip testing equipment and has a jack for external devices. It is also connected to the testing equipment by a data line, and the microprocessor controls the external device through the data in file B.
[0083] Those skilled in the art will appreciate that the embodiments in the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt a complete hardware embodiment, a complete software embodiment, or a form of an embodiment combining software and hardware. Moreover, the present application may adopt a form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0084] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0085] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0087] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.
[0088] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the present application without departing from the spirit and scope of the embodiments in the present application. Thus, if these modifications and variations of the embodiments in the present application fall within the scope of the claims and their equivalents in the embodiments of the present application, the embodiments of the present application are also intended to include these modifications and variations.
Claims
1. A back-end analysis method for chip failure, characterized in that: The steps include: Step 1: When a device on the failed chip has been identified as a key device for chip failure through SPICE simulation, use a nanoprobe of a FIB or SEM device to isolate the key device or add a new device at the endpoint of the key device for subsequent analysis; Step 2: After adding the new device, if the corresponding threshold voltage or other performance is the same as expected, directly test the chip connected with the new device. If the chip works as expected, it means that the chip failure is caused by this device, and it can be corrected in the next version of production.
2. A back-end analysis method for chip failure according to claim 1, characterized in that: The confirmation of the key component causing chip failure described in step 1 means that the probability of the key component causing chip failure is greater than a set threshold.
3. A back-end analysis method for chip failure according to claim 1, characterized in that: The confirmation of the key component causing chip failure in step 1 means that the probability of the key component causing chip failure is greater than 80%.
4. A back-end analysis method for chip failure according to claim 2 or 3, characterized in that: Ways to add a new device as described in step 1 include: Method 1: When the key device provides insufficient voltage or current, causing the chip to fail, the new device added is a controllable voltage source / current source; Method 2: When the current provided by the key device is too large and causes the chip to fail, a controlled resistor is added to the source and drain ends of the key device to reduce the excessive source and drain current in the failed circuit; Method 3: Use the same key components to replace the original problematic components, including the same key components in independent packages; Method 4: When the suspected key device is a MOSFET, the performance of the key device is changed by changing the substrate voltage of the MOSFET, thereby verifying that the chip failure is caused by the difference between the performance and the SPICE simulation result.
5. A back-end analysis method for chip failure according to claim 4, characterized in that: Method 3 in step 1 specifically has the following two situations: 3-1. Directly replace the original problematic device that caused the chip failure with a spare identical key device; 3-2. Isolate the key components on the original chip, and then reconnect a new identical key component through nanoprobes.
6. A back-end analysis method for chip failure according to claim 5, characterized in that: Step 2 is implemented as follows: If method 3 in step 1 is inconvenient to implement, the key device can only be regulated by changing the substrate voltage through method 4, and the specific implementation is as follows: ① Obtain the normal working chip status through SPICE simulation, and the corresponding relationship between the voltage of each terminal of the key device and time. The terminal voltage includes Vs, Vg and Vd; that is, at a certain moment, the values of Vd, Vs, Vg and Vb are stored in a PWL file A; ② Through the test of a single key device or SPICE simulation, the relationship between the change of the threshold voltage Vth and the voltages Vb, Vs, Vd, and Vg can be obtained; based on the PWL file A, and through a code program or a calculation formula in Excel, the value of the threshold voltage Vth at each moment can be calculated through the content recorded in the file PWLA, and the difference in the threshold voltage that needs to be adjusted is known, so the value of Vb required at the current moment can be calculated, and finally the PWL file B is obtained; ③ In the actual chip test, PWL file B is applied to the key device, and the threshold voltage or other performance of the key device will change with the chip test. Verify whether the chip works normally under the action of PWL file B. If normal, it means that the problem is with the key device.
7. A back-end analysis method for chip failure according to claim 6, characterized in that: The code program or the calculation formula in Excel is used to implement the process as follows: (1) Define the threshold voltage Vth: Id = 1e -7 The value of Vg at (2) Perform multiple simulations on the key device, with different values of Vg, Vd, and Vb in each simulation, and obtain a threshold voltage Vth in each simulation; (3) After multiple simulations are completed, the threshold voltage Vth = f(Vg, Vd, Vb) is obtained, that is, the relationship between Vth and Vg, Vd, and Vb; (4) The PWL file A describes Vg, Vd and Vb at each moment, so the Vth at each moment can be obtained through step (3); (5) In the test, the difference delta_Vth that the threshold voltage Vth needs to be adjusted is already known; continue to use the formula Vth=f(Vg, Vd, Vb) obtained in step (3), and while keeping Vg and Vd unchanged, Vth+delta_Vth=f(Vg, Vd, Vb_new) can be obtained to obtain a new Vb value; (6) In PWL file B, record the Vb_new calculated at each moment, that is, the new Vb value; using PWL file B can control the Vth of the key device to change from Vth to Vth+delta_Vth at a certain moment.
8. The back-end analysis method for chip failure according to claim 6, characterized in that: If it is a controlled voltage source or current source, you can also get PWL file B, which describes the relationship between the voltage source / current source and time.
9. The back-end analysis method for chip failure according to claim 6, characterized in that: A corresponding connection device is also provided, which is a connection device for connecting the nanoprobe to the chip. One end of the device is used to connect the probe, and the other end can directly plug and unplug the external device, so as to connect one or more external devices to the original chip through a nanoprobe.
10. A back-end analysis method for chip failure according to claim 9, characterized in that: The connection device is also provided with a register for storing the PWL file B.