Display device and driving circuit thereof

Abstract

The invention provides a display device and a driving circuit thereof, and the driving circuit comprises a gate driving circuit which comprises a plurality of cascaded shift registers and is used for providing a row driving signal for a pixel circuit of the display device; the power management circuit is used for generating a power voltage signal; the time sequence control circuit is connected with the power supply management circuit and is used for generating a time sequence reference voltage signal based on the time sequence working voltage signal provided by the power supply management circuit; and the voltage conversion circuit is connected with the power supply management circuit, the time sequence control circuit and the shift register, and is used for obtaining a target voltage signal based on the power supply voltage signal and converting the time sequence reference voltage signal into a driving voltage signal based on the target voltage signal so as to drive the shift register. The voltage conversion of the gate driving signal can be realized, different driving voltage requirements are met, and the overall energy consumption is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display device and a driving circuit thereof. Background Art

[0002] The driving circuit of the display device usually directly uses the power signal generated by the power chip (IC) to provide it to the level conversion circuit, generating a driving signal to drive the shift register, and then the shift register generates a gate driving signal to provide a row driving signal for the pixel circuit. However, this driving method is single and relatively simple, which limits the output capacity of the gate drive and cannot meet the driving requirements of large-size display scenes, different voltages and more outputs, reducing the display effect and performance of the display module. Summary of the invention

[0003] The present disclosure provides a display device and a driving circuit thereof to solve part or all of the above technical problems to a certain extent.

[0004] In a first aspect of the present disclosure, a driving circuit for a display device is provided, comprising:

[0005] A gate driving circuit, comprising a plurality of cascaded shift registers, for providing a row driving signal for a pixel circuit of the display device;

[0006] A power management circuit for generating a power supply voltage signal;

[0007] A timing control circuit, connected to the power management circuit, for generating a timing reference voltage signal based on a timing working voltage signal provided by the power management circuit;

[0008] A voltage conversion circuit is connected to the power management circuit, the timing control circuit and the shift register, and is used to obtain a target voltage signal based on the power supply voltage signal, and convert the timing reference voltage signal into a driving voltage signal based on the target voltage signal to drive the shift register.

[0009] A second aspect of the present disclosure provides a display device, comprising:

[0010] A plurality of sub-pixels arranged in an array and a plurality of pixel circuits for driving the plurality of sub-pixels;

[0011] The driving circuit as described in the first aspect is used to provide row driving signals for the plurality of pixel circuits.

[0012] It can be seen from the above that the display device and its driving circuit provided by the present invention convert the power supply voltage signal output by the power management circuit through the voltage conversion circuit to obtain the target voltage signal, so as to adjust the power supply voltage of the shift register, and then adjust the driving voltage signal of the shift register to the gate, so as to drive the pixel circuit efficiently and stably, which helps to improve the display effect and reduce energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 is a schematic diagram of a display device and a driving circuit thereof in the related art.

[0015] Figure 2 Schematic diagram of a driving circuit of a display device according to an embodiment of the present disclosure.

[0016] Figure 3 Schematic diagram of a driving circuit of a display device according to an embodiment of the present disclosure.

[0017] Figure 4 Schematic diagram of a digital-to-analog conversion circuit according to an embodiment of the present disclosure.

[0018] Figure 5 Schematic diagram of a voltage conversion branch according to an embodiment of the present disclosure.

[0019] Figure 6 Schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Organic light-emitting diode (OLED) displays are becoming more and more popular as the mainstream display medium in various fields of today's society due to their advantages of lightness, high contrast and fast response time. They are widely used in mobile phones, touch screen computers (TPCs), notebook computers (NBs) and other products. As OLED technology becomes more and more mature, new pixel circuits have also emerged, which has also put forward new requirements for the gate drive circuit of the pixel circuit. In related technologies, such as Figure 1 As shown, the display device includes a display panel, and the display panel includes a display area and a non-display area, wherein the display area may further include a plurality of pixel units P arranged in an array, and each pixel unit P may further include a sub-pixel and a pixel circuit for driving the sub-pixel. The pixel circuit completes the work of driving the sub-pixel under the driving signal provided by the peripheral driving circuit. In some scenarios, in order to achieve a narrow frame of the display device, a gate driving circuit may be provided in the non-display area of ​​the display panel. The gate driving circuit may further include a plurality of cascaded gate driving (GOA) units (or shift registers) on the array substrate, and a plurality of GOA units, for example, GOA1, GOA2, ..., GOAn, respectively generate shift pulse signals Gout1, Gout2, ..., Goutn, respectively, and output them to the pixel units P of the corresponding rows, so as to provide row driving signals for the pixel circuits of the corresponding row pixel units. Exemplarily, the shift pulse signal of each row not only drives the gate of the thin film transistor (TFT) in the pixel circuit of the pixel unit of the current row to turn on the TFT, but also serves as the start signal of the next row GOA (the first row is triggered by the frame start signal STV) and the end signal of the previous row GOA to control, thereby realizing the row-by-row scanning drive function.

[0023] The GOA signal required by the GOA unit on the display panel is usually generated by the timing chip TCON IC (GND-1.8V), and the timing signal is provided to each GOA module through the level shift circuit LS1 and LS2 integrated in the SDIC. Figure 1 As shown, the power management chip PMIC can provide up to two sets of voltage signals VGL1 / VGH1 and VGL2 / VGH2 as the working voltages of the level shift circuits LS1 and LS2 respectively. The level shift circuit LS1 converts the timing signal into the GOA signal Out1 based on the voltage signal VGL1 / VGH1, and provides it to the GOA modules GOA1 and GOA2. The level shift circuit LS1 converts the timing signal into the GOA signal Out2 based on the voltage signal VGL2 / VGH2, and provides it to the GOA module GOAn. At this time, the SDIC can only support level shifts of up to 2 sets of voltages VGL1 / VGH1 and VGL2 / VGH2, so that the GOA signal provided to the GOA module supports up to two different signals. However, with the improvement of display technology, the pixel circuit has changed. When the pixel circuit is partitioned and displayed, more sets of driving signals with different voltages are required, and it is necessary to provide multiple sets of power supply voltages to the level shift circuit. In the related art, only two sets of voltages can be provided to the level shift circuit, which cannot meet the demand of providing multiple sets of power supply voltages to the level shift circuit; and these two sets of voltages cannot be adjusted, which reduces the flexibility of gate drive. Therefore, how to provide multiple sets of adjustable driving signals, reduce power consumption, reduce size and layout difficulties have become technical problems that need to be solved urgently.

[0024] In view of this, an embodiment of the present disclosure provides a display device and a driving circuit thereof, which converts the power supply voltage signal output by the power management circuit through a voltage conversion circuit to obtain a target voltage signal, so as to adjust the power supply voltage of the shift register, and then adjust the row drive signal provided by the shift register to the pixel circuit, thereby efficiently and stably driving the pixel circuit, which helps to improve the display effect and reduce energy consumption.

[0025] See also Figure 2 , Figure 2 FIG. 2 is a schematic diagram of a driving circuit 200 of a display device according to an embodiment of the present disclosure. Exemplarily, the driving circuit 200 is used to realize driving of the display device. Figure 2 In the embodiment, the driving circuit 200 comprises:

[0026] The gate driving circuit 210 includes a plurality of cascaded shift registers GOA1 to GOAn, which are used to provide a row driving signal for the pixel circuit;

[0027] A power management circuit 220, configured to generate a power voltage signal;

[0028] The timing control circuit 230 is connected to the power management circuit 220 and is used to generate a timing reference voltage signal based on the timing working voltage signal provided by the power management circuit 220;

[0029] The voltage conversion circuit 240 is connected to the power management circuit 220, the timing control circuit 230 and the shift register 210, and is used to obtain a target voltage signal based on the power supply voltage signal, and convert the timing reference voltage signal into a driving voltage signal based on the target voltage signal to drive the shift register 210.

[0030] Among them, the shift register is a logic circuit with serial input and parallel output, which is used to shift the input data sequence into the register bit by bit, and form a parallel output sequence identical to the input data sequence at the output end. Multiple shift registers are used in cascade, and the pixel circuits of the corresponding rows can be driven in sequence. Exemplarily, the pixel circuit includes multiple TFTs, and the output of the shift register can provide a drive signal for the gate of one or more TFTs, so the row drive signal can also be considered as a gate drive signal. By controlling the input signal of the shift register, accurate control of the gate of the pixel circuit can be achieved, thereby controlling the lighting and extinguishing of the pixel. The power management circuit is used to generate the power supply voltage signal required by the gate drive circuit, and the power supply voltage signal may include DC voltages of different levels to provide a stable power supply for the gate drive circuit. The timing control circuit is connected to the power management circuit, and a timing reference voltage signal can be generated based on the timing working voltage signal provided by the power management circuit. The timing reference voltage signal can control the timing relationship of various operations in the gate drive circuit (such as the clock signal of the shift register, the reset signal, etc.). By accurately controlling the timing reference voltage signal, it can be ensured that the various parts in the gate drive circuit work in a predetermined order and time interval. The voltage conversion circuit obtains a target voltage signal based on the power supply voltage signal, and the target voltage signal may include a DC voltage or a pulse voltage of different levels. The voltage conversion circuit can also convert the timing reference voltage signal into a drive voltage signal to drive the shift register. In this way, by adjusting the levels of the target voltage signal and the drive voltage signal, precise control of the shift register (and thus controlling the pixel circuit gate) can be achieved. This helps to improve the display quality and stability of the display panel while reducing power consumption and cost.

[0031] Specifically, Figure 2As shown, the power management circuit 220 can generate power supply voltage signals VGH1 / VGL1 and VGH2 / VGL2. The power management circuit 220 can be connected to the timing control circuit 230 to provide the timing operating voltage signals Vcore and VIO thereto, and the timing control circuit 230 generates timing reference voltage signals Gin_1, Gin_2, ..., Gin_m. The voltage conversion circuit 240 can obtain target voltage signals VGH1_1 / VGL1_1, VGH1_2 / VGL1_2, ..., VGH2_1 / VGL2_1, ... based on the power supply voltage signals VGH1 / VGL1 and VGH2 / VGL2. Based on the voltage provided by the target voltage signal, the voltage conversion circuit 240 can convert the timing reference voltage signal into a driving voltage signal Out1, Out2, ..., Outk to drive the shift registers GOA1, GOA2, ..., GOAn. The outputs Gout1, Gout2, ..., Goutk of the shift registers respectively drive the gates of the pixel circuits. The output of a shift register may drive the gate of a row of pixel units; when the pixel unit includes multiple gates, the output of multiple shift registers may drive the gate of a row of pixel units, which is not limited here. It can be seen that the adjustment of the power supply voltage signals VGH1 / VGL1 and VGH2 / VGL2 realizes the adjustment of the driving voltage signals Out1, Out2, ..., Outk of the shift register, and then realizes the adjustment of the row driving signals Gout1, Gout2, ..., Goutk.

[0032] In the related art, the power supply voltage signal generated by the power management circuit is directly provided to the level converter, so that the level converter can only work based on a fixed power supply voltage signal, so the voltage signal output after the level conversion of the timing signal is also fixed and cannot be adjusted as needed. In contrast, in the driving circuit of the embodiment of the present disclosure, the driving voltage signal of the shift register can be adjusted, which can meet the requirements of the driving signals of different voltages of the shift register.

[0033] In some embodiments, the voltage conversion circuit includes at least one voltage conversion branch; wherein the voltage conversion branch includes: a first operational amplifier, a level converter, and a second operational amplifier connected in series;

[0034] The first operational amplifier and the second operational amplifier provide the target voltage signal to the level converter;

[0035] The level converter converts the timing reference voltage signal into a driving voltage signal based on the target voltage signal to drive at least one of the shift registers.

[0036] Among them, the voltage conversion circuit may include one or more voltage conversion branches to adapt to different voltage conversion requirements. Each voltage conversion branch can independently process the power supply voltage signal and the timing reference voltage signal, thereby generating an independent drive voltage signal to meet the different drive requirements of the shift register in the gate drive circuit. The first operational amplifier and the second operational amplifier convert the power supply voltage signal into a corresponding target voltage signal, and the voltage converter receives the target voltage signals provided by the first operational amplifier and the second operational amplifier respectively, and based on this, performs level conversion on the timing reference voltage signal generated by the timing control circuit. This ensures that the timing reference voltage signal can be accurately converted into a drive voltage signal to match the drive requirements of the shift register, thereby ensuring the stability and accuracy of the gate drive.

[0037] like Figure 2 As shown, the voltage conversion circuit 240 may include one or more voltage conversion branches 240_1, 240_2, ..., 240_m, and the circuit structure of each voltage conversion branch is the same. Each voltage conversion branch may include a first operational amplifier OP1, a level converter LS and a second operational amplifier OP2 connected in series. The first operational amplifier OP1 can be connected to the high level output end of the power management circuit 220, and is used to convert the high levels VGH1 and VGH2 in the power supply voltage signal to obtain the high levels VGH1-1, VGH1-2, ..., VGH2-1, ... in the target voltage signal. The output end of the first operational amplifier OP1 is connected to the high level end of the level converter LS, and the high levels VGH1-1, VGH1-2, ..., VGH2-1, ... in the target voltage signal are provided to the corresponding level converter LS. The second operational amplifier OP2 can be connected to the low level output terminal of the power management circuit 220, and is used to convert the low levels VGL1 and VGL2 in the power supply voltage signal to obtain the low levels VGL1-1, VGL1-2, ..., VGL2-1, ... in the target voltage signal. The output terminal of the second operational amplifier OP2 is connected to the low level terminal of the level converter LS, and the low levels VGL1-1, VGL1-2, ..., VGL2-1, ... in the target voltage signal are provided to the corresponding level converter LS. At this time, the level converter LS converts the timing reference voltage signals Gin_1, Gin_2, ..., Gin_m output by the timing control circuit 230 into driving voltage signals Out1, Out2, ..., Outk.

[0038] The shift registers can be grouped based on the gate drive requirements, i.e., different row drive signals. The shift registers corresponding to the row drive signals with the same drive voltage requirements can be grouped into one group, and the voltage can be adjusted by the same voltage conversion branch. The shift registers in the same group have the same drive voltage requirements and can use the same voltage conversion branch, thus avoiding unnecessary power consumption. The drive voltage signals output by different voltage conversion branches can be the same or different.

[0039] Specifically, see Figure 3 , Figure 3 A schematic diagram of a driving circuit of a display device according to an embodiment of the present disclosure is shown. Figure 3 In the SDIC (System Device Integrated Circuit), all shift registers GOA are divided into GOA1-5, GOA6-8, GOA9-11, GOA12-14, GOA15-17, GOA18-20, ... according to the driving voltage requirements. The ISP register can be used to adjust the size of multiple groups of VGH / L inside the SDIC to control the level of the driving signal Out1~20 of the shift register. For the shift register GOA1-5, the first timing reference voltage signal Gin1-5 output by the timing control circuit 230 can be converted by the corresponding voltage conversion branch to generate the first driving voltage signal Out1-5, and the first driving voltage signal Out1-5 is input to the corresponding 5 shift registers GOA1-5. Similarly, for the shift registers GOA6-8, the second timing reference voltage signal Gin6-8 output by the timing control circuit 230 can be converted through the corresponding voltage conversion branch to generate a second driving voltage signal Out6-8, and the second driving voltage signal Out6-8 is input to the corresponding five shift registers GOA6-8. For the shift registers GOA9-11, GOA12-14, GOA15-17, GOA18-20, ..., the corresponding driving voltage signals Out9-11, Out12-14, Out15-17, Out8-20, ... can be generated through the corresponding voltage conversion branch, and are input to the corresponding shift registers GOA9-11, GOA12-14, GOA15-17, GOA18-20, ...

[0040] In some embodiments, the number of the voltage conversion branches is greater than the number of the power supply voltage signals.

[0041] The number of voltage conversion branches can represent the number of driving voltage signals of the shift register. When the number of voltage conversion branches is greater than the number of power supply voltage signals, it means that a larger number of driving voltage signals can be realized based on a smaller number of power supply voltage signals. Even if the power management circuit only provides a limited number of power supply voltage signals, the voltage conversion circuit can generate and output more groups of target voltage signals through the parallel operation of multiple voltage conversion branches. Figure 2 As shown, the number of voltage conversion branches is m, the number of power supply voltage signals is 2, and m is greater than 2. It can be seen that even if the power management circuit only provides 2 groups of VGH / L power supply voltage signals, the voltage conversion circuit can generate and output more groups (for example, 6 groups) of VGH / L driving signals through multiple voltage conversion branches.

[0042] In the gate drive circuit in the related art, the power management circuit (PMIC) can usually only support a limited number of power supply voltage signals (for example, up to 2 groups of VGH / L), and these power supply voltage signals are directly provided to the level conversion circuit LS, so that the level conversion circuit LS has at most two voltage levels of power supply voltage signals, which cannot meet the driving requirements of multiple different voltages. If more voltage levels of driving signals are required, the power management circuit (PMIC) needs to output more groups of VGH / L, or multiple power management circuits (PMIC) are used. This will increase the size and cost of the power management circuit, as well as the overall power consumption, and to a certain extent limit the performance and compatibility of the gate drive circuit. In contrast, the driving circuit of the display device of the embodiment of the present disclosure realizes a circuit design with less input and more output, which not only enhances the driving capability and compatibility, but also reduces power consumption and cost, simplifies the PCB layout, and reduces the wiring complexity and space occupation. It can provide a more powerful driving capability, and even in the face of a large number of pixel circuit driving scenarios, it can ensure stable driving performance. Since it can output multiple groups of VGH / L driving signals, the gate drive circuit of the embodiment of the present disclosure can more flexibly adapt to display panels of different specifications and requirements. At the same time, since the reliance on external power management circuits is reduced, the overall power consumption and cost are also reduced.

[0043] In some embodiments, the power supply voltage signal includes a first power supply voltage signal and a second power supply voltage signal;

[0044] At least one of the voltage conversion branches includes a first group of voltage conversion branches and a second group of voltage conversion branches, wherein the first group of voltage conversion branches obtains corresponding target voltage signals based on the first power supply voltage signal, and the second group of voltage conversion branches obtains corresponding target voltage signals based on the second power supply voltage signal.

[0045] Among them, the number of power supply voltage signals can be one group or multiple groups, which can represent different voltage levels or functional requirements, and are used to provide a stable power supply for the gate drive circuit. Each group of power supply voltage signals can be the same or different. The voltage conversion branch can be divided into multiple groups according to the number of power supply voltage signals, and each group converts the same power supply voltage signal to obtain a corresponding target voltage signal. Through the parallel operation of multiple groups of power supply voltage signal conversions, the gate drive circuit can provide a more powerful driving capability. Even in the face of the need to drive a large number of pixel circuits, stable driving performance and fast response speed can be ensured. In addition, the dependence on the external power management circuit is reduced, the cost is reduced, and the PCB layout of the power management circuit is simplified.

[0046] Specifically, Figure 2 As shown, the power management circuit 220 can provide two groups of power voltage signals, namely, a first power voltage signal VGH1 / VGL1 and a second power voltage signal VGH2 / VGL2. The first power voltage signal VGH1 / VGL1 and the second power voltage signal VGH2 / VGL2 can be the same or different. Based on the first power voltage signal VGH1 / VGL1, the voltage conversion branches 240_1 and 240_2 can be divided into a first group of voltage conversion branches, indicating that the first group of voltage conversion branches is an adjustment of the first power voltage signal VGH1 / VGL1, and the target voltage signal VGH1_1 / VGL1_1 corresponding to the voltage conversion branch 240_1 and the voltage conversion branch 240_2 VGH1_2 VGL1_2 are obtained respectively. Based on the second power supply voltage signal VGH2 / VGL2, the voltage conversion branch 240_m can be divided into a second group of voltage conversion branches, indicating that the second group of voltage conversion branches adjusts the second power supply voltage signal VGH2 / VGL2 to obtain a target voltage signal VGH2_1 / VGL2_1 corresponding to the voltage conversion branch 240_m.

[0047] In some embodiments, at least one of the voltage conversion branches includes a first voltage conversion branch and a second voltage conversion branch, the target voltage signal obtained by the first voltage conversion branch is different from the target voltage signal obtained by the second voltage conversion branch, and the driving voltage signal output by the first voltage conversion branch is different from the driving voltage signal output by the second voltage conversion branch.

[0048] Among them, the voltage conversion circuit includes at least two independent voltage conversion branches, namely a first voltage conversion branch and a second voltage conversion branch. The two voltage conversion branches can each perform different voltage conversion tasks and generate different target voltage signals and drive voltage signals. In this way, each voltage conversion branch can be independently configured and optimized to adapt to different power supply voltage input and output requirements. Through different voltage conversion branches, the drive circuit of the display device can simultaneously generate a variety of different drive voltage signals, thereby meeting the drive requirements of multiple voltage levels of the drive circuit. This improves the flexibility and adaptability of the drive circuit, reduces power consumption and improves overall performance.

[0049] Specifically, Figure 2 As shown, the target voltage signals VGH1-1, VGL1-1 obtained by the first voltage conversion branch 240_1 and the target voltage signals VGH1-2, VGL1-2 obtained by the second voltage conversion branch 240_2 may be different, and the driving voltage signal Out1 output by the first voltage conversion branch 240_1 to the shift register GOA1 and the driving voltage signal Out2 output by the second voltage conversion branch 240_2 to the shift register GOA2 may be different, thereby meeting the driving requirements of multiple voltage levels of the driving circuit. It should be understood that the driving voltage signals corresponding to the multiple voltage conversion branches may be partially the same, completely the same, or completely different, and may be set based on the driving requirements, which is not limited here.

[0050] In some embodiments, the target voltage signal includes a first target voltage signal, and a target voltage range of the first target voltage signal is within a power supply voltage range of the power supply voltage signal;

[0051] The voltage conversion circuit further includes:

[0052] a control register, configured to generate a voltage setting signal for the first target voltage signal;

[0053] The digital-to-analog conversion circuit is used to convert the power supply voltage signal into the first target voltage signal based on the voltage setting signal.

[0054] Among them, the voltage value of the target voltage signal output by the voltage conversion circuit may not exceed the voltage range of the power supply voltage signal. The voltage range of the target voltage signal can be determined according to the voltage range of the power supply voltage signal. Specifically, a certain voltage margin is set based on the voltage range of the power supply voltage signal to determine the voltage range of the target voltage signal. For example, the voltage range of the power supply voltage signal is VGH1 / 2: 4.0~16.0, VGL1 / 2: -21.5~-2.0, then the voltage margin can be set to 0.5V, that is, the voltage range of the power supply voltage signal is reduced by 0.5V to obtain the voltage range of the target voltage signal, VGH1 / 2_1-3: 4.5~15.5V, VGL1 / 2_1-3: -21~-2.5V.

[0055] By adjusting the settings in the control register, the output voltage of the voltage conversion branch can be flexibly set to meet different voltage requirements. The digital-to-analog conversion circuit usually contains components such as a resistor array, a current switch or a voltage switch. The digital-to-analog conversion circuit receives a voltage setting signal from the control register, and these switches are opened or closed accordingly and converted into a corresponding analog voltage signal, i.e., the first target voltage signal. Figure 4 As shown, Figure 4 A schematic diagram of a digital-to-analog conversion circuit according to an embodiment of the present disclosure is shown. Figure 4 In the embodiment, the corresponding first target voltage signal can be generated by the voltage setting signal D2D1D0. For example, when D2D1D0 is 000 and DB2DB1DB0 is 111, switches D2, D1 and D0 are all disconnected, switches DB2, DB1 and DB0 are all closed, and the high level output by the digital-to-analog conversion circuit is V1 and the low level is V0.

[0056] In some embodiments, the number of addresses of the address bits of the control register storing data is determined based on the target voltage range and a preset adjustment step size;

[0057] The number of the digital-to-analog conversion circuits is determined based on the number of addresses and the number of branches of the voltage conversion branch.

[0058] The preset adjustment step size may refer to the minimum increment that the voltage can be adjusted. The smaller the preset adjustment step size, the higher the precision of the voltage adjustment, which can meet more driving requirements. Figure 3 The target voltage signal has a voltage range of VGH1 / 2_1-3: 4.5 to 15.5 V, VGL1 / 2_1-3: -21 to -2.5 V. The number of high-level address bits of the target voltage signal = (15.5-4.5) / 0.1 = 110. 6 =64<110<2 7 =128, so 2 7address bits to store 110 high-level data. The number of low-level address bits of the target voltage signal = (21-2.5) / 0.1 = 185, which also requires 2 7 address bits to store low-level data. Then the target voltage signal VGH / L1 / 2_1-3 requires 2 7 *6 digital-to-analog conversion circuits.

[0059] In some embodiments, the voltage conversion circuit further includes:

[0060] Data selection circuit for:

[0061] determining, based on a received first selection signal, that the first operational amplifier outputs a target high level signal in the first target voltage signal, and that the second operational amplifier outputs a target low level signal in the first target voltage signal;

[0062] Alternatively, based on the received second selection signal, it is determined that the second operational amplifier outputs a power high level signal in the power supply voltage signal, and the second operational amplifier outputs a power low level signal in the power supply voltage signal, and the target voltage signal includes the power supply voltage signal.

[0063] Among them, the data selection circuit can be a multiplexer MUX (Multiplexer). MUX has multiple input terminals for receiving different input signals. MUX also includes a selection terminal for determining which input signal will be selected and transmitted to the output terminal; and an output terminal for outputting the selected input signal. For a voltage conversion branch, 2a data selection circuits can be set. By setting the data selection circuit, the normal voltage conversion path can be bypassed in some cases, and the power supply voltage signal can be directly output, thereby ensuring that the requirements of multiple groups of target voltage signals are met while being compatible with the drive requirements of the existing two groups of power supply voltage signals. In this way, it can be ensured that the driving circuit can maintain high performance in various application scenarios, improve the flexibility and scalability of the driving circuit of the display device, enhance the reliability and stability of the driving circuit, and simplify the design and maintenance of the driving circuit.

[0064] Specifically, the target voltage signal may be a power supply voltage signal, or may be a first target voltage signal that converts the power supply voltage signal. The output of the data selection circuit is determined by setting a signal at the selection end of the data selection circuit. For example, when the selection end receives a first selection signal, the data selection circuit outputs a first target voltage signal; when the selection end receives a second selection signal, the data selection circuit outputs a power supply voltage signal. Figure 5 As shown, Figure 5 A schematic diagram of a voltage conversion branch according to an embodiment of the present disclosure is shown. Figure 5In the embodiment, for 6 voltage conversion branches, 12 data selection circuits can be set, and the output of the data selection circuit is determined by the selection terminal signal PVG_5. When the selection terminal signal PVG_5 is 0 (for example, a low level), the data selection circuit outputs the power supply voltage signal VGH1 / VGL1, VGH2 / VGL2 to the corresponding first operational amplifier or second operational amplifier, so that the power supply voltage signal is directly provided to the corresponding level converter, and two sets of drive signals are used to drive the shift register. When the selection terminal signal PVG_5 is 1 (for example, a high level), the data selection circuit outputs the first target voltage signal VGH1_1-3 / VGL1_1-3, VGH2_1-3 / VGL2_1-3 to the corresponding first operational amplifier or second operational amplifier, so that multiple sets of adjustable drive signals are used to drive the shift register.

[0065] In some embodiments, a first input terminal of the data selection circuit receives the power supply voltage signal, a second input terminal of the data selection circuit receives the target voltage signal, and an output terminal of the data selection circuit is connected to the first operational amplifier or the second operational amplifier.

[0066] Specifically, Figure 5 As shown, the first operational amplifier BUF1_GH1-3, BUF2_GH1-3 and the second operational amplifier BUF1_GL1-3, BUF2_GL1-3 can all achieve voltage following, so that their outputs are consistent with their inputs. The outputs of the first operational amplifier BUF1_GH1-3, BUF2_GH1-3 and the second operational amplifier BUF1_GL1-3, BUF2_GL1-3 are connected to the corresponding level converter to provide the target voltage signal VGH1_1-3 / VGL1_1-3, VGH2_1-3 / VGL2_1-3 to the corresponding level converter. When the output of the data selection circuit is a power supply voltage signal, the target voltage signal is kept consistent with the power supply voltage signal. When the output of the data selection circuit is an adjustable first target voltage signal, the target voltage signal is kept consistent with the first power supply voltage signal.

[0067] Among them, the operating power supply voltage of the operational amplifier (Operational Amplifier) ​​can limit the maximum range of its own output voltage. For example, if the maximum supply voltage of an operational amplifier is ±bV, then its output voltage will not exceed this range in theory. Therefore, the voltage range of the target voltage signal can be unilaterally shrunk to a preset voltage based on the power supply range of the power supply voltage signal VGH / L1 / 2. For example, the high level range can be unilaterally shrunk by 0.5V to 7.75V, and the low level range can be unilaterally shrunk by 10.5V to 0.5V, so as to reduce the electromagnetic radiation of the parameters at the edge of the circuit board, improve electromagnetic compatibility, ensure that the operational amplifier works stably and meets the use requirements of the panel.

[0068] The present disclosure also provides a display device, comprising:

[0069] A plurality of sub-pixels arranged in an array and a plurality of pixel circuits for driving the plurality of sub-pixels;

[0070] The driving circuit as described in the embodiment of the present disclosure is used to provide row driving signals for the multiple pixel circuits.

[0071] The display device can be used as a component for displaying images or videos, and can include a pixel circuit and a driving circuit. Figure 6 , Figure 6 A schematic diagram of a display device according to an embodiment of the present disclosure is shown. Figure 6 In the embodiment, the display device may include a display panel, and driving circuits SD_1, SD_2, SD_3, SD_4, ... according to the embodiment of the present disclosure. A plurality of sub-pixels (such as light-emitting units) arranged in an array and a plurality of pixel circuits for driving the plurality of sub-pixels may be provided on the display panel. The power management circuit provided on the PCB board only needs to provide two groups of power supply voltage signals to realize the driving voltage requirements of more groups of independently adjustable shift registers, reduce the cross-voltage of multiple groups of shift registers, and reduce the power consumption of the display module. The design complexity of the power management circuit is simplified, and the chip size can be reduced accordingly. Not only does it save costs, but it also makes the power management circuit more compact and reduces the volume. At the same time, it can also simplify the layout and routing on the PCB, which not only saves space, but also reduces the signal interference and electromagnetic radiation problems that may be caused by complex routing, thereby improving the stability and reliability of the system.

[0072] It should be noted that the above describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0073] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0074] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0075] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0076] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A driving circuit for a display device, comprising: A gate driving circuit, comprising a plurality of cascaded shift registers, for providing a row driving signal for a pixel circuit of the display device; A power management circuit for generating a power supply voltage signal; A timing control circuit, connected to the power management circuit, for generating a timing reference voltage signal based on a timing operating voltage signal provided by the power management circuit; A voltage conversion circuit is connected to the power management circuit, the timing control circuit and the shift register, and is used to obtain a target voltage signal based on the power supply voltage signal, and convert the timing reference voltage signal into a driving voltage signal based on the target voltage signal to drive the shift register.

2. The driving circuit according to claim 1, wherein: The voltage conversion circuit comprises at least one voltage conversion branch; wherein the voltage conversion branch comprises: a first operational amplifier, a level converter and a second operational amplifier connected in series; The first operational amplifier and the second operational amplifier provide the target voltage signal to the level converter; The level converter converts the timing reference voltage signal into the driving voltage signal based on the target voltage signal to drive at least one of the shift registers.

3. The driving circuit according to claim 2, wherein: The number of the voltage conversion branches is greater than the number of the power supply voltage signals.

4. The driving circuit according to claim 2, wherein: The power supply voltage signal includes a first power supply voltage signal and a second power supply voltage signal; At least one of the voltage conversion branches includes a first group of voltage conversion branches and a second group of voltage conversion branches, wherein the first group of voltage conversion branches obtains corresponding target voltage signals based on the first power supply voltage signal, and the second group of voltage conversion branches obtains corresponding target voltage signals based on the second power supply voltage signal.

5. The driving circuit according to claim 2, wherein: At least one of the voltage conversion branches includes a first voltage conversion branch and a second voltage conversion branch, the target voltage signal obtained by the first voltage conversion branch is different from the target voltage signal obtained by the second voltage conversion branch, and the driving voltage signal output by the first voltage conversion branch is different from the driving voltage signal output by the second voltage conversion branch.

6. The driving circuit according to claim 2, wherein: The target voltage signal comprises a first target voltage signal, wherein a target voltage range of the first target voltage signal is within a power supply voltage range of the power supply voltage signal; The voltage conversion circuit further includes: a control register, configured to generate a voltage setting signal for the first target voltage signal; The digital-to-analog conversion circuit is used to convert the power supply voltage signal into the first target voltage signal based on the voltage setting signal.

7. The driving circuit according to claim 6, wherein: The voltage conversion circuit further includes: Data selection circuit for: determining, based on a received first selection signal, that the first operational amplifier outputs a target high level signal in the first target voltage signal, and that the second operational amplifier outputs a target low level signal in the first target voltage signal; Alternatively, based on the received second selection signal, it is determined that the second operational amplifier outputs a power high level signal in the power supply voltage signal, and the second operational amplifier outputs a power low level signal in the power supply voltage signal, and the target voltage signal includes the power supply voltage signal.

8. The driving circuit according to claim 7, wherein: A first input terminal of the data selection circuit receives the power supply voltage signal, a second input terminal of the data selection circuit receives the target voltage signal, and an output terminal of the data selection circuit is connected to the first operational amplifier or the second operational amplifier.

9. The driving circuit according to claim 6, wherein: The number of addresses of the address bits of the control register storing data is determined based on the target voltage range and a preset adjustment step size; The number of the digital-to-analog conversion circuits is determined based on the number of addresses and the number of branches of the voltage conversion branch.

10. A display device, comprising: A plurality of sub-pixels arranged in an array and a plurality of pixel circuits for driving the plurality of sub-pixels; The driving circuit according to any one of claims 1 to 9, is used to provide row driving signals for the plurality of pixel circuits.

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