Preparation method of semiconductor structure

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure, and the method is characterized in that the method comprises the steps: providing a first wafer, the first wafer comprises a plurality of first chips, and first cutting channels are disposed among the plurality of first chips; a first dielectric layer, a first groove and a second groove are formed on the first surface of the first wafer, the first groove and the second groove are located in the first dielectric layer, a first alignment mark is formed in the first groove, a first contact pad is formed in the second groove, and the first contact pad is connected with the first chip; providing a plurality of second chip structures, and correspondingly bonding and connecting the second chip structures with the first chips on the side, provided with the first alignment marks, of the first wafer to form the first semiconductor structure; a second alignment mark corresponding to the first alignment mark is formed on the to-be-bonded structure; and bonding the first semiconductor structure with the to-be-bonded structure based on alignment operation between the first alignment mark and the second alignment mark.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] As semiconductor devices develop towards miniaturization, high integration and multifunctionality, the stability and reliability issues during use have also attracted widespread attention. The packaging process of semiconductor devices is a necessary stage in the formation of semiconductor devices, which is directly related to the stability and reliability of the final semiconductor devices during use.

[0003] However, in the current manufacturing process of semiconductor devices, there are still relatively complicated process steps in the packaging stage. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for preparing a semiconductor device, the method comprising:

[0005] A first semiconductor structure is provided, comprising:

[0006] Providing a first wafer, wherein the first wafer includes a plurality of first chips, and a first dicing lane is arranged between the plurality of first chips;

[0007] Forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on the first surface of the first wafer, wherein the orthographic projection of the first groove on the first surface is located within a range defined by the orthographic projection of the first cutting path on the first surface;

[0008] Performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip;

[0009] Providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form the first semiconductor structure;

[0010] A structure to be bonded is provided, on which a second alignment mark corresponding to the first alignment mark is formed; and based on an alignment operation between the first alignment mark and the second alignment mark, the first semiconductor structure is bonded to the structure to be bonded.

[0011] In some embodiments, the first semiconductor structure is provided, further comprising:

[0012] providing a carrier board, and forming a third alignment mark on the carrier board;

[0013] forming a fourth alignment mark corresponding to the third alignment mark on the second surface of the first wafer; wherein the first surface and the second surface are two surfaces of the first wafer arranged opposite to each other;

[0014] Based on the alignment operation between the third alignment mark and the fourth alignment mark, the carrier is bonded to a side of the first wafer away from the first alignment mark.

[0015] In some embodiments, the first semiconductor structure is provided, further comprising:

[0016] providing a carrier board, and forming a third alignment mark on the carrier board;

[0017] Providing a second wafer, wherein the second wafer includes a plurality of third chips;

[0018] A fifth alignment mark and a sixth alignment mark are formed on two surfaces of the second wafer that are opposite to each other; wherein the fifth alignment mark is arranged corresponding to the third alignment mark,

[0019] forming a fourth alignment mark on the second surface of the first wafer, wherein the sixth alignment mark is arranged corresponding to the fourth alignment mark;

[0020] Based on an alignment operation between the third alignment mark and the fifth alignment mark, the carrier is bonded to the second wafer, and based on an alignment operation between the sixth alignment mark and the fourth alignment mark, the second wafer is bonded to the first wafer.

[0021] In some embodiments, providing a plurality of the second chip structures comprises:

[0022] providing an initial structure including a plurality of second chips;

[0023] forming a second dielectric layer on the initial structure, wherein the second dielectric layer covers the surface of the initial structure;

[0024] forming a second contact pad in the second dielectric layer, wherein the second contact pad is connected to the second chip;

[0025] A dicing process is performed to separate the initial structure into a plurality of second chip structures.

[0026] In some embodiments, bonding the second chip structure to a side of the first wafer provided with a first alignment mark includes:

[0027] The first dielectric layer and the second dielectric layer are bonded correspondingly, and the first contact pad and the second contact pad are bonded correspondingly.

[0028] In some embodiments, after bonding the second chip structure to the side of the first wafer provided with the first alignment mark, the preparation method further includes:

[0029] A third dielectric layer is formed, wherein the third dielectric layer at least fills the gaps between adjacent second chip structures.

[0030] In some embodiments, the patterns of the first alignment mark, the second alignment mark, the third alignment mark, the fourth alignment mark, the fifth alignment mark, and the sixth alignment mark are formed using the same mask.

[0031] In some embodiments, the number of at least one of the patterns for forming the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark on the same mask may include a plurality.

[0032] In some embodiments, after the structure to be bonded is bonded to the first semiconductor structure, the orthographic projection of the first alignment mark on the first surface falls within the range defined by the orthographic projection of the second alignment mark on the first surface, and the boundary of one coincides with the boundary of the other.

[0033] In some embodiments, a size of the first alignment mark ranges from 20 μm to 80 μm.

[0034] A method for preparing a semiconductor structure provided by an embodiment of the present disclosure comprises: providing a first semiconductor structure, comprising: providing a first wafer, the first wafer comprising a plurality of first chips, a first cutting path being arranged between the plurality of first chips; forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on a first surface of the first wafer, the orthographic projection of the first groove on the first surface being located within a range defined by the orthographic projection of the first cutting path on the first surface; performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, the first contact pad being connected to the first chip; providing a plurality of second chip structures, and correspondingly bonding the second chip structures to the first chip on a side of the first wafer provided with the first alignment mark to form the first semiconductor structure; providing a structure to be bonded, a second alignment mark corresponding to the first alignment mark being formed on the structure to be bonded; and bonding the first semiconductor structure to the structure to be bonded based on an alignment operation between the first alignment mark and the second alignment mark. Thus, in the disclosed embodiment, in the same process of forming the first contact pad on the bonding surface of the first wafer for bonding with the second chip structure, a process step of forming the first alignment mark is also performed, that is, the formation of the first contact pad and the first alignment mark are combined into the same step, which helps to save multiple process steps and improve production efficiency. At the same time, in the disclosed embodiment, the orthographic projection of the first alignment mark on the first surface of the first wafer falls within the orthographic projection range of the first cutting road on the first surface, so that the presence of the first alignment mark does not occupy the position of the first chip on the first wafer, and the setting of this position is also beneficial in the process of aligning and bonding the first semiconductor structure with the structure to be bonded, and in the process of the bonding machine detecting whether the structures are effectively aligned, the light can smoothly pass through the structure to be bonded and illuminate the first alignment mark, so that the first semiconductor structure can be well bonded with the first carrier.

[0035] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1A flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0038] Figures 2 to 11 A process flow chart of the semiconductor structure during the preparation process provided by the embodiment of the present disclosure;

[0039] Fig.12 A partial perspective view of a semiconductor structure provided for an embodiment of the present disclosure;

[0040] Fig.13 A schematic structural diagram of a semiconductor structure in a manufacturing process provided by another embodiment of the present disclosure;

[0041] Fig.14 A schematic diagram of the structures of multiple alignment structures provided in an embodiment of the present disclosure;

[0042] Fig.15 A schematic diagram of the structure of a photomask provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0047] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] With the development of large-scale integrated circuits, the characteristic size of circuits is constantly shrinking, and chips are developing in the three-dimensional direction and entering the post-Moore era, thus meeting the requirements of high integration, fast transmission speed, and low power consumption. The three-dimensional direction is mainly achieved through multi-wafer stacking, melt bonding between the carrier and the device wafer, thinning and perforating the back of the device wafer, and re-making leads on the wiring layer, so that multiple wafers can be stacked in the future. Mark) alignment for bonding, as a subsequent carrier function.

[0050] However, in the above process, there is still the problem of complicated preparation process.

[0051] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0052] The present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the method includes the following steps:

[0053] A first semiconductor structure is provided, comprising:

[0054] Step S101: providing a first wafer, wherein the first wafer includes a plurality of first chips, and a first dicing lane is arranged between the plurality of first chips;

[0055] Step S102: forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on a first surface of a first wafer, wherein an orthographic projection of the first groove on the first surface is within a range defined by an orthographic projection of the first cutting path on the first surface;

[0056] Step S103: performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip;

[0057] Step S104: providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form a first semiconductor structure;

[0058] Step S105: providing a structure to be bonded, on which a second alignment mark corresponding to the first alignment mark is formed; and bonding the first semiconductor structure to the structure to be bonded based on an alignment operation between the first alignment mark and the second alignment mark.

[0059] Thus, in the disclosed embodiment, in the same process of forming the first contact pad on the bonding surface of the first wafer for bonding with the second chip structure, a process step of forming the first alignment mark is also performed, that is, the formation of the first contact pad and the first alignment mark are combined into the same step, which helps to save multiple process steps and improve production efficiency. At the same time, in the disclosed embodiment, the orthographic projection of the first alignment mark on the first surface of the first wafer falls within the orthographic projection range of the first cutting road on the first surface, so that the presence of the first alignment mark does not occupy the position of the first chip on the first wafer, and the setting of this position is also conducive to the process of aligning and bonding the first semiconductor structure with the structure to be bonded, and the bonding machine is in the process of detecting whether the structures are effectively aligned, so that the light can smoothly pass through the structure to be bonded and illuminate the first alignment mark, so that the first semiconductor structure can be well bonded with the first carrier.

[0060] It should be understood that although Figure 1 The steps in the process are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0061] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.

[0062] Figures 2 to 11 A process flow chart of the semiconductor structure during the preparation process provided by the embodiment of the present disclosure; Fig.12 A partial perspective view of a semiconductor structure provided for an embodiment of the present disclosure; Fig.13 A schematic structural diagram of a semiconductor structure in a manufacturing process provided by another embodiment of the present disclosure; Fig.14 A schematic diagram of the structures of multiple alignment structures provided in an embodiment of the present disclosure; Fig.15 A schematic diagram of the structure of a photomask provided in an embodiment of the present disclosure.

[0063] The method for preparing a semiconductor device provided by the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0064] The preparation method provided in the embodiment of the present disclosure involves a first semiconductor structure (for details, please refer to Fig. 9 A1 in) and the structure to be bonded (for details, please refer to Fig.10 The bonding process of A2) in Figure 1 In the multiple steps shown, steps S101 to S104 are to provide a first semiconductor structure (for details, please refer to Fig. 9 In step A1), step S105 is to provide a structure to be bonded (for details, please refer to Fig.10 A2) and the steps of bonding the two together will be described below.

[0065] First, execute step S101: Figure 3 As shown, a first wafer W1 is provided. The first wafer W1 includes a plurality of first chips C1. A first scribe line Q1 is arranged between the plurality of first chips C1.

[0066] It can be understood that the first cutting lane Q1 is used to separate the multiple first chips C1 on the first wafer W1 after the packaging process is completed. The cutting process will cut the first wafer W1 at this position to achieve separation between the multiple first chips C1.

[0067] Furthermore, in some embodiments, the first cutting path Q1 can also be used to place alignment marks to improve the alignment accuracy when bonding between structures, which is beneficial to improving various performances of the bonded semiconductor structure.

[0068] Next, execute step S102, such as Figure 4 and Figure 5 As shown, a first dielectric layer L1 and a first groove T1 and a second groove T2 in the first dielectric layer L1 are formed on the first surface S1 of the first wafer W1, and the orthographic projection of the first groove T1 on the first surface is within the range defined by the orthographic projection of the first cutting street Q1 on the first surface S1.

[0069] In some embodiments, the material of the first dielectric layer L1 may include but is not limited to oxide, nitride, oxynitride and the like.

[0070] In some embodiments, after forming the first dielectric layer L1, a first sub-layer La may be formed, and the material of La may include but is not limited to at least one of insulating materials such as silicon carbon nitride (SiCN), oxide or oxynitride, or a combination thereof.

[0071] However, it is not limited to this. In some embodiments, the material (first sub-layer La) may not be formed. The specific selection can be flexibly made according to the actual situation and is not specifically limited here.

[0072] However, it is not limited thereto. In some other embodiments, the material of the first dielectric layer L1 may also be any other suitable insulating material. In actual operation, it can be flexibly selected according to actual conditions, and no specific limitation is made here.

[0073] It is understandable that, in order to provide effective support for the subsequent processes, before performing the operation step S102 on the first wafer W1 , a step of bonding the first wafer W1 to the carrier 10 will be performed in advance.

[0074] Therefore, if Figures 2 to 4 As shown, in some embodiments, a first semiconductor structure A1 is provided, further comprising:

[0075] Providing a carrier 10, and forming a third alignment mark M3 on the carrier 10;

[0076] A fourth alignment mark M4 corresponding to the third alignment mark M3 is formed on the second surface S2 of the first wafer W1; wherein the first surface S1 and the second surface S2 are two surfaces of the first wafer W1 arranged opposite to each other;

[0077] Based on the alignment operation between the third alignment mark M3 and the fourth alignment mark M4 , the carrier 10 is bonded to a side of the first wafer W1 away from the first alignment mark M1 .

[0078] In some embodiments, the material of the carrier 10 may include but is not limited to waste wafers, glass substrates, semiconductor substrates, or ceramic substrates.

[0079] In some embodiments, the active surface of the first wafer W1 may be bonded to the carrier 10, but the invention is not limited thereto, and the inactive surface of the first wafer W1 may also be bonded to the carrier 10. The active surface is the surface of the first wafer W1 on which the device structure is formed. Specifically, the active surface may be flexibly selected according to the actual situation, and is not specifically limited here.

[0080] It is understandable that, considering that users have increasingly higher requirements for the integration of semiconductor structures, in some other embodiments, before the carrier 10 is bonded to the first wafer W1, the carrier 10 may be bonded to other wafers first, and then the bonding operation with the first wafer W1 is performed. For example:

[0081] In other embodiments, Fig.13 As shown, a first semiconductor structure A1 is provided, further comprising:

[0082] Providing a carrier 10, and forming a third alignment mark M3 on the carrier 10;

[0083] Providing a second wafer W2, wherein the second wafer W2 includes a plurality of third chips C3;

[0084] A fifth alignment mark M5 and a sixth alignment mark M6 are formed on two oppositely disposed surfaces of the second wafer W2; wherein the fifth alignment mark M5 is disposed corresponding to the third alignment mark M3,

[0085] A fourth alignment mark M4 is formed on the second surface S1 of the first wafer W1, and a sixth alignment mark M6 is arranged corresponding to the fourth alignment mark M4;

[0086] Based on the alignment operation between the third alignment mark M3 and the fifth alignment mark M5 , the carrier 10 is bonded to the second wafer W2 , and based on the alignment operation between the sixth alignment mark M6 and the fourth alignment mark M4 , the second wafer W2 is bonded to the first wafer W1 .

[0087] In some embodiments, a second scribe line Q2 is disposed between the plurality of third chips C3 , and in some steps of the packaging process, the plurality of third chips C3 may be separated from each other based on the location of the second scribe line Q2 .

[0088] It should be noted that although Fig.13 In the embodiment, before forming the first alignment mark M1 and the first contact pad D1, there are two wafers, which is only for exemplary description. In fact, the number of wafers can be more, such as 3, 4, 5, 8, more than a dozen, dozens or even more, etc., which is not specifically limited here.

[0089] In some embodiments, the active surface of the second wafer W2 can be bonded to the carrier 10, but it is not limited thereto, and the inactive surface of the second wafer W2 can also be bonded to the carrier 10. The active surface is the side of the second wafer W2 on which the device structure is formed. Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here. When the second wafer W2 is bonded to the first wafer W1, depending on whether the second wafer W2 is bonded to the carrier 10 with an active surface or an inactive surface, the second wafer W2 will use an inactive surface or an active surface to bond with the active surface or inactive surface of the first wafer W1.

[0090] In some specific embodiments, one side of the first wafer W1 used for bonding with the carrier 10 or the second wafer W2 can be a non-active surface, which can reduce the communication distance between the first chip C1 included in the first wafer and the second chip structure B2 bonded in the subsequent step S105, thereby improving communication efficiency.

[0091] But it is not limited to this, the bonding surface between the first wafer W1 and the second chip structure B2 may also be other situations. Specifically, it can be flexibly selected whether the bonding surface between any two is an active surface according to the type of chip in the first semiconductor structure, etc., and no specific limitation is made here.

[0092] In some embodiments, in order to make the final semiconductor structure have a smaller volume and a smaller weight, the back sides of the first wafer W1 and the second wafer W2 may be thinned before performing related bonding operations.

[0093] However, it is not limited thereto. In some embodiments, when the first wafer W1 is directly bonded to the carrier 10 , a process of thinning the back side of the first wafer W1 may be performed after the first wafer W1 is bonded to the carrier 10 .

[0094] Alternatively, the back side of the second wafer W2 may be thinned after the carrier 10 is bonded to the second wafer W2, and the back side of the first wafer W1 may be thinned after the first wafer W1 is bonded to the second wafer W2, etc. Specifically, the process may be flexibly selected according to the actual situation, and is not specifically limited here.

[0095] Next, execute step S103, as Figure 6 As shown, a filling process is performed on the first groove T1 and the second groove T2 in the same process step to form a first alignment mark M1 in the first groove T1 and a first contact pad D1 in the second groove T2, and the first contact pad D1 is connected to the first chip C1.

[0096] Here, the material of the first contact pad D1 includes, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes.

[0097] In a conventional structure, in order to realize the alignment operation between the first semiconductor structure and the structure to be bonded in the subsequent step S105, a corresponding alignment mark is usually formed on the back side of the second chip structure (for example, the side of the second chip C2 close to the structure to be bonded A2). At this time, after the bonding operation between the second chip structure B2 and the first wafer W1 is completed, an additional series of process steps need to be performed, such as material deposition, photolithography, material etching and cleaning steps, before the first alignment mark can be obtained. The operation process is relatively complicated and the number of masks used will increase. In addition to the high process complexity, the production cost is also high.

[0098] It can be understood that if the first contact pad D1 and the first alignment mark M1 are not formed in the same step, that is, in Fig. 9In the structure shown, when the first alignment mark M1 is not formed, after the first wafer W1 and the second chip structure B2 are bonded, a step similar to S102 of forming a dielectric material layer and a step similar to S103 of etching a first groove T1 for forming the first alignment mark M1 in the dielectric material layer and a step of filling the first groove T1 to form the first alignment mark M1 are additionally performed at a position of the second chip structure B2 away from the first wafer W1. At the same time, in the above process, in order to form the first groove T1, a larger number of masks are used, and further a step of forming a mask pattern on the mask is involved, as well as multiple steps such as exposure, development, and cleaning.

[0099] That is to say, compared with the case where the first contact pad D1 and the first alignment mark M1 are formed together in the same step, when the two are not formed in the same step, in addition to the need to increase the number of masks used, additional operation steps such as material deposition, photolithography, etching and cleaning will be added. The process flow is more complicated, which can easily increase production costs and reduce production efficiency.

[0100] In the embodiments of the present disclosure, in some embodiments, the mask pattern for forming the first contact pad D1 and the mask pattern for forming the first alignment mark can be designed on the same mask, which can save the number of masks.

[0101] In addition, compared with the case where the first contact pad D1 and the first alignment mark M1 are not formed in the same step, the operation of forming the two in the same step does not increase the number of masks used, and does not require additional execution of the above-mentioned series of multiple steps. In other words, the operation of forming the two in the same step can not only save the number of masks, but also help simplify the steps in the entire process, and can save the execution of a series of operation steps: such as but not limited to material deposition, photolithography, etching and cleaning steps, which helps to simplify the process flow and improve production efficiency.

[0102] Then, step S104 is performed, as shown in FIG. Figures 7 to 9 As shown, a plurality of second chip structures B2 are provided, and the second chip structures B2 are bonded and connected to the first chips C1 on the side of the first wafer W1 provided with the first alignment mark M1 to form a first semiconductor structure A1.

[0103] In some embodiments, providing a plurality of second chip structures B2 includes:

[0104] Provide an initial structure B1 including a plurality of second chips C2 (for details, please refer to Figure 7 );

[0105] A second dielectric layer L2 is formed on the initial structure B1, and the second dielectric layer L2 covers the surface of the initial structure B1 (for details, please refer to Figure 7 );

[0106] A second contact pad D2 is formed in the second dielectric layer L2, and the second contact pad D2 is connected to the second chip C2 (for details, please refer to Figure 7 );

[0107] Perform a cutting process to divide the initial structure B1 into a plurality of second chip structures B2 (for details, please refer to Figure 8 ).

[0108] In some embodiments, Fig. 9 As shown, after bonding the second chip structure B2 to the side of the first wafer W1 provided with the first alignment mark M1, the preparation method further includes:

[0109] A third dielectric layer L3 is formed, and the third dielectric layer L3 at least fills the gaps between adjacent second chip structures B2.

[0110] In some embodiments, the material of the third dielectric layer L3 may be the same as or different from the material of the first dielectric layer L1 or the second dielectric layer L2, which is not specifically limited herein.

[0111] In some specific embodiments, the material of the third dielectric layer L3 may include oxide, such as silicon oxide.

[0112] In addition, in the subsequent bonding process, the visible light needs to pass through the carrier 10 and the third dielectric layer L3 before irradiating the first alignment mark M1. Therefore, in the embodiment of the present disclosure, certain requirements are imposed on the light transmittance of the third dielectric layer L3.

[0113] It should be noted that, since during the subsequent step S105, the alignment operation between the bonded structure A2 and the first semiconductor structure A1 during bonding needs to use the first alignment mark M1 as one of the criteria for detecting whether the two structures are aligned, the third dielectric layer L3 needs to have a certain transmittance for visible light.

[0114] In some embodiments, the material included in the third dielectric layer L3 has a transmittance range of 75%-100% for visible light (wavelength range: 380 nm-780 nm).

[0115] In some embodiments, a through silicon via structure (not labeled in the figure) and a metal layer (not labeled in the figure) located on the through silicon via structure (not labeled in the figure) are also formed on the first chip C1 , the second chip C2 , and the third chip C3 .

[0116] In some embodiments, a third scribe line Q3 is disposed between the plurality of second chips C2 , and when forming the second chip structure B2 , the initial structure B1 is cut at the location of the third scribe line Q3 to form a plurality of second chip structures B2 separated from each other.

[0117] In some embodiments, the material of the second dielectric layer L2 on the second chip structure B2 may be the same as or different from the material of the first dielectric layer L1 , which is not specifically limited herein.

[0118] In some embodiments, the material of the second contact pad D2 on the second chip structure B2 may be the same as or different from the material of the first contact pad D1 , which is not specifically limited herein.

[0119] Finally, execute step S105, as Fig.10 and Fig.11 As shown, a structure A2 to be bonded is provided, on which a second alignment mark M2 corresponding to the first alignment mark M1 is formed; and based on an alignment operation between the first alignment mark M1 and the second alignment mark M2, the first semiconductor structure A1 is bonded to the structure A2 to be bonded.

[0120] In the structure obtained by bonding the first semiconductor structure A1 and the structure to be bonded A2, a side of the first semiconductor structure A1 where the second chip structure B2 is disposed is bonded to the structure to be bonded A2.

[0121] It can be understood that in the process of bonding the first conductor structure A1 and the structure to be bonded A2 in this step, since the first alignment mark M1 is formed in advance in the same step of forming the first contact pad D1, there is no need to specially make an alignment mark on the side of the second chip structure B2 away from the first wafer W1. During the bonding process, the bonding machine can use visible light to irradiate the second alignment mark M2 and then pass through the structure to be bonded A2 and the third dielectric layer L3 to irradiate the first alignment mark M1. By detecting whether the two are aligned, the bonding accuracy can be improved and a good bonding effect can be obtained.

[0122] In some embodiments, the structure to be bonded A2 can be a carrier to provide effective support for the semiconductor structure during the process of packaging, protecting the semiconductor structure from damage or breakage due to stress generated during the process.

[0123] In some embodiments, the material of the structure A2 to be bonded, such as a carrier, may include but is not limited to a waste wafer, a glass substrate, a semiconductor substrate, or a ceramic substrate.

[0124] It is understandable that in order to achieve better alignment between the first semiconductor structure and the structure to be bonded, during the alignment detection operation performed by the bonding machine, visible light needs to pass through the structure to be bonded A2 and the inside of the third dielectric layer L3 at the same time. Therefore, there are certain requirements for the transmittance of visible light of the structure to be bonded. For example:

[0125] In some embodiments, the material included in the to-be-bonded structure A2 has a transmittance of visible light in a range of 75%-100%.

[0126] In some embodiments, the bonding between the first semiconductor structure A1 and the to-be-bonded structure A2 may be performed by at least one of a fusion bonding process and a hybrid bonding process.

[0127] In some specific embodiments, when a hybrid bonding process is adopted, bonding the second chip structure B2 to a side of the first wafer W1 provided with the first alignment mark M1 includes:

[0128] The first dielectric layer L1 and the second dielectric layer L2 are bonded correspondingly, and the first contact pad D1 and the second contact pad D2 are bonded correspondingly.

[0129] It can be understood that in the embodiment of the present disclosure, among the multiple alignment marks involved, except that the first alignment mark M1 can be set on the same mask used to form the first contact pad D1, it can also be set on the same mask with other alignment marks. Specifically, it can be selected according to actual conditions and is not specifically limited here.

[0130] In some embodiments, Fig.15 As shown, the same mask M is used to form the patterns of the first alignment mark M1, the second alignment mark M2, the third alignment mark M3, the fourth alignment mark M4, the fifth alignment mark M5 and the sixth alignment mark M6 as shown in the figure.

[0131] It can be understood that this processing method can effectively reduce the number of masks used in the entire semiconductor structure formation process, which is beneficial to saving costs. It is only necessary to select the area where the corresponding pattern is located for normal process processing when forming the corresponding mark.

[0132] Continue to refer Fig.15 In some embodiments, among the patterns of the first alignment mark, the second alignment mark, the third alignment mark and the fourth alignment mark (the first group Z1, the second group Z2, the third group Z3, the fourth group Z4, the fifth group Z5) located on the same mask M, the number of at least one of them may include multiple ones.

[0133] It should be noted that the attached Fig.15The figure only schematically shows the case where a group of patterns contains multiple numbers. This is only for illustrative purposes. In fact, the number of any one of them can be set to multiple numbers, which are not listed here one by one. The method of setting it to multiple numbers helps to select a pattern structure with the required accuracy during the preparation process to meet the use requirements of the final mark.

[0134] In some embodiments, Fig.14 and Fig.15 As shown, among the alignment marks obtained by the same set of patterns on the mask M, the marks used to achieve bonding alignment can be of complementary shapes, that is, the structures composed of the two have overlapping boundaries in the orthographic projection direction and no gap inside the edges. This helps to more efficiently detect whether the alignment is good.

[0135] The following will take the M1 and M2 alignment marks as an example to illustrate this situation, and the same setting can also be used between other pairs of alignment marks used to detect whether the two structures are effectively aligned:

[0136] In any of the above embodiments, if Fig.11 and Fig.12 As shown, after the bonded structure A2 is bonded to the first semiconductor structure A1, the orthographic projection of the first alignment mark M1 on the first surface S1 falls within the range defined by the orthographic projection of the second alignment mark M2 on the first surface S1, and the boundary of one coincides with the boundary of the other.

[0137] In some specific embodiments, Fig.14 As shown, the shape of a pair of alignment marks used to detect whether the bonding process is well aligned may include but is not limited to Fig.14 For example, a pair of marks shown in Figure (a1) and Figure (a2), a pair of marks shown in Figure (b1) and Figure (b2), a pair of marks shown in Figure (c1) and Figure (c2), a pair of marks shown in Figure (d1) and Figure (d2), a pair of marks shown in Figure (e1) and Figure (e2), etc. Any pair of alignment marks helps to improve the efficiency of detecting whether the alignment is good.

[0138] In some embodiments, the size range of the first alignment mark M2 can be between 20μm and 80μm (including endpoint values), for example, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, etc.

[0139] It is understandable that the size ranges of other alignment marks may also be within the above ranges, which will not be elaborated here.

[0140] It should be noted that the method for preparing the semiconductor structure provided by the embodiments of the present disclosure can be applied to any integrated circuit including the structure, including but not limited to vertical integration of processed integrated circuits for 3D SOC, micro-pad packaging, low-cost and high-efficiency replacement of flip-chip bonding, wafer-level packaging, thermal management, unique device structures (such as metal substrate devices). Applications further include but are not limited to integrated circuits (such as back-illuminated image sensors), RF front-ends, micro-electromechanical structures (MEMS) (including but not limited to pico-projectors and gyroscopes), 3D stacked memory (including but not limited to hybrid memory blocks), high-bandwidth memory, DIRAM, 2.5D (including but not limited to FPGA tilted on an insert) and products using these circuits (including but not limited to mobile phones and other mobile devices, laptops, servers).

[0141] The technical features in the technical solutions described in the embodiments can be combined arbitrarily without conflict. Those skilled in the art can change the order of the steps of the above-mentioned formation method without departing from the protection scope of the present disclosure. The steps in the embodiments of the present disclosure can be performed simultaneously or in sequence without conflict.

[0142] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: A first semiconductor structure is provided, comprising: Providing a first wafer, wherein the first wafer includes a plurality of first chips, and a first dicing lane is arranged between the plurality of first chips; Forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on the first surface of the first wafer, wherein the orthographic projection of the first groove on the first surface is located within a range defined by the orthographic projection of the first cutting path on the first surface; Performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip; Providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form the first semiconductor structure; A structure to be bonded is provided, on which a second alignment mark corresponding to the first alignment mark is formed; and based on an alignment operation between the first alignment mark and the second alignment mark, the first semiconductor structure is bonded to the structure to be bonded.

2. The method according to claim 1, characterized in that The first semiconductor structure is provided, further comprising: providing a carrier board, and forming a third alignment mark on the carrier board; forming a fourth alignment mark corresponding to the third alignment mark on the second surface of the first wafer; wherein the first surface and the second surface are two surfaces of the first wafer arranged opposite to each other; Based on the alignment operation between the third alignment mark and the fourth alignment mark, the carrier is bonded to a side of the first wafer away from the first alignment mark.

3. The method according to claim 1, characterized in that The first semiconductor structure is provided, further comprising: providing a carrier board, and forming a third alignment mark on the carrier board; Providing a second wafer, wherein the second wafer includes a plurality of third chips; A fifth alignment mark and a sixth alignment mark are formed on two surfaces of the second wafer that are opposite to each other; wherein the fifth alignment mark is arranged corresponding to the third alignment mark, forming a fourth alignment mark on the second surface of the first wafer, wherein the sixth alignment mark is arranged corresponding to the fourth alignment mark; Based on an alignment operation between the third alignment mark and the fifth alignment mark, the carrier is bonded to the second wafer, and based on an alignment operation between the sixth alignment mark and the fourth alignment mark, the second wafer is bonded to the first wafer.

4. The method according to claim 1, characterized in that: Providing a plurality of the second chip structures comprises: providing an initial structure including a plurality of second chips; forming a second dielectric layer on the initial structure, wherein the second dielectric layer covers the surface of the initial structure; forming a second contact pad in the second dielectric layer, wherein the second contact pad is connected to the second chip; A dicing process is performed to separate the initial structure into a plurality of second chip structures.

5. The method according to claim 4, characterized in that Bonding the second chip structure to a side of the first wafer provided with a first alignment mark, comprising: The first dielectric layer and the second dielectric layer are bonded correspondingly, and the first contact pad and the second contact pad are bonded correspondingly.

6. The method according to claim 1, characterized in that After bonding the second chip structure to the side of the first wafer provided with the first alignment mark, the preparation method further includes: A third dielectric layer is formed, wherein the third dielectric layer at least fills the gaps between adjacent second chip structures.

7. The method according to claim 3, characterized in that The patterns of the first alignment mark, the second alignment mark, the third alignment mark, the fourth alignment mark, the fifth alignment mark, and the sixth alignment mark are formed by using the same mask.

8. The method according to claim 7, characterized in that Among the patterns for forming the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark on the same mask, the number of at least one of them may include a plurality.

9. The method according to any one of claims 1 to 8, characterized in that: After the structure to be bonded is bonded to the first semiconductor structure, the orthographic projection of the first alignment mark on the first surface falls within the range defined by the orthographic projection of the second alignment mark on the first surface, and the boundary of one coincides with the boundary of the other.

10. The method according to claim 8, characterized in that The size of the first alignment mark ranges from 20 μm to 80 μm.

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