A chip testing method and system

Abstract

The application discloses a chip testing method and system, the system comprises: interference synchronization device and interference device; the first end of the interference synchronization device is connected with the measured chip; the second end of the interference synchronization device and one end of the interference device are connected, the third end of the interference synchronization device and the other end of the interference device are connected; wherein, when the interference synchronization device receives the synchronization instruction sent by the measured chip, the interference device generates a synchronization interference signal and tests the measured chip; the measured chip sends a confirmation signal to the interference synchronization device at a fixed time during the test; if the interference synchronization device does not receive the confirmation signal within a preset time, an abnormal signal is sent to the measured chip to output abnormal processing information. Through the accurate control of the timing of the interference signal by the interference synchronization device, the accurate control can make the interference signal coupled with the sensitive instruction, and thus the abnormal performance of the chip under specific interference conditions can be effectively exposed, so that effective fault detection and positioning of the chip can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a chip testing method and system. BACKGROUND

[0002] After CP and FT screening, chip manufacturers sell qualified chips to electrical and electronic equipment manufacturers for application. After the chips are integrated into specific products, the equipment manufacturers still need to test the reliability of the chips in the interference environment.

[0003] Currently, the interference pulse group is generated by a fast transient generator to periodically impact various ports of the chip to detect the reliability of the chip in the interference environment. Although this method can reveal the abnormal working state of the chip in the interference environment to a certain extent, since the execution of the pulse group and the sensitive instructions of the chip (such as abnormal instructions or register bit mutations executed by the chip in the interference environment) is asynchronous, the exception can only be exposed when the execution timing of the interference pulse and the key instructions is synchronized. However, this timing synchronization usually occurs accidentally, and in most cases, the interference pulse cannot trigger an exception, making it difficult to effectively detect and locate the fault of the chip.

[0004] Therefore, how to effectively detect and locate the fault of the chip has become a problem to be solved in the field. SUMMARY

[0005] The present application provides a chip testing method and system, which aims to effectively detect and locate the fault of the chip.

[0006] In order to achieve the above purpose, the present application provides the following technical solutions:

[0007] A chip testing system, comprising: an interference synchronization device and an interference device;

[0008] The first end of the interference synchronization device is connected with the measured chip;

[0009] The second end of the interference synchronization device and one end of the interference device are connected, and the third end of the interference synchronization device is connected with the other end of the interference device;

[0010] The interference synchronization device generates a synchronization interference signal according to the preset delay time when receiving the synchronization instruction sent by the measured chip, and tests the measured chip through the synchronization interference signal; during the testing process, the measured chip periodically sends an acknowledgement signal to the interference synchronization device; when the interference synchronization device does not receive the acknowledgement signal within the preset time, an exception signal is sent to the measured chip; after receiving the exception signal, the measured chip outputs exception processing information.

[0011] Optionally, the interference device includes a first interference source and a second interference source;

[0012] The first interference source is connected to the second end of the interference synchronization device, and the second interference source is connected to the third end of the interference synchronization device.

[0013] Optionally, the first interference source includes a first relay, a switch and an interference source;

[0014] One end of the first relay is connected to the second end of the interference synchronization device;

[0015] The other end of the switch is connected to the interference source.

[0016] Optionally, the interference synchronization device includes: a wiring terminal, a main control chip, a button group, a driver chip, a digital tube and a second relay;

[0017] One end of the connection terminal is connected to the chip under test, and the other end of the connection terminal is connected to the first interference source;

[0018] The input and output ends of the connection terminals are connected to the input and output ends of the main control chip, and the first input end of the main control chip is connected to the output end of the button group;

[0019] The first output terminal of the main control chip is connected to the input terminal of the driver chip, and the output terminal of the driver chip is connected to the input terminal of the digital tube;

[0020] The second output terminal of the main control chip is connected to the input terminal of the second relay, and the output terminal of the second relay is connected to the second interference source;

[0021] When the main control chip receives the synchronization instruction sent by the chip under test, it triggers the first interference source or the second interference source to generate an interference signal according to the delay parameter input by the key group.

[0022] Optionally, the interference synchronization device further includes: a power supply;

[0023] The output end of the power supply is connected to the second input end of the main control chip; wherein, the power supply supplies power to the interference synchronization device.

[0024] Optionally, the chip testing system further includes: an oscilloscope;

[0025] The oscilloscope is connected to the chip under test; wherein, the oscilloscope is used to collect sensitive instructions and interference signals.

[0026] Optionally, the chip testing system described above includes:

[0027] Sending synchronization instructions to the interference synchronization device through the chip under test;

[0028] When the synchronization instruction is received, the interference synchronization device is triggered to generate an interference signal according to a preset delay time, and the chip under test is tested by the interference signal; the interference device includes a first interference source and a second interference source;

[0029] During the test, the chip under test periodically sends a confirmation signal to the interference synchronization device;

[0030] When the confirmation signal is not received within a preset time, an abnormal signal is sent to the chip under test through the interference synchronization device;

[0031] When the abnormal signal is received, abnormal processing information is outputted through the chip under test.

[0032] Optionally, after sending the synchronization instruction to the interference synchronization device through the chip under test, the method further includes:

[0033] Obtain the time intervals between multiple sensitive instructions and interference signals acquired by an oscilloscope;

[0034] Calculate the average value of the time interval according to each of the time intervals;

[0035] An average value of the time intervals is determined as the preset delay time.

[0036] Optionally, when the synchronization instruction is received, triggering the interference device to generate an interference signal according to a preset delay time by the interference synchronization device, and testing the chip under test by using the interference signal, includes:

[0037] When the synchronization instruction is received, the main control chip in the interference synchronization device controls the first relay in the first interference source to be energized according to the preset delay time to obtain an interference signal, and the chip under test is tested by the interference signal.

[0038] Optionally, when the synchronization instruction is received, triggering the interference device to generate an interference signal according to a preset delay time by the interference synchronization device, and testing the chip under test by using the interference signal, includes:

[0039] When the synchronization instruction is received, the main control chip in the interference synchronization device controls the second relay in the interference synchronization device to be energized according to the preset delay time to obtain an interference signal, and the chip under test is tested by the interference signal.

[0040] The technical solution provided by the present application includes: an interference synchronization device and an interference device; the first end of the interference synchronization device is connected to the chip under test; the second end of the interference synchronization device is connected to one end of the interference device, and the third end of the interference synchronization device is connected to the other end of the interference device; wherein, when the interference synchronization device receives a synchronization instruction sent by the chip under test, it triggers the interference device to generate a synchronous interference signal and test the chip under test; during the test process, the chip under test sends a confirmation signal to the interference synchronization device at regular intervals; when the interference synchronization device does not receive the confirmation signal within a preset time, it sends an abnormal signal to the chip under test to output abnormal processing information. By accurately controlling the timing of the interference signal through the interference synchronization device, this precise control can couple the interference signal with the sensitive instruction, thereby effectively exposing the abnormal performance of the chip under specific interference conditions, thereby effectively detecting and locating the chip fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 A schematic diagram of the architecture of a chip testing system provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of the architecture of another chip testing system provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the architecture of another chip testing system provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the architecture of an interference synchronization device provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the architecture of another interference synchronization device provided in an embodiment of the present application;

[0047] Figure 6 A flowchart of a chip testing method provided in an embodiment of the present application;

[0048] Figure 7 A flowchart of a method for determining a preset delay time provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0050] In this application, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0051] like Figure 1 , which is a schematic diagram of the architecture of a chip testing system provided by an embodiment of the present application, the chip testing system includes: an interference synchronization device 11 and an interference device 12;

[0052] A first end of the interference synchronization device 11 is connected to the chip under test 13 .

[0053] The second end of the interference synchronization device 11 is connected to one end of the interference device 12 , and the third end of the interference synchronization device 11 is connected to the other end of the interference device 12 .

[0054] Among them, when the interference synchronization device 11 receives the synchronization instruction sent by the chip under test 13, it triggers the interference device 12 to generate a synchronous interference signal according to the preset delay time, and tests the chip under test 13 through the synchronous interference signal; during the test process, the chip under test 13 periodically sends a confirmation signal to the interference synchronization device 11; when the interference synchronization device 11 does not receive the confirmation signal within the preset time, it sends an abnormal signal to the chip under test 13; after receiving the abnormal signal, the chip under test 13 outputs abnormal processing information.

[0055] Further, see Figure 2 The interference device 12 includes a first interference source 21 and a second interference source 22 .

[0056] The first interference source 21 is connected to the second end of the interference synchronization device 11 , and the second interference source 22 is connected to the third end of the interference synchronization device 11 .

[0057] The first interference source 21 is an interference component carried by the chip under test itself (such as a defrost heating wire in a refrigerator).

[0058] Optionally, the second interference source 22 may be an independent interference source, which is an interference source independently constructed by simulating the interference source of the device, for example, a radio transmitting device.

[0059] It should be noted that by cutting off the connection between the chip under test 13 and the first interference source 21 in the device through the interference synchronization device 11, the second interference source can be independently controlled to generate an interference signal. The chip under test 13 or circuit board can also be taken out of the original device and then connected to an independent interference source to flexibly construct an interference signal.

[0060] It should be emphasized that, during actual testing, only one of the first interference source 21 and the second interference source 22 needs to be selected, and the first interference source 21 and the second interference source 22 do not need to work at the same time.

[0061] Further, see Figure 3 The first interference source 21 includes a first relay 31 , a switch 32 and an interference source 33 .

[0062] One end of the first relay 31 is connected to the second end of the interference synchronization device 11 .

[0063] The other end of the switch 32 is connected to the interference source 33 .

[0064] It can be understood that the interference synchronization device 11 generates an interference signal by controlling the first relay 31 to be attracted so that the switch is closed.

[0065] Further, see Figure 4 The interference synchronization device 11 includes: a connection terminal 41, a main control chip 42, a button group 43, a driving chip 44, a digital tube 45 and a second relay 46.

[0066] One end of the connection terminal 41 is connected to the chip under test 13 , and the other end of the connection terminal 41 is connected to the first interference source 21 .

[0067] It can be seen that the connection terminals 41 are hardware connection ports between the interference synchronization device 11 and the chip under test 13 , and control ports for connecting the interference synchronization device 11 and the first interference source 21 .

[0068] The input and output ends of the connection terminal 41 are connected to the input and output ends of the main control chip 42 , and the first input end of the main control chip 42 is connected to the output end of the key group 43 .

[0069] The main control chip 42 includes but is not limited to: stm32f103. The main control chip is used to receive the synchronization instruction sent by the chip under test 13, and delay trigger the interference device 12 to generate an interference signal according to the delay parameter sent by the key group 43.

[0070] Optionally, the button group 43 is composed of multiple buttons, and the delay parameters (and preset delay time) can be input through the button group 43.

[0071] The first output terminal of the main control chip 42 is connected to the input terminal of the driving chip 44 , and the output terminal of the driving chip 44 is connected to the input terminal of the digital tube 45 .

[0072] The driver chip 44 is used to drive the digital tube 45 , and the digital tube 45 is used to display the delay parameter input by the key group 43 .

[0073] The second output terminal of the main control chip 42 is connected to the input terminal of the second relay 46 , and the output terminal of the second relay 46 is connected to the second interference source 22 .

[0074] When the main control chip 42 receives the synchronization instruction sent by the chip under test 13 , it triggers the first interference source 21 or the second interference source 22 to generate an interference signal according to the delay parameter input by the key group 43 .

[0075] Optionally, the second relay is used to connect to an external independent interference source (ie, the second interference source 22 ) so as to separate the interference source in the device to which the chip under test belongs (ie, the first interference source 21 ).

[0076] Further, combined Figure 4 For the contents shown, see Figure 5 The interference synchronization device 11 also includes: a power supply 51.

[0077] The output terminal of the power supply 51 is connected to the second input terminal of the main control chip 42 .

[0078] The power supply 51 supplies power to the interference synchronization device 11 .

[0079] Furthermore, the chip testing system also includes: an oscilloscope.

[0080] The oscilloscope is connected to the chip under test 13 .

[0081] Among them, the oscilloscope is used to collect sensitive instructions and interference signals.

[0082] It is understandable that the two channels of the oscilloscope collect data simultaneously, one channel collects sensitive instructions, and the other channel collects interference signals. The interference signal collection channel is connected to the power supply port of the chip under test 13, and the power supply port of the chip under test 13 is interfered with when the relay is closed.

[0083] It should be noted that if only the first interference source 21 is present, the code in the interference synchronization device 11 needs to be modified to delay the triggering of the first interference source 21 to generate the interference signal, thereby achieving a time interval between the sensitive instruction and the interference signal and improving the coupling between the two. Each test requires powering off the system based on the oscilloscope observation results, writing and compiling the code in the interference synchronization control module, and then powering it on for testing.

[0084] However, if the first interference source 21 and the second interference source 22 are present, there is no need to modify the code in the interference synchronization device 11 when constructing the interference signal. By combining the time interval between the sensitive instruction and the interference signal acquired in real time by the oscilloscope, the interference source triggering timing can be flexibly set online through the corresponding buttons provided with the interference synchronization device 11. This effectively improves the efficiency of chip reliability testing and fault point location in interference environments.

[0085] To sum up, when the interference synchronization device receives the synchronization instruction sent by the chip under test, it triggers the interference device to generate a synchronous interference signal according to the preset delay time. The timing of the interference signal is precisely controlled by the interference synchronization device. This precise control can couple the interference signal with the sensitive instruction, and then effectively expose the abnormal performance of the chip under specific interference conditions, thereby effectively detecting and locating the chip fault.

[0086] Corresponding to the chip testing system provided in the above embodiment of the present application, the embodiment of the present application further provides a chip testing method, which is applicable to the chip testing system mentioned in the above embodiment of the present application, such as Figure 6 As shown, the following steps are included:

[0087] S601: Sending a synchronization instruction to the interference synchronization device through the chip under test.

[0088] The synchronization instruction indicates an interference signal triggering instruction.

[0089] Optionally, after step S601, a preset delay time needs to be set first, and the coupling between the interference signal and the sensitive instruction is achieved by the preset delay time. Therefore, another embodiment of the present application provides a method for determining the preset delay time, such as Figure 7 As shown, the following steps are included:

[0090] S701: Acquire time intervals between multiple sensitive instructions and interference signals acquired by an oscilloscope.

[0091] It can be understood that obtaining the time interval between multiple sensitive instructions and interference signals acquired by the oscilloscope is, that is, obtaining the time interval between multiple acquisitions of sensitive instructions and interference signals by the oscilloscope.

[0092] S702: Calculate an average value of each time interval according to the time interval.

[0093] It can be understood that, based on each time interval, the average value of the time interval is calculated. Specifically, the sum of all intervals is calculated, and the sum of all intervals is divided by the total number of time intervals to obtain the average value of the time interval.

[0094] S703: Determine the average value of the time intervals as the preset delay time.

[0095] S602: When a synchronization instruction is received, the interference synchronization device is triggered to generate an interference signal according to a preset delay time, and the chip under test is tested by the interference signal.

[0096] The interference device includes a first interference source and a second interference source.

[0097] It can be understood that, according to the preset delay time input by the key group in the interference synchronization device, the delay triggers the interference device to generate an interference signal, and the chip under test is tested by the interference signal.

[0098] Optionally, in another embodiment of the present application, the specific implementation of step S602 includes:

[0099] When a synchronization instruction is received, the main control chip in the interference synchronization device controls the first relay in the first interference source to be energized according to the preset delay time, so that the switch is closed, an interference signal is obtained, and the chip under test is tested by the interference signal.

[0100] It can be understood that the interference signal is obtained by delaying the main control chip in the interference synchronization device to control the first relay in the first interference source to be closed according to the preset delay time.

[0101] Optionally, in another embodiment of the present application, the specific implementation of step S602 includes:

[0102] When a synchronization instruction is received, the main control chip in the interference synchronization device controls the second relay in the interference synchronization device to be closed according to the preset delay time, thereby obtaining an interference signal, and testing the chip under test through the interference signal.

[0103] S603: During the test process, the chip under test periodically sends a confirmation signal to the interference synchronization device.

[0104] The confirmation signal indicates that the chip under test is not interfered with.

[0105] Optionally, the chip under test may send a confirmation signal to the interference synchronization device at intervals of 0.5 ms.

[0106] S604: When no confirmation signal is received within a preset time, an abnormal signal is sent to the chip under test through the interference synchronization device.

[0107] The abnormal signal indicates that an abnormality has occurred in the chip under test.

[0108] The preset time includes but is not limited to 0.5ms.

[0109] S605: After receiving the abnormal signal, the chip under test outputs abnormality processing information.

[0110] Among them, the exception handling information includes sensitive instructions and register values ​​where bit errors occur.

[0111] Optionally, sensitive instructions include but are not limited to: interrupt scene protection push and pop instructions, abnormal instructions executed during chip operation, and related operation instructions that cause register bit abnormalities.

[0112] It is understandable that when an abnormal signal is received, the chip under test outputs abnormal processing information to confirm that an abnormality has occurred in the chip under test. After the abnormality has occurred in the chip under test, the chip under test is reset to start the next abnormality capture.

[0113] To sum up, when the interference synchronization device receives the synchronization instruction sent by the chip under test, it triggers the interference device to generate a synchronous interference signal according to the preset delay time. The timing of the interference signal is precisely controlled by the interference synchronization device. This precise control can couple the interference signal with the sensitive instruction, and then effectively expose the abnormal performance of the chip under specific interference conditions, thereby effectively detecting and locating the chip fault.

[0114] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Ordinary technicians in this field can understand and implement it without expending creative work.

[0115] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0116] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip testing system, characterized in that: The chip testing system includes: an interference synchronization device and an interference device; The first end of the interference synchronization device is connected to the chip under test; The second end of the interference synchronization device is connected to one end of the interference device, and the third end of the interference synchronization device is connected to the other end of the interference device; Wherein, the interference device includes a first interference source and a second interference source; The first interference source is connected to the second end of the interference synchronization device, and the second interference source is connected to the third end of the interference synchronization device; The interference synchronization device includes: a connection terminal, a main control chip, a key group, a driver chip, a digital tube and a second relay; One end of the connection terminal is connected to the chip under test, and the other end of the connection terminal is connected to the first interference source; The input and output ends of the connection terminals are connected to the input and output ends of the main control chip, and the first input end of the main control chip is connected to the output end of the button group; The first output terminal of the main control chip is connected to the input terminal of the driver chip, and the output terminal of the driver chip is connected to the input terminal of the digital tube; The second output terminal of the main control chip is connected to the input terminal of the second relay, and the output terminal of the second relay is connected to the second interference source; When the main control chip receives the synchronization instruction sent by the chip under test, it triggers the first interference source or the second interference source to generate an interference signal according to the delay parameter input by the key group; When the interference synchronization device receives the synchronization instruction sent by the chip under test, it triggers the interference device to generate a synchronization interference signal according to a preset delay time, and tests the chip under test through the synchronization interference signal; During the test process, if the interference synchronization device does not receive a confirmation signal within a preset time, an abnormal signal is sent to the chip under test; the confirmation signal is a signal that the chip under test periodically sends to the interference synchronization device during the test process; after the chip under test receives the abnormal signal, it outputs abnormal processing information.

2. The system according to claim 1, wherein: The first interference source includes a first relay, a switch and an interference source; One end of the first relay is connected to the second end of the interference synchronization device; The other end of the switch is connected to the interference source.

3. The system according to claim 1, wherein: The interference synchronization device further includes: a power supply; The output end of the power supply is connected to the second input end of the main control chip; wherein, the power supply supplies power to the interference synchronization device.

4. The system according to claim 1, wherein: The chip testing system further includes: an oscilloscope; The oscilloscope is connected to the chip under test; wherein, the oscilloscope is used to collect sensitive instructions and interference signals.

5. A chip testing method, characterized in that: The chip testing system according to any one of claims 1 to 4 comprises: Sending synchronization instructions to the interference synchronization device through the chip under test; When the synchronization instruction is received, the interference synchronization device is triggered to generate an interference signal according to a preset delay time, and the chip under test is tested by the interference signal; the interference device includes a first interference source and a second interference source; During the test, the chip under test periodically sends a confirmation signal to the interference synchronization device; When the confirmation signal is not received within a preset time, an abnormal signal is sent to the chip under test through the interference synchronization device; When the abnormal signal is received, abnormal processing information is outputted through the chip under test.

6. The method according to claim 5, characterized in that After the synchronization instruction is sent to the interference synchronization device through the chip under test, the method further includes: Obtain the time intervals between multiple sensitive instructions and interference signals acquired by an oscilloscope; Calculate the average value of the time interval according to each of the time intervals; An average value of the time intervals is determined as the preset delay time.

7. The method according to claim 5, characterized in that When the synchronization instruction is received, triggering the interference device to generate an interference signal according to a preset delay time by the interference synchronization device, and testing the chip under test by using the interference signal, includes: When the synchronization instruction is received, the main control chip in the interference synchronization device controls the first relay in the first interference source to be energized according to the preset delay time to obtain an interference signal, and the chip under test is tested by the interference signal.

8. The method according to claim 5, characterized in that When the synchronization instruction is received, triggering the interference device to generate an interference signal according to a preset delay time by the interference synchronization device, and testing the chip under test by using the interference signal, includes: When the synchronization instruction is received, the main control chip in the interference synchronization device controls the second relay in the interference synchronization device to be energized according to the preset delay time to obtain an interference signal, and the chip under test is tested by the interference signal.

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