Burr-free numerical control ring oscillator

Abstract

The invention discloses a burr-free numerical control ring oscillator. The burr-free numerical control oscillator is realized based on a controllable delay chain and comprises a delay module, a control module and a decoding module. The delay module forms an oscillation loop, the control module processes control words and then outputs the control words to the decoding module, and the decoding module outputs the decoded control words to the delay module. According to the invention, the introduction of clock burrs during control word switching of the ring oscillator can be avoided, the output frequency of the ring oscillator is adjustable, the frequency range is wide, the circuit structure is simple, the design has universality, the portability is high, the overhead is low, and the ring oscillator is suitable for the field of highly integrated systems on chips and integrated circuits with higher requirements on portability.

Description

Technical Field

[0001] The invention relates to the field of clock generators for circuits and systems, and in particular to a glitch-free digitally controlled ring oscillator. Background Art

[0002] With the continuous development of integrated circuit technology, the scale, integration and design complexity of SoC chips have greatly increased. Phase-locked loops are an important part of chips. Traditional analog phase-locked loops contain passive devices, occupy a large area, have poor anti-interference ability, and are difficult to reduce in proportion to the process reduction. The modules of the fully digital phase-locked loop are all implemented by digital circuits, which have the advantages of high integration, strong portability, low cost and strong anti-noise ability. The digitally controlled oscillator is the most critical part of the fully digital phase-locked loop. Therefore, it is extremely necessary to design and optimize the digitally controlled oscillator. The digitally controlled oscillator generates a stable oscillation clock, and adjusts the oscillation frequency of the oscillator by changing the external digital control signal to achieve the purpose of controllable oscillator frequency. The digitally controlled ring oscillator is a ring oscillator formed by connecting an odd number of inverters end to end. The output frequency is determined by the number of delay units and the delay time. According to the way of controlling the frequency, it can be divided into two structures: changing the delay of the delay unit and changing the length of the delay chain. The first one has a higher resolution, but low linearity and a large number of control words, while the second one has high linearity, wide frequency range, and strong applicability, but is prone to clock glitches, so a corresponding solution needs to be proposed for this problem. In the currently proposed digitally controlled ring oscillator schemes, there are still problems such as a large number of control words, large area, high power consumption, and glitches. Therefore, it is necessary to design a low-cost and reliable digitally controlled oscillator. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a burr-free digitally controlled ring oscillator in view of the problem involved in the background.

[0004] The present invention adopts the following technical solutions to solve the above technical problems: A glitch-free digitally controlled ring oscillator circuit comprises a delay module, a decoding module and a control module; The delay module includes a fixed delay unit, a fine-adjustment delay unit, a medium-adjustment delay unit and a coarse-adjustment delay unit; The fixed delay unit comprises a NAND gate and M delay buffers connected in sequence, M being a natural number greater than or equal to 1, wherein the output end of the NAND gate is connected to the input end of the first delay buffer, the output end of the Mth delay buffer serves as the output end of the fixed delay module, the first input end of the NAND gate serves as the input end of the fixed delay unit, and the second input end of the NAND gate serves as the enable end of the fixed delay unit; The fine adjustment delay unit comprises a 4-to-1 data selector, and first to third fine adjustment buffers, wherein the input end of the first fine adjustment buffer is connected to the first input end of the 4-to-1 data selector, the output end of the first fine adjustment buffer is respectively connected to the second input end of the 4-to-1 data selector and the input end of the second fine adjustment buffer, the output end of the second fine adjustment buffer is respectively connected to the third input end of the 4-to-1 data selector and the input end of the third fine adjustment buffer, the output end of the third fine adjustment buffer is connected to the fourth input end of the 4-to-1 data selector, two selection ends of the 4-to-1 data selector are connected to the control module, the input end of the first fine adjustment buffer serves as the input end of the fine adjustment delay unit, and the output end of the 4-to-1 data selector serves as the output end of the fine adjustment delay unit; The intermediate delay unit comprises 2 K-N-2 2-to-1 data selector and 2 K-N-2 -1 intermediate delay chain, N is a natural number greater than or equal to 1, K is a natural number greater than or equal to 4, and KN-2>0; The intermediate adjustment delay chain comprises three intermediate adjustment buffers connected in sequence; 2 K-N-2 The second input ends of the 2-to-1 intermediate modulation data selectors are connected to serve as the input ends of the intermediate modulation delay unit; K-N-2 The selection ends of the 2-to-1 intermediate adjustment data selectors are all connected to the control module; the first input end of the i-th 2-to-1 intermediate adjustment data selector is connected to the output end of the i-th intermediate adjustment delay chain, and the input end of the i-th intermediate adjustment delay chain is connected to the output end of the i+1-th 2-to-1 intermediate adjustment data selector, where i is greater than or equal to 1 and less than or equal to 2 K-N-2 -1 natural number; 2nd K-N-2 The first input end of the 2-to-1 intermediate modulation data selector is grounded; the output end of the first 2-to-1 intermediate modulation data selector is used as the output end of the intermediate modulation delay unit; The coarse adjustment delay unit comprises 2 N 2-to-1 coarse data selector and 2 N -1 coarse delay chain; The coarse delay chain comprises 2 K-N-2 A delay chain, and 2 K-N-2 -1 2-to-1 delay data selector, the first input end of the i-th 2-to-1 delay data selector is connected to the output end of the i-th coarse adjustment delay chain, and the output end of the i-th 2-to-1 delay data selector is connected to the input end of the i+1-th coarse adjustment delay chain; the 2 K-N-2 - A selection terminal and a second input terminal of a 2-to-1 delay data selector are both grounded; 2 N The second input ends of the 2-to-1 coarse adjustment data selectors are connected to serve as the input ends of the coarse adjustment delay unit;N The selection ends of the 2-to-1 coarse adjustment data selectors are all connected to the control module; the first input end of the j-th 2-to-1 coarse adjustment data selector is connected to the output end of the j-th coarse adjustment delay chain, the input end of the j-th coarse adjustment delay chain is connected to the output end of the j+1-th 2-to-1 coarse adjustment data selector, and j is greater than or equal to 1 and less than or equal to 2 N -1 natural number; 2nd N The first input end of the 2-to-1 coarse adjustment data selector is grounded, and the output end of the first 2-to-1 coarse adjustment data selector serves as the output end of the coarse adjustment delay unit; The delay buffer, fine adjustment buffer and medium adjustment buffer have the same structure and all include two inverters connected in series; The output end of the fixed delay module is connected to the input end of the coarse adjustment delay unit; the output end of the coarse adjustment delay unit is connected to the input end of the medium adjustment delay unit; the output end of the medium adjustment delay unit is connected to the input end of the fine adjustment module; the output end of the fine adjustment delay unit is used to output the clock CLK, and is respectively connected to the input end of the fixed delay unit and the control module; The decoding module includes a coarse-tuning decoding module and a medium-tuning decoding module, wherein the coarse-tuning decoding module adopts N-bit input, 2 N The one-hot code decoding circuit with bit output has the same output as the 2 N The selection ends of the 2-to-1 coarse adjustment data selectors are connected one by one; the intermediate adjustment decoding module adopts KN-2 bit input, 2 K-N-2 The one-hot code decoding circuit with bit output has the same output as the 2 K-N-2 The selection ends of the 2-to-1 coarse adjustment data selectors are connected one by one; The control module includes a coarse adjustment control unit, a medium adjustment control unit and a fine adjustment control unit; The coarse adjustment control unit and the medium adjustment control unit have the same structure and both use a control word instruction unit; The control word instruction unit comprises a delay trigger group, a comparator, a first selection update trigger, a second selection update trigger, an XOR gate, a 2-to-1 control data selector, a 2-to-1 update data selector group and a first control update trigger group; The comparator adopts an M-bit comparator. When the input of the first input terminal is equal to the input of the second input terminal, the output of the first output terminal and the second output terminal are both 0; when the input of the first input terminal is less than the input of the second input terminal, the output of the first output terminal is 0 and the output of the second output terminal is 1; when the input of the first input terminal is greater than the input of the second input terminal, the output of the first output terminal is 1 and the output of the second output terminal is 0; The delay trigger group includes M D triggers, and the 2-to-1 update data selector group includes M 2-to-1 update data selectors; the input ends of the M D triggers are respectively connected to the second input ends of the M 2-to-1 update data selectors and the M bits of the first input end of the comparator in a one-to-one correspondence, and then serve as the input end of the control word instruction unit for receiving the control word input from the outside; the clock input ends of the M D triggers are connected to the clock CLK output by the output end of the fine-tuning delay unit; the output ends of the M D triggers are respectively connected to the M bits of the second input end of the comparator in a one-to-one correspondence; The first control update trigger group includes M control update triggers, the clock input ends of the M control update triggers are connected to the output end of the 2-to-1 control data selector, the clock input end of the first selection update trigger, and the clock input end of the second selection update trigger respectively; the output ends of the M control update triggers are connected to the first input ends of the M 2-to-1 update data selectors in a one-to-one correspondence, as the output ends of the control word instruction unit; the data input ends of the M control update triggers are connected to the output ends of the M 2-to-1 update data selectors in a one-to-one correspondence; the reset ends of the M control update triggers are connected to an external control reset signal; The selection ends of the M 2-to-1 update data selectors are all connected to the output end of the XOR gate; The data input terminal of the first selection update trigger is connected to the first output terminal of the comparator, and the output terminal is connected to the first input terminal of the XOR gate; The data input terminal of the second selection update trigger is connected to the second output terminal of the comparator, and the output terminal is respectively connected to the selection terminal of the 2-to-1 control data selector and the second input terminal of the XOR gate; The first input terminal of the 2-to-1 control data selector is connected to the clock CLK, and the second input terminal is connected to the inverted signal of the clock CLK; The input instruction of the control module is a K-bit control word Code from the outside world; The M in the control word instruction unit used by the coarse adjustment control unit signal is N, and its input is Code [K-1: KN], and the output end is connected to the input end of the coarse adjustment decoding module in a one-to-one correspondence; The M in the control word instruction unit used by the middle modulation control unit signal is KN-2, its input is Code[KN-1:2], and the output end is connected to the input end of the middle modulation decoding module in a one-to-one correspondence; The fine adjustment control unit comprises a four-input XOR gate and a second control update trigger group; The second control update trigger group includes 2 control update triggers; The first input end of the four-input XOR gate is respectively connected to the input end of the fine adjustment delay unit, the second input end is connected to the output end of the first fine adjustment buffer, the third input end is connected to the output end of the second fine adjustment buffer, the fourth input end is connected to the output end of the third fine adjustment buffer, and the output ends are respectively connected to the clock ends of the two control update triggers; The input ends of the two control update triggers are connected to Code[0] and Code[1] respectively, the output ends of the two control update triggers are respectively connected to the two selection ends of the 4-to-1 data selector of the fine-tuning delay module, and the reset ends of the two control update triggers are connected to an external control reset signal.

[0005] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The present invention replaces part of the buffer in the delay loop of the digital controlled ring oscillator with a 2-to-1 data selector, so that the outer path of the loop maintains a low level, thereby reducing the power consumption of the ring oscillator; 2. The buffer and the 2-to-1 data selector used in the present invention form a delay oscillation loop. Compared with the prior art regulation method using a combination of a one-hot code control word and a temperature code control word, the function can be realized using only a one-hot code control word, which simplifies the circuit structure and improves the circuit reliability. 3. The present invention uses three methods of coarse adjustment, medium adjustment and fine adjustment to adjust the control word, which reduces the number of required one-hot code control words and avoids excessive input load of the coarse adjustment delay unit and the medium adjustment delay unit; 4. The present invention proposes a control module structure according to the change of the control word and different delay units, which can avoid the oscillation loop from introducing clock glitches during the change of the control word, thereby improving the circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic diagram of a module of the present invention; Figure 2 It is a circuit diagram of the fine-tuning delay unit in the present invention; Figure 3 It is a circuit diagram of the intermediate adjustment delay unit in the present invention; Figure 4 It is a circuit diagram of the coarse adjustment delay unit in the present invention; Figure 5 is a circuit diagram of a coarse adjustment delay chain in the present invention; Figure 6 It is a circuit diagram of the control word instruction unit in the present invention; Figure 7 is a function table of the comparator in the present invention; Figure 8is a circuit diagram of a fine adjustment control unit in the present invention; Fig. 9 It is a waveform diagram of glitches generated when the control word of the numerically controlled oscillator changes without a control module; Fig.10 It is a waveform diagram correctly output when the control word of the digital controlled oscillator under the control module of the present invention changes. DETAILED DESCRIPTION

[0007] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings: The present invention may be implemented in many different forms and should not be considered limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0008] It should be understood that although the terms first, second, third, etc. can be used here to describe various elements, components and / or parts, these elements, components and / or parts are not limited by these terms. These terms are only used to distinguish elements, components and / or parts from each other. Therefore, the first element, component and / or part discussed below can become the second element, component or part without departing from the teaching of the present invention.

[0009] like Figure 1 As shown, the present invention discloses a glitch-free digital controlled ring oscillator circuit, including a delay module composed of standard units such as inverters and selectors, a control module that can avoid glitches introduced by circuit switching, and a one-hot code decoding module. In this embodiment: 1) TT, 1.2V, 25℃ PVT conditions; 2) 55nm process; 3) 8-bit control word Code[7:0], where the coarse adjustment control word is Code[7:5], the medium adjustment control word is Code[4:2], and the fine adjustment control word is Code[1:0].

[0010] The fixed delay unit comprises a NAND gate and 130 delay buffers connected in sequence, the first input end of the NAND gate serves as the input end of the fixed delay unit, and the second input end of the NAND gate serves as the enable end of the fixed delay unit.

[0011] like Figure 2As shown, the fine-tuning delay unit includes a 4-to-1 data selector and first to third fine-tuning buffers, wherein the input end of the first fine-tuning buffer is connected to the first input end of the 4-to-1 data selector, the output end of the first fine-tuning buffer is respectively connected to the second input end of the 4-to-1 data selector and the input end of the second fine-tuning buffer, the output end of the second fine-tuning buffer is respectively connected to the third input end of the 4-to-1 data selector and the input end of the third fine-tuning buffer, the output end of the third fine-tuning buffer is connected to the fourth input end of the 4-to-1 data selector, the two selection ends of the 4-to-1 data selector are connected to the control module, the input end of the first fine-tuning buffer serves as the input end of the fine-tuning delay unit, and the output end of the 4-to-1 data selector serves as the output end of the fine-tuning delay unit.

[0012] like Figure 3 As shown, the intermediate adjustment delay unit includes 8 2-to-1 intermediate adjustment data selectors and 7 intermediate adjustment delay chains; The intermediate adjustment delay chain comprises three intermediate adjustment buffers connected in sequence; The second input ends of the eight 2-in-1 intermediate modulation data selectors are all connected to serve as the input end of the intermediate modulation delay unit; the selection ends of the eight 2-in-1 intermediate modulation data selectors are all connected to the control module; the first input end of the i-th 2-in-1 intermediate modulation data selector is connected to the output end of the i-th intermediate modulation delay chain, the input end of the i-th intermediate modulation delay chain is connected to the output end of the i+1-th 2-in-1 intermediate modulation data selector, i being a natural number greater than or equal to 1 and less than or equal to 7; the first input end of the eighth 2-in-1 intermediate modulation data selector is grounded; the output end of the first 2-in-1 intermediate modulation data selector serves as the output end of the intermediate modulation delay unit.

[0013] like Figure 4 As shown, the coarse adjustment delay unit includes 8 2-to-1 coarse adjustment data selectors and 7 coarse adjustment delay chains; like Figure 5 As shown, the coarse adjustment delay chain includes 8 medium adjustment delay chains and 7 2-to-1 delay data selectors, the first input end of the i-th 2-to-1 delay data selector is connected to the output end of the i-th coarse adjustment delay chain, and the output end of the i-th 2-to-1 delay data selector is connected to the input end of the i+1-th coarse adjustment delay chain; the selection ends and second input ends of the 7 2-to-1 delay data selectors are both grounded; The second input ends of the eight 2-to-1 coarse adjustment data selectors are all connected to serve as the input end of the coarse adjustment delay unit; the selection ends of the eight 2-to-1 coarse adjustment data selectors are all connected to the control module; the first input end of the j-th 2-to-1 coarse adjustment data selector is connected to the output end of the j-th coarse adjustment delay chain, the input end of the j-th coarse adjustment delay chain is connected to the output end of the j+1-th 2-to-1 coarse adjustment data selector, and j is a natural number greater than or equal to 1 and less than or equal to 7; the first input end of the eighth 2-to-1 coarse adjustment data selector is grounded, and the output end of the first 2-to-1 coarse adjustment data selector serves as the output end of the coarse adjustment delay unit.

[0014] The delay buffer, fine adjustment buffer and medium adjustment buffer have the same structure and all include two inverters connected in series; The output end of the fixed delay module is connected to the input end of the coarse adjustment delay unit; the output end of the coarse adjustment delay unit is connected to the input end of the medium adjustment delay unit; the output end of the medium adjustment delay unit is connected to the input end of the fine adjustment module; the output end of the fine adjustment delay unit is used to output the clock CLK, and is respectively connected to the input end of the fixed delay unit and the control module; The decoding module comprises a coarse adjustment decoding module and a mid-adjustment decoding module, wherein the coarse adjustment decoding module adopts a one-hot code decoding circuit with 3-bit input and 8-bit output, and its output is connected to the selection ends of the 8 2-to-1 coarse adjustment data selectors in a one-to-one correspondence; the mid-adjustment decoding module adopts a one-hot code decoding circuit with 3-bit input and 8-bit output, and its output is connected to the selection ends of the 8 2-to-1 coarse adjustment data selectors in a one-to-one correspondence; The control module includes a coarse adjustment control unit, a medium adjustment control unit and a fine adjustment control unit; The coarse adjustment control unit and the medium adjustment control unit have the same structure and the same number of bits, and both use a control word instruction unit with 3 bits of input and output, such as Figure 6 As shown; The control word instruction unit comprises a delay trigger group, a comparator, a first selection update trigger, a second selection update trigger, an XOR gate, a 2-to-1 control data selector, a 2-to-1 update data selector group and a first control update trigger group; like Figure 7 As shown, the comparator adopts a 3-bit comparator. When the input of the first input terminal is equal to the input of the second input terminal, the outputs of the first output terminal and the second output terminal are both 0; when the input of the first input terminal is less than the input of the second input terminal, the output of the first output terminal is 0, and the output of the second output terminal is 1; when the input of the first input terminal is greater than the input of the second input terminal, the output of the first output terminal is 1, and the output of the second output terminal is 0; The delay trigger group includes three D triggers, and the 2-to-1 update data selector group includes three 2-to-1 update data selectors; the input ends of the three D triggers are respectively connected to the second input ends of the three 2-to-1 update data selectors and the three bits of the first input end of the comparator in a one-to-one correspondence, and then serve as the input end of the control word instruction unit for receiving the control word input from the outside; the clock input ends of the three D triggers are connected to the clock CLK output by the output end of the fine-tuning delay unit; the output ends of the three D triggers are respectively connected to the three bits of the second input end of the comparator in a one-to-one correspondence; The first control update trigger group includes three control update triggers, the clock input ends of the three control update triggers are connected to the output end of the 2-to-1 control data selector, the clock input end of the first selection update trigger, and the clock input end of the second selection update trigger respectively; the output ends of the three control update triggers are connected to the first input ends of the three 2-to-1 update data selectors in a one-to-one correspondence, as the output ends of the control word instruction unit; the data input ends of the M control update triggers are connected to the output ends of the three 2-to-1 update data selectors in a one-to-one correspondence; the reset ends of the three control update triggers are connected to an external control reset signal; The selection ends of the three 2-to-1 update data selectors are all connected to the output end of the XOR gate; The data input terminal of the first selection update trigger is connected to the first output terminal of the comparator, and the output terminal is connected to the first input terminal of the XOR gate; The data input terminal of the second selection update trigger is connected to the second output terminal of the comparator, and the output terminal is respectively connected to the selection terminal of the 2-to-1 control data selector and the second input terminal of the XOR gate; The first input terminal of the 2-to-1 control data selector is connected to the clock CLK, and the second input terminal is connected to the inverted signal of the clock CLK; The input instruction of the control module is an external 8-bit control word Code[7:0]; The M in the control word instruction unit used by the coarse adjustment control unit signal is 3, its input is Code[7:5], and the output end is connected to the input end of the coarse adjustment decoding module in a one-to-one correspondence; The M in the control word instruction unit used by the middle modulation control unit signal is 3, its input is Code[4:2], and the output end is connected to the input end of the middle modulation decoding module in a one-to-one correspondence; like Figure 8 As shown, the fine adjustment control unit includes a four-input XNOR gate and a second control update trigger group; The second control update trigger group includes 2 control update triggers; The first input end of the four-input XOR gate is respectively connected to the input end of the fine adjustment delay unit, the second input end is connected to the output end of the first fine adjustment buffer, the third input end is connected to the output end of the second fine adjustment buffer, the fourth input end is connected to the output end of the third fine adjustment buffer, and the output ends are respectively connected to the clock ends of the two control update triggers; The input ends of the two control update triggers are connected to Code[0] and Code[1] respectively, the output ends of the two control update triggers are respectively connected to the two selection ends of the 4-to-1 data selector of the fine-tuning delay module, and the reset ends of the two control update triggers are connected to an external control reset signal.

[0015] A ring oscillator is usually formed by cascading an odd number of inverters end to end to form an oscillation. In the present invention, a fixed delay unit, a coarse-adjustment delay unit, a medium-adjustment delay unit, and a fine-adjustment delay unit together constitute an oscillation loop. The more delay units there are in the loop, the lower the output frequency. The entire loop is divided into three types of adjustment units with different precisions in order to reduce the number of bits of the control word after decoding, while avoiding too much load on the input end of each delay unit. Therefore, the number of control bits of the delay unit and the medium-adjustment delay unit should be reasonably allocated according to the circuit scale. The fixed delay unit determines the maximum oscillation frequency of the oscillator, and the total number of buffers contained in the fixed delay unit, the coarse-adjustment delay unit, the medium-adjustment delay unit, and the fine-adjustment delay unit determines the minimum oscillation frequency of the oscillator. In this embodiment, when the Code is 8'b00000000, the oscillator outputs a maximum frequency clock, and the oscillation loop includes a NAND gate, 130 buffers of fixed delay units, a 2-to-1 coarse adjustment data selector, a 2-to-1 medium adjustment data selector and a 4-to-1 data selector. Suppose the sum of the delays of these units is T0. At this time, the oscillator outputs a maximum frequency clock with a frequency of 1 / (2*T0); when the Code is 8'b11111111, the oscillator outputs a minimum frequency clock. The oscillation loop includes a NAND gate, 130 buffers of fixed delay units, 7 coarse adjustment delay chains, 8 2-to-1 coarse adjustment data selectors, 7 medium adjustment delay chains, 8 2-to-1 medium adjustment data selectors, 3 fine adjustment buffers and a 4-to-1 data selector. Suppose the sum of the delays of these units is T1. At this time, the oscillator outputs a minimum frequency clock with a frequency of 1 / (2*T1).

[0016] The working principle of the glitch-free digitally controlled ring oscillator proposed by the present invention is described as follows: The present invention includes four external signals, namely, an enable signal EN, a control word signal Code, a control word initialization signal and a clock signal CLK. The enable signal, the control word and the control word initialization signal are input signals, and the clock signal is an output signal. The enable signal controls the oscillation of the numerically controlled oscillator. When the enable signal is at a low level, the oscillator is in a closed state and no clock signal is output; when the enable signal is at a high level, the oscillator is in a working state, and the clock signal outputs a fixed frequency clock according to the number of total delay units in the delay module.

[0017] In the control module, according to the classification of the delay module, the control module is divided into a coarse adjustment control unit, a medium adjustment control unit and a fine adjustment control unit, and the control words of the coarse adjustment delay unit, the medium adjustment delay unit and the fine adjustment control unit are updated separately. The delay trigger group delays the external control word Code for a period of time, and the comparator compares the control word before and after the delay to generate the selection update signal Sel_upd[0] and Sel_upd[1], which are used to judge the Code change state. The comparator function table is as follows: Figure 7 As shown. The clock signal CLK of the control module comes from the output clock CLK of the delay module. The function of the 2-to-1 data selector in the control module is to switch the update clock CLK_upd according to the Code state. When the delay module oscillates, the waveforms on each path node in the oscillation loop are of the same frequency but different phases, and the path nodes outside the loop remain at a low level. When the Code decreases or remains unchanged, the delay path selected by the control word becomes shorter, that is, the nodes on the path switch from the phase-lagging waveform to the phase-advanced waveform, and the phase difference does not exceed half a cycle of the current clock. Therefore, CLK_upd selects CLK output, that is, the control word is updated to the rising edge of CLK to avoid clock glitches; when the Code increases, the delay path selected by the control word becomes longer, that is, the path switches from the node with the output waveform to the node with a low level. Therefore, CLK_upd selects the inverted signal output of CLK, that is, the control word is updated to the falling edge of CLK to avoid clock glitches.

[0018] Fig. 9 and Fig.10 This is the comparison of the output clock simulation waveform when the coarse adjustment control word increases. Fig. 9 When there is no control circuit, the loop is prone to produce an output waveform with glitches because the timing of switching the control word is arbitrary. Fig.10 This is the normal output waveform of the circuit proposed in the present invention when switching the control word. Assume that between 0 and t1, the loop oscillates stably under Code=8'b00010000. Fig.10As shown, at time t1, the control word increases. First, CLK_upd performs clock switching at the rising edge, switching from CLK to the inverted output of CLK. This is to avoid generating redundant rising edges or avoiding early updating of the control word. After the clock switching is completed, the next rising edge of CLK_upd (i.e., the falling edge of CLK) is used to control Code to switch to 8'b10010000 at time t2, so that the output clock can achieve smooth frequency conversion without clock glitches. When the control word decreases, CLK_upd switches to CLK output. The XOR gate is used to determine whether the control word changes, and the delay is used to ensure that the control word is updated after the clock switching is completed. When the control word changes and is updated by selecting the update trigger, the control update trigger group selects the second input terminal to update the control word output, otherwise the original control word remains unchanged.

[0019] The fine control unit is different from the coarse control unit and the medium control unit in that it avoids clock glitches by monitoring the level of each node in the loop. The fine delay unit is selected for output by a 4-to-1 data selector. The input terminals, n1, n2, and n3 of the fine delay unit have output waveforms of the same frequency but different phases. Therefore, when the fine control word changes, the XOR gate ensures that the fine control word changes only when the waveforms of the four nodes remain at the same level, thereby achieving smooth switching of the output waveform.

[0020] All control update trigger groups have asynchronous reset terminals. In order for the circuit to work properly, a short reset is required when power is turned on.

[0021] In summary, the glitch-free digitally controlled ring oscillator circuit proposed in the present invention realizes a universal wide-range, low-overhead ring oscillator and can avoid introducing glitches when the control word is switched. The circuit can be highly integrated and has strong portability.

[0022] The specific implementations shown above have described the purpose and technical solutions of the present invention in detail. It should be noted that several substitutions and improvements can be made without departing from the principle of the present invention, and these substitutions and improvements should also be considered as the protection scope of the present invention.

Claims

1. A glitch-free digitally controlled ring oscillator circuit, characterized in that: It includes a delay module, a decoding module and a control module; The delay module includes a fixed delay unit, a fine-adjustment delay unit, a medium-adjustment delay unit and a coarse-adjustment delay unit; The fixed delay unit comprises a NAND gate and M delay buffers connected in sequence, M being a natural number greater than or equal to 1, wherein the output end of the NAND gate is connected to the input end of the first delay buffer, the output end of the Mth delay buffer serves as the output end of the fixed delay module, the first input end of the NAND gate serves as the input end of the fixed delay unit, and the second input end of the NAND gate serves as the enable end of the fixed delay unit; The fine adjustment delay unit comprises a 4-to-1 data selector, and first to third fine adjustment buffers, wherein the input end of the first fine adjustment buffer is connected to the first input end of the 4-to-1 data selector, the output end of the first fine adjustment buffer is respectively connected to the second input end of the 4-to-1 data selector and the input end of the second fine adjustment buffer, the output end of the second fine adjustment buffer is respectively connected to the third input end of the 4-to-1 data selector and the input end of the third fine adjustment buffer, the output end of the third fine adjustment buffer is connected to the fourth input end of the 4-to-1 data selector, two selection ends of the 4-to-1 data selector are connected to the control module, the input end of the first fine adjustment buffer serves as the input end of the fine adjustment delay unit, and the output end of the 4-to-1 data selector serves as the output end of the fine adjustment delay unit; The intermediate delay unit comprises 2 K-N-2 2-to-1 data selector and 2 K-N-2 -1 intermediate delay chain, N is a natural number greater than or equal to 1, K is a natural number greater than or equal to 4, and KN-2>0; The intermediate adjustment delay chain comprises three intermediate adjustment buffers connected in sequence; 2 K-N-2 The second input ends of the 2-to-1 intermediate modulation data selectors are connected to serve as the input ends of the intermediate modulation delay unit; K-N-2 The selection ends of the 2-to-1 intermediate adjustment data selectors are all connected to the control module; the first input end of the i-th 2-to-1 intermediate adjustment data selector is connected to the output end of the i-th intermediate adjustment delay chain, and the input end of the i-th intermediate adjustment delay chain is connected to the output end of the i+1-th 2-to-1 intermediate adjustment data selector, where i is greater than or equal to 1 and less than or equal to 2 K-N-2 -1 natural number; 2nd K-N-2 The first input end of the 2-to-1 intermediate modulation data selector is grounded; the output end of the first 2-to-1 intermediate modulation data selector is used as the output end of the intermediate modulation delay unit; The coarse adjustment delay unit comprises 2 N 2-to-1 coarse data selector and 2 N -1 coarse delay chain; The coarse delay chain comprises 2 K-N-2 A delay chain, and 2 K-N-2 -1 2-to-1 delay data selector, the first input end of the i-th 2-to-1 delay data selector is connected to the output end of the i-th coarse adjustment delay chain, and the output end of the i-th 2-to-1 delay data selector is connected to the input end of the i+1-th coarse adjustment delay chain; the 2 K-N-2 - A selection terminal and a second input terminal of a 2-to-1 delay data selector are both grounded; 2 N The second input ends of the 2-to-1 coarse adjustment data selectors are connected to serve as the input ends of the coarse adjustment delay unit; N The selection ends of the 2-to-1 coarse adjustment data selectors are all connected to the control module; the first input end of the j-th 2-to-1 coarse adjustment data selector is connected to the output end of the j-th coarse adjustment delay chain, the input end of the j-th coarse adjustment delay chain is connected to the output end of the j+1-th 2-to-1 coarse adjustment data selector, and j is greater than or equal to 1 and less than or equal to 2 N -1 natural number; 2nd N The first input end of the 2-to-1 coarse adjustment data selector is grounded, and the output end of the first 2-to-1 coarse adjustment data selector serves as the output end of the coarse adjustment delay unit; The delay buffer, fine adjustment buffer and medium adjustment buffer have the same structure and all include two inverters connected in series; The output end of the fixed delay module is connected to the input end of the coarse adjustment delay unit; the output end of the coarse adjustment delay unit is connected to the input end of the medium adjustment delay unit; the output end of the medium adjustment delay unit is connected to the input end of the fine adjustment module; the output end of the fine adjustment delay unit is used to output the clock CLK, and is respectively connected to the input end of the fixed delay unit and the control module; The decoding module includes a coarse-tuning decoding module and a medium-tuning decoding module, wherein the coarse-tuning decoding module adopts N-bit input, 2 N The one-hot code decoding circuit with bit output has the same output as the 2 N The selection ends of the 2-to-1 coarse adjustment data selectors are connected one by one; the intermediate adjustment decoding module adopts KN-2 bit input, 2 K-N-2 The one-hot code decoding circuit with bit output has the same output as the 2 K-N-2 The selection ends of the 2-to-1 coarse adjustment data selectors are connected one by one; The control module includes a coarse adjustment control unit, a medium adjustment control unit and a fine adjustment control unit; The coarse adjustment control unit and the medium adjustment control unit have the same structure and both use a control word instruction unit; The control word instruction unit comprises a delay trigger group, a comparator, a first selection update trigger, a second selection update trigger, an XOR gate, a 2-to-1 control data selector, a 2-to-1 update data selector group and a first control update trigger group; The comparator adopts an M-bit comparator. When the input of the first input terminal is equal to the input of the second input terminal, the output of the first output terminal and the second output terminal are both 0; when the input of the first input terminal is less than the input of the second input terminal, the output of the first output terminal is 0 and the output of the second output terminal is 1; when the input of the first input terminal is greater than the input of the second input terminal, the output of the first output terminal is 1 and the output of the second output terminal is 0; The delay trigger group includes M D triggers, and the 2-to-1 update data selector group includes M 2-to-1 update data selectors; the input ends of the M D triggers are respectively connected to the second input ends of the M 2-to-1 update data selectors and the M bits of the first input end of the comparator in a one-to-one correspondence, and then serve as the input end of the control word instruction unit for receiving the control word input from the outside; the clock input ends of the M D triggers are connected to the clock CLK output by the output end of the fine-tuning delay unit; the output ends of the M D triggers are respectively connected to the M bits of the second input end of the comparator in a one-to-one correspondence; The first control update trigger group includes M control update triggers, the clock input ends of the M control update triggers are connected to the output end of the 2-to-1 control data selector, the clock input end of the first selection update trigger, and the clock input end of the second selection update trigger respectively; the output ends of the M control update triggers are connected to the first input ends of the M 2-to-1 update data selectors in a one-to-one correspondence, as the output ends of the control word instruction unit; the data input ends of the M control update triggers are connected to the output ends of the M 2-to-1 update data selectors in a one-to-one correspondence; the reset ends of the M control update triggers are connected to an external control reset signal; The selection ends of the M 2-to-1 update data selectors are all connected to the output end of the XOR gate; The data input terminal of the first selection update trigger is connected to the first output terminal of the comparator, and the output terminal is connected to the first input terminal of the XOR gate; The data input terminal of the second selection update trigger is connected to the second output terminal of the comparator, and the output terminal is respectively connected to the selection terminal of the 2-to-1 control data selector and the second input terminal of the XOR gate; The first input terminal of the 2-to-1 control data selector is connected to the clock CLK, and the second input terminal is connected to the inverted signal of the clock CLK; The input instruction of the control module is a K-bit control word Code from the outside world; The M in the control word instruction unit used by the coarse adjustment control unit signal is N, and its input is Code [K-1: KN], and the output end is connected to the input end of the coarse adjustment decoding module in a one-to-one correspondence; The M in the control word instruction unit used by the middle modulation control unit signal is KN-2, its input is Code[KN-1:2], and the output end is connected to the input end of the middle modulation decoding module in a one-to-one correspondence; The fine adjustment control unit comprises a four-input XOR gate and a second control update trigger group; The second control update trigger group includes 2 control update triggers; The first input end of the four-input XOR gate is respectively connected to the input end of the fine adjustment delay unit, the second input end is connected to the output end of the first fine adjustment buffer, the third input end is connected to the output end of the second fine adjustment buffer, the fourth input end is connected to the output end of the third fine adjustment buffer, and the output ends are respectively connected to the clock ends of the two control update triggers; The input ends of the two control update triggers are connected to Code[0] and Code[1] respectively, the output ends of the two control update triggers are respectively connected to the two selection ends of the 4-to-1 data selector of the fine-tuning delay module, and the reset ends of the two control update triggers are connected to an external control reset signal.

Images