Digital-analog hybrid simulation method and simulator based on QEMU, SystemC and SystemC-AMS

Abstract

The invention provides a digital-analog hybrid simulation method and simulator based on a QEMU, a SystemC and a SystemC-AMS. The digital-analog hybrid simulation method comprises the following steps: adding an external memory access interface and a time sequence synchronization interface in the QEMU; the method comprises the following steps: constructing a virtual CPU (Central Processing Unit) device in a SystemC; a register interface function and a logic signal function are realized by adopting a systemc model in the equipment, and a port analog signal function is realized by adopting a systemc-am model; the starting parameters are analyzed in the main program, and the simulation component is loaded; executing a virtual target machine instruction in the instruction core environment; switching to a systemc running environment, changing the value of an on-chip device register, and updating the logic function state and the port state of the device; and exiting from the systemc operation environment, and entering the operation environment of the instruction core again. The technical advantages of the QEMU, the SystemC and the SystemC-AMS are combined, a QEMU instruction set is reused, meanwhile, the hardware description language characteristics of the SystemC and the analog signal processing capacity of a simulation scheduler and the SystemC-AMS are utilized, digital-analog hybrid simulation is achieved, and the verification efficiency and accuracy of SoC design are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation debugging, and in particular to a digital-analog hybrid simulation method and a simulator based on QEMU, SystemC and SystemC-AMS. Background Art

[0002] With the rapid development of integrated circuit technology, the design of system-on-chip is becoming increasingly complex, often integrating high-performance digital circuits and key analog circuit components, which makes simulating and verifying system functions and performance a challenge for chip design. In traditional system-on-chip design, the processing of digital signals and analog signals is usually carried out separately, resulting in problems such as long design cycle, low integration and difficult debugging.

[0003] For example, QEMU, SystemC, and SystemC-AMS are usually used as independent simulation systems, each with its own unique advantages and limitations. QEMU (Quick EMUlator) is usually used as an open source hardware simulator and virtualizer to simulate a variety of processor architectures and computer hardware platforms, including x86, ARM, PowerPC, etc. At the same time, QEMU itself has a very rich virtual device such as CPU, interrupt controller, system bus, etc., which can easily and quickly build a virtual system-on-chip for user program development and testing. However, QEMU belongs to the object-level simulation and cannot simulate the digital and analog signals of the device.

[0004] The C++-based hardware description language SystemC inherits the rich programming features and object-oriented design ideas of C++. In addition, it also incorporates the modeling capabilities of the hardware description language (HDL). It can achieve seamless conversion and collaborative design from software algorithms to hardware structures on a single platform. It is efficient and flexible in digital signal simulation of equipment, but it does not support analog signal simulation and is only suitable for early verification and performance evaluation of modern complex electronic systems.

[0005] SystemC-AMS, an extension of SystemC, integrates the capability of analog signal simulation and can provide a unified platform to simulate and verify complex systems containing mixed digital and analog signals. It is more prominent in the application of analog signal simulation and can accurately model the behavior of analog circuits, including changes in physical quantities such as voltage, current, and power, as well as how these physical quantities change over time.

[0006] The above simulation technologies have different focuses. Some can support multiple architectures but have difficulty running general operating systems, some can run general operating systems but run slowly, and some do not have good scalability. Therefore, a hybrid digital-analog simulation method is needed that can integrate QEMU, SystemC, and SystemC-AMS technologies to improve the verification efficiency and accuracy of SoC design. Summary of the invention

[0007] The digital-analog hybrid simulation method and simulator based on QEMU, SystemC and SystemC-AMS provided by the present invention are mainly used to solve the problems of long design cycle, low integration and difficult debugging caused by the separate processing of existing digital and analog signal simulations, thereby achieving the effect of realizing digital-analog hybrid simulation and improving the verification efficiency and accuracy of SoC design.

[0008] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0009] A digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS, comprising:

[0010] S1: Add external memory access interface and timing synchronization interface in QEMU, and QEMU provides instruction core.

[0011] S2: construct a virtual CPU device in SystemC, and construct hardware interconnection of the on-chip network based on the memory access interface and the timing synchronization interface.

[0012] S3: The systemc model is used in the on-chip device to implement the register interface function and logic signal function, and the systemc-ams model is used to implement the port analog signal function.

[0013] S4: The systemc model is used in off-chip devices to implement logic signal functions, and the systemc-ams model is used to implement port analog signal functions.

[0014] S5: inputting startup parameters into the main program, parsing the startup parameters to obtain device parameters, loading simulation components according to the device parameters and performing pin binding, and establishing a running environment for the device.

[0015] S6: Initialize the operating environment of the instruction core and enter the operating environment of the instruction core.

[0016] S7: Execute a virtual target machine instruction in the operating environment of the instruction core and call the relevant functional interface according to the execution result of the instruction.

[0017] S8: handing over the control right of the main program to Systemc by calling the timing synchronization interface function to enter the systemc operating environment.

[0018] S9: In the systemc operating environment, the value of the on-chip device register is changed and the logical function status and port status of the device are updated according to the operating instructions of the virtual CPU device.

[0019] S10: exit the systemc operating environment, re-enter the instruction core operating environment, and return to execute step S7 until the virtual system-on-chip simulation is completed.

[0020] A further solution is that, in step S1, the method further includes:

[0021] S11: Cut QEMU and compile it into a dynamic library in the form of instruction core.

[0022] A further solution is that, in step S2, the method further includes:

[0023] S21: Implementing the register interface function interface and the timing synchronization interface function through the virtual CPU device, and compiling the virtual CPU device into a dynamic library.

[0024] A further solution is to use a signal conversion module in both the on-chip device and the off-chip device to realize the mutual conversion function between digital signals and analog signals. The signal conversion module converts the digital signal into an analog signal by calling the sc_to_ams function, and converts the analog signal into a digital signal by calling the ams_to_sc function.

[0025] A further solution is that step S3 further includes S31: packaging the on-chip device into a dynamic library.

[0026] Step S4 also includes S41: packaging the off-chip device into a dynamic library.

[0027] A further solution is that the startup parameters include: instruction core configuration information, CPU configuration information, on-chip device configuration information, off-chip device configuration information, and port binding information of on-chip devices and off-chip devices.

[0028] A further solution is that the loading simulation component in step S5 includes:

[0029] S51: Parse the startup parameters and obtain the device parameters through the config_init function.

[0030] S52: Loading the specified instruction core dynamic library, CPU dynamic library, on-chip device dynamic library and off-chip device dynamic library into the main program according to the device parameters.

[0031] S53: Create a corresponding module instance in the main program.

[0032] A further solution is that the pin binding in step S5 includes:

[0033] S54: Exporting the memory access interface and timing synchronization interface in QEMU.

[0034] S55: Bind the memory access interface and the timing synchronization interface to corresponding interfaces in the CPU instance through the interface_register function.

[0035] S56: Bind the ports of the on-chip device and the off-chip device through the port_bind function.

[0036] A further solution is that if the virtual target machine instruction is a read IO instruction, the Systemc coroutine is called in the timing synchronization to cause the register to generate a read action.

[0037] If the virtual target machine instruction is a write IO instruction, the Systemc coroutine is called in the timing synchronization to cause the register to generate a write action.

[0038] A digital-analog hybrid simulator based on QEMU, SystemC and SystemC-AMS is applied to the digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS, comprising a QEMU module, a SystemC module, a SystemC-AMS module and a signal conversion module, wherein the QEMU module establishes a data exchange channel with an on-chip device via a memory bus to provide an instruction core; the SystemC module is used to provide a computing environment for the logical function and port status of the device, and is connected to the SystemC-AMS module via the signal conversion module to convert a digital signal into an analog signal and then output it to the SystemC-AMS module, the SystemC-AMS module is used to realize a port analog signal function, and performs analog-to-digital conversion via the signal conversion module to realize system simulation of a digital-analog hybrid signal on a virtual chip.

[0039] It can be seen that the present invention has the following beneficial effects:

[0040] The present invention provides a CPU instruction execution environment through a QEMU instruction core, and hands over the control of the main program to Systemc through a timing synchronization interface function. Systemc provides a logical function and a port state calculation environment for the device, and realizes the mutual conversion of digital signals and analog signals between SystemC and SystemC-AMS through signal conversion, thereby realizing system simulation of digital-analog mixed signals on a virtual chip. Compared with the traditional single simulation method, the present invention combines the technical advantages of QEMU, SystemC and SystemC-AMS, reuses the instruction set of QEMU, and utilizes the hardware description language characteristics and simulation scheduler of SystemC and the analog signal processing capability of SystemC-AMS at the same time, which can comprehensively cover the simulation from instruction core to digital circuit to analog circuit, thereby meeting the demand for mixed simulation of digital and analog signals in modern SoC design. At the same time, the chip development mode using the digital-analog mixed simulation method of the present invention can not only improve the accuracy and reliability of on-chip system design, but also accelerate the on-chip system design process and reduce development costs.

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a flow chart of a digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to an embodiment of the present invention.

[0043] Figure 2 It is a schematic diagram of a mixed analog-digital simulator based on QEMU, SystemC and SystemC-AMS according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] A digital-analog hybrid simulation method and simulator based on QEMU, SystemC and SystemC-AMS

[0046] Example

[0047] See also Figure 1 The present invention relates to a digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS, comprising:

[0048] S1: Add external memory access interface memory_read_write and timing synchronization interface systemc_sync in QEMU, and QEMU provides the instruction core.

[0049] S2: Build a virtual CPU device in SystemC and build the hardware interconnection of the on-chip network based on the memory access interface memory_read_write and the timing synchronization interface systemc_sync.

[0050] S3: The systemc model is used in the on-chip device to implement the register interface function and logic signal function, and the systemc-ams model is used to implement the port analog signal function.

[0051] S4: The systemc model is used in off-chip devices to implement logic signal functions, and the systemc-ams model is used to implement port analog signal functions.

[0052] S5: inputting startup parameters into the main program, parsing the startup parameters to obtain device parameters, loading simulation components according to the device parameters and performing pin binding, and establishing a running environment for the device.

[0053] S6: Initialize the operating environment of the instruction core and enter the operating environment of the instruction core.

[0054] S7: Execute a virtual target machine instruction in the operating environment of the instruction core and call the relevant functional interface according to the execution result of the instruction.

[0055] S8: The control right of the main program is handed over to Systemc by calling the timing synchronization interface function systemc_sync to enter the systemc operating environment.

[0056] S9: In the systemc operating environment, the value of the on-chip device register is changed and the logical function status and port status of the device are updated according to the operating instructions of the virtual CPU device.

[0057] S10: exit the systemc operating environment, re-enter the instruction core operating environment, and return to execute step S7 until the virtual system-on-chip simulation is completed.

[0058] Specifically, in this embodiment, QEMU has high-performance processor instruction set simulation capabilities, is responsible for processing and executing CPU instructions, and is used for virtual system-on-chip simulation. A kernel virtual machine (KVM) is used to accelerate virtualization or implement CPU virtualization based on intermediate code.

[0059] Among them, when the processor supports virtualization technology (VMX), QEMU can support different types of operating systems based on KVM, thereby simulating processor cores of different architectures, such as x86, ARM, etc., to support cross-platform development and testing. When the processor does not support VMX, QEMU simulates the CPU instruction set, and when the instruction is executed, QEMU's CPU execution simulation program is simulated on the host CPU.

[0060] In this embodiment, step S1 further includes:

[0061] S11: Cut QEMU and compile it into a dynamic library in the form of instruction core.

[0062] Specifically, this embodiment compiles qemu into a libqemu_arm32.so instruction core dynamic library so that it can be loaded in the main program.

[0063] In this embodiment, step S2 further includes:

[0064] S21: Implementing the register interface function interface and the timing synchronization interface systemc_sync function through the virtual CPU device, and compiling the virtual CPU device into a dynamic library.

[0065] Specifically, the instruction core of this embodiment accesses the register of the on-chip device through the register interface function interface, or accesses the entry or exit of the logic function signal of the memory bus device.

[0066] Specifically, the instruction core of this embodiment accesses the register of the on-chip device through the register interface function interface, and establishes a data transmission channel between the memory bus and the entry or exit of the device logic function signal. The instruction core switches the running environment of the main program to the systemc running environment through the timing synchronization interface systemc_sync. In the systemc running environment, the Systemc coroutine and the Systemc-AMS coroutine will be scheduled due to the change of the value of the device register and the change of the device port status.

[0067] Specifically, in the Systemc coroutine and Systemc-AMS coroutine of this embodiment, the output signal of the device logic function module is converted into an analog signal at the device port by the signal conversion module, and the input signal of the logic function module is converted into a digital signal by the signal conversion module from the analog signal of the device port.

[0068] Specifically, the SystemC of this embodiment has a powerful digital signal simulation capability, which is used to accurately simulate the internal logic functions of the device, including the processing of data flow, the execution of control logic, and the conversion of state machines, thereby ensuring that the hardware design can be thoroughly verified and debugged at the software level.

[0069] Specifically, this embodiment compiles the virtual CPU device into a libcortex_m3.so dynamic library so as to be loaded in the main program.

[0070] In this embodiment, a signal conversion module is used in both the on-chip device and the off-chip device to realize the mutual conversion function between digital signals and analog signals. The signal conversion module converts digital signals into analog signals by calling the sc_to_ams function, and converts analog signals into digital signals by calling the ams_to_sc function.

[0071] Specifically, the on-chip devices and off-chip devices in this embodiment are components of the on-chip system, which integrates a memory controller, rich input / output interfaces, a timer module, and a serial communication interface, etc. The memory controller is used to efficiently manage data access; the rich input / output interfaces are used to ensure that the SoC can flexibly interact with the external environment; the timer module is used to accurately control time events and provide a time reference for the system; the serial communication interface includes an asynchronous receiver / transmitter (UART), a serial peripheral interface (SPI), a two-wire serial interface (I2C), and a controller area network (CAN) bus interface, etc., which provide the SoC with diverse communication capabilities, enabling it to be seamlessly integrated with other devices or systems to achieve high-speed and reliable data transmission.

[0072] In this embodiment, step S3 further includes S31: packaging the on-chip device into a dynamic library.

[0073] Specifically, this embodiment encapsulates the on-chip device into a libstm32_gpio.so dynamic library so as to be loaded in the main program.

[0074] Step S4 also includes S41: packaging the off-chip device into a dynamic library.

[0075] Specifically, this embodiment encapsulates the off-chip device into a libat24c02.so dynamic library so as to be loaded in the main program.

[0076] In this embodiment, the startup parameters include: instruction core configuration information, CPU configuration information, on-chip device configuration information, off-chip device configuration information, and port binding information of on-chip devices and off-chip devices.

[0077] In this embodiment, the loading simulation component in step S5 includes:

[0078] S51: Parse the startup parameters and obtain the device parameters through the config_init function.

[0079] S52: Loading the specified instruction core dynamic library, CPU dynamic library, on-chip device dynamic library and off-chip device dynamic library into the main program according to the device parameters.

[0080] S53: Create a corresponding module instance in the main program.

[0081] In this embodiment, the pin binding in step S5 includes:

[0082] S54: Export the memory access interface memory_read_write and the timing synchronization interface systemc_sync in QEMU.

[0083] S55: Bind the memory access interface memory_read_write and the timing synchronization interface systemc_sync to the corresponding interfaces in the CPU instance through the interface_register function.

[0084] S56: Bind the ports of the on-chip device and the off-chip device through the port_bind function.

[0085] Specifically, this embodiment further includes S57: the main program initializes the systemc operating environment to establish the operating environment of the simulation device.

[0086] In this embodiment, if the virtual target machine instruction is a read IO instruction, the Systemc coroutine is called in the timing synchronization to cause the register to generate a read action.

[0087] Specifically, in the on-chip device of this embodiment, the write action of the register in the systemc operating environment will update the value of the register to the input digital signal of the logic function module, and the output digital signal of the logic function module is converted into an analog signal through the sc_to_ams interface, and the analog signal is used as the driving circuit of the port to change the circuit state of the port.

[0088] If the virtual target machine instruction is a write IO instruction, the Systemc coroutine is called in the timing synchronization to cause the register to generate a write action.

[0089] Specifically, in the on-chip device of this embodiment, the register read action in the systemc operating environment will read the register value. The analog signal received at the port is converted into a digital signal through the ams_to_sc module and input into the logic function module. The output digital signal of the logic function module is determined by the input digital signal, and the register value comes from the output digital signal of the corresponding logic function module.

[0090] Specifically, the signal conversion operation of the off-chip device in this embodiment is consistent with the signal conversion operation of the on-chip device described above, and will not be described in detail here.

[0091] S9: In the systemc operating environment, the value of the on-chip device register is changed and the logical function status and port status of the device are updated according to the operating instructions of the virtual CPU device.

[0092] Specifically, in step S9 of this embodiment, the logical function and port status of the device are updated through a timing synchronization operation in the systemc operating environment, thereby respectively realizing systemc development and systemc-ams development.

[0093] A mixed analog-digital simulator implementation based on QEMU, SystemC and SystemC-AMS

[0094] See also Figure 2 The present invention relates to a digital-analog hybrid simulator based on QEMU, SystemC and SystemC-AMS, which applies the digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS, including a QEMU module, a SystemC module, a SystemC-AMS module and a signal conversion module. The QEMU module establishes a data exchange channel with an on-chip device through a memory bus to provide an instruction core; the SystemC module is used to provide a computing environment for the logical function and port status of the device, and is connected to the SystemC-AMS module through the signal conversion module to convert a digital signal into an analog signal and then output it to the SystemC-AMS module. The SystemC-AMS module is used to realize the port analog signal function, and performs analog-to-digital conversion through the signal conversion module to realize system simulation of digital-analog hybrid signals on a virtual chip.

[0095] Specifically, the instruction core described in this embodiment is used to provide an execution environment for CPU instructions; the QEMU module and the Systemc module call each other through an interface function; the digital signal of the Systemc module and the analog signal of the Systemc-AMS module are converted to each other through a signal conversion module in the operating environment of Systemc.

[0096] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS, characterized in that: include: S1: Add external memory access interface and timing synchronization interface in QEMU, and QEMU provides instruction core; S2: construct a virtual CPU device in SystemC, and construct hardware interconnection of the on-chip network according to the memory access interface and the timing synchronization interface; S3: The systemc model is used in the on-chip device to implement the register interface function and the logic signal function, and the systemc-ams model is used to implement the port analog signal function; S4: Use the systemc model to implement the logic signal function in the off-chip device, and use the systemc-ams model to implement the port analog signal function; S5: inputting startup parameters into the main program, parsing the startup parameters to obtain device parameters, loading simulation components according to the device parameters and performing pin binding, and establishing a running environment for the device; S6: Initializing the operating environment of the instruction core and entering the operating environment of the instruction core; S7: executing a virtual target machine instruction in the running environment of the instruction core and calling a related functional interface according to the execution result of the instruction; S8: handing over the control right of the main program to Systemc by calling the timing synchronization interface function to enter the systemc operating environment; S9: In the systemc operating environment, the value of the on-chip device register is changed, and the logical function state and port state of the device are updated according to the operation instructions of the virtual CPU device; S10: exit the systemc operating environment, re-enter the instruction core operating environment, and return to execute step S7 until the virtual system-on-chip simulation is completed.

2. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 1, characterized in that: In step S1, it also includes: S11: Cut QEMU and compile it into a dynamic library in the form of instruction core.

3. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 1, characterized in that: In step S2, it also includes: S21: Implementing the register interface function interface and the timing synchronization interface function through the virtual CPU device, and compiling the virtual CPU device into a dynamic library.

4. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 1, characterized in that: A signal conversion module is used in both the on-chip device and the off-chip device to realize the mutual conversion function between digital signals and analog signals. The signal conversion module converts digital signals into analog signals by calling the sc_to_ams function, and converts analog signals into digital signals by calling the ams_to_sc function.

5. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 4, characterized in that: Step S3 also includes S31: packaging the on-chip device into a dynamic library; Step S4 also includes S41: packaging the off-chip device into a dynamic library.

6. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to any one of claim 1, characterized in that: The startup parameters include: instruction core configuration information, CPU configuration information, on-chip device configuration information, off-chip device configuration information, and port binding information between on-chip devices and off-chip devices.

7. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to any one of claims 1 to 6, characterized in that: The loading simulation component in step S5 includes: S51: parsing the startup parameters and obtaining the device parameters through the config_init function; S52: loading the specified instruction core dynamic library, CPU dynamic library, on-chip device dynamic library and off-chip device dynamic library into the main program according to the device parameters; S53: Create a corresponding module instance in the main program.

8. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 7, characterized in that: The pin binding in step S5 includes: S54: exporting the memory access interface and timing synchronization interface in QEMU; S55: Binding the memory access interface and the timing synchronization interface to corresponding interfaces in the CPU instance through the interface_register function; S56: Bind the ports of the on-chip device and the off-chip device through the port_bind function.

9. The digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS according to claim 1, characterized in that: If the virtual target machine instruction is a read IO instruction, then the Systemc coroutine is called in the timing synchronization to cause the register to generate a read action; If the virtual target machine instruction is a write IO instruction, the Systemc coroutine is called in the timing synchronization to cause the register to generate a write action.

10. A digital-analog hybrid simulator based on QEMU, SystemC and SystemC-AMS, characterized in that: A digital-analog hybrid simulation method based on QEMU, SystemC and SystemC-AMS as claimed in any one of claims 1 to 9 is applied, comprising: QEMU module, SystemC module, SystemC-AMS module and signal conversion module, the QEMU module establishes a data exchange channel with the on-chip device through the memory bus to provide an instruction core; the SystemC module is used to provide a computing environment for the logical functions and port states of the device, and is connected to the SystemC-AMS module through the signal conversion module to convert digital signals into analog signals and output them to the SystemC-AMS module; the SystemC-AMS module is used to realize the port analog signal function, and performs analog-to-digital conversion through the signal conversion module to realize system simulation of digital-analog mixed signals on a virtual chip.

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