Packaging structure and forming method thereof

Abstract

According to the packaging structure and the forming method thereof provided by the invention, the top of the internal rewiring layer of the bridging chip is not provided with a conductive column, so that the overall thickness of the bridging chip is reduced, the coating thickness of the bridging chip during plastic packaging is further reduced, the thickness of a wiring insertion layer formed by the first plastic packaging layer and the bridging chip assembly is reduced, and the reliability of the packaging structure is improved. And the influence of warping on process operation is avoided. Moreover, according to the forming method, the adhesion layer is arranged on the top surface of the internal rewiring layer of the bridge chip, and the bridge chip is inversely arranged on the top surface of the first carrier plate, so that the embedding of the ultrathin bridge chip is facilitated. The bridging chip is directly connected with the chip packaging assembly through fan-out of the internal rewiring layer, the internal rewiring layer does not need to be connected with the chip packaging assembly through a conductive column, on one hand, the interconnection density is improved, the product application requirement of high-frequency and high-speed signals is better met, on the other hand, the height of other components is reduced, and the cost is reduced. And the distance between other components and the key size can be shortened, so that higher connection density is formed, and miniaturization of products is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] Advanced Packaging is a new type of electronic packaging technology that aims to integrate multiple chips or other electronic components with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Wafer Level Package (WLP) is a packaging process in which most of the process steps are performed on wafers. The demand for wafer level packaging is not only limited by the requirements of smaller package size and height, but also must meet the requirements of simplifying the supply chain, reducing overall costs, and improving overall performance.

[0004] Fan-out wafer-level packaging can be divided into die first and die last according to the process. The die first process simply means putting the chip on first and then doing the wiring (Redistribution layer, referred to as RDL). The die last process means doing the wiring first and then putting the chip on after the unit has passed the test. In the advanced packaging structure using the die last, a bridge chip (Si Bridge Die) needs to be buried in the wiring insertion layer (interposer). The bridge chip is a structure with TSV and DTC functions. Among them, one side of the bridge chip needs to be connected to the corresponding redistribution layer through a conductive column (Stud), and the other side needs to be connected to the corresponding redistribution layer through a bump. The thickness of the bridge chip, the thickness of the conductive column, and the thickness of the bump are superimposed, which makes the thickness of the initial pre-coated structure and the thickness of the wiring insertion layer formed in the end thicker, and the warping is larger, which affects the process operation.

[0005] Therefore, how to reduce the thickness of the wiring insertion layer and thus reduce the warping of the wiring insertion layer has become the focus of current research. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a packaging structure and a method for forming the same, which can reduce the thickness of the wiring insertion layer, thereby reducing the warping of the wiring insertion layer and avoiding the warping of the wiring insertion layer to affect the process operation.

[0007] In order to solve the above problems, the present invention provides a method for forming a packaging structure, which includes: forming a bridge chip component, the bridge chip component includes a bridge chip and an adhesive layer, the bridge chip includes a substrate and an internal redistribution layer covering the top surface of the substrate, the adhesive layer covers the top surface of the internal redistribution layer; flipping the bridge chip on the top surface of a first carrier board, and fixing the bridge chip on the top surface of the first carrier board through the adhesive layer; plastic sealing to form a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip and the top surface of the first carrier board, and the bottom surface of the substrate is exposed to the first plastic sealing layer; forming a bottom interconnection structure on the surface of the first plastic sealing layer away from the first carrier board and the bottom surface of the substrate; removing the first carrier board and the adhesive layer; forming a chip packaging component on the surface of the first plastic sealing layer away from the bottom interconnection structure and the top surface of the internal redistribution layer.

[0008] The embodiment of the present invention also provides a packaging structure, which includes: a bridge chip, including a substrate and an internal redistribution layer covering the top surface of the substrate; a first plastic encapsulation layer, covering the side of the bridge chip, and the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the substrate, and the top surface of the first plastic encapsulation layer is flush with the top surface of the internal redistribution layer; a chip packaging component, arranged on the top surface of the first plastic encapsulation layer and the top surface of the internal redistribution layer, and the internal redistribution layer is in contact with and connected to the chip packaging component; a bottom interconnection structure, arranged on the bottom surface of the first plastic encapsulation layer and the bottom surface of the substrate, and the bridge chip is electrically connected to the bottom interconnection structure

[0009] In the packaging structure and the forming method thereof provided by the embodiment of the present invention, the top of the internal redistribution layer of the bridge chip is not provided with a conductive column, which reduces the overall thickness of the bridge chip, thereby reducing the defects caused by the excessive thickness of the bridge chip in the process technology, for example, reducing the coating thickness when the bridge chip is plastic-sealed, reducing the thickness of the wiring insertion layer composed of the first plastic sealing layer and the bridge chip component, reducing the warping of the wiring insertion layer, and avoiding the warping of the wiring insertion layer to affect the process operation. In addition, the forming method sets the adhesive layer on the top surface of the internal redistribution layer of the bridge chip, and the bridge chip is flip-chip arranged on the top surface of the first carrier board, which is conducive to the embedding of the ultra-thin bridge chip. In the packaging structure, the bridge chip is directly connected to the chip packaging component through the fan-out of the internal redistribution layer, and the internal redistribution layer does not need to be connected to the chip packaging component through the conductive column. On the one hand, the interconnection density is improved to better meet the product application requirements of high-frequency and high-speed signals, and on the other hand, it is conducive to reducing the height of other components, such as reducing the height of the metal column, which can shorten the metal column spacing and key dimensions, thereby forming a higher connection density, which is conducive to the miniaturization of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is a schematic diagram of steps of a method for forming a packaging structure provided by an embodiment of the present invention;

[0012] Figure 2 to Figure 10 is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention;

[0013] Fig.11 It is a schematic diagram of a packaging structure formed by a forming method provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0014] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 is a schematic diagram of the steps of a method for forming a packaging structure provided by an embodiment of the present invention. Figure 1 The formation method comprises: step S10, forming a bridge chip component, the bridge chip component comprises a bridge chip and an adhesive layer, the bridge chip comprises a substrate and an internal redistribution layer covering the top surface of the substrate, the adhesive layer covers the top surface of the internal redistribution layer; step S11, flip-chipping the bridge chip on the top surface of a first carrier, the bridge chip is fixed to the top surface of the first carrier through the adhesive layer; step S12, plastic encapsulation, forming a first plastic encapsulation layer, the first plastic encapsulation layer covers the side surface of the bridge chip and the top surface of the first carrier, and the bottom surface of the substrate is exposed to the first plastic encapsulation layer; step S13, forming a bottom interconnection structure on the surface of the first plastic encapsulation layer away from the first carrier and the bottom surface of the substrate; step S14, removing the first carrier and the adhesive layer; step S15, forming a chip packaging component on the surface of the first plastic encapsulation layer away from the bottom interconnection structure and the top surface of the internal redistribution layer.

[0016] No conductive column is set on the top of the internal redistribution layer of the bridge chip, which reduces the overall thickness of the bridge chip, thereby reducing the defects caused by the bridge chip being too thick in the process technology, such as reducing the coating thickness when the bridge chip is plastic-sealed, reducing the thickness of the wiring insertion layer composed of the first plastic sealing layer and the bridge chip assembly, reducing the warping of the wiring insertion layer, and avoiding the warping of the wiring insertion layer affecting the process operation.

[0017] Furthermore, the forming method arranges the adhesive layer on the top surface of the internal redistribution layer of the bridge chip, and the bridge chip is flip-chip arranged on the top surface of the first carrier board, which is conducive to the embedding of the ultra-thin bridge chip.

[0018] In the packaging structure formed by the formation method, the bridge chip is directly connected to the chip packaging component through the internal redistribution layer fan-out, and the internal redistribution layer does not need to be connected to the chip packaging component through a conductive column. On the one hand, the interconnection density is improved to better meet the product application requirements of high-frequency and high-speed signals. On the other hand, it is beneficial to reduce the height of other components. For example, reducing the height of metal columns can shorten the metal column spacing and critical dimensions, thereby forming a higher connection density, which is beneficial to the miniaturization of products.

[0019] Figure 2 to Figure 10 It is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention.

[0020] See also Figure 1 and Figure 2 , step S10, forming a bridge chip assembly 100, the bridge chip assembly 100 includes a bridge chip 110 and an adhesive layer 120, the bridge chip 110 includes a substrate 111 and an internal redistribution layer 114 covering the top surface of the substrate 111, and the adhesive layer 120 covers the top surface of the internal redistribution layer 114. In some embodiments, the bridge chip 110 also includes a through silicon via 112, the through silicon via 112 passes through the substrate 111, and the internal redistribution layer 114 is in contact with and connected to the top surface of the through silicon via 112. In other embodiments, according to the design requirements of the packaging structure, the bridge chip 110 may not include the through silicon via 112. In the following embodiments, the bridge chip 110 including the through silicon via 112 is taken as an example for explanation.

[0021] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, and the internal redistribution layer 114 covers the top surface of the silicon substrate and is electrically connected to the top surface of the through silicon via 112. The internal redistribution layer 114 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the through silicon via 112, and the other side is used for contact connection with the chip packaging component. The dielectric layer can be a silicon dioxide layer or a silicon nitride layer. In one embodiment, a passivation layer 113 is also provided on the side of the through silicon via 112, and the passivation layer 113 is used to isolate the through silicon via 112 from the substrate 111 to prevent the metal ions in the through silicon via 112 from diffusing into the substrate 111, and the passivation layer 113 includes but is not limited to silicon oxide, silicon nitride and a combination thereof.

[0022] The adhesive layer 120 is made of a material with a certain viscosity, such as acrylic resin. In some embodiments, the adhesive layer 120 is a die attachment film (DAF) having excellent thermal conductivity and adhesion.

[0023] The embodiment of the present invention further provides a method for forming a bridge chip assembly 100. Specifically, the steps of forming the bridge chip assembly 100 include:

[0024] A device wafer is provided, the device wafer comprising a bridge chip 110, the bridge chip 110 comprising an initial substrate and the internal redistribution layer 114 disposed on the top surface of the initial substrate. In this embodiment, the bridge chip 110 further comprises an initial through silicon via extending from the top surface of the initial substrate to the inside of the initial substrate, the top surface of the initial through silicon via is in contact with the internal redistribution layer 114, and the side and bottom surfaces of the initial through silicon via are covered with a passivation layer 113.

[0025] The initial substrate is thinned from the bottom surface of the initial substrate to a set thickness to form the substrate 111. In the present embodiment, this step also includes: thinning the initial through silicon via and the passivation layer 113 to form the through silicon via 112, and the side of the through silicon via 112 is covered with the passivation layer 113. In various embodiments of the present invention, the bridge chip 110 does not include a deep trench capacitor (DTC), then in this step, the substrate 111 and the through silicon via 112 can be directly thinned by grinding and planarization until the substrate 111 and the through silicon via 112 meet the preset height requirements, and even if the metal ions generated during grinding migrate and expand into the substrate 111, they will not cause reliability failure of the packaging structure. At the same time, thinning the substrate 111 by grinding and planarization can provide a flat surface for subsequent processes.

[0026] The top surface of the internal redistribution layer 114 is covered with the adhesive layer 120, and the device wafer is cut to form a plurality of independent bridge chip components 100. The adhesive layer 120 can be covered on the top surface of the internal redistribution layer 114 by coating or other processes.

[0027] See also Figure 1 and Figure 3 Step S11 , the bridge chip 110 is flip-chip mounted on the top surface of a first carrier 300 , and the bridge chip 110 is fixed on the top surface of the first carrier 300 through the adhesive layer 120 . Specifically, the internal redistribution layer 114 is fixed on the top surface of the first carrier 300 through the adhesive layer 120 .

[0028] In some embodiments, the first carrier 300 is a glass substrate, and a temporary bonding layer 301 and a buffer metal layer 302 are formed on the surface of the first carrier 300. The bridge chip 110 is disposed on the buffer metal layer 302 by a die attach or die bonding (DA) process.

[0029] In some embodiments, this step also includes the step of forming a metal column 130. Specifically, this step further includes: forming a metal column 130 on the top surface of the first carrier 300, and the metal column 130 can be formed by an electroplating process, which can better meet the product application requirements of high-frequency and high-speed signals. The bridge chip 110 is flip-chip mounted on the top surface of the first carrier 300, and the top surface of the metal column 130 is higher than the bottom surface of the substrate 111.

[0030] In the formation method provided by the embodiment of the present invention, the top of the internal redistribution layer 114 of the bridge chip 110 is not provided with a conductive column, which reduces the overall thickness of the bridge chip 110, thereby reducing the initial height of the metal column 130, and can shorten the spacing and critical dimensions of the metal column 130, thereby forming a higher connection density, which is conducive to the miniaturization of the product. Specifically, the spacing and critical dimensions of the metal column 130 are related to the height of the metal column 130. The higher the height of the metal column 130, the larger the spacing and critical dimensions of the metal column 130. In the formation method provided by the embodiment of the present invention, the bridge chip 110 does not need to be provided with a conductive column, and has been thinned to the required thickness. Therefore, when the metal column 130 is provided on the surface of the carrier, it is not necessary to form a higher metal column 130. It is only necessary to form a metal column 130 slightly higher than the bridge chip 110. The initial height of the metal column 130 is reduced, and the spacing and critical dimensions of the metal column 130 can be shortened, thereby forming a higher connection density, which is conducive to the miniaturization of the product.

[0031] See also Figure 1 and Figure 4 Step S12: plastic encapsulation to form a first plastic encapsulation layer 140, wherein the first plastic encapsulation layer 140 covers the side surface of the bridge chip 110 and the top surface of the first carrier 300, and the bottom surface of the substrate 111 is exposed to the first plastic encapsulation layer 140. In this step, the first plastic encapsulation layer 140 also covers the side surface of the metal column 130. The surface of the first plastic encapsulation layer 140 facing away from the first carrier 300 is flush with the surface of the bridge chip assembly 100 facing away from the first carrier 300. Specifically, the surface of the first plastic encapsulation layer 140 facing away from the first carrier 300 is flush with the bottom surface of the substrate 111.

[0032] This step further includes: forming an initial plastic encapsulation layer, the initial plastic encapsulation layer covers the bridge chip 110, the metal column 130 and the top surface of the first carrier 300; thinning the initial plastic encapsulation layer and the metal column 130 until the bottom surface of the substrate 111 is exposed, and the remaining initial plastic encapsulation layer serves as the first plastic encapsulation layer 140. The step of thinning the initial plastic encapsulation layer and the metal column 130 further includes: preliminarily thinning the initial plastic encapsulation layer to expose the metal column 130; etching the metal column 130 to a preset height; continuing to thin the initial plastic encapsulation layer to form the first plastic encapsulation layer 140, the surface of the first plastic encapsulation layer 140 is flush with the surface of the metal column 130 and the bottom surface of the substrate 111, and the surface of the metal column 130 and the bottom surface of the substrate 111 are not covered by the first plastic encapsulation layer 140. In this step, the metal column 130 is etched after the initial plastic encapsulation layer is initially thinned. On the one hand, a preset height can be formed, and on the other hand, the oxide layer on the surface of the metal column 130 can be removed to expose the substrate and reduce the contact resistance between the metal column 130 and other device layers (such as the top redistribution layer).

[0033] See also Figure 1 and Figure 5 Step S13, forming a bottom interconnection structure 150 on the surface of the first plastic encapsulation layer 140 away from the first carrier 300 and the bottom surface of the substrate 111. In this embodiment, the bottom interconnection structure 150 is electrically connected to the through silicon via 112 and the metal column 130.

[0034] In one embodiment, the bottom interconnect structure 150 includes a bottom redistribution layer 151 and a conductive connection structure 152, and the step further includes:

[0035] A bottom redistribution layer 151 is formed on the surface of the first plastic encapsulation layer 140 away from the first carrier 300 and the bottom surface of the substrate 111, and the bottom redistribution layer 151 includes a dielectric layer and a plating circuit formed by sputtering and / or electroplating in the dielectric layer. Specifically, a dielectric layer is formed on the surface of the first plastic encapsulation layer 140 away from the first carrier 300 and the bottom surface of the substrate 111; a through hole is formed on the dielectric layer to expose the bottom surface of the through silicon via 112 and the bottom surface of the metal column 130; and a plating circuit is formed by sputtering and / or electroplating in the through hole, and the plating circuit is in contact with and connected to the through silicon via 112 and the metal column 130. In this step, the plating circuit is formed by sputtering and electroplating, and tin (Sn) welding is not required, which eliminates the aging problem of tin welding in the process processing, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding point, which improves the reliability of the packaging structure, and the sputtering and electroplating are coordinated to take into account both efficiency and cost.

[0036] A conductive connection structure 152 is formed on the bottom surface of the bottom redistribution layer 151, and the conductive connection structure 152 and the bottom redistribution layer 151 together serve as the bottom interconnect structure 150. In some embodiments, the conductive connection structure 152 includes but is not limited to a controllably collapsed chip connection bump (C4).

[0037] Optionally, see Figure 6 In some embodiments, after the step of forming a bottom interconnect structure 150 on the surface of the first molding layer 140 facing away from the first carrier 300 and the bottom surface of the substrate 111 , the step includes: bonding the bottom interconnect structure 150 to a second carrier 600 .

[0038] The second carrier 600 includes but is not limited to a glass carrier. Further, the step of bonding the bottom interconnect structure 150 to the second carrier 600 includes: forming a cover layer 601, the cover layer 601 covers the bottom interconnect structure 150; using the surface of the second carrier 600 and the surface of the cover layer 601 as bonding surfaces, bonding the second carrier 600 to the cover layer 601.

[0039] See also Figure 1 and Figure 7 , step S14, removing the first carrier plate 300 and the adhesive layer 120. When performing this step, the second carrier plate 600 plays a supporting role.

[0040] In this step, a suitable debonding process is selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc., to remove the first carrier 300. After removing the first carrier 300, the temporary bonding layer 301 and the buffer metal layer 302 on the surface of the first carrier 300 are also removed by etching. In this step, according to the material characteristics and molecular system of the adhesion layer 120, a suitable process is selected to remove the adhesion layer 120. For example, the adhesion layer 120 can be removed by ultraviolet irradiation, dry etching or wet etching, or by using a high-viscosity material film layer for adhesion.

[0041] After removing the adhesive layer 120, the top surface of the internal redistribution layer 114 is lower than the top surface of the first plastic encapsulation layer 140, forming a groove, and the first plastic encapsulation layer 140 protrudes from the top surface of the internal redistribution layer 114. For further information, please refer to Figure 8, thinning the first plastic encapsulation layer 140 so that the top surface of the first plastic encapsulation layer 140 is flush with the top surface of the internal redistribution layer 114. In some embodiments, a chemical mechanical polishing process (CMP) is used to thin the first plastic encapsulation layer 140. In the step of removing the adhesion layer 120, if a dry etching process is used, the surface of the first plastic encapsulation layer 140 will be too rough. Therefore, when the chemical mechanical polishing process is used to thin the first plastic encapsulation layer 140, the bottom surface of the first plastic encapsulation layer 140 can be polished to form a surface with a roughness that meets the requirements. In one embodiment, in the step of thinning the first plastic encapsulation layer 140 by using the chemical mechanical polishing process, the metal column 130 is etched so that the surface of the metal column 130 away from the second carrier 600 is flush with the surface of the first plastic encapsulation layer 140 away from the second carrier 600.

[0042] See also Figure 1 and Fig. 9 Step S15, forming a chip packaging component 160 on the surface of the first plastic packaging layer 140 away from the bottom interconnect structure 150 and the top surface of the internal redistribution layer 114. In this embodiment, the chip packaging component 160 is in contact with the internal redistribution layer 114 and the metal pillar 130.

[0043] In one embodiment, the chip package assembly 160 includes a top redistribution layer 161, a top pad 162, and a top device 163. The steps of forming the chip package assembly 160 on the surface of the first plastic encapsulation layer 140 away from the bottom interconnect structure 150 and the top surface of the internal redistribution layer 114 include:

[0044] A top redistribution layer 161 is formed on the surface of the first plastic encapsulation layer 140 away from the bottom interconnect structure 150 and on the top surface of the internal redistribution layer 114. The top redistribution layer 161 includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with the internal redistribution layer 114. In some embodiments, the material of the dielectric layer may be a polymer material such as polybutylene styrene (PBO) and polyimide (PI). The conductive circuit is formed by an electroplating process, and there is no need to use tin (Sn) welding, which eliminates the aging problem of tin welding during the process processing, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding points, thereby improving the reliability of the packaging structure. In one embodiment, the top redistribution layer 161 can be formed by a photolithography process and an electroplating process, for example, the top redistribution layer 161 is formed by adding layers through processes such as gluing, exposure, development, electroplating, and degumming.

[0045] A top pad 162 is formed on the top surface of the top redistribution layer 161, and the top pad 162 is electrically connected to the top redistribution layer 161. In one embodiment, the top pad 162 is a micro pad (μPad), and the top pad 162 can be formed by photolithography and electroplating.

[0046] A top device 163 is disposed on the top redistribution layer 161, and the top device 163 is welded to the top pad 162. In some embodiments, the top device 163 is flip-chip mounted on the top redistribution layer 161. The top device 163 is welded to the top pad 162 via a conductive bump. The top device 163 may be a SOC device or the like.

[0047] The second plastic encapsulation layer 164 is formed by plastic encapsulation, and the second plastic encapsulation layer 164 covers the top device 163. In some embodiments, before the top device 163 is plastic encapsulated, a filling layer 165 is formed between the bottom of the top device 163 and the top redistribution layer 161. The filling layer 165 is used to protect the conductive structure of the top device 163 and the top pad 162. The second plastic encapsulation layer 164 covers the top device 163, the surface of the top redistribution layer 161, and the surface of the filling layer 165.

[0048] Optionally, the forming method further comprises: Fig.10 , thinning the second plastic packaging layer 164 to expose the top surface of the top device 163, which is useful for heat dissipation of the device.

[0049] For further information, see Fig.10 After forming the chip package assembly 160, the second carrier 600 is debonded. In this step, after debonding the second carrier 600, the cover layer 601 is also removed, and the bottom interconnect structure 150 is exposed. In some embodiments, a suitable debonding process can be selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc.

[0050] Furthermore, after the second carrier 600 is debonded, singulation is performed to form a plurality of independent package structures, each of which may include a plurality of the bridge chip components 100 and a plurality of the top devices 163 .

[0051] In the above embodiment, the bottom surface of the through silicon via 112 is not provided with a bottom pad, but is directly connected to the bottom interconnection structure 150. In another embodiment, the bridge chip 110 also includes a bottom pad, which is provided on the bottom surface of the through silicon via 112, and the through silicon via 112 is connected to the bottom interconnection structure 150 through the bottom pad. In one embodiment, the bottom pad is a micro pad (μPad). The bottom pad is provided on the bottom surface of the through silicon via 112, so that the thickness of the first plastic sealing layer 140 covering the bridge chip 110 can be reduced in the packaging structure using the bridge chip assembly 100, thereby reducing the warping of the part structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad is larger than the cross-sectional area of ​​the through silicon via 112, so as to ensure that the through silicon via 112 can be fully in contact with the bottom pad, reduce the contact resistance, and thus make the delay of the electrical signal smaller.

[0052] Specifically, see Fig.11 , which is a schematic diagram of a packaging structure formed by a forming method provided in another embodiment of the present invention. In this embodiment, in the process of forming the bridge chip assembly 100, after the step of thinning the initial silicon via and the passivation layer 113 to form the silicon via 112, the forming method further includes: forming a bottom pad 170 on the bottom surface of the silicon via 112, the bottom pad 170 is arranged on the bottom surface of the silicon via 112, and is electrically connected to the silicon via 112. After the step of forming the first plastic encapsulation layer 140, the bottom pad 170 is also exposed to the first plastic encapsulation layer 140. After the step of forming the bottom interconnect structure 150, the bottom interconnect structure 150 is electrically connected to the bottom pad 170.

[0053] In the method for forming the packaging structure provided in the embodiment of the present invention, the defects caused by the excessive thickness of the bridge chip 110 in the process technology are reduced, the thickness of the wiring insertion layer composed of the first plastic encapsulation layer 140 and the bridge chip assembly 100 is reduced, the warping of the wiring insertion layer is reduced, and the warping of the wiring insertion layer is avoided to affect the process operation. In addition, the formation method sets the adhesive layer 120 on the top surface of the internal redistribution layer 114 of the bridge chip 110, and the bridge chip 110 is flip-chip arranged on the top surface of the first carrier 300, which is conducive to the embedding of the ultra-thin bridge chip 110. In the packaging structure formed by the formation method, the bridge chip 110 is directly connected to the chip packaging assembly 160 through the fan-out of the internal redistribution layer 114, which improves the interconnection density on the one hand and better meets the product application requirements of high-frequency and high-speed signals, and on the other hand, it is conducive to reducing the height of other components, thereby forming a higher connection density, which is conducive to the miniaturization of products.

[0054] Based on the same inventive concept, an embodiment of the present invention also provides a packaging structure formed by the above-mentioned forming method. Figure 2 to Figure 10 The packaging structure includes: a bridge chip 110, including a substrate 111 and an internal redistribution layer 114 covering the top surface of the substrate 111; a first plastic encapsulation layer 140, covering the side of the bridge chip 110, and the bottom surface of the first plastic encapsulation layer 140 is flush with the bottom surface of the substrate 111, and the top surface of the first plastic encapsulation layer 140 is flush with the top surface of the internal redistribution layer 114; a chip packaging component 160, arranged on the top surface of the first plastic encapsulation layer 140 and the top surface of the internal redistribution layer 114, and the internal redistribution layer 114 is in contact with the chip packaging component 160; a bottom interconnection structure 150, arranged on the bottom surface of the first plastic encapsulation layer 140 and the bottom surface of the substrate 111, and the bridge chip 110 is electrically connected to the bottom interconnection structure 150.

[0055] In the packaging structure provided by the embodiment of the present invention, the top of the internal redistribution layer 114 of the bridge chip 110 is not provided with a conductive column, which reduces the overall thickness of the bridge chip 110, thereby reducing the defects caused by the bridge chip 110 being too thick in the process technology, for example, reducing the coating thickness when the bridge chip 110 is plastic-sealed, reducing the thickness of the wiring insertion layer composed of the first plastic sealing layer 140 and the bridge chip component 100, reducing the warping of the wiring insertion layer, and avoiding the warping of the wiring insertion layer to affect the process operation. The bridge chip 110 is fanned out through the internal redistribution layer 114 and directly connected to the chip packaging component 160. The internal redistribution layer 114 does not need to be connected to the chip packaging component 160 through a conductive column. On the one hand, the interconnection density is improved to better meet the product application requirements of high-frequency and high-speed signals. On the other hand, it is conducive to reducing the height of other components, such as reducing the height of the metal column 130, which can shorten the spacing and critical dimensions of the metal column 130, thereby forming a higher connection density, which is conducive to the miniaturization of the product.

[0056] In one embodiment, the internal redistribution layer 114 includes a dielectric layer and a conductive circuit in the dielectric layer. One side of the conductive circuit is electrically connected to the top surface of the through silicon via 112 , and the other side of the conductive circuit is electrically connected to the chip packaging component 160 .

[0057] In one embodiment, the bridge chip 110 further includes a through silicon via 112, the through silicon via 112 penetrates the substrate 111, a passivation layer 113 is disposed on the side of the through silicon via 112, the internal redistribution layer 114 is in contact with and connected to the top surface of the through silicon via 112, and the bottom interconnect structure 150 is electrically connected to the through silicon via 112. The passivation layer 113 is used to isolate the through silicon via 112 from the substrate 111 to prevent metal ions in the through silicon via 112 from diffusing into the substrate 111.

[0058] In one embodiment, the packaging structure further includes a metal column 130, the metal column 130 penetrates the first plastic packaging layer 140, and the bottom surface of the metal column 130 is flush with the bottom surface of the first plastic packaging layer 140, and the top surface of the metal column 130 is flush with the top surface of the first plastic packaging layer 140. The top surface of the metal column 130 is electrically connected to the chip packaging component 160, and the bottom surface of the metal column 130 is electrically connected to the bottom interconnection structure 150. The packaging structure may include a plurality of the bridge chips 110 and a plurality of the metal columns 130, and the metal columns 130 are distributed around the bridge chip 110 and between two adjacent bridge chips 110.

[0059] In one embodiment, the chip packaging component 160 includes: a top redistribution layer 161, which is arranged on the top surface of the first plastic packaging layer 140 and the top surface of the internal redistribution layer 114, and the top redistribution layer 161 includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with and connected to the internal redistribution layer 114; a top solder pad 162, which is arranged on the top redistribution layer 161 and is electrically connected to the top redistribution layer 161; a top device 163, which is arranged on the top redistribution layer 161, and the top device 163 is welded to the top solder pad 162; and a second plastic packaging layer 164, which covers the top device 163.

[0060] In one embodiment, the top redistribution layer 161 includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with the bridge chip assembly 100. The material of the dielectric layer can be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI). The conductive circuit refers to a wire formed by an electroplating process. The conductive circuit is formed by an electroplating process, and there is no need to use tin (Sn) welding, which eliminates the aging problem of tin welding during process processing, and there is no problem of voids and cracks at the welding points, thereby improving the reliability of the packaging structure. The top device 163 can be flip-chip arranged on the top redistribution layer 161 and welded to the top pad 162. The top device 163 can be a SOC device, etc. In some embodiments, the packaging structure also includes a filling layer 165 filled between the bottom of the top device 163 and the top redistribution layer 161, and the filling layer 165 is used to protect the conductive structure of the top device 163 and the top pad 162. The second plastic encapsulation layer 164 covers the top device 163 , the surface of the top redistribution layer 161 , and the surface of the filling layer 165 .

[0061] In one embodiment, the bottom interconnect structure 150 also includes: a bottom redistribution layer 151, the bottom redistribution layer 151 includes a dielectric layer and an electroplating circuit located in the dielectric layer; a conductive connection structure 152, which is arranged on the bottom surface of the bottom redistribution layer 151 and is electrically connected to the bottom redistribution layer 151.

[0062] In some embodiments, the bottom redistribution layer 151 includes a dielectric layer and an electroplating circuit located in the dielectric layer, and the electroplating circuit is in contact with the silicon through hole 112 of the bridge chip 110 and the metal column 130. The material of the dielectric layer can be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI) to further relieve stress. The electroplating circuit refers to a bump formed by an electroplating process. In one embodiment, the electroplating circuit is formed on the bottom surface of the silicon through hole 112 and the bottom surface of the metal column 130 by an electroplating process, without the need for tin (Sn) welding, eliminating the aging problem of tin welding during process processing, and there is no problem of voids (Void) and cracks (Crack) appearing at the welding point, thereby improving the reliability of the packaging structure. The conductive connection structure 152 is arranged on the bottom surface of the bottom redistribution layer 151. In some embodiments, the conductive connection structure 152 includes but is not limited to a controllable collapse chip connection bump (C4).

[0063] In one embodiment, see Fig.11 , the bridge chip 110 further includes a bottom pad 170, the bottom pad 170 is arranged on the bottom surface of the through silicon via 112, the bottom surface of the first plastic encapsulation layer 140 is flush with the bottom surface of the bottom pad 170, and the bottom interconnection structure 150 is electrically connected to the bottom pad 170. In one embodiment, the bottom pad 170 is a micro pad (μPad). The bottom pad 170 is arranged on the bottom surface of the through silicon via 112, so that the thickness of the first plastic encapsulation layer 140 covering the bridge chip component 100 can be reduced in the packaging structure using the bridge chip component 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 170 is larger than the cross-sectional area of ​​the through silicon via 112, so as to ensure that the through silicon via 112 can be fully in contact with the bottom pad 170, reduce the contact resistance, and thus make the delay of the electrical signal smaller.

[0064] In the packaging structure provided by the embodiment of the present invention, the overall thickness of the bridge chip 110 is reduced, thereby reducing the defects caused by the bridge chip 110 being too thick in the process. The bridge chip 110 is directly connected to the chip packaging component 160 through the internal redistribution layer 114 fan-out, which on the one hand improves the interconnection density and better meets the product application requirements of high-frequency and high-speed signals, and on the other hand helps to reduce the height of other components, thereby forming a higher connection density, which is conducive to the miniaturization of products.

[0065] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0066] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a packaging structure, characterized in that: include: Forming a bridge chip assembly, the bridge chip assembly comprising a bridge chip and an adhesive layer, the bridge chip comprising a substrate and an internal redistribution layer covering a top surface of the substrate, the adhesive layer covering a top surface of the internal redistribution layer; The bridge chip is flip-chip mounted on a top surface of a first carrier board, and the bridge chip is fixed on the top surface of the first carrier board through the adhesive layer; Plastic encapsulation to form a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the side surface of the bridge chip and the top surface of the first carrier board, and the bottom surface of the substrate is exposed to the first plastic encapsulation layer; forming a bottom interconnection structure on a surface of the first plastic packaging layer facing away from the first carrier board and a bottom surface of the substrate; removing the first carrier plate and the adhesive layer; A chip packaging component is formed on the surface of the first plastic packaging layer away from the bottom interconnection structure and the top surface of the internal redistribution layer.

2. The method for forming a packaging structure according to claim 1, characterized in that: The steps of forming the bridge chip assembly further include: Providing a device wafer, the device wafer comprising a bridge chip, the bridge chip comprising an initial substrate and the internal redistribution layer arranged on the top surface of the initial substrate; Thinning the initial substrate from the bottom surface of the initial substrate to a set thickness to form the substrate; Covering the adhesion layer on the top surface of the internal redistribution layer; The device wafer is cut into pieces to form a plurality of independent bridge chip components.

3. The method for forming a packaging structure according to claim 2, wherein: In the step of providing the device wafer, the bridge chip further comprises an initial through silicon via extending from the top surface of the initial substrate to the interior of the initial substrate, the top surface of the initial through silicon via is in contact with the internal redistribution layer, and the side and bottom surfaces of the initial through silicon via are covered with a passivation layer; The step of thinning the initial substrate from the bottom surface of the initial substrate to a set thickness further includes: thinning the initial through silicon via and the passivation layer to form a through silicon via, wherein the through silicon via penetrates the substrate and the side surface of the through silicon via is covered with the passivation layer; In the step of covering the adhesion layer with the top surface of the internal redistribution layer, the adhesion layer also covers the bottom surface of the through silicon via.

4. The method for forming a packaging structure according to claim 3, characterized in that: After the step of thinning the initial substrate to a set thickness from the bottom surface of the initial substrate, the method also includes: forming a bottom pad on the bottom surface of the through silicon via; after the step of forming the first plastic encapsulation layer, the bottom pad is also exposed to the first plastic encapsulation layer; after the step of forming the bottom interconnection structure, the bottom interconnection structure is electrically connected to the bottom pad.

5. The method for forming a packaging structure according to claim 1, wherein: The step of flip-chipping the bridge chip on the top surface of a first carrier further includes: Forming a metal column on the top surface of the first carrier; flip-chipping the bridge chip on the top surface of the first carrier, wherein the top surface of the metal column is higher than the bottom surface of the substrate; The step of forming a first plastic encapsulation layer further comprises: Plastic encapsulation to form an initial plastic encapsulation layer, wherein the initial plastic encapsulation layer covers the bridge chip, the metal column and the top surface of the first carrier board; The initial plastic encapsulation layer and the metal column are thinned until the bottom surface of the substrate is exposed, and the remaining initial plastic encapsulation layer serves as the first plastic encapsulation layer.

6. The method for forming a packaging structure according to claim 1, characterized in that: The step of removing the first carrier and the adhesive layer further includes: removing the first carrier and the adhesive layer, the first plastic sealing layer protruding from the substrate; thinning the first plastic sealing layer so that the bottom surface of the first plastic sealing layer is flush with the bottom surface of the substrate.

7. The method for forming a packaging structure according to claim 1, characterized in that: The step of forming a bottom interconnection structure on the surface of the first plastic encapsulation layer facing away from the first carrier and the bottom surface of the substrate further comprises: The surface of the first plastic packaging layer facing away from the first carrier board and the bottom surface of the substrate forms a bottom redistribution layer, and the bottom redistribution layer includes a dielectric layer and an electroplating circuit formed by sputtering and / or electroplating in the dielectric layer; A conductive connection structure is formed on the bottom surface of the bottom redistribution layer, and the conductive connection structure and the bottom redistribution layer together serve as the bottom interconnection structure.

8. The method for forming a packaging structure according to claim 1, wherein: After the step of forming a bottom interconnection structure on the surface of the first plastic encapsulation layer away from the first carrier and the bottom surface of the substrate, the method includes: bonding the bottom interconnection structure to a second carrier; and after forming the chip packaging assembly, debonding the second carrier.

9. The method for forming a packaging structure according to claim 1, wherein: The step of forming a chip packaging component on the surface of the first plastic packaging layer away from the bottom interconnect structure and the top surface of the internal redistribution layer further includes: A top redistribution layer is formed on the surface of the first plastic packaging layer away from the bottom interconnect structure and on the top surface of the internal redistribution layer, wherein the top redistribution layer includes a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with and connected to the internal redistribution layer; forming a top pad on a top surface of the top redistribution layer, wherein the top pad is electrically connected to the top redistribution layer; Disposing a top device on the top redistribution layer, wherein the top device is welded to the top pad; Plastic encapsulation is performed to form a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the top device.

10. A packaging structure, characterized in that: include: A bridge chip, comprising a substrate and an internal redistribution layer covering a top surface of the substrate; A first plastic encapsulation layer covers the side surface of the bridge chip, wherein the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the substrate, and the top surface of the first plastic encapsulation layer is flush with the top surface of the internal redistribution layer; A chip packaging component is arranged on the top surface of the first plastic packaging layer and the top surface of the internal redistribution layer, and the internal redistribution layer is in contact and connected with the chip packaging component; The bottom interconnection structure is arranged on the bottom surface of the first plastic packaging layer and the bottom surface of the substrate, and the bridge chip is electrically connected to the bottom interconnection structure.

11. The packaging structure according to claim 10, characterized in that: The bridge chip further comprises a through silicon via, the through silicon via penetrates the substrate, a passivation layer is arranged on the side of the through silicon via, and the internal redistribution layer is in contact and connected with the top surface of the through silicon via.

12. The packaging structure according to claim 11, characterized in that: The bridge chip further includes a bottom pad, which is disposed on the bottom surface of the through silicon via, the bottom surface of the first plastic encapsulation layer is flush with the bottom surface of the bottom pad, and the bottom interconnection structure is electrically connected to the bottom pad.

13. The packaging structure according to claim 10, characterized in that: The packaging structure further includes a metal column, which penetrates the first plastic packaging layer, and the bottom surface of the metal column is flush with the bottom surface of the first plastic packaging layer, and the top surface of the metal column is flush with the top surface of the first plastic packaging layer.

14. The packaging structure according to claim 10, characterized in that: The chip packaging assembly comprises: a top redistribution layer, which is arranged on the top surface of the first plastic packaging layer and the top surface of the internal redistribution layer, the top redistribution layer comprises a dielectric layer and a conductive circuit located in the dielectric layer, and the conductive circuit is in contact with and connected to the internal redistribution layer; A top pad is disposed on the top redistribution layer and is electrically connected to the top redistribution layer; a top device is disposed on the top redistribution layer, and the top device is welded to the top pad; The second plastic packaging layer covers the top device.

15. The packaging structure according to claim 10, characterized in that: The bottom interconnect structure further comprises: a bottom redistribution layer, the bottom redistribution layer comprising a dielectric layer and an electroplating line located in the dielectric layer; The conductive connection structure is arranged on the bottom surface of the bottom redistribution layer and is electrically connected to the bottom redistribution layer.

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