Multi-Point CTS-based chip clock design optimization method

Abstract

The invention discloses a Multi-Point CTS-based chip clock design optimization method, and relates to the technical field of chip clock design optimization, and the method comprises the following steps: using a hardware description language VHDL to compile RTL codes describing circuit behaviors, using a DC EDA tool of Synopsys to convert the RTL codes into a logic netlist, using a standard algorithm H-Tree to construct a preliminary clock tree structure layout, and using the standard algorithm H-Tree to construct the logic netlist. Obtaining a primary clock tree topological graph; a Multi-Point CTS method is introduced, a plurality of clock sources are adopted to optimize the initial clock tree topological graph, and an optimized clock tree topological graph is obtained; a static time sequence analysis tool PrimeTime is adopted to analyze the optimized clock tree topological graph, and a time sequence analysis result is obtained; identifying the longest path from a clock source to a register in the optimized clock tree topological graph according to a time sequence analysis result, marking the longest path as a critical path, and finding the optimal position for placing a buffer in the critical path by adopting a heuristic search algorithm; and calculating a difference value between the actual delay and the maximum allowable delay of the optimized clock tree topological graph by using PrimeTime again.

Description

Technical Field

[0001] The invention relates to the technical field of chip clock design optimization, and in particular to a chip clock design optimization method based on Multi-Point CTS. Background Art

[0002] Chip clock design optimization refers to a series of processes and technologies that ensure that the clock signal can be efficiently and reliably transmitted to all logic units that need it, while meeting the design timing requirements, reducing power consumption, reducing area occupancy, and improving manufacturability through the design, implementation, and verification of the clock distribution network during the chip design phase.

[0003] In the prior art, there may be time differences when the clock signal reaches different registers, which is the so-called clock skew. This phenomenon will cause synchronization errors or increase the minimum clock cycle of the system, thereby affecting system performance. In large-scale integrated circuits, due to factors such as path delays and process variations, setup time and hold time violations will occur, affecting the functional correctness of the circuit. At the same time, on high-density integrated circuits, wiring resources are limited, which can easily cause congestion, thereby affecting the quality and efficiency of the clock distribution network. Summary of the invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a chip clock design optimization method based on Multi-PointCTS to solve the problem that limited wiring resources on high-density integrated circuits easily cause congestion, thereby affecting the quality and efficiency of the clock distribution network.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In the first aspect, the present invention provides a chip clock design optimization method based on Multi-Point CTS, which includes using the hardware description language VHDL to write RTL code describing circuit behavior, using Synopsys's DC EDA tool to convert the RTL code into a logic netlist, using the standard algorithm H-Tree to build a preliminary clock tree structure layout, and obtaining a preliminary clock tree topology diagram; introducing Multi-Point The CTS method uses multiple clock sources to optimize the preliminary clock tree topology diagram to obtain the optimized clock tree topology diagram; the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis results; according to the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology diagram is identified and marked as the critical path, and the heuristic search algorithm is used to find the best position to place the buffer in the critical path; PrimeTime is used again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology diagram, and the position of the buffer is adjusted according to the difference value to update the clock tree topology diagram; the power consumption of the updated clock tree topology diagram is evaluated to obtain the power consumption sensitivity analysis results, and the high power consumption buffer is replaced with a low power consumption buffer according to the power consumption sensitivity analysis results; the DRC tool Mentor's Calibre is used to identify and correct the physical rules violated in the updated clock tree topology diagram, timing analysis results, and power consumption sensitivity analysis results, and generate a verification report for the chip clock design optimization.

[0008] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the RTL code describing the circuit behavior is written using the hardware description language VHDL, the RTL code is converted into a logic netlist using the DCEDA tool of Synopsys, and a preliminary clock tree structure layout is constructed using the standard algorithm H-Tree to obtain a preliminary clock tree topology diagram. The specific steps include: using the hardware description language VHDL to write a behavioral level description of the circuit to obtain the VHDL RTL code; importing the VHDL RTL code into Synopsys DC EDA, performing logic synthesis, converting the RTL code into a logic netlist based on a standard cell library, saving the synthesized design in a logic netlist format, and using PrimeTime to identify all registers that require clock signals, and determine the clock source and register position; according to the clock source and register position, calculating the chip center point, the expression is:

[0009]

[0010] Where W is the width, H is the height, C is the center point, and the coordinates of the center point C are C(C x ,C y); Set the center point as the starting point of the clock tree H-Tree, and place the trunk buffer from the clock source to the center point as the root node of the H-Tree, and set the location of the clock source to CLK (CLK x ,CLK y ), find the best path from CLK to C to place the trunk buffer, and calculate the distance from the clock source to the center point. The expression is:

[0011]

[0012] Among them, d CLK-C is the distance from the clock source to the center of the chip, C x and C y are the coordinates of the chip center point on the x-axis and y-axis, CLK x and CLK y are the coordinates of the clock source on the x-axis and y-axis respectively; starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree, and a buffer is placed in the center of each partition as a new node of the branch. The expression is;

[0013]

[0014]

[0015] P y (t i )=(1-t i ) · CLK y +t i ·C y ;

[0016] Where N is the number of buffers planned to be placed, Δd is the interval between buffers, and t i is the relative position of each buffer i on the path, P x (t i ) is the coordinate of the i-th buffer on the x-axis, P y (t i ) is the coordinate of the i-th buffer on the y-axis;

[0017] Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree construction is completed; after the clock tree H-Tree construction is completed, check to confirm that no registers are missed and all clock paths are correctly connected; save the constructed clock tree in a logic netlist format to generate a preliminary clock tree topology diagram.

[0018] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the Multi-Point CTS method is introduced, and multiple clock sources are used to optimize the preliminary clock tree topology diagram to obtain the optimized clock tree topology diagram. The specific steps are: selecting the multi-point CTS strategy based on regional division and dynamic buffer insertion as the priority solution; according to the preliminary clock tree topology diagram, the entire chip is divided into several sub-areas, each sub-area will be configured with one or more clock sources, and the optimal clock source position of each sub-area is determined, and the expression is:

[0019]

[0020] Among them, S eff is the effectiveness index of the clock source, A and B are the starting point and end point of the integration interval, ρ(r) is the load density function at distance r, dT(r) is the clock transmission delay differential at distance r, N is the number of clock sources, and f i is the frequency of the ith clock source; select the maximum value S eff , as the best clock source location for each sub-area, and obtain the optimized clock tree topology.

[0021] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis result, and the specific steps are: using the static timing analysis STA in PrimeTime, defining the delay calculation expression, and calculating all clock path delays in the entire clock tree, the expression is:

[0022] D elem =f(T input ,T output ,C load );

[0023] Among them, D elem is the delay of a single component or network segment, T input is the arrival time of the input signal, T output is the departure time of the output signal, C load is the load capacitance, f is the delay calculation function; then the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is:

[0024]

[0025] Among them, T arrival (P,i) represents the arrival time of the input signal at the i-th node on the clock path P, T arrival(P,i-1) is the arrival time of the input signal of the previous node on the clock path P, is the delay of the i-th element or segment on the path; calculate the time required for the output signal, which is the time the data must reach the trigger before the clock edge and the time it remains unchanged after the clock edge. The expression is:

[0026] T required (P,j)=T clk -S req ;

[0027] T required (P,j)=H req ;

[0028] Among them, T clk is the target clock period, S req and H req They are setup time and hold time requirements, P refers to a specific clock path, j refers to the register or logic unit on the path, and T required (P,j) represents the time required for the output signal of the jth register or logic unit on path P; according to the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and obtain the timing analysis result based on the compared values, the expression is:

[0029] Setup Violation P =T required (P,j)-T arrival (P,j);

[0030] Hold Violation P =T arrival (P,j)-T required (P,j);

[0031] Among them, Setup Violation P To set a time violation, Hold Violation P To keep time violation.

[0032] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the longest path from the clock source to the register in the optimized clock tree topology diagram is identified according to the timing analysis result, marked as the critical path, and the best position for placing the buffer in the critical path is found by using a heuristic search algorithm. The specific steps are: according to the obtained timing analysis result, the maximum delay path from the clock source to the register is found, which is the critical path, and the expression is:

[0033]

[0034] T crit =max(D P );

[0035] Among them, P is each path, D P is the total delay on each path P, is the number of elements or segments on the path, T crit is the critical path with the maximum delay; according to the critical path in the clock tree topology diagram, all possible buffer placement positions are identified, and several positions are randomly selected to place the buffer among the placement positions, an initial buffer placement scheme is generated, and a fitness function is defined to evaluate the fitness of each buffer placement position, and the expression is:

[0036] S={s i |∈L,i=1,2,...,n};

[0037] F(S)=w1·ΔE-w2·ΔM-w3·C b ;

[0038] Where ΔE is the delay reduction after placing the buffer, ΔM is the power consumption increase after placing the buffer, and C b is the routing congestion degree on the path after the buffer is placed, L represents the set of all possible buffer placement positions, S represents the buffer placement scheme, F(S) is the fitness value of the buffer placement scheme S, w1, w2, w3 are weight coefficients; the fitness with a higher value is selected as the new placement scheme, and the crossover and mutation operations are used to iteratively optimize the placement scheme. The expression is as follows:

[0039] S c =S a [:R]+S b [R:],S d =S b [:R]+S a [R:];

[0040]

[0041] Among them, S c and S d is the newly generated offspring solution, R is the location of the crossover point, S' is the solution after mutation, and s i is the position to be replaced, l j is a new position randomly selected from the set L of all possible buffer placement positions, P mut is the mutation probability; after iteration, the buffer placement scheme with the highest fitness value is obtained, which is the optimal location for placing the buffer, and the expression is:

[0042]

[0043] L opt = {l j |∈S opt};

[0044] Among them, S opt is the best buffer placement solution obtained after the iteration, Final Population represents the final population at the end of the iteration, F(S) is the fitness value of the buffer placement solution S, and L opt The best location for placing the buffer.

[0045] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: PrimeTime is used again to calculate the difference between the actual delay and the maximum allowable delay of the clock tree topology diagram, the position of the buffer is adjusted according to the difference, and the clock tree topology diagram is updated. The specific steps are: using PrimeTime to extract the actual delay time of the critical path from the timing analysis result as T arrival (P,i); Set the maximum allowed delay D on the path max , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is:

[0046] ΔD=T arrival (P,i)-D max ;

[0047] Where ΔD is the difference between the actual delay and the maximum allowed delay, T arrival (P,i) is the arrival time of the input signal at the i-th node on path P, D max The maximum allowed delay is set on the path; the path with the largest delay difference value is selected as the priority adjustment object, and buffers are placed at several positions on this path; for each newly placed buffer position, the actual delay and difference value of its path are recalculated; the smallest difference value is selected as the optimal configuration for placing buffers on the entire path; the selected optimal configuration is applied to the clock tree topology diagram, the position of the buffer is updated, and an updated clock tree topology diagram is obtained.

[0048] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the power consumption of the updated clock tree topology is evaluated to obtain the power consumption sensitivity analysis result, and the high power consumption buffer is replaced with a low power consumption buffer according to the power consumption sensitivity analysis result. The specific steps are: using Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report; according to the power consumption report, the power consumption sensitivity score of each buffer is calculated, and the expression is:

[0049]

[0050] in, Score the power consumption sensitivity, is the estimated power consumption of buffer ∪, is the sum of the power consumption estimates for all buffers, is the routing congestion level of buffer ∪, is the sum of the routing congestion levels of all buffers, N is the total number of buffers; according to the power sensitivity score Sort all buffers and select buffers with higher power consumption. For buffers with higher power sensitivity scores, find alternatives with similar electrical characteristics but lower power consumption. Replace buffers with higher power sensitivity scores with buffers with lower power consumption.

[0051] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the DRC tool Mentor's Calibre is used to identify and correct the physical rules violated in the updated clock tree topology diagram, timing analysis results and power sensitivity analysis results, and generate a verification report for the chip clock design optimization. The specific steps are: using Mentor's Calibre to configure the DRC rule file according to the target manufacturing process node; using Mentor's Calibre to check the design, find potential physical rule violations, and generate a report; according to the violation report, introduce the impact factor evaluation formula to calculate the impact of each violation item, and obtain the impact factor, which is expressed as:

[0052] I f =o1·Y impact +o2·K fix +o3·B risk ;

[0053] Among them, I f is the impact factor of the violation, Y impact is the impact score of the violation on the design performance, K fix is the complexity score required to fix the violation, B riskis the risk score brought by the violation, o1, o2, and o3 are weight coefficients, corresponding to the performance impact, repair complexity, and risk importance, respectively; manually correct the violation problems in the design based on Mentor's Calibre violation report and impact factors; integrate the updated clock tree topology diagram, timing analysis results, power sensitivity analysis results, and physical violation verification report to obtain a verification report for chip clock design optimization.

[0054] In a second aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the chip clock design optimization method based on Multi-PointCTS as described in the first aspect of the present invention is implemented.

[0055] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the chip clock design optimization method based on Multi-Point CTS as described in the first aspect of the present invention.

[0056] The beneficial effects of the present invention are as follows: RTL code describing circuit behavior is written using hardware description language VHDL, and a preliminary clock tree topology diagram is constructed, so as to realize the first step of conversion from high-level design description to physical implementation, and achieve the effect of ensuring design accuracy and consistency; the static timing analysis tool PrimeTime is used to analyze the preliminary clock tree topology diagram, identify the critical path, and by defining the delay calculation expression, the input signal arrival time of each node is calculated incrementally to ensure that all registers can receive the clock signal within the specified time, and provide a clear goal for subsequent optimization; by placing multiple clock sources in different sub-areas, the clock signal can be distributed more evenly, thereby reducing the time difference of receiving the clock signal between each register; a heuristic search algorithm is used to find the best position for placing the buffer in the critical path, so as to realize effective optimization of the critical path, and achieve the effect of minimizing the critical path delay and improving the overall performance; PrimeTime is used to calculate the difference between the actual delay and the maximum allowable delay of the clock tree topology diagram, and the buffer position is adjusted to realize further optimization of the clock tree topology diagram, so as to achieve the effect of ensuring that all paths meet the timing requirements; the power consumption of the updated clock tree topology diagram is evaluated, and the high power consumption buffer is replaced, so as to achieve the effect of reducing the overall power consumption and improving the energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0058] Figure 1 This is a flow chart of the chip clock design optimization method based on Multi-Point CTS in Example 1.

[0059] Figure 2 This is a flow chart of the impact factors in Example 1. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0062] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0063] Example 1, reference Figure 1 and Figure 2 , which is the first embodiment of the present invention, and provides a chip clock design optimization method based on Multi-Point CTS, comprising the following steps:

[0064] S1. Use the hardware description language VHDL to write RTL code that describes the circuit behavior, use Synopsys's DC EDA tool to convert the RTL code into a logic netlist, use the standard algorithm H-Tree to build a preliminary clock tree structure layout, and obtain a preliminary clock tree topology diagram;

[0065] Furthermore, the RTL code describing the circuit behavior is written using the hardware description language VHDL, the RTL code is converted into a logic netlist using the Synopsys DC EDA tool, and the standard algorithm H-Tree is used to build a preliminary clock tree structure layout to obtain a preliminary clock tree topology diagram. The specific steps include: using the hardware description language VHDL to write the behavioral level description of the circuit to obtain the VHDL RTL code; importing the VHDL RTL code into Synopsys DC EDA, performing logic synthesis, converting the RTL code into a logic netlist based on a standard cell library, saving the synthesized design in a logic netlist format, and using PrimeTime to identify all registers that require clock signals, determine the clock source and register location; according to the clock source and register location, calculate the chip center point, the expression is:

[0066]

[0067] Where W is the width, H is the height, C is the center point, and the coordinates of the center point C are C(C x ,C y ); Set the center point as the starting point of the clock tree H-Tree, and place the trunk buffer from the clock source to the center point as the root node of the H-Tree, and set the location of the clock source to CLK (CLK x ,CLK y ), find the best path from CLK to C to place the trunk buffer, and calculate the distance from the clock source to the center point. The expression is:

[0068]

[0069] Among them, d CLK-C is the distance from the clock source to the center of the chip, C x and C y are the coordinates of the chip center point on the x-axis and y-axis, CLK x and CLK y are the coordinates of the clock source on the x-axis and y-axis respectively; starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree, and a buffer is placed in the center of each partition as a new node of the branch. The expression is;

[0070]

[0071] P x (t i )=(1-t i ) · CLK x +t i ·C x ;

[0072] Py (t i )=(1-t i ) · CLK y +t i ·C y ;

[0073] Where N is the number of buffers planned to be placed, Δd is the interval between buffers, and t i is the relative position of each buffer i on the path, P x (t i ) is the coordinate of the i-th buffer on the x-axis, P y (t i ) is the coordinate of the i-th buffer on the y-axis;

[0074] Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree construction is completed; after the clock tree H-Tree construction is completed, check to confirm that no registers are missed and all clock paths are correctly connected; save the constructed clock tree in a logic netlist format to generate a preliminary clock tree topology diagram.

[0075] It should be noted that the standard algorithm H-Tree is used to construct the preliminary clock tree structure layout, which ensures the uniform distribution and low skewness of the clock signal on the chip. This method not only improves the quality of the clock signal, but also simplifies the subsequent optimization work. The construction of the preliminary clock tree provides a solid foundation for subsequent optimization, reduces uncertainty, and ensures the consistency and accuracy of the clock distribution network.

[0076] S2, introduce the Multi-Point CTS method, use multiple clock sources to optimize the preliminary clock tree topology, and obtain the optimized clock tree topology;

[0077] Furthermore, the Multi-PointCTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain the optimized clock tree topology. The specific steps are: select the multi-point CTS strategy based on regional division and dynamic buffer insertion as the priority scheme; divide the entire chip into several sub-regions according to the preliminary clock tree topology, each sub-region will be configured with one or more clock sources, and determine the optimal clock source position for each sub-region. The expression is:

[0078]

[0079] Among them, S eff is the effectiveness index of the clock source, A and B are the starting point and end point of the integration interval, ρ(r) is the load density function at distance r, dT(r) is the clock transmission delay differential at distance r, N is the number of clock sources, and fi is the frequency of the ith clock source; select the maximum value S eff , as the best clock source location for each sub-area, and obtain the optimized clock tree topology.

[0080] It should be noted that the multi-point CTS strategy based on regional division and dynamic buffer insertion is chosen based on comprehensive considerations of reducing clock skew, reducing jitter, and minimizing power consumption. The strategy allows designers to customize clock distribution according to the specific conditions of different regions, thereby improving the reliability of the overall system. The chip is divided into multiple sub-regions to better manage complexity and ensure the quality of the clock signal in each local area. In this way, the clock delay and load balancing of each part can be more accurately controlled, thereby improving global timing convergence.

[0081] S3. Use the static timing analysis tool PrimeTime to analyze the optimized clock tree topology diagram to obtain the timing analysis results;

[0082] Furthermore, the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis results. The specific steps are: use the static timing analysis STA in PrimeTime to define the delay calculation expression and calculate all clock path delays in the entire clock tree. The expression is:

[0083] D elem =f(T input ,T output ,C load );

[0084] Among them, D elem is the delay of a single component or network segment, T input is the arrival time of the input signal, T output is the departure time of the output signal, C load is the load capacitance, f is the delay calculation function; then the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is:

[0085]

[0086] Among them, T arrival (P,i) represents the arrival time of the input signal at the i-th node on the clock path P, T arrival (P,i-1) is the arrival time of the input signal of the previous node on the clock path P, is the delay of the i-th element or segment on the path; calculate the time required for the output signal, which is the time the data must reach the trigger before the clock edge and the time it remains unchanged after the clock edge. The expression is:

[0087] T required (P,j)=T clk -S req ;

[0088] T required (P,j)=H req ;

[0089] Among them, T clk is the target clock period, S req and H req They are setup time and hold time requirements, P refers to a specific clock path, j refers to the register or logic unit on the path, and T required (P,j) represents the time required for the output signal of the jth register or logic unit on path P; according to the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and obtain the timing analysis result based on the compared values, the expression is:

[0090] Setup Violation P =T required (P,j)-T arrival (P,j);

[0091] Hold Violation P =T arrival (P,j)-T required (P,j);

[0092] Among them, Setup Violation P To set a time violation, Hold Violation P To keep time violation.

[0093] It should be noted that the delay calculation expression is defined, the input signal arrival time of each node is calculated incrementally, and the timing performance of the entire clock tree is evaluated based on these data, including factors such as component or network segment delay and load capacitance. By accurately calculating the delay of all clock paths, it is ensured that all registers can receive the clock signal within the specified time, thereby meeting the design timing requirements and improving the reliability and performance of the system.

[0094] S4. According to the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology diagram is identified, marked as the critical path, and the best position for placing the buffer in the critical path is found by using a heuristic search algorithm;

[0095] Furthermore, the longest path from the clock source to the register in the optimized clock tree topology is identified based on the timing analysis results, marked as the critical path, and the heuristic search algorithm is used to find the best location for placing the buffer in the critical path. The specific steps are as follows: Based on the obtained timing analysis results, the maximum delay path from the clock source to the register is found, which is the critical path. The expression is:

[0096]

[0097] T crir =max(D P );

[0098] Among them, P is each path, D P is the total delay on each path P, is the number of elements or segments on the path, T crit is the critical path with the maximum delay; according to the critical path in the clock tree topology diagram, all possible buffer placement positions are identified, and several positions are randomly selected to place the buffer among the placement positions, an initial buffer placement scheme is generated, and a fitness function is defined to evaluate the fitness of each buffer placement position, and the expression is:

[0099] S={s i |∈L,i=1,2,...,n};

[0100] F(S)=w1·ΔE-w2·ΔM-w3·C b ;

[0101] Where ΔE is the delay reduction after placing the buffer, ΔM is the power consumption increase after placing the buffer, and C b is the routing congestion degree on the path after the buffer is placed, L represents the set of all possible buffer placement positions, S represents the buffer placement scheme, F(S) is the fitness value of the buffer placement scheme S, w1, w2, w3 are weight coefficients; the fitness with a higher value is selected as the new placement scheme, and the crossover and mutation operations are used to iteratively optimize the placement scheme. The expression is as follows:

[0102] S c =S a [:R]+S b [R:],S d =S b [:R]+S a [R:];

[0103]

[0104] Among them, S c and S dis the newly generated offspring solution, R is the location of the crossover point, S' is the solution after mutation, and s i is the position to be replaced, l j is a new position randomly selected from the set L of all possible buffer placement positions, P mut is the mutation probability; after iteration, the buffer placement scheme with the highest fitness value is obtained, which is the optimal location for placing the buffer, and the expression is:

[0105]

[0106] L opt = {l j |∈S opt};

[0107] Among them, S opt is the best buffer placement solution obtained after the iteration, Final Population represents the final population at the end of the iteration, F(S) is the fitness value of the buffer placement solution S, and L opt The best location for placing the buffer.

[0108] It should be noted that the optimal buffer placement position is found on the critical path through a heuristic search algorithm, and a fitness function is defined to evaluate each possible solution. The solution with the highest fitness value is selected as the final configuration, minimizing the delay on the critical path while taking power consumption and routing congestion into consideration, thereby improving the overall performance and reliability of the chip and ensuring the optimal configuration of the design.

[0109] S5. Use PrimeTime again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology, adjust the position of the buffer according to the difference, and update the clock tree topology.

[0110] Furthermore, PrimeTime is used again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology, adjust the position of the buffer according to the difference, and update the clock tree topology. The specific steps are as follows: Use PrimeTime to extract the actual delay time of the critical path from the timing analysis results as T arrival (P,i); Set the maximum allowed delay D on the path max , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is:

[0111] ΔD=T arrival (P,i)-D max ;

[0112] Where ΔD is the difference between the actual delay and the maximum allowed delay, T arrival(P,i) is the arrival time of the input signal at the i-th node on path P, D max The maximum allowed delay is set on the path; the path with the largest delay difference value is selected as the priority adjustment object, and buffers are placed at several positions on this path; for each newly placed buffer position, the actual delay and difference value of its path are recalculated; the smallest difference value is selected as the optimal configuration for placing buffers on the entire path; the selected optimal configuration is applied to the clock tree topology diagram, the position of the buffer is updated, and an updated clock tree topology diagram is obtained.

[0113] It should be noted that PrimeTime is reused to calculate the difference between the actual delay and the maximum allowed delay, and the position of the buffer is adjusted according to the difference, especially for those critical paths whose delay exceeds the allowed value, to ensure that all critical paths meet the specified maximum allowed delay, further optimizing the clock tree topology and improving the timing performance and stability of the system.

[0114] S6, performing power consumption evaluation on the updated clock tree topology diagram to obtain power consumption sensitivity analysis results, and replacing the high power consumption buffer with the low power consumption buffer according to the power consumption sensitivity analysis results;

[0115] Furthermore, the power consumption of the updated clock tree topology is evaluated to obtain the power consumption sensitivity analysis results. According to the power consumption sensitivity analysis results, the high power consumption buffer is replaced with a low power consumption buffer. The specific steps are as follows: Use Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report; According to the power consumption report, calculate the power consumption sensitivity score of each buffer, which is expressed as:

[0116]

[0117] in, Score the power consumption sensitivity, is the estimated power consumption of buffer ∪, is the sum of the power consumption estimates for all buffers, is the routing congestion level of buffer ∪, is the sum of the routing congestion levels of all buffers, N is the total number of buffers; according to the power sensitivity score Sort all buffers and select buffers with higher power consumption. For buffers with higher power sensitivity scores, find alternatives with similar electrical characteristics but lower power consumption. Replace buffers with higher power sensitivity scores with buffers with lower power consumption.

[0118] It should be noted that Redhawk is used to evaluate the power consumption of the updated clock tree, generate a detailed power consumption report, identify and replace high-power buffers based on power consumption sensitivity scores, and select alternatives with lower power consumption but similar electrical characteristics, thereby reducing overall power consumption, improving the energy efficiency of the chip, reducing heat generation, extending the service life of the equipment, and reducing operating costs.

[0119] S7. Use Mentor's Calibre, a DRC tool, to identify and correct the physical rule violations in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for chip clock design optimization.

[0120] Furthermore, the DRC tool Mentor's Calibre is used to identify and correct the physical rule violations in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for chip clock design optimization. The specific steps are: use Mentor's Calibre to configure the DRC rule file according to the target manufacturing process node; Mentor's Calibre checks the design to find potential physical rule violations and generates a report; based on the violation report, the impact factor evaluation formula is introduced to calculate the impact of each violation item and obtain the impact factor, which is expressed as:

[0121] I f =o1·Y impact +o2·K fix +o3·B risk ;

[0122] Among them, I f is the impact factor of the violation, Y impact is the impact score of the violation on the design performance, K fix is the complexity score required to fix the violation, B risk is the risk score brought by the violation, o1, o2, and o3 are weight coefficients, corresponding to the performance impact, repair complexity, and risk importance, respectively; manually correct the violation problems in the design based on Mentor's Calibre violation report and impact factors; integrate the updated clock tree topology diagram, timing analysis results, power sensitivity analysis results, and physical violation verification report to obtain a verification report for chip clock design optimization.

[0123] It should be noted that Mentor's Calibre is used to load the updated design data, configure the DRC rule file, and perform a comprehensive physical rule check to discover and correct potential physical rule violations, ensuring that the design meets the manufacturing process requirements, improving the manufacturability of the design, reducing uncertainties and risks in the production process, improving the yield and product quality, and ensuring the successful mass production of the design.

[0124] This embodiment also provides a computer device, which is suitable for the chip clock design optimization method based on Multi-Point CTS, including: a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute computer executable instructions to implement the chip clock design optimization method based on Multi-Point CTS as proposed in the above embodiment.

[0125] The computer device may be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, or a key, trackball or touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse, etc.

[0126] In summary, the present invention uses the hardware description language VHDL to write RTL code that describes circuit behavior and constructs a preliminary clock tree topology diagram, thereby realizing the first step of conversion from high-level design description to physical implementation, achieving the effect of ensuring design accuracy and consistency, using the static timing analysis tool PrimeTime to analyze the preliminary clock tree topology diagram, identifying the critical path, and by defining the delay calculation expression, incrementally calculating the arrival time of the input signal of each node, ensuring that all registers can receive the clock signal within the specified time, providing a clear goal for subsequent optimization, and placing multiple clock sources in different sub-areas, The clock signal can be distributed more evenly, thereby reducing the time difference between each register receiving the clock signal, and using a heuristic search algorithm to find the best position for placing the buffer in the critical path, achieving effective optimization of the critical path, achieving the effect of minimizing the critical path delay and improving the overall performance, using PrimeTime, calculating the difference between the actual delay of the clock tree topology diagram and the maximum allowed delay, adjusting the buffer position, and achieving further optimization of the clock tree topology diagram, achieving the effect of ensuring that all paths meet the timing requirements, and evaluating the power consumption of the updated clock tree topology diagram, and replacing the high-power buffer, achieving the effect of reducing overall power consumption and improving energy efficiency.

[0127] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A chip clock design optimization method based on Multi-PointCTS, characterized in that: include, Use the hardware description language VHDL to write RTL code that describes the circuit behavior, use Synopsys's DC EDA tool to convert the RTL code into a logic netlist, use the standard algorithm H-Tree to build a preliminary clock tree structure layout, and obtain a preliminary clock tree topology diagram; The Multi-Point CTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain the optimized clock tree topology. Use the static timing analysis tool PrimeTime to analyze the optimized clock tree topology diagram and obtain the timing analysis results; According to the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology is identified and marked as the critical path. The heuristic search algorithm is used to find the best location to place the buffer in the critical path. PrimeTime is used again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology, and the position of the buffer is adjusted according to the difference to update the clock tree topology. Perform power consumption evaluation on the updated clock tree topology diagram to obtain power consumption sensitivity analysis results, and replace the high power consumption buffer with the low power consumption buffer according to the power consumption sensitivity analysis results; Use Mentor's DRC tool Calibre to identify and correct violations of physical rules in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for chip clock design optimization.

2. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 1, characterized in that: The RTL code describing the circuit behavior is written using the hardware description language VHDL, the RTL code is converted into a logic netlist using the DC EDA tool of Synopsys, and a preliminary clock tree structure layout is constructed using the standard algorithm H-Tree to obtain a preliminary clock tree topology diagram. The specific steps include: Use the hardware description language VHDL to write the behavioral level description of the circuit and obtain VHDLRTL code; Import the VHDL RTL code into Synopsys DC, perform logic synthesis, convert the RTL code into a logic netlist based on the standard cell library, save the synthesized design in a logic netlist format, and use PrimeTime to identify all registers that require clock signals, determine the clock source and register location; According to the clock source and register position, the chip center point is calculated as follows: Where W is the width, H is the height, C is the center point, and the coordinates of the center point C are C(C x ,C y ); Set the center point as the starting point of the clock tree H-Tree, and place the trunk buffer from the clock source to the center point as the root node of the H-Tree, and set the location of the clock source to CLK (CLK x ,CLK y ), find the best path from CLK to C to place the trunk buffer, and calculate the distance from the clock source to the center point. The expression is: Among them, d CLK-C is the distance from the clock source to the center of the chip, C x and C y are the coordinates of the chip center point on the x-axis and y-axis, CLK x and CLK y are the coordinates of the clock source on the x-axis and y-axis respectively; Starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree. A buffer is placed in the center of each partition as a new node of the branch. The expression is; P x (t i )=(1-t i )·CLK x +t i ·C x ; P y (t i )=(1-t i )·CLK y +t i ·C y ; Where N is the number of buffers planned to be placed, Δd is the interval between buffers, and t i is the relative position of each buffer i on the path, P x (t i ) is the coordinate of the i-th buffer on the x-axis, P y (t i ) is the coordinate of the i-th buffer on the y-axis; Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree construction is completed; After the clock tree H-Tree is built, check to confirm that no registers are missed and all clock paths are correctly connected; Save the constructed clock tree in a logic netlist format and generate a preliminary clock tree topology diagram.

3. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 2, characterized in that: The Multi-Point CTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain an optimized clock tree topology. The specific steps are: Select the multi-point CTS strategy based on zone partitioning and dynamic buffer insertion as the priority solution; According to the preliminary clock tree topology diagram, the entire chip is divided into several sub-areas. Each sub-area will be configured with one or more clock sources. The optimal clock source position for each sub-area is determined by the expression: Among them, S eff is the effectiveness index of the clock source, A and B are the starting point and end point of the integration interval, ρ(r) is the load density function at distance r, dT(r) is the clock transmission delay differential at distance r, N is the number of clock sources, and f i is the frequency of the i-th clock source; Select the maximum value of S eff , as the best clock source location for each sub-area, and obtain the optimized clock tree topology.

4. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 3, characterized in that: The static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis results. The specific steps are as follows: Use static timing analysis STA in PrimeTime to define the delay calculation expression and calculate all clock path delays in the entire clock tree. The expression is: D elem =f(T input ,T output ,C load ); Among them, D elem is the delay of a single component or network segment, T input is the arrival time of the input signal, T output is the departure time of the output signal, C load is the load capacitance, f is the delay calculation function; Then the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is: Among them, T arrival (P, i) represents the arrival time of the input signal at the i-th node on the clock path P, T arrival (P, i-1) is the arrival time of the input signal of the previous node on the clock path P, is the delay of the ith element or segment on the path; Calculate the time required for the output signal, which is the time the data must reach the trigger before the clock edge and the time it remains unchanged after the clock edge. The expression is: T required (P,j)=T clk -S req ; T required (P,j)=H req ; Among them, T clk is the target clock period, S req and H req They are setup time and hold time requirements, P refers to a specific clock path, j refers to the register or logic unit on the path, and T required (P, j) represents the time required for the output signal of the jth register or logic unit on path P; According to the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and get the timing analysis result according to the compared values. The expression is: Setup Violation P =T required (P,j)-T arrival (P,j); Hold Violation P =T arrival (P,j)-T required (P,j); Among them, Setup Violation P To set a time violation, Hold Violation P To keep time violation.

5. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 3, characterized in that: The method further comprises the following steps: identifying the longest path from the clock source to the register in the optimized clock tree topology diagram according to the timing analysis result, marking it as the critical path, and using a heuristic search algorithm to find the best location for placing the buffer in the critical path. According to the obtained timing analysis results, find the maximum delay path from the clock source to the register, which is the critical path, and the expression is: T crit =max(D P ); Among them, P is each path, D P is the total delay on each path P, is the number of elements or segments on the path, T crit is the critical path with the maximum delay; According to the critical path in the clock tree topology, all possible buffer placement locations are identified, and several locations are randomly selected to place the buffers. The initial buffer placement plan is generated, and the fitness function is defined to evaluate the fitness of each buffer placement location. The expression is: S={s i |∈L,i=1,2,...,n}; F(S)=W1·ΔE-W2·ΔM-W3·C b ; Where ΔE is the delay reduction after placing the buffer, ΔM is the power consumption increase after placing the buffer, and C b is the routing congestion degree on the path after the buffer is placed, L represents the set of all possible buffer placement locations, S represents the buffer placement scheme, F(S) is the fitness value of the buffer placement scheme S, and w1, w2, and w3 are weight coefficients; Select a higher fitness value as the new placement plan, and use crossover and mutation operations to iteratively optimize the placement plan. The expression is as follows: S c =S a [:R]+S b [R:],S d =S b [:R]+S a [R:]; Among them, S c and S d is the newly generated offspring solution, R is the location of the crossover point, S′ is the solution after mutation, and s i is the position to be replaced, l j is a new position randomly selected from the set L of all possible buffer placement positions, P mut is the mutation probability; After iteration, the buffer placement scheme with the highest fitness value is obtained, which is the optimal location for placing the buffer. The expression is: L opt ={l j |∈S opt }; Among them, S opt is the best buffer placement solution obtained after the iteration, Final Population represents the final population at the end of the iteration, F(S) is the fitness value of the buffer placement solution S, and L opt The best location for placing the buffer.

6. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 5, characterized in that: The PrimeTime is used again to calculate the difference between the actual delay of the clock tree topology and the maximum allowed delay, adjust the position of the buffer according to the difference, and update the clock tree topology. The specific steps are as follows: The actual delay time of the critical path is extracted from the timing analysis results using PrimeTime as T arrival (P,i); Set the maximum allowed delay D on the path max , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is: ΔD=T arrival (P,i)-D max ; Where ΔD is the difference between the actual delay and the maximum allowed delay, T arrival (P,i) is the arrival time of the input signal at the i-th node on path P, D max The maximum allowed delay set on the path; Select the path with the largest delay difference value as the priority adjustment object, and place buffers at several locations on this path; For each newly placed buffer location, recalculate the actual delay and variance values ​​of its path; The smallest difference value is selected as the optimal configuration for placing buffers on the entire path; The selected optimal configuration is applied to the clock tree topology diagram, the position of the buffer is updated, and an updated clock tree topology diagram is obtained.

7. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 6, characterized in that: The power consumption of the updated clock tree topology is evaluated to obtain a power consumption sensitivity analysis result, and according to the power consumption sensitivity analysis result, a high power consumption buffer is replaced with a low power consumption buffer, and the specific steps are as follows: Use Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report. Based on the power consumption report, the power consumption sensitivity score of each buffer is calculated as: in, Score the power consumption sensitivity, is the estimated power consumption of buffer ∪, is the sum of the power consumption estimates for all buffers, is the routing congestion level of buffer ∪, is the sum of the routing congestion levels of all buffers, and N is the total number of buffers; Scoring by Power Sensitivity Sort all buffers and select the buffer with higher power consumption; For buffers with a high power sensitivity score, look for alternatives with similar electrical characteristics but lower power consumption; Replace a buffer with a higher power sensitivity score with a lower power buffer.

8. The chip clock design optimization method based on Multi-Point CTS as claimed in claim 7, characterized in that: The DRC tool Mentor's Calibre is used to identify and correct the physical rules that are violated in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for chip clock design optimization. The specific steps are as follows: Mentor's Calibre configures the DRC rule file based on the target manufacturing process node; Use Mentor's Calibre to check the design for potential physical rule violations and generate reports; According to the violation report, the impact factor evaluation formula is introduced to calculate the impact of each violation item and obtain the impact factor, which is expressed as: I f =o1·Y impact +o2·K fix +o3·B risk ; Among them, I f is the impact factor of the violation, Y impact is the impact score of the violation on the design performance, K fix is the complexity score required to fix the violation, B risk is the risk score brought by the violation, o1, o2, and o3 are weight coefficients, corresponding to performance impact, repair complexity, and risk importance, respectively; Manually correct violations in the design based on Mentor's CalibrePT violation reports and impact factors; The updated clock tree topology diagram, timing analysis results, power consumption sensitivity analysis results, and physical violation verification report are integrated to obtain a verification report for chip clock design optimization.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the chip clock design optimization method based on Multi-PointCTS according to any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip clock design optimization method based on Multi-Point CTS according to any one of claims 1 to 8 are implemented.

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