Low-temperature hybrid bonding interconnection structure and manufacturing method

Abstract

The invention discloses a low-temperature hybrid bonding interconnection structure and a manufacturing method thereof. The low-temperature hybrid bonding interconnection structure comprises a first substrate with an embedded metal structure, a second substrate with an embedded metal structure, an etching barrier layer, an amorphous dielectric layer, a bonding auxiliary layer, a first bonding layer, a second bonding layer, a first bonding layer and a second bonding layer, and the interconnection metal is embedded in the bonding auxiliary layer, the amorphous dielectric layer and the etching barrier layer, and the interconnection metal has a conductive diffusion barrier and a seed layer on a contact interface with the bonding auxiliary layer, the amorphous dielectric layer and the etching barrier layer. The interconnect metal forms an electrical connection with the embedded metal structure of the first substrate and the embedded metal structure of the second substrate. The ultra-vacuum oxygen-free surface activation bonding technology is adopted, the amorphous media are bonded together through the polycrystalline bonding auxiliary layer, and mixed bonding with lower metal interconnection resistance can be achieved at low temperature or even room temperature.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronic integration, and in particular relates to a hybrid bonding interconnection structure and a manufacturing method. Background Art

[0002] With the rapid development of artificial intelligence, high-performance computing and the Internet of Things, the semiconductor industry is approaching the limit of Moore's Law. It is becoming increasingly challenging to enhance device functionality by increasing the number of transistors on a two-dimensional plane and by reducing feature sizes. People expect to further increase chip density through three-dimensional integration. Hybrid bonding has attracted widespread attention as a leading technology for high-density interconnection in three-dimensional integration. Hybrid bonding combines dielectric bonding with embedded metal to achieve interconnection between electrodes below 10 μm, which is an interconnection density that is difficult to achieve with traditional bump bonding and copper pillar interconnection technologies. This technology has been applied to the manufacture of back-illuminated CMOS image sensor chips, stacked integration of Micro-LED micro-display chips and CMOS driver chips, and integration of GaN RF chips with CMOS digital chips. Cu pad pitch is a key factor affecting interconnection density and pitch. As the Cu pad pitch further decreases, the proportion of surface Cu and SiO2 dielectrics further increases, greatly increasing the difficulty of thermal management and stress management. Due to the thermal expansion coefficient mismatch of about 400% and -83% between Cu metal and Si and SiO2 dielectrics, respectively, the high temperature (300-400°C) during the traditional hybrid bonding process is very high. ) can easily cause a very large deformation of the wafer, resulting in failure to bond. The development of low-temperature or even room-temperature hybrid bonding processes is a key technology that needs to be broken through in future high-density interconnection technology. However, the current traditional hybrid bonding process is limited by the process principle and it is difficult to achieve a process temperature below 200 Therefore, it is very necessary to develop new hybrid bonding technologies to meet the future high interconnect density, low temperature (<200 ) or even room temperature hybrid bonding requirements.

[0003]

[0004] There are two main bonding technologies in the prior art, and their process flows and defects are as follows.

[0005] The first technical solution: Typical hybrid bonding technology key processes such as Figure 1As shown. After the RDL wiring layer is completed on the upper and lower chip wafers, SiO2 dielectric is deposited on the surface. Through a series of processes such as photolithography, etching, Cu metal plating and chemical mechanical polishing, the SiO2 / Cu mixed surface is flattened and polished, so that the Cu metal surface is about 3~5nm lower than the SiO2 surface, which is the so-called Cu electrode concave disk effect (Cu dishing); then through fusion bonding technology, the SiO2 dielectric is first bonded together; then heated, so that the Cu electrodes on the upper and lower wafer surfaces expand to form contact; finally, annealing is performed at a high temperature of 300~400℃ for half an hour to several hours, so that the Cu atoms of the upper and lower Cu electrodes diffuse with each other at the contact interface to form a good conductive connection.

[0006] The first defect: Cu metal is easily oxidized, so in a typical hybrid bonding process, an oxide layer is usually formed on the Cu surface. When the upper and lower Cu electrodes expand due to heat to form contact, there is a layer of copper oxide of about several nanometers at the interface. This oxide layer blocks the diffusion of Cu atoms, thereby increasing the interconnection resistance. Therefore, in order to allow the Cu atoms of the upper and lower Cu electrodes to diffuse with each other to form a smaller contact resistance, a higher annealing temperature (such as 400°C) and annealing time are usually required. Since the thermal expansion coefficients of Cu metal and SiO2 medium differ by dozens of times (~35 times), it is easy to generate large thermal stress, resulting in large deformation of the wafer and alignment deviation between the electrodes. Refer to Figure 2 (From Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes, Journal of ELECTRONIC MATERIALS, Vol. 39, No. 12, 2010 DOI: 10.1007 / s11664-010-1341-y2010 TMS) and Figure 3 (Source: Kim, Sarah Eunkyung; Kim, Sungdong. (2015). Wafer level Cu–Cu direct bonding for 3D integration. Microelectronic Engineering, 137(),158–163.doi:10.1016 / j.mee.2014.12.012). Especially when the interconnection density is further increased, the proportion of metal and dielectric increases, and the stress caused by the mismatch of thermal expansion coefficients will become more serious under high temperature processes.

[0007] The second technical solution: In order to reduce the process temperature, people proposed a low-temperature hybrid bonding technology based on surface activated bonding (SAB), such as Figure 4 Surface activated bonding technology refers to the process of bonding in ultra-high vacuum (10 -8 In an environment of 1000 mbar, high-energy ions are used to bombard the wafer surface, thereby generating high-density dangling bonds on the surface, and then the dangling bonds on the upper and lower wafer surfaces are combined at room temperature to achieve wafer bonding. In this process, high-energy ions can effectively remove the oxide layer on the surface of the Cu electrode, and because the bonding is carried out in an ultra-high vacuum environment, the oxidation of the Cu electrode surface can be effectively suppressed, thereby reducing the annealing temperature to below 150°C, greatly reducing the process thermal budget.

[0008] The second defect: Although SAB bonding technology can achieve a strong bond between metal and crystal materials under low temperature conditions, it cannot achieve a strong bond between dielectrics, especially SiO2 dielectrics, whose bonding strength is 0.5 J / m 2 Therefore, in order to improve the hybrid bonding strength, Figure 5 In the process, a layer of amorphous silicon bonding layer several nanometers thick is deliberately deposited on the upper and lower wafer surfaces. Figure 5 (b) is a transmission electron microscopy image of the Cu-Cu interface based on SAB hybrid bonding. Figure 5 (c) is a transmission electron microscope image of the SiO2-SiO2 interface based on SAB hybrid bonding. Although this layer of amorphous silicon bonding layer can increase the bonding strength to 1.5 J / m 2 But it also increases the contact resistance between Cu electrodes. Figure 5 In the example of (b), the contact resistance of the Cu electrode is as high as 4.1 Ω. In addition, the amorphous silicon adhesive layer covers the surface of both Cu and SiO2 dielectrics, which may cause leakage between the electrodes. Summary of the invention

[0009] Based on the above description, the present invention provides a low-temperature hybrid bonding interconnect structure and a manufacturing method to solve the problem that SAB low-temperature bonding technology is difficult to achieve strong bonding between dielectrics and the problem that SAB hybrid bonding using an amorphous silicon adhesive layer has a large electrode contact resistance.

[0010] A low temperature hybrid bonding interconnect structure comprises a first interconnect structure and a second interconnect structure, both having the same structure; The first interconnect structure and the second interconnect structure both include a substrate connected with an embedded metal structure, and one side of the substrate is sequentially connected with an etching stop layer, an amorphous dielectric layer, and a bonding auxiliary layer; A countersunk hole is opened at a position corresponding to the embedded metal in the middle of the first interconnection structure and the second interconnection structure, and the countersunk hole spans the bonding auxiliary layer, the amorphous dielectric layer, and the etching stop layer; The inner wall of the countersunk hole is connected to the diffusion barrier and the seed layer, and the top surface of the embedded metal structure has no diffusion barrier and the seed layer; The interconnection metal is embedded in the countersunk holes of the two structures, and the two ends are respectively connected to the embedded metal of the first interconnection structure and the embedded metal of the second interconnection structure; the interconnection metal, the embedded metal structure of the first interconnection structure, and the embedded metal structure of the second interconnection structure can form an electrical connection; The first interconnect structure and the second interconnect structure are directly connected together through surface atomic covalent bonds formed by the bonding auxiliary layers of the two structures.

[0011] Furthermore, in the above-mentioned low-temperature hybrid bonding interconnect structure, the bonding auxiliary layer is polycrystalline and insulating, and the material is AlN, AlON, Al2O3, HfO2 or ZrO2.

[0012] Furthermore, in the above-mentioned low-temperature hybrid bonding interconnect structure, the material of the bonding auxiliary layer is polycrystalline AlN, and the bonding auxiliary layers are connected by Al-N bonds instead of Al-O-Al bonds.

[0013] Furthermore, in the above-mentioned low-temperature hybrid bonding interconnection structure, the surface roughness of the bonding auxiliary layer is less than 1 nm, and the surface impurity atomic concentration is less than 1E15 / cm 3 .

[0014] Furthermore, in the above-mentioned low-temperature hybrid bonding interconnect structure, the amorphous dielectric layer is amorphous and insulating, and its material is SiO2, SiN or Al2O3.

[0015] Furthermore, in the above-mentioned low-temperature hybrid bonding interconnect structure, the diffusion barrier and seed layer is conductive and can prevent the interconnect metal from diffusing into the amorphous dielectric layer and the substrate, and is Ti or Ta.

[0016] A method for manufacturing a low-temperature hybrid bonding interconnection structure comprises the following steps: in an ultra-vacuum, oxygen-free environment, using plasma to bombard the surfaces of a first interconnection structure and a second interconnection structure, bonding the bonding auxiliary layer of the first interconnection structure and the bonding auxiliary layer of the second interconnection structure together under low temperature (≤ 100 ° C, including room temperature), aligning the interconnection metal up and down, and bonding vacuum degree ≤ 10 -7 mbar, temperature ≤100°C; annealing at a low temperature of 100-150°C so that the interconnection metals of the first interconnection structure and the second interconnection structure are combined together to obtain a hybrid bonding interconnection structure.

[0017] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, the bonding auxiliary layer and the amorphous dielectric layer are etched downward through a mask, and the lower surface reaches the surface of the substrate and the embedded metal structure to form a countersunk hole; Depositing a diffusion barrier layer and a seed layer on the upper surface of the bonding auxiliary layer, the sidewall and the bottom surface of the countersunk hole (depositing the diffusion barrier layer first and then the seed layer); A layer of interconnect metal is deposited by CVD or electroplating, and the interconnect metal covers the entire surface; Chemical mechanical polishing is used to remove part of the interconnect metal, the diffusion barrier layer, the seed layer and part of the bonding auxiliary layer to expose the surface of the bonding auxiliary layer, so that the surface roughness of the bonding auxiliary layer is less than 1 nm, the interconnect metal surface is lower than the auxiliary layer surface, and the height difference is less than 10 nm; thus obtaining a first interconnect structure.

[0018] Furthermore, the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, Provide a first substrate and a second substrate including embedded metal structures and used to form a first interconnect structure and a second interconnect structure respectively; Depositing an etching stop layer on the surface of the first substrate by physical vapor deposition or chemical vapor deposition; Depositing an amorphous dielectric layer on the etch barrier layer using a PVD or CVD process; depositing a bonding auxiliary layer on the amorphous dielectric layer; The processing method of the second substrate is the same as that of the first substrate.

[0019] Furthermore, the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure uses magnetron sputtering or pulsed laser sputtering to deposit a polycrystalline AlN bonding auxiliary layer, and during the deposition process, Y2O3 impurities are doped to enhance the insulation capability of the polycrystalline AlN bonding auxiliary layer.

[0020] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnection structure, the embedded metal is Al, Cu or W metal; and the interconnection metal is Cu, Al, Ti.

[0021] Furthermore, in the above-mentioned method for manufacturing a low-temperature hybrid bonding interconnect structure, the seed layer is AlCu alloy or Cu.

[0022] Compared with the prior art, the beneficial effects of the present invention are: Using a polycrystalline bonding auxiliary layer, typically polycrystalline AlN material, can bond amorphous media together through ultra-vacuum oxygen-free surface activation bonding technology. Compared with the second technical solution using an amorphous Si nano-adhesive layer, it has greater bonding strength and smaller Cu-Cu interface contact resistance; The ultra-vacuum oxygen-free surface activation bonding technology can achieve oxygen-free and room temperature bonding between Cu-Cu electrodes. Compared with the first technical solution, it has a lower mixed bonding temperature (≤ 150 ℃) and lower Cu-Cu interface resistance. The polycrystalline bonding auxiliary layer material (AlN) can also serve as a barrier layer for Cu diffusion. For example, when there is an alignment error between the upper and lower Cu metals, there is a diffusion channel for Cu metal. If there is only an amorphous dielectric layer (SiO2), Cu can easily diffuse into it. The use of a polycrystalline bonding auxiliary layer can block the diffusion of Cu. Through doping, the polycrystalline bonding auxiliary layer can also obtain a higher resistivity and achieve a better isolation effect.

[0023] The hybrid bonding structure and hybrid bonding method can be realized at low temperature or even room temperature, and can be applied to three-dimensional integration between chips or between wafers, thereby shortening the interconnection spacing, reducing the interconnection resistance and increasing the integration density to obtain a higher performance microelectronic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The flowchart of the key process of the typical hybrid bonding technology mentioned in the first process of the background technology, wherein (a) the Cu electrode is embedded in SiO2, and the surface is polished by chemical mechanical polishing so that the surface of the Cu electrode is within 5 nm lower than the surface of the SiO2 medium; (b) the SiO2 medium is first bonded together by a melt bonding process; (c) the upper and lower Cu electrodes are expanded by heating to form contact; (d) further annealing at a high temperature of 300-400℃ is performed to make the upper and lower Cu electrodes diffuse into each other to form a good conductive connection; Figure 2 The figure is a typical warpage change curve of a Si wafer during the bonding process using the first process of the background technology; Figure 3 The wafer warping of the first process using the background technology causes the alignment deviation of the electrodes during the bonding process; Figure 4 A schematic diagram of the process flow of low temperature hybrid bonding based on surface activated bonding (SAB) technology mentioned in the second process of the background technology; Figure 5 The second process is a transmission electron micrograph of the interface based on SAB hybrid bonding, (b) is a transmission electron micrograph of the Cu-Cu interface based on SAB hybrid bonding, and (c) is a transmission electron micrograph of the SiO2-SiO2 interface based on SAB hybrid bonding; Figure 6 A schematic structural diagram of a low-temperature hybrid bonding interconnect structure provided by an embodiment of the present invention; Figure 7A process flow chart of a method for manufacturing a low-temperature hybrid bonding interconnection structure provided by an embodiment of the present invention, wherein (a) a substrate including an embedded metal structure is provided, (b) an etch barrier layer is deposited on the substrate, (c) an amorphous dielectric layer is deposited on the etch barrier layer, (d) a bonding auxiliary layer is deposited on the amorphous dielectric layer, (e) a countersink is formed by etching downward through a mask, (f) a diffusion barrier and a seed layer are deposited on the upper surface of the bonding auxiliary layer, the sidewall and the bottom surface of the countersink (the diffusion barrier layer is deposited first, and then the seed layer is deposited), (g) an interconnection metal is deposited, (h) a part of the interconnection metal and the diffusion barrier layer and the seed layer and a part of the bonding auxiliary layer are removed by chemical mechanical polishing to expose the surface of the bonding auxiliary layer, (i) a first interconnection structure and a second interconnection structure are interconnected, and (j) annealing is performed under low temperature conditions so that the interconnection metals of the first interconnection structure and the second interconnection structure are combined together to obtain a hybrid bonding interconnection structure; Figure 8 The invention provides a diffusion path of Cu when there is an alignment error between the upper and lower Cu metals in a low-temperature hybrid bonding interconnect structure.

[0025] In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Substrate; 2. Embedded metal structure; 3. Etching barrier layer; 4. Amorphous dielectric layer; 5. Bonding auxiliary layer; 6. Diffusion barrier and seed layer; 7. Interconnection metal; 100. First interconnection structure; 200. Second interconnection structure. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present application, the present application will be described more comprehensively below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0028] It will be appreciated that spatial relationship terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be appreciated that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0029] In order to solve the problem that SAB low-temperature bonding technology is difficult to achieve strong bonding between dielectrics and the problem that SAB hybrid bonding using an amorphous silicon adhesive layer has a large electrode contact resistance, the present invention provides a low-temperature hybrid bonding interconnect structure and a manufacturing method, as follows.

[0030] A low-temperature hybrid bonding interconnection structure: comprising a first substrate with an embedded metal structure 2 and a second substrate with an embedded metal structure 2, an etching barrier layer 3, an amorphous dielectric layer 4, a bonding auxiliary layer 5 arranged between the first substrate and the second substrate, and an interconnection metal 7 embedded in the bonding auxiliary layer 5, the amorphous dielectric layer 4 and the etching barrier layer 3, wherein the interconnection metal 7 has a conductive diffusion barrier and a seed layer at the contact interface with the bonding auxiliary layer 5, the amorphous dielectric layer 4 and the etching barrier layer 3. The interconnection metal 7 forms an electrical connection with the embedded metal structure 2 of the first substrate and the embedded metal structure 2 of the second substrate.

[0031] Bonding auxiliary layer 5 features: polycrystalline, insulating, including but not limited to AlN, AlON, Al2O3, HfO2, ZrO2. Polycrystalline AlN is preferred as bonding auxiliary layer 5. Bonding auxiliary layer 5 can assist in achieving bonding between amorphous dielectric layers 4 at low temperature / room temperature. The surface roughness of bonding auxiliary layer 5 is less than 1 nm, and the surface impurity atom concentration is less than 1E15 / cm 3 (Surface impurity atoms refer to atoms other than the elements contained in the bonding auxiliary layer 5 material. For example, when the bonding auxiliary layer 5 is AlN, the surface does not contain elements such as H, O, and Si.) The bonding auxiliary layers 5 are directly connected through covalent bonds between surface atoms, and there is no indirect bonding with other atoms. For example, when the bonding auxiliary layer 5 material is AlN, the bonding auxiliary layers 5 are connected through Al-N bonds, not Al-O-Al bonds.

[0032] Characteristics of the amorphous dielectric layer 4: amorphous, insulating, including but not limited to SiO2, SiN, Al2O3, etc., typically SiO2 is used.

[0033] Substrate 1 and its embedded metal structure 2 features: After the post-process (BEOL) RDL wiring is completed, the embedded metal is usually Al, Cu or W metal.

[0034] Characteristics of the etching stop layer 3: In the dry etching process, the etching rate is slower than that of the amorphous dielectric layer 4. For example, when the amorphous dielectric layer 4 is SiO2, the etching stop layer 3 can be SiN or SiON.

[0035] Characteristics of interconnection metal 7: including but not limited to Cu, Al, Ti, preferably Cu. Interconnection metal 7 has no oxide layer at the bonding interface.

[0036] Diffusion barrier and seed layer characteristics: conductive, can prevent the interconnect metal 7 from diffusing into the amorphous dielectric layer 4 and the substrate 1, usually Ti, Ta, the seed layer is AlCu or Cu.

[0037] A method for manufacturing a low temperature hybrid bonding interconnect structure: Providing a first substrate including an embedded metal structure 2; Depositing an etching stop layer 3 on the surface by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method; Depositing an amorphous dielectric layer 4 on the etching stop layer 3 by using a PVD or CVD process; A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, for example, a polycrystalline AlN layer is deposited by magnetron sputtering or pulsed laser sputtering. During the deposition process, other impurities, such as Y2O3, may be added to enhance the insulation capability of the polycrystalline AlN layer.

[0038] The bonding auxiliary layer 5 and the amorphous dielectric layer 4 are etched downward through the mask until the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2, thereby forming a countersunk hole; Depositing a diffusion barrier layer and a seed layer on the upper surface of the bonding auxiliary layer 5, the sidewall and the bottom surface of the countersunk hole (depositing the diffusion barrier layer first, and then depositing the seed layer); Depositing a layer of interconnection metal 7 by CVD or electroplating, the interconnection metal 7 covers the entire surface; Chemical mechanical polishing (CMP) is used to remove part of the interconnection metal 7, the diffusion barrier layer, the seed layer and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5, so that the surface roughness of the bonding auxiliary layer 5 is less than 1 nm, the surface of the interconnection metal 7 is lower than the surface of the bonding auxiliary layer 5, and the height difference is less than 10 nm; thus obtaining the first interconnection structure 100; Provide a second substrate including an embedded metal structure 2, and repeat steps (2) to (8) to obtain a second interconnect structure 200; In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnection structure 100 and the second interconnection structure 200, and the bonding auxiliary layer 5 of the first interconnection structure 100 and the bonding auxiliary layer 5 of the second interconnection structure 200 are bonded together at low temperature (25-100 °C), and the interconnection metal 7 is aligned up and down. Bonding vacuum degree ≤10 -7 mbar, temperature ≤100℃ (including room temperature).

[0039] Annealing is performed under low temperature (100-150° C.) conditions, so that the interconnection metal 7 of the first interconnection structure 100 and the second interconnection structure 200 are bonded together to obtain a hybrid bonding interconnection structure.

[0040] Example 1 A low-temperature hybrid bonding interconnection structure: comprising a first substrate with an embedded metal structure 2 and a second substrate with an embedded metal structure 2, an etching barrier layer 3, an amorphous dielectric layer 4, a bonding auxiliary layer 5 arranged between the first substrate and the second substrate, and an interconnection metal 7 embedded in the bonding auxiliary layer 5, the amorphous dielectric layer 4 and the etching barrier layer 3, wherein the interconnection metal 7 has a conductive diffusion barrier and a seed layer (the diffusion barrier layer is deposited first, and then the seed layer is deposited) at the contact interface with the bonding auxiliary layer 5, the amorphous dielectric layer 4 and the etching barrier layer 3. The interconnection metal 7 forms an electrical connection with the embedded metal structure 2 of the first substrate and the embedded metal structure 2 of the second substrate.

[0041] Bonding auxiliary layer 5 features: polycrystalline, insulating, AlN. The surface roughness of bonding auxiliary layer 5 is 0.9 nm, and the surface impurity atomic concentration is 5E14 / cm 3 The bonding auxiliary layers 5 of the first interconnect structure and the second interconnect structure are connected via an Al-N bond, rather than an Al-O-Al bond.

[0042] Characteristics of the amorphous dielectric layer 4: SiO2.

[0043] Substrate 1 and its embedded metal structure 2 features: Wafer after completion of post-process (BEOL) RDL wiring, the embedded metal is Al.

[0044] Characteristics of the etch stop layer 3: The etch stop layer 3 is SiN.

[0045] Interconnection metal 7 features: Cu. Interconnection metal 7 has no oxide layer at the bonding interface.

[0046] Diffusion barrier and seed layer characteristics: conductive, can prevent the interconnect metal 7 from diffusing into the amorphous dielectric layer 4 and the substrate 1, is Ti, and the seed layer is AlCu alloy.

[0047] A method for manufacturing a low temperature hybrid bonding interconnect structure: Providing a first substrate including an embedded metal structure 2; Depositing an etching stop layer 3 on the surface by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method; Depositing an amorphous dielectric layer 4 on the etching stop layer 3 by using a PVD or CVD process; A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline AlN layer is deposited by magnetron sputtering. During the deposition process, Y2O3 is doped to enhance the insulation capability of the polycrystalline AlN layer.

[0048] The bonding auxiliary layer 5 and the amorphous dielectric layer 4 are etched downward through the mask until the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2, thereby forming a countersunk hole; Depositing a diffusion barrier and seed layer on the upper surface of the bonding auxiliary layer 5, the sidewall and the bottom of the countersunk hole; A layer of interconnect metal 7 is deposited by CVD method, and the interconnect metal 7 covers the entire surface; Chemical mechanical polishing is used to remove part of the interconnection metal 7, the diffusion barrier layer, the seed layer and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5, so that the surface roughness of the bonding auxiliary layer 5 is 0.9 nm, and the surface of the interconnection metal 7 is lower than the surface of the bonding auxiliary layer 5, with a height difference of 9 nm; thus obtaining a first interconnection structure 100; Providing a second substrate including an embedded metal structure 2, and repeating the above steps to obtain a second interconnect structure 200; In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200, and the bonding auxiliary layer 5 of the first interconnect structure 100 and the bonding auxiliary layer 5 of the second interconnect structure 200 are bonded together at 25°C, and the interconnect metal 7 is aligned up and down. The bonding vacuum degree is 1E-7 mbar and the temperature is 25°C.

[0049] Annealing is performed at 120° C. so that the interconnection metals 7 of the first interconnection structure 100 and the second interconnection structure 200 are bonded together to obtain a hybrid bonding interconnection structure.

[0050] Example 2 Embodiment 2 is substantially the same as Embodiment 1, except that: Bonding auxiliary layer 5 features: polycrystalline, insulating, HfO2. The surface roughness of bonding auxiliary layer 5 is 0.5 nm, and the surface impurity atomic concentration is 1E14 / cm 3 .

[0051] Characteristics of the amorphous dielectric layer 4: SiN.

[0052] Substrate 1 and its embedded metal structure 2 features: Wafer after completion of post-process (BEOL) RDL wiring, the embedded metal is Cu.

[0053] Characteristics of the etching stop layer 3: In the dry etching process, the etching rate is slower than that of the amorphous dielectric layer 4. The etching stop layer 3 is SiN.

[0054] Interconnection metal 7 features: Al. Interconnection metal 7 has no oxide layer at the bonding interface.

[0055] Diffusion barrier and seed layer characteristics: conductive, can prevent the interconnect metal 7 from diffusing into the amorphous dielectric layer 4 and the substrate 1, is Ta, and the seed layer is Cu.

[0056] A method for manufacturing a low temperature hybrid bonding interconnect structure: Providing a first substrate including an embedded metal structure 2; Depositing an etching stop layer 3 on the surface by a chemical vapor deposition (CVD) method; Depositing an amorphous dielectric layer 4 on the etching stop layer 3 by using a CVD process; A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline HfO2 layer is deposited by pulsed laser sputtering.

[0057] The bonding auxiliary layer 5 and the amorphous dielectric layer 4 are etched downward through the mask until the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2, thereby forming a countersunk hole; Depositing a diffusion barrier and seed layer on the upper surface of the bonding auxiliary layer 5, the sidewall and the bottom of the countersunk hole; A layer of interconnection metal 7 is deposited by electroplating, and the interconnection metal 7 covers the entire surface; Chemical mechanical polishing (CMP) is used to remove part of the interconnection metal 7, the diffusion barrier layer, the seed layer and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5, so that the surface roughness of the bonding auxiliary layer 5 is 0.5 nm, the surface of the interconnection metal 7 is lower than the surface of the bonding auxiliary layer 5, and the height difference is less than 5 nm; thus obtaining the first interconnection structure 100; Providing a second substrate including an embedded metal structure 2, and repeating the above steps to obtain a second interconnect structure 200; In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200, and the bonding auxiliary layer 5 of the first interconnect structure 100 and the bonding auxiliary layer 5 of the second interconnect structure 200 are bonded together at 25°C, and the interconnect metal 7 is aligned up and down. The bonding vacuum degree is 1E-7mbar and the temperature is 25°C.

[0058] Annealing is performed at 120° C. so that the interconnection metals 7 of the first interconnection structure 100 and the second interconnection structure 200 are bonded together to obtain a hybrid bonding interconnection structure.

[0059] Example 3 Embodiment 3 is substantially the same as Embodiment 1, except that: Bonding auxiliary layer 5 features: polycrystalline, insulating, ZrO2. The surface roughness of bonding auxiliary layer 5 is 0.3 nm, and the surface impurity atomic concentration is 5E14 / cm 3 .

[0060] Characteristics of the amorphous dielectric layer 4: Al2O3.

[0061] The substrate 1 and its embedded metal structure 2 have the following characteristics: the wafer after the post-process (BEOL) RDL wiring is completed, and the embedded metal is W metal.

[0062] Characteristics of the etching stop layer 3: In the dry etching process, the etching rate is slower than that of the amorphous dielectric layer 4. The etching stop layer 3 is SiN.

[0063] Interconnection metal 7 features: Ti. Interconnection metal 7 has no oxide layer at the bonding interface.

[0064] Diffusion barrier and seed layer characteristics: conductive, can prevent the interconnect metal 7 from diffusing into the amorphous dielectric layer 4 and the substrate 1, is Ti, and the seed layer is Cu.

[0065] A method for manufacturing a low temperature hybrid bonding interconnect structure: Providing a first substrate including an embedded metal structure 2; Depositing an etching stop layer 3 on the surface by a physical vapor deposition (PVD) method; Depositing an amorphous dielectric layer 4 on the etching stop layer 3 by using a PVD process; A bonding auxiliary layer 5 is deposited on the amorphous dielectric layer 4, that is, a polycrystalline ZrO2 layer is deposited by magnetron sputtering.

[0066] The bonding auxiliary layer 5 and the amorphous dielectric layer 4 are etched downward through the mask until the lower surface reaches the surface of the substrate 1 and the embedded metal structure 2, thereby forming a countersunk hole; Depositing a diffusion barrier and seed layer on the upper surface of the bonding auxiliary layer 5, the sidewall and the bottom of the countersunk hole; A layer of interconnect metal 7 is deposited by CVD method, and the interconnect metal 7 covers the entire surface; Chemical mechanical polishing (CMP) is used to remove part of the interconnection metal 7, the diffusion barrier layer, the seed layer and part of the bonding auxiliary layer 5, exposing the surface of the bonding auxiliary layer 5, so that the surface roughness of the bonding auxiliary layer 5 is 0.3 nm, and the surface of the interconnection metal 7 is lower than the surface of the bonding auxiliary layer 5, with a height difference of 3 nm; thus obtaining a first interconnection structure 100; Providing a second substrate including an embedded metal structure 2, and repeating the above steps to obtain a second interconnect structure 200; In an ultra-vacuum, oxygen-free environment, plasma is used to bombard the surfaces of the first interconnect structure 100 and the second interconnect structure 200, and the bonding auxiliary layer 5 of the first interconnect structure 100 and the bonding auxiliary layer 5 of the second interconnect structure 200 are bonded together at 60° C., and the interconnect metal 7 is aligned up and down. The bonding vacuum degree is 1E-8 mbar and the temperature is 60° C.

[0067] Annealing is performed at 100° C. so that the interconnection metals 7 of the first interconnection structure 100 and the second interconnection structure 200 are bonded together to obtain a hybrid bonding interconnection structure.

[0068] The advantages of the present invention are: A polycrystalline bonding auxiliary layer 5, typically a polycrystalline AlN material, can be used to bond amorphous media together through ultra-vacuum oxygen-free surface activation bonding technology. Compared with the second technical solution using an amorphous Si nano-adhesive layer, it has greater bonding strength and smaller Cu-Cu interface contact resistance; The ultra-vacuum oxygen-free surface activation bonding technology can achieve oxygen-free and room temperature bonding between Cu-Cu electrodes. Compared with the first technical solution, it has a lower mixed bonding temperature (≤ 150 ℃) and lower Cu-Cu interface resistance. The polycrystalline bonding auxiliary layer 5 material (AlN) can also serve as a barrier layer for Cu diffusion. For example, when there is an alignment error between the upper and lower Cu metals, there is a diffusion channel for Cu metal. If there is only an amorphous dielectric layer 4 (SiO2), Cu can easily diffuse into it. However, when a polycrystalline bonding auxiliary layer 5 is used, Cu cannot diffuse into the amorphous dielectric layer 4 due to the barrier of the polycrystalline bonding auxiliary layer 5. Through doping, the polycrystalline bonding auxiliary layer 5 can also obtain a higher resistivity, thereby achieving a better isolation effect.

[0069] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0070] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A low temperature hybrid bonding interconnect structure, characterized in that: It comprises a first interconnection structure (100) and a second interconnection structure (200), both of which have the same structure; The first interconnect structure (100) and the second interconnect structure (200) both comprise a substrate (1) connected to an embedded metal structure (2), one side of the substrate (1) being sequentially connected to an etching stop layer (3), an amorphous dielectric layer (4), and a bonding auxiliary layer (5); Countersunk holes are provided at positions corresponding to the embedded metal in the middle of the first interconnection structure (100) and the second interconnection structure (200), and the countersunk holes span the bonding auxiliary layer (5), the amorphous dielectric layer (4), and the etching stop layer (3); The inner wall of the countersunk hole is connected to the diffusion barrier and the seed layer (6), and the top surface of the embedded metal structure is free of the diffusion barrier and the seed layer (6); The interconnection metal (7) is embedded in the countersunk holes of the two structures, and the two ends are respectively connected to the embedded metal of the first interconnection structure (100) and the embedded metal of the second interconnection structure (200); the interconnection metal (7), the embedded metal structure (2) of the first interconnection structure (100), and the embedded metal structure (2) of the second interconnection structure (200) can form an electrical connection; The first interconnect structure (100) and the second interconnect structure (200) are directly connected together via surface atomic covalent bonds formed by the bonding auxiliary layers (5) of the two.

2. A low temperature hybrid bonding interconnect structure according to claim 1, characterized in that: The bonding auxiliary layer (5) is polycrystalline and insulating, and its material is AlN, AlON, Al2O3, HfO2 or ZrO2.

3. A low temperature hybrid bonding interconnect structure according to claim 2, characterized in that: The material of the bonding auxiliary layer (5) is polycrystalline AlN, and the bonding auxiliary layers (5) are connected via Al-N bonds rather than Al-O-Al bonds.

4. A low temperature hybrid bonding interconnect structure according to claim 1, characterized in that: The surface roughness of the bonding auxiliary layer (5) is less than 1 nm, and the surface impurity atom concentration is less than 1E15 / cm 3 .

5. The low temperature hybrid bonding interconnect structure according to claim 1, characterized in that: The amorphous dielectric layer (4) is amorphous and insulating, and its material is SiO2, SiN or Al2O3.

6. The low temperature hybrid bonding interconnect structure according to claim 1, characterized in that: The diffusion barrier and seed layer is conductive and can block the interconnect metal (7) from diffusing into the amorphous dielectric layer (4) and the substrate (1), and is made of Ti or Ta.

7. A method for manufacturing a low temperature hybrid bonding interconnect structure, characterized in that: The method comprises the following steps: in an ultra-vacuum, oxygen-free environment, using plasma to bombard the surfaces of a first interconnect structure (100) and a second interconnect structure (200), bonding the bonding auxiliary layer (5) of the first interconnect structure (100) and the bonding auxiliary layer (5) of the second interconnect structure (200) together under low temperature conditions, aligning the interconnect metal (7) up and down, and bonding at a vacuum degree of ≤10 -7 mbar, temperature ≤100℃; Annealing is performed under low temperature conditions of 100 to 150° C., so that the interconnection metals (7) of the first interconnection structure (100) and the second interconnection structure (200) are combined together to obtain a hybrid bonding interconnection structure.

8. The method for manufacturing a low temperature hybrid bonding interconnect structure according to claim 7, characterized in that: Etching the bonding auxiliary layer (5) and the amorphous dielectric layer (4) downwards through a mask until the lower surface reaches the surface of the substrate (1) and the embedded metal structure (2), thereby forming a countersunk hole; Depositing a diffusion barrier and seed layer on the upper surface of the bonding auxiliary layer (5), the sidewalls and the bottom surface of the countersunk hole; Depositing a layer of interconnect metal (7) by CVD or electroplating, wherein the interconnect metal (7) covers the entire surface; Chemical mechanical polishing is used to remove a portion of the interconnection metal (7), the diffusion barrier layer, the seed layer, and a portion of the bonding auxiliary layer (5), exposing the surface of the bonding auxiliary layer (5), so that the surface roughness of the bonding auxiliary layer (5) is less than 1 nm, the surface of the interconnection metal (7) is lower than the surface of the auxiliary layer, and the height difference is less than 10 nm; a first interconnection structure (100) is obtained, and a second interconnection structure (200) is processed using the same method.

9. The method for manufacturing a low temperature hybrid bonding interconnect structure according to claim 8, characterized in that: Provided are a first substrate (1) and a second substrate (1) comprising an embedded metal structure (2) and used to form a first interconnect structure (100) and a second interconnect structure (200) respectively; Depositing an etching stop layer (3) on the surface of the first substrate (1) by a physical vapor deposition or chemical vapor deposition method; Depositing an amorphous dielectric layer (4) on the etching stop layer (3) using a PVD or CVD process; Depositing a bonding auxiliary layer (5) on the amorphous dielectric layer (4); The processing method of the second substrate (1) is the same as that of the first substrate (1).

10. The method for manufacturing a low temperature hybrid bonding interconnect structure according to claim 9, characterized in that: A layer of polycrystalline AlN bonding auxiliary layer (5) is deposited by magnetron sputtering or pulse laser sputtering. During the deposition process, Y2O3 impurities are doped to enhance the insulation capability of the polycrystalline AlN bonding auxiliary layer (5).

Images