Sparse matrix distributed solution method, computer equipment and storage medium

Abstract

The invention provides a sparse matrix distributed solution method, computer equipment and a storage medium, which are used for simulation of a circuit and an electromagnetic field, and the method comprises the following steps: generating a super node based on an elimination tree of a matrix generated in a simulation process; constructing an assembly tree according to the elimination tree and the super nodes; constructing a wavefront matrix according to the rows and columns of the matrix corresponding to the super nodes; traversing the assembly tree layer by layer, and carrying out parallel calculation on complete assembly blocks and incomplete assembly blocks of the wavefront matrix on the same layer of the assembly tree; according to the incomplete assembly blocks of each layer, the complete assembly blocks of the next layer of the assembly tree are updated until the last layer of the assembly tree is reached; and ending the traversal of the assembly tree, and solving an equation LUx = b by using the complete assembly blocks of all the wavefront matrixes. According to the scheme, the solving speed can be greatly improved, memory occupation is reduced, and simulation of a circuit and an electromagnetic field is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit and electromagnetic field simulation, and in particular to a sparse matrix distributed solution method, computer equipment and storage medium. Background Art

[0002] In EDA circuit and electromagnetic field finite element simulation, the time and memory consumption of matrix solving occupy the vast majority of the entire simulation cycle. For complex PCBs, if you want to simulate accurately, the unknown numbers in the equations are often tens of millions, resulting in very low efficiency in matrix solving. Therefore, a low-time matrix solving method is urgently needed. Summary of the invention

[0003] The purpose of the present invention is to provide a sparse matrix distributed solution method, computer equipment and storage medium, which can greatly improve the solution speed, reduce memory usage, and facilitate the simulation of circuits and electromagnetic fields.

[0004] The technical solution provided by the present invention is as follows: In a first aspect, the present invention provides a sparse matrix distributed solution method for circuit and electromagnetic field simulation, comprising the steps of: Generate supernodes based on the elimination tree of the matrix generated during the simulation; constructing an assembly tree based on the elimination tree and the supernodes; Constructing a wavefront matrix according to the rows and columns of the matrix corresponding to the supernode; Traversing the assembly tree layer by layer, and calculating in parallel the complete assembly blocks and incomplete assembly blocks of the wavefront matrix at the same layer of the assembly tree, wherein the complete assembly blocks are dense matrix blocks formed when the wavefront matrix is ​​constructed according to the super nodes, and the incomplete assembly blocks are matrix blocks other than the dense matrix blocks; According to the incomplete assembly blocks of each layer, the complete assembly blocks of the next layer of the assembly tree are updated until the last layer of the assembly tree is reached; The traversal of the assembly tree is terminated, and the equation LUx=b is solved using the fully assembled blocks of all the wavefront matrices.

[0005] This scheme uses super nodes to aggregate multiple wavefront matrices into a larger wavefront matrix, and makes each wavefront matrix have approximately the same amount of data, so that the calculation load is more balanced, the calculation efficiency of the wavefront matrix is ​​improved, and the efficiency of matrix solution is greatly accelerated. It also reduces the memory usage during the calculation process, which is beneficial to the simulation of circuits and electromagnetic fields.

[0006] In some implementations, the elimination tree based on the matrix generated during the simulation process generates a supernode, specifically including: Based on the elimination tree of the matrix, nodes with the same fill-in value are merged to form a first supernode; Each of the first super nodes having a parent-child relationship in the elimination tree is merged into a second super node, so that the number of non-zero elements of each of the second super nodes is within a preset range.

[0007] In some embodiments, constructing an assembly tree according to the elimination tree and the supernodes specifically includes: According to the structure of the supernode, the nodes in the elimination tree belonging to the same supernode are merged to form a new elimination tree as the assembly tree.

[0008] In some implementations, traversing the assembly tree layer by layer and calculating in parallel the complete assembly blocks and the incomplete assembly blocks of the wavefront matrix at the same layer of the assembly tree specifically include: According to the nodes of the assembly tree, the assembly tree is traversed layer by layer, and the wavefront matrices at the same layer of the assembly tree are allocated to different computing nodes; The completely assembled block is calculated first, and then the incompletely assembled block is calculated.

[0009] In some implementations, updating the complete assembly blocks of a next layer of the assembly tree according to the incomplete assembly blocks of each layer specifically includes: The fully assembled block of the parent wavefront matrix of the current wavefront matrix is ​​subtracted from the incompletely assembled block of the current wavefront matrix to obtain an updated fully assembled block of the parent wavefront matrix, and the memory of the incompletely assembled block of the current wavefront matrix is ​​released after the calculation is completed.

[0010] In some embodiments, the fully assembled block is used to solve the upper and lower triangular matrix blocks of the LU decomposition of the matrix; The incomplete assembly block is used to update data for the parent node of the wavefront matrix of the current layer.

[0011] In a second aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a sparse matrix distributed solution method described in the first aspect.

[0012] In a third aspect, the present application provides a computer storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the steps of a sparse matrix distributed solution method described in the first aspect.

[0013] In a fourth aspect, the present application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of a sparse matrix distributed solution method described in the first aspect.

[0014] According to a sparse matrix distributed solution method, computer device and storage medium provided by the present invention, by utilizing super nodes, multiple wavefront matrices can be aggregated into a larger wavefront matrix, and each wavefront matrix has approximately the same amount of data, thereby making the calculation load more balanced, improving the calculation efficiency of the wavefront matrix, and thus greatly accelerating the efficiency of matrix solution, and reducing memory usage during the calculation process, which is beneficial to the simulation of circuits and electromagnetic fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0016] Figure 1 It is a schematic diagram of the overall process of an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0018] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0019] In EDA circuit and electromagnetic field finite element simulation, the time and memory consumption of matrix solving occupy the vast majority of the entire simulation cycle. For complex PCBs, if you want to simulate accurately, the unknown numbers in the equations are often tens of millions, resulting in very low efficiency in matrix solving. Therefore, a low-time matrix solving method is urgently needed.

[0020] Generally, large-scale sparse matrix solutions are mostly solved by iterative methods. The iterative method mainly relies on the spMv operator, which is simple to implement, easy to accelerate, and has low memory consumption, and does not need to process a large number of fill-in values. However, the limitations of the iterative method are also very obvious: poor stability, and it is difficult to converge without a suitable preprocessor. Especially when dealing with complex systems in EDA, the condition number of the solution matrix is ​​often above 1e13. Even if the tolerance of the iterative method reaches the order of 1e-13, the absolute error of the equation is far lower than the accuracy requirement. Therefore, the iterative method in EDA software needs to use the approximation of the incomplete decomposition of the direct method as the preprocessing operator of the iterative method. Only the preprocessing matrix obtained by the direct method can effectively reduce the condition number of the solution matrix, accelerate the convergence of the iteration, and improve the operation speed.

[0021] In EDA simulation, the performance of the direct method for solving matrices determines the efficiency of EDA simulation. Although the direct method for solving matrices consumes a lot of memory, the direct method is stable and accurate, which is the golden standard for EDA simulation. More importantly, in EDA simulation, it is often necessary to solve sparse matrices of the same structure. Because the direct method uses LU decomposition, it can save frequent symbolic decomposition or numerical decomposition when solving multiple times, and quickly solve the matrix.

[0022] The matrix solution of the direct method includes four parts: matrix preprocessing, symbolic decomposition, numerical decomposition, and solution. The numerical decomposition part accounts for more than 90% of the time and memory consumption. Improving the solution speed of numerical decomposition is the core of an efficient matrix solver. For complex PCBs, the scale of matrix solution reaches tens of millions or even hundreds of millions. The distributed solution method is a better method for large-scale matrix solution. The multi-frontal algorithm, also known as the multi-wavefront algorithm, is a distributed solution method. This solution uses the multi-wavefront algorithm for large-scale matrix solution. The core idea of ​​the multi-wavefront algorithm is to decompose a large-scale linear equation system into multiple small subsystems (called "wavefronts") and gradually solve each subsystem through iteration. The wavefront division method enables the algorithm to make full use of the parallel processing capabilities of modern computers, thereby improving efficiency. Solving matrices using the multi-wavefront algorithm has the following advantages: the original sparse matrix is ​​decomposed into multiple "wavefronts", which correspond to different calculation stages. Each wavefront is a submatrix, usually obtained by matrix filling operations. Each submatrix is ​​small in size and can be solved independently. Gaussian elimination or other solution methods can be performed in each wavefront. The solution of each subsystem is independent and connected to the subsequent wavefronts through elimination. Since each wavefront can be calculated independently on different processing units, the multi-wavefront algorithm can adapt well to the parallel computing architecture and reduce the calculation time. After each wavefront is processed, the solution will be merged into the previous wavefront until the complete solution to the linear equations is finally obtained.

[0023] However, since the equation matrices in EDA simulation design are often very sparse, a wavefront matrix may only have a dozen or dozens of elements, which is very small in scale. Repeated calculation of many wavefront matrices with small data volumes is very inefficient. In addition, due to differences in matrix structure, the amount of calculation of multiple wavefront matrices may differ by ten or even a hundred times the amount of data, which makes the load on each computing node vary greatly, and the efficiency of parallelization is also reduced. Therefore, using only the multi-wavefront algorithm for large-scale sparse matrix solving still cannot maximize the computing efficiency.

[0024] This application proposes a supernode-multi-wavefront matrix data structure, combining supernodes with multi-wavefront algorithms. By first constructing a supernode based on a sparse matrix, and then constructing a wavefront matrix based on the supernode, it is equivalent to aggregating multiple wavefront matrices into several larger wavefront matrices. Parallel calculations with the wavefront matrix can greatly accelerate the matrix solution speed, thereby improving the simulation speed of circuits and electromagnetic fields. The following is a detailed description of this scheme in conjunction with the accompanying drawings: In one embodiment, the reference specification Figure 1 The present invention provides a sparse matrix distributed solution method for circuit and electromagnetic field simulation, comprising the steps of: S100. Generate super nodes based on the elimination tree of the matrix generated during the simulation process. In the process of EDA circuit and electromagnetic field simulation calculation, matrix solving is often indispensable. These matrices are not only huge in scale, but also have a large number of matrix element values ​​of zero. If the traditional dense matrix solving algorithm is used, the invalid calculation will be greatly increased. Therefore, an efficient sparse matrix solving algorithm needs to analyze the pattern of non-zero elements in the matrix, that is, the arrangement of non-zero values ​​of the elements in the matrix. Only the items with non-zero elements in the matrix are calculated, which greatly reduces the situation of 0×a = 0, and accelerates the solution of the matrix more efficiently. LU decomposition of the matrix is ​​the core of various matrix solving problems. The most common matrix decomposition algorithm, the left-looking algorithm, adopts the strategy of column decomposition. The elements of each column of the matrix are solved from left to right. The current solving column is determined by the calculation results of the columns that have been decomposed on its left. Each column is regarded as a node, and the numerical results of each column can be regarded as the dependency of the current node on the nodes that have been solved. Such dependency relationships can form a tree structure, which is called an elimination tree. The relationship between nodes determines the numerical dependency in the decomposition algorithm. To solve any node, its child nodes need to complete the solution, so as to completely determine its numerical solution. In EDA circuits or electrical simulation systems, a matrix graph structure called a cluster is usually formed. The so-called cluster represents the connection between n nodes of the matrix. Because of this cluster structure, many adjacent column nodes can be regarded as a large node. The non-zero element patterns of these nodes are completely consistent. We call them super nodes. Because the nodes of the super node are interconnected, their topological relationship makes the matrix block composed of these nodes no longer a sparse matrix, but a dense matrix block. Not only does it make the node that needs to be solved n times become a decomposition of the super node, but the sparse matrix originally scattered with non-zero elements becomes a dense matrix block, which greatly improves the efficiency of the solution.

[0025] S200, constructing an assembly tree according to the elimination tree and supernodes. After obtaining the elimination tree and supernodes according to the sparse matrix, this solution will further construct a more compact tree structure according to the elimination tree and supernodes to further improve the calculation efficiency. This application refers to it as an assembly tree. In other embodiments, other naming methods can also be used, and this application does not limit it.

[0026] S300, constructing a wavefront matrix according to the rows and columns of the matrix corresponding to the supernode. After the supernode is generated, multiple interconnected nodes can be calculated uniformly. The present application constructs a wavefront matrix based on the supernode. Compared with directly constructing a wavefront matrix based on a sparse matrix, it is equivalent to aggregating multiple wavefront matrices into several larger wavefront matrices, and performing parallel calculations with the larger wavefront matrices.

[0027] S400, traverse the assembly tree layer by layer, and parallelly calculate the complete assembly blocks and incomplete assembly blocks of the wavefront matrix of the same layer of the assembly tree. The complete assembly block is a dense matrix block formed when the wavefront matrix is ​​constructed according to the super node, and the incomplete assembly block is a matrix block other than the dense matrix block. When performing specific calculations, due to the characteristics of the wavefront matrix, parallel calculations can be performed. According to the level of the assembly tree, the calculation is performed layer by layer. After each layer is calculated, the next layer is calculated until all layers of the assembly tree are traversed. The complete assembly block and the incomplete assembly block are a definition method of the wavefront matrix structure in this application. The complete assembly block is a dense matrix block formed when the wavefront matrix is ​​constructed according to the super node, and the incomplete assembly block is a relatively sparse matrix block other than the dense matrix block. Since there is a parent-child relationship between the nodes of each layer of the tree structure, the complete assembly block of the next layer can be updated through the incomplete assembly block, thereby ensuring that the calculation of all matrix blocks of the wavefront matrix is ​​completed, and the calculation efficiency can be improved, and the calculation of the relatively sparse incomplete assembly block is prevented from affecting the overall calculation efficiency of the sparse matrix. In other embodiments, other naming methods may be used for the completely assembled blocks and the incompletely assembled blocks, and this application does not limit this.

[0028] S500, according to the incomplete assembly blocks of each layer, the complete assembly blocks of the next layer of the assembly tree are updated until the last layer of the assembly tree is reached. As described above, when calculating the wavefront matrix of each layer, according to the parent-child relationship between the nodes of each layer of the assembly tree, according to the incomplete assembly blocks of each layer, the complete assembly blocks of the next layer of the assembly tree can be updated, thereby ensuring the complete solution of the wavefront matrix and further improving the calculation efficiency.

[0029] S600, end the traversal of the assembly tree, and use the complete assembly blocks of all wavefront matrices to solve the equation LUx=b. Since the incomplete assembly blocks of each layer of the assembly tree can update the complete assembly blocks of the next layer, the sparse matrix can be solved according to the complete assembly blocks of all wavefront matrices. As for the incomplete assembly blocks of the last layer, since the present application is aggregated multiple times through super nodes, assembly trees, etc., the data volume of the incomplete assembly blocks itself is relatively small, and the incomplete assembly blocks of other layers of the assembly tree except the last layer are involved in the update of the complete assembly blocks of the next layer. Therefore, the data volume of the incomplete assembly blocks of the last layer is even smaller. If the calculation accuracy requirement for the sparse matrix is ​​not extremely high, it can be directly ignored. If the accuracy requirement is extremely high, the calculation of the incomplete assembly blocks of the last layer can be added. Since the data volume of the incomplete assembly blocks of this layer is extremely small, the calculation of the incomplete assembly blocks of this layer will have a relatively small impact on the overall calculation efficiency.

[0030] The present application combines supernodes with multi-wavefront algorithms through the data structure of supernode-multi-wavefront matrix. By first constructing a supernode based on a sparse matrix and then constructing a wavefront matrix based on the supernode, it is equivalent to aggregating multiple wavefront matrices into several larger wavefront matrices. Parallel calculations are performed using the wavefront matrix, which can greatly accelerate the matrix solution speed, thereby improving the simulation speed of circuits and electromagnetic fields.

[0031] In a specific implementation, generating a supernode based on an elimination tree of a matrix generated during a simulation process specifically includes: S110, based on the elimination tree of the matrix, merging nodes with the same filled-in value to form a first supernode; S120: Merge first super nodes having a parent-child relationship in the elimination tree into second super nodes, so that the number of non-zero elements of each second super node is within a preset range.

[0032] After obtaining the elimination tree and the supernode (the first supernode), in order to avoid differences in the amount of calculation of each wavefront matrix, resulting in huge differences in the load on each computing node, the first supernode can be further processed. Since some supernodes of the elimination tree have a parent-child relationship, the first supernode with a parent-child relationship in the elimination tree can be merged into a second supernode in the application, and the number of non-zero elements of each second supernode is within a preset range, that is, the number of non-zero elements of each supernode is kept as consistent as possible, so that the amount of calculation of each wavefront matrix is ​​basically consistent. The preset range can be adjusted according to the load limit and computing speed requirements of the system, and the application does not impose any restrictions.

[0033] In a specific implementation, constructing an assembly tree based on the elimination tree and the supernode specifically includes: according to the structure of the supernode, merging the nodes in the elimination tree that belong to the same supernode to form a new elimination tree as an assembly tree. Through the assembly tree, the efficiency of solving the matrix can be further improved.

[0034] In a specific implementation, a wavefront matrix is ​​constructed according to the rows and columns of the matrix corresponding to the supernode, specifically including: forming a number of dense matrix blocks according to the members of the supernode using the values ​​of each element of the matrix, using each dense matrix block as a complete assembly block and other matrix blocks as incomplete assembly blocks to construct the wavefront matrix. For example, a supernode is composed of three nodes 3, 4 and 5, then the three dense matrix blocks correspond to A[3:5,3:5], A[3:5,:] and A[:, 3:5] respectively. For the convenience of description, they are written as A11, A12, A21 respectively, and these three dense matrix blocks are called complete assembly blocks.

[0035] In a specific implementation, the assembly tree is traversed layer by layer, and the complete assembly blocks and incomplete assembly blocks of the wavefront matrix at the same layer of the assembly tree are calculated in parallel, specifically including: according to the nodes of the assembly tree, the assembly tree is traversed layer by layer, and the wavefront matrices at the same layer of the assembly tree are assigned to different computing nodes; the complete assembly blocks are calculated first, and then the incomplete assembly blocks are calculated.

[0036] Taking the three dense matrix blocks A11, A12, and A21 as an example, when calculating, the fully assembled blocks are calculated first: A11 = L11 × U11 A12 = inv(L11)×A12 ==> U12 A21 = A21×inv(U11) ==> L12 Then calculate the incomplete assembly block S = L21 × U12.

[0037] The fully assembled block is used to solve the upper and lower triangular matrix blocks of the LU decomposition of the matrix, and the incomplete assembled block is used to update the data for the parent node of the wavefront matrix of the current layer. According to the incomplete assembled blocks of each layer, the fully assembled blocks of the next layer of the assembly tree are updated, specifically including: subtracting the incomplete assembled blocks of the current wavefront matrix from the fully assembled blocks of the parent wavefront matrix of the current wavefront matrix to obtain the updated fully assembled blocks of the parent wavefront matrix, and releasing the memory of the incomplete assembled blocks of the current wavefront matrix after the calculation is completed. For example, the parent wavefront matrix of the current wavefront matrix is ​​defined as B, and the incomplete assembled blocks of the current wavefront matrix are subtracted from the fully assembled blocks of the parent wavefront matrix of the current wavefront matrix, that is: B11 = B11 - S, to obtain the updated fully assembled blocks of the parent wavefront matrix, and then release the memory of the incomplete assembled block S.

[0038] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a sparse matrix distributed solution method of the aforementioned embodiment.

[0039] In one embodiment, the present application provides a computer storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the steps of a sparse matrix distributed solution method of the aforementioned embodiment.

[0040] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements the steps of a sparse matrix distributed solution method of the aforementioned embodiment.

[0041] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0042] The memory may be an internal storage unit of the simulation system, such as a hard disk or memory of an intelligent device. The memory may also be an external storage device of the intelligent device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the intelligent device. Further, the memory is used to store the computer program and other programs and data required by the verification method of the FPGA. The memory may also be used to temporarily store data that has been output or is to be output.

[0043] The communication bus is a circuit that connects the elements described and implements transmission between these elements. For example, the central processing unit receives commands from other elements through the communication bus, decrypts the received commands, and performs calculations or data processing according to the decrypted commands. The memory may include program modules, such as a kernel, middleware, an application programming interface (API) and an application. The program module may be composed of software, firmware or hardware, or at least two of them. The input / output interface forwards commands or data entered by the user through the input / output interface (such as a sensor, keyboard, touch screen). The communication interface connects the speed measurement device of the artificial heart with other network devices, user devices, and networks. For example, the communication interface can be connected to the network via wired or wireless connection to connect to other external network devices or user devices. Wireless communication may include at least one of the following: wireless fidelity (WiFi), Bluetooth (BT), near field communication technology (NFC), global satellite positioning system (GPS) and cellular communication, etc. Wired communication may include at least one of the following: universal serial bus (USB), high-definition multimedia interface (HDMI), asynchronous transmission standard interface (RS-232), etc. The network may be a telecommunication network and a communication network. The communication network may be a computer network, the Internet, the Internet of Things, or a telephone network. The verification device of the FPGA may be connected to the network via a communication interface, and the protocol used by the speed measuring device of the artificial heart and other network devices to communicate may be supported by at least one of an application, an application programming interface (API), a middleware, a kernel, and a communication interface.

[0044] A sparse matrix distributed solution method of the present application can be implemented with program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0045] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A sparse matrix distributed solution method for circuit and electromagnetic field simulation, characterized in that: Includes steps: Generate supernodes based on the elimination tree of the matrix generated during the simulation; constructing an assembly tree based on the elimination tree and the supernodes; Constructing a wavefront matrix according to the rows and columns of the matrix corresponding to the supernode; Traversing the assembly tree layer by layer, and calculating in parallel the complete assembly blocks and incomplete assembly blocks of the wavefront matrix at the same layer of the assembly tree, wherein the complete assembly blocks are dense matrix blocks formed when the wavefront matrix is ​​constructed according to the super nodes, and the incomplete assembly blocks are matrix blocks other than the dense matrix blocks; According to the incomplete assembly blocks of each layer, the complete assembly blocks of the next layer of the assembly tree are updated until the last layer of the assembly tree is reached; The traversal of the assembly tree is terminated, and the equation LUx=b is solved using the fully assembled blocks of all the wavefront matrices.

2. A sparse matrix distributed solution method according to claim 1, characterized in that: The elimination tree based on the matrix generated in the simulation process generates a supernode, specifically including: Based on the elimination tree of the matrix, nodes with the same fill-in value are merged to form a first supernode; Each of the first super nodes having a parent-child relationship in the elimination tree is merged into a second super node, so that the number of non-zero elements of each of the second super nodes is within a preset range.

3. A sparse matrix distributed solution method according to claim 1, characterized in that: The step of constructing an assembly tree according to the elimination tree and the supernodes specifically includes: According to the structure of the supernode, the nodes in the elimination tree belonging to the same supernode are merged to form a new elimination tree as the assembly tree.

4. A sparse matrix distributed solution method according to claim 1, characterized in that: The step of traversing the assembly tree layer by layer and calculating in parallel the complete assembly blocks and the incomplete assembly blocks of the wavefront matrix at the same layer of the assembly tree specifically includes: According to the nodes of the assembly tree, the assembly tree is traversed layer by layer, and the wavefront matrices at the same layer of the assembly tree are allocated to different computing nodes; The completely assembled block is calculated first, and then the incompletely assembled block is calculated.

5. A sparse matrix distributed solution method according to claim 1, characterized in that: The updating of the complete assembly blocks of the next layer of the assembly tree according to the incomplete assembly blocks of each layer specifically includes: The fully assembled block of the parent wavefront matrix of the current wavefront matrix is ​​subtracted from the incompletely assembled block of the current wavefront matrix to obtain an updated fully assembled block of the parent wavefront matrix, and the memory of the incompletely assembled block of the current wavefront matrix is ​​released after the calculation is completed.

6. A sparse matrix distributed solution method according to claim 1, characterized in that: The fully assembled block is used to solve the upper and lower triangular matrix blocks of the LU decomposition of the matrix; The incomplete assembly block is used to update data for the parent node of the wavefront matrix of the current layer.

7. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of a sparse matrix distributed solution method as described in any one of claims 1-6.

8. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of a sparse matrix distributed solution method described in any one of claims 1 to 6 are implemented.

9. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of a sparse matrix distributed solution method described in any one of claims 1 to 6 are implemented.

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