Ferroelectric transistor capable of generating thousands of polarization states and preparation and use method thereof

Abstract

The invention discloses a ferroelectric transistor capable of generating thousands of polarization states and a preparation and use method thereof, the ferroelectric transistor is prepared based on a Gr / hBN heterojunction, the top layer of the heterojunction is a Gr sheet, the bottom layer of the heterojunction is an hBN sheet, the rotation angle between Gr and hBN is controlled within 1 degree through dry transfer, and the Gr / hBN heterojunction is fixed on a silicon wafer substrate (SiO2 / Si); and further depositing a source electrode and a drain electrode through electron beam exposure and electron beam evaporation processes to construct the Gr / hBN ferroelectric transistor. A single device can generate dozens of discrete polarization states through source-drain pulse modulation; meanwhile, the Fermi level of the graphene can be reversibly adjusted among dozens of nonvolatile doping levels by overlapping the grid voltage while the source-drain pulse acts, and the polarization state can be modulated through the source-drain pulse at each doping level; the number of stable polarization states reaches thousands at room temperature; different polarization states may be retained for more than 105 seconds, and may be maintained for more than 10 years according to linear extrapolation.

Description

Technical Field

[0001] The present invention relates to the field of ferroelectric functional devices, and in particular to a ferroelectric transistor capable of generating thousands of polarization states and a preparation and use method thereof. Background Art

[0002] Large-scale neural networks require the measurement of billions of parameters, where the huge data throughput poses a major challenge to existing hardware architectures. Emerging neuromorphic computing is an effective way to overcome this dilemma, which requires the realization of multiple stable states in a single unit to improve computing accuracy and storage density, thereby efficiently completing complex data-intensive tasks. In this context, ferroelectric materials that can produce multiple electrically addressable polarization states have developed into strong candidates for neuromorphic hardware. Despite extensive efforts in traditional three-dimensional ferroelectrics and recently emerging two-dimensional ferroelectrics, the number of stable polarization states created at room temperature does not exceed 32, which severely limits the applicability of existing ferroelectrics in future neuromorphic hardware. In response to the shortcomings of the prior art, the present invention discloses a ferroelectric transistor that can generate thousands of polarization states, which is two orders of magnitude higher than the optimal value of existing ferroelectric systems. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a ferroelectric transistor capable of generating thousands of polarization states and a method for preparing and using the same in view of the defects involved in the background technology.

[0004] The present invention adopts the following technical solutions to solve the above technical problems: A ferroelectric transistor capable of generating thousands of polarization states, which is a vertical stacking structure, comprising a Gr thin sheet, an hBN thin sheet and a silicon wafer substrate from top to bottom; The Gr thin sheet and the hBN thin sheet are combined by van der Waals force to form a Gr / hBN heterojunction; The hBN thin sheet is fixed on the upper surface of the silicon wafer substrate; The upper surface of the silicon wafer substrate is provided with metal electrodes connected to the two ends of the Gr thin slice, namely, a source electrode and a drain electrode; A gate is arranged on the lower surface of the silicon wafer substrate.

[0005] As a further optimization scheme of the ferroelectric transistor of the present invention that can generate thousands of room temperature non-volatile polarization states, the thickness of the Gr thin sheet is 0.3-2 nm, and the thickness of the hBN thin sheet is 20 nm.

[0006] The present invention also discloses a method for preparing the ferroelectric transistor capable of generating thousands of polarization states, comprising the following steps: Step 1), strip-shaped Gr thin sheets and strip-shaped hBN thin sheets are peeled off respectively and placed on different silicon wafer substrates; Step 2), preparing a PPC / PDMS transfer carrier; Step 2.1), the cut PDMS is placed on a clean glass slide, and the surface of the PDMS is treated with oxygen plasma; Step 2.2), spin coating the PPC reagent on the PDMS surface, and then placing it on a hot plate and heating it to form a PPC film; Step 2.3), using oxygen plasma to treat the surface of the PPC film to obtain a PPC / PDMS transfer carrier; Step 3), preparing a PC film, and covering the PC film on a PPC / PDMS transfer carrier to obtain a PC / PPC / PDMS dry transfer carrier; Step 4), at a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered on the Gr thin slice, the PC / PPC / PDMS dry transfer carrier is slowly lifted to stick the target Gr thin slice from the silicon wafer substrate, and then the Gr thin slice is attached to the hBN thin slice on the silicon wafer substrate; then, the PPC / PC film is heated to melt and release heat to the silicon wafer substrate, and then, the PDMS carrier is slowly removed to form a Gr / hBN heterojunction on the silicon wafer substrate; finally, the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon wafer substrate are cleaned; Step 5), placing the Gr / hBN heterojunction on the silicon wafer substrate horizontally so that the Gr sheet is located at the top; Step 6), spin coating PMMA on the upper surface of the silicon wafer substrate at a speed higher than a preset speed threshold and then heating until the solvent in the PMMA evaporates to form a PMMA layer; Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon wafer substrate covers the Gr thin sheet; Step 8), using a field emission electron microscope and an electron beam exposure system to expose the source and drain electrodes on the PMMA layer, followed by development to expose the source and drain regions, and then using an electron beam deposition device to evaporate Ti / Au on the source and drain regions; Step 9), post-processing is performed to remove the PMMA-carrying metal thin layer in the unexposed area; then cleaning and drying are performed to obtain a quasi-ferroelectric transistor with a source and a drain; Step 10), a wire is led out from the lower surface of the silicon wafer substrate as a gate to obtain a Gr / hBN ferroelectric transistor.

[0007] As a further optimization scheme of the preparation method of the ferroelectric transistor capable of generating thousands of polarization states of the present invention, the detailed steps of peeling off the Gr thin sheet and the hBN thin sheet in step 1) are as follows: Step 1.1), using an oxygen plasma system to clean the silicon wafer to increase the bonding strength between the silicon wafer and the Gr thin film and the hBN thin film; Step 1.2), use blue tape to stick a little Gr crystal and hBN crystal respectively, and then cover the tape on the silicon wafer; Step 1.3), place the silicon wafer covered by the blue tape on a hot plate to heat it to enhance the adhesion between the tape and the silicon wafer; In step 1.4, the silicon wafer covered by the blue tape is removed from the hot plate, and after cooling, the blue tape is slowly peeled off, and the Gr and hBN wafers are obtained by mechanical peeling.

[0008] As a further optimization scheme of the preparation method of a ferroelectric transistor capable of generating thousands of polarization states of the present invention, the detailed steps of preparing the PC film in step 3) are as follows: PC reagent is dropped on the upper surface of glass slide No. 1, and then the lower surface of glass slide No. 2 is covered on the upper surface of glass slide No. 1, and finally glass slides No. 1 and No. 2 are horizontally dragged and separated, thereby forming a layer of prepared PC film on the upper surface of glass slide No. 1 and the lower surface of glass slide No. 2, respectively.

[0009] As a further optimization scheme of the preparation method of a ferroelectric transistor capable of generating thousands of polarization states of the present invention, the mass fraction of the PPC reagent is 15% by mass, and the solvent is anisole.

[0010] As a further optimization scheme of the preparation method of the ferroelectric transistor capable of generating thousands of polarization states of the present invention, the mass fraction of the PC reagent is 5%, and the solvent is dichloromethane.

[0011] As a further optimization scheme of the preparation method of the ferroelectric transistor capable of generating thousands of polarization states of the present invention, when cleaning the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon wafer substrate in step 4), they are sequentially placed in dichloromethane for 20 minutes, acetone for 15 minutes, and isopropanol for 5 minutes for cleaning.

[0012] The present invention also discloses a method for using the ferroelectric transistor that can generate thousands of polarization states, by applying direct current pulses to the Gr channels of the source and drain to tune the ferroelectric polarization states; at the same time, the gate voltage is preset to control the injection and discharge of carriers into and out of the Gr channel, thereby achieving non-volatile doping of the Gr channel.

[0013] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: The present invention provides a ferroelectric transistor capable of generating thousands of polarization states and a method for preparing the same. At room temperature, by applying a DC pulse (Vpulse) between the source-drain electrodes, the ferroelectric transistor can generate 56 stable and discrete polarization states; by setting the gate voltage (VG_Pre) while applying a source-drain pulse stack, the Dirac peak of graphene can be reversibly locked at no less than 84 doping levels; at each doping level, no less than 36 polarization states can be precisely modulated by the source-drain pulse, thereby significantly increasing the number of adjustable polarization states to 3024; different polarization states can retain more than 10 5 seconds, and potentially over 10 years based on linear extrapolation, thus enabling nonvolatile multi-state operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure and working principle of a Gr / hBN ferroelectric transistor in an embodiment of the present invention; Figure 2 (a) is a schematic diagram of modulating multi-state polarization in a Gr / hBN ferroelectric transistor by a source-drain pulse in an embodiment of the present invention, Figure 2 (b) Schematic diagram of the channel current corresponding to 56 discrete polarization states as a function of time; Figure 3 Schematic diagram of the stability of the channel current corresponding to different polarization states of the Gr / hBN ferroelectric transistor in an embodiment of the present invention; Figure 4 Schematic diagram of transfer curves of Gr / hBN ferroelectric transistors at different doping levels at 1.5 K in an embodiment of the present invention; Figure 5 Schematic diagram of the transfer curve of the Gr / hBN ferroelectric transistor under different doping levels at 300 K in an embodiment of the present invention; Figure 6 (a) shows the Gr / hBN ferroelectric transistor in the embodiment of the present invention. V G_Pre = 0, 1, 2, 3, 4, 5 V, schematic diagram of the change of channel current modulated by positive source-drain pulse over time; Figure 6 (b) Figure 6 (a) Corresponding device weight ( W d ) Schematic diagram of changes over time; Figure 7 (a) shows the Gr / hBN ferroelectric transistor in the embodiment of the present invention. V G_Pre = 5, 4, 3, 2, 1, 0 V conditions, schematic diagram of the change of channel current modulated by negative source-drain pulses over time; Figure 7 (b) Figure 7 (a) Schematic diagram of the corresponding device weight changing over time; Figure 8 To dynamically adjust V pulse and V G_Pre , a schematic diagram of the change of 3024 polarization states over time demonstrated by the Gr / hBN ferroelectric transistor in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings: The present invention can be implemented in many different forms and should not be considered to be limited to the embodiments described herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully express the scope of the present invention to those skilled in the art. In the accompanying drawings, components are enlarged for clarity.

[0016] like Figure 1 As shown, the present invention discloses a ferroelectric transistor capable of generating thousands of polarization states, which is a vertical stacking structure, and includes a Gr thin slice, an hBN thin slice and a silicon wafer substrate from top to bottom; The Gr thin sheet and the hBN thin sheet are combined by van der Waals force to form a Gr / hBN heterojunction; The hBN thin sheet is fixed on the upper surface of the silicon wafer substrate; The upper surface of the silicon wafer substrate is provided with metal electrodes connected to the two ends of the Gr thin slice, namely, a source electrode and a drain electrode; A gate is arranged on the lower surface of the silicon wafer substrate.

[0017] The thickness of the Gr sheet is preferably 0.3-2 nm, and the thickness of the hBN sheet is preferably 20 nm.

[0018] like Figure 1 As shown, when the present invention is used, the ferroelectric polarization state is tuned by applying a DC pulse to the Gr channel of the source and drain; at the same time, the gate voltage is preset to control the injection and discharge of carriers into and out of the Gr channel, thereby achieving non-volatile doping of the Gr channel.

[0019] The reagents and instruments required for the preparation of the embodiments of the present invention are as follows: Graphite crystal (HQ graphene); hBN crystal (HQ graphene); Silicon wafer (University, 300 nm SiO2 / Si); Blue tape for mechanical stripping (ultronsystems); White tape (3M); PDMS (DOW CORNING 184); PC (Sigma-Aldrich); PPC (Sigma-Aldrich); PMMA (MicroChem 495 A4); Dichloromethane (Bai Lingwei, pesticide residue grade 99.9%); Anisole (alladin, chromatography grade 99.9%); Acetone (Vokay, chromatography grade 99.9%); Isopropyl alcohol (Tedia, chromatography grade 99.9%); Two-dimensional material transfer station (Meita Optoelectronics), electron beam deposition equipment (Syskey E-Beam Evaporationsystem), oxygen plasma system (Femto Scince Convance), spin coater (Spin Processor POLOS), optical microscope (Nikon LV100ND), field emission electron microscope (Zeiss Sigma 300), electron beam exposure system (RaithQuantum), atomic force microscope (SmartSPM-1000), Raman spectrometer (Horiba JY Labram EVO, 532nm), low-temperature transport equipment (OXFORD TeslatronPT), source meter (Keithley 2400 / Keithley 6430).

[0020] The specific preparation method comprises the following steps: Step 1), strip-shaped Gr thin sheets and strip-shaped hBN thin sheets are peeled off respectively and placed on different silicon wafer substrates; Step 1.1), using an oxygen plasma system to clean the silicon wafer at 50W / 50sccm / 2min to increase the bonding strength between the silicon wafer and the Gr wafer and the hBN wafer; Step 1.2), use blue tape to stick a little Gr crystal and hBN crystal respectively, and then cover the tape on the silicon wafer; Step 1.3), place the silicon wafer covered by the blue tape on a hot plate and heat it at 100°C for 1 min to enhance the adhesion between the tape and the silicon wafer; In step 1.4, the silicon wafer covered by the blue tape is removed from the hot plate, and after cooling, the blue tape is slowly peeled off, and the Gr and hBN wafers are obtained by mechanical peeling.

[0021] After peeling off the Gr thin film and hBN thin film, an optical microscope is used to confirm the positions of the Gr thin film and hBN thin film on the silicon wafer by the difference in optical contrast; and an atomic force microscope is used to confirm the thickness of the two-dimensional material at the corresponding position and the surface cleanliness.

[0022] Step 2), preparing a PPC / PDMS transfer carrier; Step 2.1), cut a piece of PDMS and place it on a clean glass slide, and treat its surface with oxygen plasma at 30W / 20sccm / 30s; turn the PDMS over and treat the surface again with oxygen plasma at 50W / 50sccm / 2min; Step 2.2), spin coat the PPC reagent (15% mass fraction, anisole solvent) on the PDMS surface at 4000 rpm / s for 1 min using a spin coater, and then heat on a hot plate at 105°C for 3 min to form a PPC film; Step 2.3), treating the PDMS spin-coated with PPC with oxygen plasma under the condition of 20W / 10sccm / 3s to obtain a PPC / PDMS transfer carrier; Step 3), take two clean glass slides, add 3 ml of PC reagent (5% mass fraction, dichloromethane solvent) on one of them, then immediately cover it with another glass slide, and then slowly pull the two glass slides apart to form a layer of PC film on the glass slide. After standing for 5 minutes, use a scalpel to cut the PC film into small pieces; cut a square hole in the middle of the 3M white tape, the area of ​​the square hole should be slightly larger than the small piece of PDMS, and then use it to stick the PC film, and cover the PC film on the PPC / PDMS transfer carrier to obtain a PC / PPC / PDMS dry transfer carrier; Step 4), at a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered on the Gr thin slice, the PC / PPC / PDMS dry transfer carrier is slowly lifted to stick the target Gr thin slice from the silicon wafer substrate, and then the Gr thin slice is attached to the hBN thin slice on the silicon wafer substrate; then, it is heated to 180°C and maintained for 2 minutes, so that the PPC / PC film melts and releases heat to the silicon wafer substrate, and then, the PDMS carrier is slowly removed to form a Gr / hBN heterojunction on the silicon wafer substrate; finally, it is cleaned with dichloromethane for 20 minutes, acetone for 15 minutes, and isopropanol for 5 minutes in sequence to remove the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon wafer substrate; Step 5), placing the Gr / hBN heterojunction on the silicon wafer substrate horizontally so that the Gr sheet is located at the top; Step 6), spin-coating PMMA on the upper surface of the silicon wafer substrate at a speed of 4000 rmp / s, and heating until the solvent in the PMMA evaporates to form a PMMA layer; Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon wafer substrate covers the Gr thin sheet; Step 8), using a field emission electron microscope and an electron beam exposure system to expose the source and drain electrodes on the PMMA layer, and then placing it in a developer (isopropyl alcohol: water = 3:1) for 30 seconds to expose the source and drain regions, and then using an electron beam deposition device to evaporate Ti / Au on the source and drain regions; Step 9), post-processing is performed by soaking the evaporated device in acetone reagent, placing it on a hot plate and heating it at 65°C to make the PMMA-carrying metal thin layer in the unexposed area fall off; then the device is soaked in isopropanol reagent for cleaning for 5 minutes, and blown dry with nitrogen to obtain a quasi-ferroelectric transistor with a source and a drain; Step 10), a wire is led out from the lower surface of the silicon wafer substrate as a gate to obtain a Gr / hBN ferroelectric transistor.

[0023] Source-drain pulse control and electrical transport test of Gr / hBN ferroelectric transistors: Based on the sample holder of the low-temperature transport equipment, the device leads are completed, such as Figure 2 (a) The sample is placed in the chamber and the vacuum is pumped to 1×10 -6 torr, and the chamber temperature was lowered to 1.5 K. In order to achieve the regulation of multi-state polarization, we designed a source-drain bias pulse with a monotonically changing amplitude ( V pulse ) at the gate voltage ( V G ) is zero. The change in polarization direction and intensity causes a difference in carrier concentration inside Gr, so that the change in the polarization state of the system can be detected by the channel current. V pulse The amplitude is 1 mV, and after each pulse, the source-drain voltage is 1 mV ( V DS ) to record the change of channel current over time; it was found that 56 discrete polarization states could be generated in a single device, and the retention performance of each state was at least more than 1000 seconds, such as Figure 2 (b) As shown in Figure 2, +13 V and -13 V are applied respectively. V pulse , making the net polarization of the system downward and upward; the corresponding two channel current levels are more than 10 5 It is still clearly discernible after seconds, and based on linear extrapolation, the retention time may exceed 10 years, such as Figure 3 shown.

[0024] Nonvolatile doping control of Gr / hBN ferroelectric transistors: In addition to source-drain pulses, another degree of freedom in Gr / hBN devices is the bottom gate voltage. We found that by applying source-drain pulses and presetting a gate voltage ( V G_Pre), the Dirac peak of graphene can be locked to V G_Pre At 1.5 K, V G_Pre = +60 V ~ -60 V and -60 V ~ +60 V conditions, such as Figure 4 As shown in Figure 1, source-drain pulses with an amplitude of -12 V and a width of 1 second are applied in sequence, and at each V pulse Scanning transfer curve after action; the upper inset demonstrates the method of adjusting the nonvolatile doping level, and the other inset describes the carrier density and V G_Pre A linear relationship is found between them; it is found that the position of the Dirac peak of graphene produces a significant linear shift, indicating the effective modulation of the system doping level.

[0025] Demonstration of room temperature control of thousands of polarization states in Gr / hBN ferroelectric transistors: Control of nonvolatile doping levels can be extended to 300 K at room temperature V G_Pre = +40 V ~ -40 V, the transfer curve of graphene shows dozens of different Dirac peak positions, which correspond to different Fermi levels of graphene, such as Figure 5 As shown. V G_Pre = 0, 1, 2, 3, 4, 5 V, for example, a series of positive V pulse The application of makes the channel current gradually increase, such as Figure 6 As shown in (a), different current levels correspond to the evolution of polarization states. In order to intuitively distinguish all polarization states, we define the device weight as 𝑊 d =𝑉 𝐺_𝑃𝑟𝑒 + 𝛼𝐼 𝐷𝑆 (𝛼 is the scaling factor, 𝛼 = 1 / (𝐼 𝐷𝑆 (𝑚𝑎𝑥)−𝐼 𝐷𝑆 (𝑚in)), 𝐼 𝐷𝑆 The unit is nanoampere); based on this, all measured channel current levels are converted into device weights, and the modulation process is presented as 𝑊 d is monotonically increasing, such as Figure 6 (b). In contrast, a series of negative V pulse Suppressing channel current, such as Figure 7 As shown in (a), the modulation 𝑊 d Monotonically decreasing, so that the modulation process of the polarization state is reversible, such as Figure 7(b). We selectively demonstrate modulation of 36 distinguishable channel current levels at 84 specific doping levels; by converting all states to the corresponding 𝑊 d , we demonstrated 3024 discrete and uniformly distributed polarization states in a single Gr / hBN device, such as Figure 8 shown.

[0026] The present invention further demonstrates the realization of more than 3,000 non-volatile polarization states at room temperature in a ferroelectric transistor, and improving the test resolution has the potential to further increase the number of states exponentially, laying a solid foundation for the realization of efficient memory computing and edge hardware at the atomic scale.

[0027] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0028] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A ferroelectric transistor capable of generating thousands of polarization states, characterized in that: The ferroelectric transistor is a vertical stacking structure, which includes a Gr thin slice, an hBN thin slice and a silicon wafer substrate from top to bottom; The Gr thin sheet and the hBN thin sheet are combined by van der Waals force to form a Gr / hBN heterojunction; The hBN thin sheet is fixed on the upper surface of the silicon wafer substrate; The upper surface of the silicon wafer substrate is provided with metal electrodes connected to the two ends of the Gr thin slice, namely, a source electrode and a drain electrode; A gate is arranged on the lower surface of the silicon wafer substrate.

2. The ferroelectric transistor capable of generating thousands of room temperature non-volatile polarization states according to claim 1, characterized in that: The thickness of the Gr thin sheet is 0.3-2 nm, and the thickness of the hBN thin sheet is 20 nm.

3. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 1, characterized in that: The following steps are involved: Step 1), strip-shaped Gr thin sheets and strip-shaped hBN thin sheets are peeled off respectively and placed on different silicon wafer substrates; Step 2), preparing a PPC / PDMS transfer carrier; Step 2.1), the cut PDMS is placed on a clean glass slide, and the surface of the PDMS is treated with oxygen plasma; Step 2.2), spin coating the PPC reagent on the PDMS surface, and then placing it on a hot plate and heating it to form a PPC film; Step 2.3), using oxygen plasma to treat the surface of the PPC film to obtain a PPC / PDMS transfer carrier; Step 3), preparing a PC film, and covering the PC film on a PPC / PDMS transfer carrier to obtain a PC / PPC / PDMS dry transfer carrier; Step 4), at a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered on the Gr thin slice, the PC / PPC / PDMS dry transfer carrier is slowly lifted to stick the target Gr thin slice from the silicon wafer substrate, and then the Gr thin slice is attached to the hBN thin slice on the silicon wafer substrate; then, the PPC / PC film is heated to melt and release heat to the silicon wafer substrate, and then, the PDMS carrier is slowly removed to form a Gr / hBN heterojunction on the silicon wafer substrate; finally, the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon wafer substrate are cleaned; Step 5), placing the Gr / hBN heterojunction on the silicon wafer substrate horizontally so that the Gr sheet is located at the top; Step 6), spin coating PMMA on the upper surface of the silicon wafer substrate at a speed higher than a preset speed threshold and then heating until the solvent in the PMMA evaporates to form a PMMA layer; Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon wafer substrate covers the Gr thin sheet; Step 8), using a field emission electron microscope and an electron beam exposure system to expose the source and drain electrodes on the PMMA layer, followed by development to expose the source and drain regions, and then using an electron beam deposition device to evaporate Ti / Au on the source and drain regions; Step 9), post-processing is performed to cause the PMMA-carrying metal thin layer in the unexposed area to fall off; Then, the quasi-ferroelectric transistor with source and drain is obtained by washing and drying. Step 10), a wire is led out from the lower surface of the silicon wafer substrate as a gate to obtain a Gr / hBN ferroelectric transistor.

4. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 3, characterized in that: The detailed steps for peeling off the Gr flakes and hBN flakes in step 1) are as follows: Step 1.1), using an oxygen plasma system to clean the silicon wafer to increase the bonding strength between the silicon wafer and the Gr thin film and the hBN thin film; Step 1.2), use blue tape to stick a little Gr crystal and hBN crystal respectively, and then cover the tape on the silicon wafer; Step 1.3), place the silicon wafer covered by the blue tape on a hot plate to heat it to enhance the adhesion between the tape and the silicon wafer; In step 1.4, the silicon wafer covered by the blue tape is removed from the hot plate, and after cooling, the blue tape is slowly peeled off, and the Gr and hBN wafers are obtained by mechanical peeling.

5. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 3, characterized in that: The detailed steps for preparing the PC film in step 3) are as follows: PC reagent is dropped on the upper surface of glass slide No. 1, and then the lower surface of glass slide No. 2 is covered on the upper surface of glass slide No. 1, and finally glass slides No. 1 and No. 2 are horizontally dragged and separated, thereby forming a layer of prepared PC film on the upper surface of glass slide No. 1 and the lower surface of glass slide No. 2, respectively.

6. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 3, characterized in that: The mass fraction of the PPC reagent is 15% by mass, and the solvent is anisole.

7. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 5, characterized in that: The mass fraction of the PC reagent is 5%, and the solvent is dichloromethane.

8. The method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to claim 3, characterized in that: When cleaning the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon wafer substrate in step 4), they are sequentially placed in dichloromethane for 20 minutes, acetone for 15 minutes, and isopropanol for 5 minutes for cleaning.

9. A method for using a ferroelectric transistor capable of generating thousands of polarization states according to claim 1, characterized in that: The following steps are involved: The ferroelectric polarization state is tuned by applying direct current pulses to the Gr channel of the source and drain; at the same time, the gate voltage is preset to control the injection and discharge of carriers into and out of the Gr channel, thereby achieving non-volatile doping of the Gr channel.

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