A chip testing method optimized based on deep learning

Abstract

The present invention discloses a chip testing method optimized based on deep learning, which relates to the technical field of chip testing, and includes: outputting the optimal power-on sequence through the Q-value update and the prioritized experience replay mechanism; extracting the electrical signal feature vectors of the pins through a convolutional neural network, adopting self-supervised learning, detecting abnormal connections between the pin signals through a contrast loss function, and judging whether there is a short circuit or an open circuit in the pins by calculating the signal feature distance to obtain the open-short circuit detection result of the chip; using a multi-layer perceptron for automatic tuning of configuration parameters to obtain optimized chip configuration parameters; using a recurrent neural network for system-level chip testing and verification to obtain system-level test results. The present invention achieves high efficiency, accuracy, and comprehensiveness that cannot be achieved by traditional methods in terms of power-on sequence optimization, open-short circuit detection, parameter tuning, and system-level testing, improves the efficiency and reliability of chip testing, and is applicable to the mass production and quality control of high-complexity chips.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and more particularly, to a chip testing method optimized based on deep learning. Background Art

[0002] With the rapid development of semiconductor technology, the integration and complexity of chips are increasing day by day. Traditional chip testing methods have become difficult to meet the testing requirements of complex system-on-chip (SoC) and system-in-package (SIP). Current chip testing methods usually rely on automatic test equipment (ATE) and preset test vectors. However, when facing the diversity of chip functions and performances, the testing efficiency and accuracy are greatly limited. The traditional chip testing process depends on a fixed power-on sequence, manual configuration of parameters, and the analysis and determination of test results relying on engineering experience. As the complexity of chip design increases, the amount of chip test data grows rapidly, making manual analysis and optimization more difficult and prone to testing blind spots, which affects the reliability of chips and the mass production process. On the other hand, in recent years, deep learning technology has made remarkable progress in fields such as image recognition and natural language processing, and its potential in processing complex data and automated decision-making has been widely recognized. Therefore, introducing deep learning technology into the field of chip testing, especially in optimizing automated testing processes, data analysis, and decision support, has become an important direction to solve the current bottleneck of chip testing. Summary of the Invention

[0003] The present invention aims to provide a chip testing method optimized based on deep learning, aiming to solve problems such as low chip testing efficiency, complex data analysis, and poor reliability of test results in the prior art.

[0004] To solve the above problems, the technical solutions adopted by the present invention are as follows:

[0005] The present invention provides a chip testing method optimized based on deep learning, including:

[0006] (1) According to the power supply configuration file and historical initialization data, use a deep Q-network to optimize the power-on sequence of the chip, and output the optimal power-on sequence through Q-value update and prioritized experience replay mechanism;

[0007] (2) According to the optimal power-on sequence and the chip pin connection diagram, extract the electrical signal feature vectors of the pins through a convolutional neural network, adopt self-supervised learning, detect abnormal connections between pin signals through a contrast loss function, and judge whether there is a short circuit or open circuit in the pins by calculating the signal feature distance, so as to obtain the open-short circuit detection result of the chip;

[0008] (3)According to the optimal power-on sequence, open / short circuit detection results, and chip configuration file, use a multi-layer perceptron to automatically optimize the configuration parameters and obtain the optimized chip configuration parameters;

[0009] (4)Based on the chip test data, chip design standards, target parameter set, and optimized chip configuration parameters, use a recurrent neural network to perform system-level chip testing and verification to obtain system-level test results.

[0010] Specifically, in step (1), the power configuration file describes the power requirements and power-on timing of each module of the chip, and the historical initialization data records the initialization success rates under different power-on sequences.

[0011] Specifically, in step (1), utilize the superposition property of qubits to construct a quantum Q-value table, and update and adjust the Q-values through quantum gate operations; at each moment, the system queries the quantum Q-value table according to the current state and selects a power-on operation; meanwhile, utilize the quantum entanglement property to achieve quantum optimization adjustment of the TD error, and accelerate the convergence rate of the Q-values through the superposition and entanglement of quantum states; the construction of the quantum Q-value table includes initializing the qubit state, updating the qubit state according to the power-on decision, and obtaining the Q-value through quantum measurement; the quantum gate operations include the Hadamard gate, CNOT gate, and rotation gate, which are used to operate on the qubits to achieve the update and adjustment of the Q-values; the quantum optimization adjustment also includes quantum error correction of the Q-values, detecting and correcting errors in the Q-value update process through quantum error correction codes to ensure the accuracy of the Q-values.

[0012] Specifically, in step (1), the Q-value is used to guide the power-on decision, including the power-on decision for the current state, the Q-value maximization principle, the power-on decision mechanism, and the adjustment of the TD error; the power-on decision for the current state refers to that at each moment, the system queries the currently known Q-value table or deep Q-network according to the current state and selects a power-on operation; the Q-value maximization principle refers to selecting the maximum Q-value among all possible power-on operations in the future state; the power-on decision mechanism refers to selecting the operation that maximizes the Q-value in the current state; the adjustment of the TD error refers to continuously updating the Q-value to minimize the deviation between the current Q-value and the target Q-value.

[0013] Specifically, in step (1), the prioritized experience replay mechanism refers to preferentially learning the operations with large TD errors based on the experience replay weights.

[0014] Specifically, in step (2), the contrast loss function formula is:

[0015]

[0016] Where represents the pin electrical state characteristics is the pin and the Euclidean distance between, indicating the calculation of the loss when the two pins are connected differently; m is the threshold for normal and abnormal connections.

[0017] Specifically, in step (2), during the process of extracting the electrical signal feature vector of the pin, multi-modal data is also obtained through several sensors, including the temperature and vibration of the chip; the multi-modal data is fused with the electrical signal feature vector; the fusion process includes data preprocessing, feature extraction, and feature fusion; data preprocessing includes normalizing and denoising the multi-modal data; feature extraction includes using different neural network models to extract features from the multi-modal data respectively, and the extracted features include the temperature feature vector and the vibration feature vector; feature fusion includes fusing the electrical signal feature vector with the feature vectors of other modalities, and using weighted summation or splicing to obtain an enhanced feature vector, and performing dimensionality reduction on the enhanced feature vector, using principal component analysis or autoencoder methods to reduce the dimension of the feature vector.

[0018] Specifically, in step (3), the Adam optimizer is used to update the configuration parameter set in the multi-layer perceptron, and by minimizing the comprehensive loss function, the chip configuration parameters are gradually adjusted and optimized. The comprehensive loss function combines the power consumption, frequency, and temperature performance indicators; the learning rate warm restart strategy is adopted to periodically adjust the learning rate to avoid local optimal solutions of the comprehensive loss function; the learning rate adjustment formula is:

[0019]

[0020] where, is the current learning rate, and are the minimum and maximum learning rates respectively, is the current iteration step, is the learning rate restart period.

[0021] Specifically, in step (4), the hidden state of the recurrent neural network is used to store the information derived from the previous time step and is updated at each time step. The hidden layer of the recurrent neural network is used to process the temporal information of the input data, and the multi-layer recurrent units are used to learn the dependencies over time.

[0022] Optionally, in step (4), if the value of the system-level test result reaches 0.9, it is determined that the chip passes all tests, otherwise it fails.

[0023] Compared with the prior art, the beneficial effects of the present invention are:

[0024] Optimize the power-on sequence of the chip through a Deep Q-Network (DQN). Combine the power supply configuration file and historical initialization data. Through Q-value update and prioritized experience replay mechanisms, dynamically adjust the power-on sequence and output the optimal power-on scheme for the power supply. Compared with the traditional fixed power-on sequence, it can be adaptively optimized according to the actual test environment, avoid test failures caused by improper power-on sequences, and improve the success rate and overall efficiency of chip startup testing;

[0025] Extract the feature vectors of the electrical signals of the chip pins based on a Convolutional Neural Network (CNN). Adopt a self-supervised learning method. Detect abnormal connections between pin signals through a contrast loss function. By calculating the signal feature distance, it can accurately judge whether there is a short circuit or open circuit in the chip pins. This open / short circuit detection method based on neural networks has the characteristics of high automation and strong accuracy, can effectively reduce the errors of manual detection, and improve the detection accuracy and speed;

[0026] Use a Multi-Layer Perceptron (MLP) to automatically optimize the configuration parameters of the chip according to the optimal power-on sequence, open / short circuit detection results, and the chip's configuration file, ensuring that the chip is always in the optimal configuration state during the test. Compared with the traditional manual parameter adjustment method, the automated optimization process can significantly improve the parameter adjustment efficiency, reduce the debugging time, and optimize parameters such as the power consumption and frequency of the chip, ensuring the stability and performance of the chip during the test;

[0027] Analyze the test data of the chip through a Recurrent Neural Network (RNN). Combine the chip's design standards and target parameter sets, as well as the optimized configuration parameters, for system-level testing and verification. The RNN can capture the temporal dependencies in the test data, comprehensively analyze the performance of the chip in different test scenarios, and finally output the system-level test results. These results not only cover the performance of the chip in various test scenarios but also can effectively judge whether the chip meets the design standards, providing an accurate system-level test evaluation to ensure that the functions and performance of the chip meet the expected requirements.

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically presents embodiments of the present invention and, in conjunction with the accompanying drawings, gives a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can be obtained based on these drawings.

[0030] Figure 1It is the flowchart of the chip testing method optimized based on deep learning described in the embodiments. Detailed implementation manners

[0031] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention.

[0032] The embodiments of the present invention disclose a chip testing method optimized based on deep learning. This method is carried out in an ATE (Automatic Test Equipment) testing system. After the PCB of the ATE is completed, chip testing can be performed. Combining Figure 1 as shown, it specifically includes the following four steps: power-on sequence optimization, open / short circuit testing, online parameter configuration optimization, and system-level testing and verification.

[0033] 1. Power-on sequence optimization

[0034] According to the power supply configuration file and historical initialization data , the power-on sequence of the chip is optimized using a Deep Q-Network (DQN). Through Q-value update and prioritized experience replay mechanisms, the optimal power-on sequence is output to maximize the success rate of chip initialization.

[0035] Among them, using the superposition property of qubits, a quantum Q-value table is constructed, and the Q-value is updated and adjusted through quantum gate operations; at each moment, the system queries the quantum Q-value table according to the current state and selects the power-on operation; at the same time, using the quantum entanglement property, quantum optimization adjustment of the TD error is realized. Through the superposition and entanglement of quantum states, the convergence speed of the Q-value is accelerated, and the efficiency and accuracy of power-on sequence optimization are improved; the construction of the quantum Q-value table includes initializing the qubit state, updating the qubit state according to the power-on decision, and obtaining the Q-value through quantum measurement; the quantum gate operations include Hadamard gates, CNOT gates, and rotation gates, which are used to operate on qubits to realize the update and adjustment of the Q-value; the quantum optimization adjustment also includes quantum error correction of the Q-value, and errors in the Q-value update process are detected and corrected through quantum error correction codes to ensure the accuracy of the Q-value.

[0036] The power supply configuration file describes the power supply requirements and power-on timings of each module of the chip, and the historical initialization data records the initialization success rates under different power-on sequences.

[0037] The Q-value update formula is used to calculate the value of each power-on operation, which is specifically as follows:

[0038]

[0039] Wherein:

[0040] represents the current state under which the current power-on operation is selected and the Q value at this time represents the expected cumulative reward that can be obtained after performing the operation under the state ; is the state of the current chip, including historical initialization data and the current power configuration; is the power-on operation at the current moment, that is, the power-on sequence operation selected by the chip at time point t; is the immediate reward, indicating the improvement in the success rate of the current power-on sequence; γ is the discount factor, weighing the impact of future rewards on the current decision-making. γ ∈ [0, 1]. If γ is close to 1, it means that the importance of future rewards is relatively high. On the contrary, if γ is close to 0, it means that the system pays more attention to the current immediate reward; α is the learning rate, controlling the step size of Q value update, which is a decimal number used to balance the weights of new and old information.

[0041] represents the maximum Q value among all possible power-on operations A selected under the state at the next moment. This value represents the future reward that can be obtained by performing the optimal operation at the moment. A represents an operation in the set of all possible power-on operations. Usually, different power-on strategies will generate different operation sequences.

[0042] The Q value is used to guide the power-on decision-making, including the power-on decision for the current state, the Q value maximization principle, the power-on decision mechanism, and the adjustment of TD error.

[0043] The power-on decision for the current state is: at each moment t, the system queries the currently known Q value table or deep Q network according to the current state and selects the power-on operation .

[0044] The Q value maximization principle means that: in order to obtain the best power-on sequence, according to in the Q value update formula, that is, under the future state , select the maximum Q value among all possible power-on operations. This maximum value represents the long-term cumulative benefit that the current operation can bring.

[0045] The power-on decision mechanism means that: under the state , select the operation that maximizes the Q value , This is done to ensure that in each state, the power-on operation selected by the system can bring the optimal cumulative reward, that is, to ensure that the chip is in the best state in each power-on step, thereby avoiding the adverse effects of unreasonable power-on sequences on the chip.

[0046] The adjustment of the TD error means that the Q value is updated through the TD error. The TD error reflects the deviation between the current Q value and the target Q value. By continuously updating the Q value, this error is minimized, thereby continuously improving the power-on sequence.

[0047] The TD error at the current moment is the core of the experience replay priority calculation and is directly related to the Q value calculation formula. The TD error calculation formula is:

[0048]

[0049] The TD error at the current moment represents the gap between the currently predicted Q value and the actual reward. The larger the TD error, the more inaccurate the model's estimation of the current power-on operation, that is, the larger the estimation error of the current Q value, and the higher the learning priority. Prioritizing the learning of these experiences helps the model quickly converge to the optimal policy.

[0050] In this embodiment, a prioritized experience replay mechanism is adopted to sort the experience priorities for each power-on operation, and the operations with large TD errors are preferentially learned. The experience replay weight calculation formula is:

[0051]

[0052] Where: is the TD error of the i-th experience, representing the prediction error of the Q value in this experience; is the TD error of the k-th experience, serving as a reference value in the experience set; β is a parameter that controls the influence of the priority, taking values between 0 and 1, and is used to adjust the weight of the experience replay.

[0053] The prioritized experience replay mechanism ensures that the model learns the effective power-on sequence faster.

[0054] Through repeated training and Q value update, the optimal action sequence for each power-on sequence can be determined, that is, the optimal power supply power-on sequence , This sequence is composed of the Q value maximization strategy obtained through multiple iterations of optimization, that is, the set of the best power-on action sequences selected in different states, ensuring the highest initialization success rate.

[0055] 2. Open and short circuit test

[0056] After the power supply power-on sequence optimization is completed, according to the optimal power supply power-on sequence and the chip pin connection diagram , the electrical signal feature vectors of the pins are extracted through a convolutional neural network (CNN). , self-supervised learning is adopted to detect abnormal connections between pin signals through a contrast loss function. By calculating the signal feature distance, it is judged whether there is a short circuit or an open circuit in the pins, and the open-short circuit detection result of the chip is obtained. .

[0057] During the process of extracting the electrical signal feature vectors of the pins, in addition to extracting the electrical signal feature vectors, multi-modal data such as the temperature and vibration of the chip are also obtained through other sensors, and these multi-modal data are fused with the electrical signal feature vectors; the multi-modal data fusion includes three steps: data preprocessing, feature extraction, and feature fusion; data preprocessing is to perform normalization, denoising, etc. on the multi-modal data to make it meet the requirements of feature extraction; feature extraction is to use different neural network models to extract features from the multi-modal data respectively to obtain temperature feature vectors, vibration feature vectors, etc.; feature fusion is to fuse the electrical signal feature vectors with the feature vectors of other modalities, and adopt the method of weighted summation or splicing to obtain the enhanced feature vectors; the feature fusion also includes dimensionality reduction processing on the fused feature vectors, and methods such as principal component analysis or autoencoder are used to reduce the dimensionality of the feature vectors and improve the efficiency of subsequent self-supervised learning.

[0058] In this embodiment, the chip pin connection diagram shows the electrical connection relationship of the chip pins.

[0059] The contrast loss function formula is:

[0060]

[0061] Among them: is the feature vector of pin , representing the electrical state characteristics of the pin; is the pin and the Euclidean distance between them, representing the electrical state difference between them; means calculating the loss when the two pins are connected differently; m is the threshold for normal and abnormal connections. When the distance between the feature vectors exceeds the threshold, it is determined as a short circuit or open circuit fault, that is, the open-short circuit detection result of the chip is obtained. , this result is used to ensure the integrity of the chip connection.

[0062] 3. Online configuration parameter optimization

[0063] After the chip passes the open-short circuit test, according to the optimal power-on sequence , the open-short circuit detection result and the chip configuration file , the multi-layer perceptron (MLP) is used for automatic tuning of configuration parameters to obtain optimized chip configuration parameters .

[0064] During the automatic tuning of configuration parameters, a reinforcement learning algorithm can be introduced to dynamically adjust test parameters such as test frequency and test voltage according to real-time feedback during the test process to optimize the test effect; the reinforcement learning algorithm includes four parts: state representation, action space, reward function, and policy update; state representation encodes the state of the current test process, including information such as test parameters and test results; the action space is a set of adjustable test parameters; the reward function rewards or punishes actions according to the quality of the test results; policy update updates the policy of the reinforcement learning model according to the feedback of the reward function to select better test parameters.

[0065] Chip configuration file defines the functions and performance parameters of the chip, and the initial file includes an initial set of configuration parameters .

[0066] In this embodiment, the Adam optimizer is used to update the set of configuration parameters in the multi-layer perceptron , and by minimizing the loss function, the chip configuration parameters are gradually adjusted to reach the optimal state. Specifically, the Adam optimizer calculates the gradient according to the loss function of the multi-layer perceptron (i.e., the deviation between the configuration parameters and the chip performance), and then updates the set of configuration parameters in each iteration to minimize this loss function.

[0067] Loss function is used to measure the impact of the current set of configuration parameters on the chip performance, and its form depends on the performance goals of the chip. In this embodiment, the loss function is a comprehensive function that combines important performance indicators such as the power consumption, frequency, and temperature of the chip, aiming to minimize the deviation between these actual indicators and the target values to ensure optimal adjustment of the chip performance. The specific form is as follows:

[0068]

[0069] where: is the power consumption value of the current chip; is the target power consumption value, which is the design specification of the chip; is the operating frequency of the current chip; is the target operating frequency; is the operating temperature of the current chip; is the maximum operating temperature of the chip, exceeding which will cause performance degradation or even chip damage; is a weight coefficient used to adjust the contribution of different performance metrics to the objective function, depending on the priority in the design goal.

[0070] During the optimization process, the loss function avoids local optimal solutions through periodic adjustment of the learning rate, thereby ensuring that the finally obtained set of configuration parameters can maximize the chip performance.

[0071] In this embodiment, a learning rate warm restart strategy is adopted to periodically adjust the learning rate to avoid falling into local optimal solutions. The learning rate adjustment formula is:

[0072]

[0073] Where: is the current learning rate, representing the learning rate used during the optimization process, which is dynamically adjusted through the learning rate warm restart strategy; and are the minimum and maximum learning rates respectively, defining the range of learning rate adjustment; is the current iteration step, representing the progress of the optimization; is the learning rate restart period, determining the learning rate.

[0074] The Adam optimizer is used to iteratively update the set of configuration parameters to minimize the loss function .

[0075] During the model training process, the Adam optimizer iteratively updates the set of parameters in the neural network to minimize the loss function of the configuration parameters.

[0076] The update rule of the Adam optimizer is as follows:

[0077] 1) First, Adam calculates the gradient of the loss function based on the current set of parameters

[0078] ;

[0079] 2) Adam calculates the first-order momentum by taking a weighted average of the gradients:

[0080]

[0081] Where is a hyperparameter that controls the decay of the first-order momentum;

[0082] 3) Adam calculates the weighted average of the squared gradients to obtain the second-order momentum :

[0083]

[0084] where is a hyperparameter that controls the decay of the second-order momentum;

[0085] 4) Adam updates the parameter set according to the first-order momentum and the second-order momentum , and the update formula is as follows:

[0086]

[0087] where is a small constant to avoid division by zero, is the learning rate.

[0088] Through the above update process, the Adam optimizer can effectively adjust the parameter set in the multi-layer perceptron to minimize the loss function , thereby realizing the automatic tuning of the configuration parameters, and finally obtaining the optimal combination of configuration parameters, that is, the optimized chip configuration parameters , which includes the final configuration values of each functional module.

[0089] In this step, the dynamic adjustment of the learning rate ensures the flexibility in the optimization process, avoids getting stuck in local optimal solutions, and thus improves the global optimization ability of the model. The iterative update of the parameter set is carried out through the Adam optimizer, which ensures the full utilization of gradient information, thereby improving the optimization efficiency and accuracy. The output is the finally optimized configuration parameters, and the chip configuration reaches the best performance through the deep learning model and the gradient optimization algorithm.

[0090] 4. Chip System Testing and Verification

[0091] After the configuration parameters are optimized, based on the chip test data , the design standard of the chip and the target parameter set and the optimized chip configuration parameters , a recurrent neural network (RNN) is used for system-level chip testing and verification to obtain the system-level test results , specifically as follows:

[0092] First, standardize the chip test data to ensure that data in different dimensions have the same magnitude; then extract the timing features from the chip test data and combine them with the optimized chip configuration parameters Combine to obtain the data to be input into the RNN 。

[0093]

[0094] where n is the number of test time points, which are the voltage, power consumption, and temperature at each moment respectively.

[0095] The RNN is used to process the temporal information in the test data and can capture the changing trends of various parameters of the chip in the time dimension. The RNN includes a hidden state , an input layer, a hidden layer, and an output layer. The hidden state is used to store the information derived from the previous time step and is updated at each time step. The input layer inputs the standardized test data sequence into the RNN. The hidden layer is used to process the temporal information of the input data and learns the temporal dependencies through multiple recurrent units. The output layer is used to output the output at each time step 。

[0096] The update formula of the RNN is:

[0097]

[0098] where, is the input data at the current moment; is the weight matrix, which is used for the mapping between the input and the hidden layer respectively; is the bias vector; σ is the activation function, and here the ReLU function is adopted.

[0099] The output at each time step indicates whether the test result at the current time step meets the design requirements of the chip. The output value is a binary classification result, where 1 indicates meeting the requirements and 0 indicates not meeting the requirements.

[0100] By synthesizing the outputs of all time steps, the final test determination is obtained, and the output formula is:

[0101]

[0102] If , it is determined that the chip passes under this test scenario; otherwise, it is determined that the test fails.

[0103] We calculate the difference between the test data and the design target at each time step t, and the error calculation formula is:

[0104]

[0105] where, is a certain parameter in the test data, which is the target value in the design stage.

[0106] After statistically analyzing the errors in all test scenarios, an error analysis report is generated to output the overall performance of the chip.

[0107] System-level test results include the pass / fail determination for each test scenario, the error analysis report, and the overall performance evaluation of the chip.

[0108] The system evaluation formula is:

[0109]

[0110] where m1 is the number of test scenarios, is the final test determination for each scenario. If the value of the system-level test result reaches 0.9, it is determined that the chip passes all tests.

[0111] For the chip testing method described in this embodiment, the following operations can also be performed:

[0112] In the system-level test and verification stage, a generative adversarial network (GAN) can also be used to generate more test data samples to cover more test scenarios and boundary conditions; the generative adversarial network includes two parts: a generator and a discriminator; the generator is used to generate test data samples, and the discriminator is used to determine whether the generated data conforms to the distribution of real data; through the adversarial training of the generator and the discriminator, the generator can generate test data samples similar to real data; the generated test data samples include different input stimuli, environmental conditions, and chip configuration parameters to comprehensively test the performance of the chip.

[0113] For the data that needs to be stored, blockchain technology can also be used to encrypt and store the test data to ensure the security and integrity of the test data; blockchain technology includes the generation of data blocks, the construction of a chain structure, and the implementation of a consensus mechanism; the generation of data blocks is to perform a hash operation on the test data to generate a unique identifier for the data block; the construction of the chain structure is to link the data blocks in chronological order to form an immutable chain structure; the implementation of the consensus mechanism is to verify and confirm the data blocks through nodes in a distributed network to ensure the consistency and reliability of the data.

[0114] When processing data, edge computing technology can also be used to process test data in real time, reduce data transmission latency, and improve test response speed. Edge computing technology includes the deployment of edge devices, data preprocessing, and edge intelligent analysis. The deployment of edge devices is to deploy computing nodes near the test devices to reduce the data transmission distance. Data preprocessing is to perform preliminary processing on the test data, such as filtering and downsampling, to reduce the data volume. Edge intelligent analysis is to use lightweight machine learning models to perform data analysis on edge devices and quickly obtain preliminary results.

[0115] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip testing method optimized based on deep learning, characterized in that It includes the following steps: (1) According to the power supply configuration file and historical initialization data, use the deep Q-network to optimize the power-on sequence of the chip. Through Q-value update and prioritized experience replay mechanism, output the optimal power-on sequence; (2) According to the optimal power-on sequence and the chip pin connection diagram, extract the electrical signal feature vectors of the pins through a convolutional neural network. Adopt self-supervised learning, detect abnormal connections between pin signals through a contrast loss function, and judge whether there is a short circuit or open circuit in the pins by calculating the signal feature distance, so as to obtain the open-short circuit detection result of the chip; (3) According to the optimal power-on sequence, open-short circuit detection result and chip configuration file, use a multi-layer perceptron to automatically tune the configuration parameters to obtain optimized chip configuration parameters; (4) Based on the chip test data, the design standards and target parameter sets of the chip, and the optimized chip configuration parameters, use a recurrent neural network to perform system-level chip testing and verification to obtain system-level test results.

2. The chip testing method according to claim 1, wherein In step (1), the power supply configuration file describes the power supply requirements and power-on timing of each module of the chip, and the historical initialization data records the initialization success rates under different power-on sequences.

3. The chip testing method according to claim 1, characterized in that, In step (1), utilize the superposition property of qubits to construct a quantum Q-value table, and update and adjust the Q-value through quantum gate operations; at each moment, the system queries the quantum Q-value table according to the current state and selects a power-on operation; meanwhile, utilize the quantum entanglement property to realize the quantum optimization adjustment of the TD error, and accelerate the convergence speed of the Q-value through the superposition and entanglement of quantum states; the construction of the quantum Q-value table includes initializing the qubit state, updating the qubit state according to the power-on decision, and obtaining the Q-value through quantum measurement; the quantum gate operations include Hadamard gate, CNOT gate and rotation gate, which are used to operate on qubits to realize the update and adjustment of the Q-value; the quantum optimization adjustment also includes quantum error correction of the Q-value, detecting and correcting errors in the Q-value update process through quantum error correction codes to ensure the accuracy of the Q-value.

4. The chip testing method according to claim 1, wherein In step (1), the Q-value is used to guide the power-on decision, including the power-on decision of the current state, the Q-value maximization principle, the power-on decision mechanism and the adjustment of the TD error; The power-on decision of the current state refers to that at each moment, the system queries the current known Q-value table or deep Q-network according to the current state and selects a power-on operation; the Q-value maximization principle refers to selecting the maximum Q-value among all possible power-on operations in the future state; The power-on decision mechanism refers to selecting the operation that maximizes the Q-value in the current state; the adjustment of the TD error refers to continuously updating the Q-value to minimize the deviation between the current Q-value and the target Q-value.

5. The chip testing method according to claim 1, wherein In step (1), the prioritized experience replay mechanism refers to preferentially learning the operations with large TD errors based on the experience replay weight.

6. The chip testing method according to claim 1, wherein In step (2), the contrast loss function formula is: Among them, represents the electrical state characteristic of the pin , is the Euclidean distance between the pins and , represents calculating the loss when the connections of two pins are different; m is the threshold for normal and abnormal connections.

7. The chip testing method according to claim 1, wherein In step (2), during the process of extracting the electrical signal feature vectors of the pins, multi-modal data including the temperature and vibration of the chip are also obtained through several sensors; the multi-modal data are fused with the electrical signal feature vectors; the fusion process includes data preprocessing, feature extraction and feature fusion; Data preprocessing includes normalizing and denoising multi-modal data; feature extraction includes using different neural network models to extract features from multi-modal data respectively, and the extracted features include temperature feature vectors and vibration feature vectors; feature fusion includes fusing the electrical signal feature vectors with the feature vectors of other modalities, and adopting weighted summation or splicing to obtain enhanced feature vectors, and performing dimensionality reduction on the enhanced feature vectors, using principal component analysis or autoencoder methods to reduce the dimensionality of the feature vectors.

8. The chip testing method according to claim 1, wherein In step (3), the Adam optimizer is used to update the configuration parameter set in the multi-layer perceptron, and by minimizing the comprehensive loss function, the chip configuration parameters are gradually adjusted and optimized. The comprehensive loss function combines the power consumption, frequency, and temperature performance metrics; the learning rate warm restart strategy is adopted to periodically adjust the learning rate to avoid the local optimal solution of the comprehensive loss function; the learning rate adjustment formula is: wherein, is the current learning rate, and are the minimum and maximum learning rates respectively, is the current iteration step, is the learning rate restart period.

9. The chip testing method according to claim 1, wherein In step (4), the hidden state of the recurrent neural network is used to store the information derived from the previous time step and is updated at each time step. The hidden layer of the recurrent neural network is used to process the temporal information of the input data, and the multi-layer recurrent units are used to learn the temporal dependencies.

10. The chip testing method according to claim 1, wherein In step (4), if the value of the system-level test result reaches 0.9, it is determined that the chip passes all tests; otherwise, it fails.

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