Macro-based multi-mode circuit design method, equipment and medium

Abstract

The invention discloses a macro-based multi-mode circuit design method and device and a medium, and belongs to the technical field of electronic design automation (EDA) design, and the method comprises the steps: setting a working mode, and configuring a relation between the mode and a macro; performing grammar and lexical analysis on the RTL code, abstracting and converting modules, signals, parameters and macro in the code into class and data structures, constructing a relationship between the modules, forming a new data relationship model, and marking macro on each object; copying, dispersing and merging the modes; a new data relation model is generated after operation, and new RTL codes are constructed according to the sequence; checking circuit connectivity; and outputting the RTL code containing multiple modes according to the latest data model. According to the design method, the macro-based multi-mode circuit design is supported, the mode comprises the combination of a plurality of macros, copying, dispersing and merging operation can be carried out among the modes, connectivity can be checked based on circuits among the modes, and the efficiency and quality of chip design are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation (EDA) design, and in particular to a macro-based multi-mode circuit design method, device and medium. Background Art

[0002] The final product of chip design is certain, including ASIC dedicated integrated circuit chip, FPGA programmable array logic circuit chip, DUT chip, etc. At present, most chip design companies use FPGA prototype verification scheme to verify whether the design meets expectations. The front-end codes of FPGA and ASIC are developed based on Verilog, so ASIC code can theoretically run on the FPGA platform, and this method is currently widely used. Therefore, general design companies will have ASIC engineers and FPGA engineers to develop different circuits respectively. In addition, complex chips may be completed by a development team of hundreds of people. If two sets of codes are used to manage, the collaborative cost will increase and the design efficiency will be low. At the same time, it is difficult to achieve code reuse on different chip designs, and there is no good way to check whether the design of a certain chip meets the connectivity requirements. In actual scenarios, only part of the code of ASIC circuits and FPGA circuits can be reused. At present, multiple sets of codes are managed manually, which is inefficient and has high management costs. Therefore, in order to solve the shortcomings of the existing technology, it is urgent to provide a method for realizing multi-mode circuit design. Summary of the invention

[0003] The present invention aims to provide a macro-based multi-mode circuit design method to coordinate the design of circuits such as ASIC and FPGA to improve the efficiency and quality of the design.

[0004] To achieve the above object, the technical solution of the present invention is:

[0005] A macro-based multi-mode circuit design method, comprising: step S1, setting the working mode of a chip project and configuring the relationship between the working mode and the macro, wherein a single working mode includes a combination of one or more macros, and the working mode includes a common mode, an ASIC mode, and an FPGA mode; step S2, performing syntax and lexical analysis on the corresponding RTL code in the working mode, abstracting the modules, signals, parameters, and macros in the RTL code into classes and data structures in a high-level language C++, and abstracting the operations of creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters. The method for operating and processing classes and data structures and constructing the relationship between modules forms a data relationship model, and each object is marked with a macro; step S3, based on the data relationship model, performs copying, dispersing, and merging operations between the working modes; step S4, repeatedly uses the dispersing operation and copying operation in step S3 until the circuit design is completed, and generates a new data relationship model after the operation; step S5, based on the new data relationship model, checks whether the circuit connectivity of all working modes is correct; step S6, after the circuit connectivity check is passed, outputs the RTL code containing multiple working modes according to the new data relationship model, and checks whether the output RTL code syntax conforms to the syntax.

[0006] In a preferred embodiment of the present invention, the circuits in the common mode are visible and operable in the ASIC mode and the FPGA mode, and the circuits between the ASIC mode and the FPGA mode are invisible to each other.

[0007] In a preferred embodiment of the present invention, the circuits in the ASIC mode and the FPGA mode can be copied to each other, and the circuits in the common mode can be dispersed into the designated ASIC mode and FPGA mode. After the dispersion, the circuits are marked with the macros corresponding to the mode; the same circuits in the ASIC mode and the FPGA mode can be merged into the common mode.

[0008] In a preferred embodiment of the present invention, the working mode also includes a DUT mode, and the circuits in the ASIC mode, FPGA mode, and DUT mode can be copied to each other, and the circuits in the common mode can be dispersed into the specified ASIC mode, FPGA mode, and DUT mode. After dispersion, the circuits are marked with macros corresponding to the mode; the same circuits in the ASIC mode, FPGA mode, and DUT mode can be merged into the common mode.

[0009] In a preferred embodiment of the present invention, the circuit in step S3 can be abstracted into instances, ports, parameters, macros, connections, lines, parameters to instantiate specific classes and data structures, and the copy, scatter, and merge operations are abstracted into operations and processing on classes and data structures.

[0010] In a preferred embodiment of the present invention, the step of checking circuit connectivity in step S5 includes: step S51, collecting scattered objects, wherein the objects include instances and ports; step S52, collecting connection relationships of the objects; step S53, dispersing the collected objects and their connection relationships to a specified working mode; step S54, collecting the connection relationships of the dispersed objects in a specified mode; and step S55, comparing the connection relationships before and after dispersion.

[0011] In a preferred embodiment of the present invention, the macro-based multi-mode circuit design method is encapsulated as a graphical operation and a command line operation.

[0012] An electronic design EDA tool includes the above-mentioned macro-based multi-mode circuit design method.

[0013] An EDA device comprises a memory and a processor; wherein the memory is used to store executable instructions that can be run on the processor; and the processor is used to execute the macro-based multi-mode circuit design method as described above when running the executable instructions.

[0014] A computer storage medium stores a computer program, which implements the macro-based multi-mode circuit design method as described above when executed by a chip circuit layout device, or implements the macro-based multi-mode circuit design method as described above when executed by an EDA device.

[0015] Beneficial effects: A macro-based multi-mode circuit design method, device and medium of the present invention support macro-based multi-mode circuit design. The mode includes a combination of one or more macros. Copying, distributing and merging operations can be performed between modes. Circuit connectivity checks between modes can be performed, and Verilog code based on macro packaging is supported, which greatly improves the efficiency and quality of chip design.

[0016] In order to make the above features and advantages of the invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the steps of the multi-mode circuit design method of the present invention.

[0018] Figure 2 The figure is a schematic diagram of the steps for connectivity check.

[0019] Figure 3 This is an example of performing dispersed operations on instances after encapsulating the multi-mode circuit design method of the present invention into a graphical operation flow. DETAILED DESCRIPTION

[0020] In order to make the purpose and technical solution of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In order to solve the above problems in the chip design process, the present invention provides a macro-based multi-mode circuit design method. Figure 1 The following is a schematic diagram of the steps of the multi-mode circuit design method of the present invention. After the chip designer determines the macro branching scheme of the project, the core steps of the main process of circuit design are as follows:

[0022] Step S1, setting the working mode of the chip project and configuring the relationship between the working mode and the macro, a single working mode includes a combination of one or more macros, and the working mode includes a common mode, an ASIC mode, an FPGA mode, and a DUT mode. The circuit in the common mode is visible and operable in other modes (i.e., the ASIC mode, the FPGA mode, and the DUT mode); the circuits in other modes are mutually exclusive and invisible to each other.

[0023] Step S2, perform syntax and lexical analysis on the corresponding RTL code in the working mode, and abstract the modules, signals, parameters, macros, etc. in the RTL code into classes and data structures in the high-level language C++. Create / modify / delete instances, create / modify / delete ports, create / modify / delete connections, create / modify / delete parameters, create / modify / delete macros, instantiate parameters, etc., and abstract operations such as creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters into operations and processing methods for the above classes and data structures, and build the relationship between modules to form a data relationship model, and each object is marked with a macro, and the objects include signals, parameters, macros, parameter instantiations, wires, and connections.

[0024] In step S2, the module in the RTL code generally includes module name, signal, parameter, macro, instance, connection, wire, which is as follows before conversion:

[0025]

[0026]

[0027] Abstract the objects in the module and convert them into classes and data structures in the high-level language C++. Specifically, the examples are as follows:

[0028] Object After conversion Module Name m_name: string parameter m_params:List<Parameter*> Signal m_ports:List<Ports*> Examples m_instances:List<Instance*> Connection m_connections:List<Connection*> Wire m_wires:List<Wire*> Macro m_macros:List<Macro*>

[0029] The operation on an object is abstracted into the operation and processing method of the class and data structure. Taking "instance" as an example, the example is as follows:

[0030] operate After conversion Create a new instance addInstance(string,Module*,string):Instances* Modify the instance modifyInstance(string,Module*,string):Instances* Deleting an instance delInstance(string,Module*,string):Instances*

[0031] Step S3, based on the data relationship model, copy, distribute, and merge operations are performed between the working modes. Specifically, some circuits in the ASIC mode, FPGA mode, and DUT mode can be copied to each other, and some circuits in the public mode can be distributed to the specified ASIC mode, FPGA mode, and DUT mode. After distribution, the circuits are marked with the macro corresponding to the working mode; the same circuits in the ASIC mode, FPGA mode, and DUT mode can also be merged into the public mode, that is, a circuit exists in all the working modes, and this circuit belongs to the public mode, and the circuit does not need to be wrapped by a macro.

[0032] Step S4, repeatedly adopting the scattering operation and the copying operation in step S3 until the circuit design is completed, after which a new data relationship model is generated.

[0033] Step S5: Check whether the circuit connectivity of all working modes is correct based on the new data relationship model.

[0034] Step S6, after the circuit connectivity check is passed, output the RTL code containing multiple working modes according to the latest data relationship model, and check whether the syntax of the output RTL code complies with the syntax.

[0035] In the above steps, the circuit in step S3 can be abstracted into specific classes and data structures such as instances, ports, parameters, macros, connections, lines, parameter instantiations, etc., and operations such as copying, distributing, and merging are also abstracted into operations and processing on classes and data structures.

[0036] The step S5 is to check the circuit connectivity. Figure 2 The following is a schematic diagram of the steps for connectivity check. Figure 2 As shown, the steps of connectivity check are as follows:

[0037] Step S51, collecting scattered objects, the objects include instances and ports.

[0038] Step S52: collecting connection relationships of objects.

[0039] Step S53, distributing the collected objects and their connection relationships to the specified working mode.

[0040] Step S54, collecting the connection relationship of the dispersed objects in the specified mode.

[0041] Step S55, comparing the connection relationships before and after the dispersion.

[0042] In step S55, if the connection relationship before and after the dispersion is the same, the circuit connectivity check is passed; if the connection relationship is not the same, the dispersion fails.

[0043] In actual use, the multi-mode circuit design method of the present invention can be encapsulated into graphical operations and command line operations to facilitate collaborative work among designers. Figure 3 This is an example of performing dispersed operations on instances after encapsulating the multi-mode circuit design method of the present invention into a graphical operation flow.

[0044] The following code is an example of distributing and copying instances after encapsulating the multi-mode circuit design method of the present invention into a command line operation flow.

[0045] scatter-o test.U_APB_Bridge_0,test.U_AHB_Master_0-M ASIC,FPGA

[0046] copy-o test.U_APB_Bridge_0,test.U_AHB_Master_0-M ASIC,FPGA

[0047] Based on this method, engineers only need to specify the instance to be adjusted and the corresponding mode for dispersing and copying operations, without directly changing the relevant design files. They can quickly obtain the relevant design code and intuitively display the effects before and after the adjustment. They can also check the connectivity of the circuit and output the corresponding dispersing report.

[0048] The multi-mode circuit design method of the present invention can be used in EDA tools to make the circuit design process in the chip more convenient.

[0049] Similarly, the method of the present invention can also be used in an EDA device, wherein the EDA device includes a memory and a processor. The memory is used to store executable instructions that can be run on the processor. The processor is used to execute the multi-mode circuit design method of the present invention when running the executable instructions.

[0050] In addition, the method of the invention can also be used in a computer storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by an EDA device of a chip circuit, the multi-mode circuit design method of the invention is implemented. Or when the computer program is executed by an EDA device, the multi-mode circuit design method of the invention is implemented.

[0051] In summary, the macro-based multi-mode circuit design method, device and medium of the present invention support macro-based multi-mode circuit design. The mode includes a combination of one or more macros. Copying, distributing and merging operations can be performed between modes, and circuit connectivity checks between modes can be performed, supporting Verilog code based on macro packaging.

[0052] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A macro-based multi-mode circuit design method, characterized in that: include, Step S1, setting the working mode of the chip project and configuring the relationship between the working mode and the macro, wherein a single working mode includes a combination of one or more macros, and the working modes include a common mode, an ASIC mode, and an FPGA mode; Step S2, performing syntax and lexical analysis on the corresponding RTL code in the working mode, abstracting the modules, signals, parameters, and macros in the RTL code into classes and data structures in the high-level language C++, abstracting the operations of creating / modifying / deleting instances, creating / modifying / deleting ports, creating / modifying / deleting connections, creating / modifying / deleting parameters, creating / modifying / deleting macros, and instantiating parameters into operations and processing methods for classes and data structures, and constructing the relationship between modules to form a data relationship model, and marking each object with a macro; Step S3, based on the data relationship model, performing copy, distribution, and merging operations between the working modes; Step S4, repeatedly performing the scattering operation and the copying operation in step S3 until the circuit design is completed, and generating a new data relationship model after the operation; Step S5, based on the new data relationship model, checking whether the circuit connectivity of all working modes is correct; Step S6, after the circuit connectivity check is passed, output the RTL code containing multiple working modes according to the new data relationship model, and check whether the syntax of the output RTL code complies with the syntax.

2. A macro-based multi-mode circuit design method as claimed in claim 1, characterized in that: The circuits in the public mode are visible and operable in the ASIC mode and the FPGA mode, but the circuits between the ASIC mode and the FPGA mode are not visible to each other.

3. A macro-based multi-mode circuit design method as claimed in claim 1, characterized in that: Circuits in ASIC mode and FPGA mode can be copied to each other, and circuits in public mode can be distributed to specified ASIC mode and FPGA mode. After distribution, the circuits are marked with the macro corresponding to the mode. The same circuits in ASIC mode and FPGA mode can be merged into a common mode.

4. The macro-based multi-mode circuit design method according to claim 1, characterized in that: The working mode also includes DUT mode. The circuits in ASIC mode, FPGA mode, and DUT mode can be copied to each other. The circuits in the common mode can be distributed to the specified ASIC mode, FPGA mode, and DUT mode. After distribution, the circuits are marked with macros corresponding to the mode. The same circuits in ASIC mode, FPGA mode, and DUT mode can be merged into a common mode.

5. The macro-based multi-mode circuit design method according to claim 1, characterized in that: The circuit in step S3 can be abstracted into instances, ports, parameters, macros, connections, lines, parameters to instantiate specific classes and data structures, and the copy, scatter, and merge operations are abstracted into operations and processing on classes and data structures.

6. The macro-based multi-mode circuit design method according to claim 1, characterized in that: The step of checking circuit connectivity in step S5 includes: Step S51, collecting scattered objects, wherein the objects include instances and ports; Step S52, collecting the connection relationship of the objects; Step S53, distributing the collected objects and their connection relationships to a specified working mode; Step S54, collecting the connection relationship of the dispersed objects in a specified mode; Step S55, comparing the connection relationships before and after the dispersion.

7. A macro-based multi-mode circuit design method according to any one of claims 1 to 6, characterized in that: The macro-based multi-mode circuit design method is encapsulated into graphical operations and command line operations.

8. An electronic design EDA tool, characterized in that: The invention comprises the macro-based multi-mode circuit design method as claimed in any one of claims 1 to 7.

9. An EDA device, characterized in that: The EDA device includes a memory and a processor; wherein, The memory is used to store executable instructions that can be run on the processor; The processor is configured to execute the macro-based multi-mode circuit design method according to any one of claims 1 to 7 when running the executable instructions.

10. A computer storage medium, characterized in that: The computer storage medium stores a computer program, and when the computer program is executed by a layout device of a chip circuit, the macro-based multi-mode circuit design method according to any one of claims 1 to 7 is implemented. Or when executed by an EDA device, the macro-based multi-mode circuit design method as described in any one of claims 1 to 7 is implemented.

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