Multi-interface shared interrupt processing method
By using the MCU to configure the interrupt acquisition cycle and priority of the FPGA in an embedded multi-interface communication system, multiple interfaces are realized, which solves the problem of limited interface number caused by limited FPGA performance resources and reduces the interrupt processing burden of the MCU.
Patent Information
- Application Number
- CN202411750677.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-04-25
AI Technical Summary
In embedded multi-interface communication scenarios, the performance resources of FPGA are limited, resulting in limited number of extended interfaces and large number of MCU reception interrupts, which increases the requirements for MCU interface and performance.
The interrupt acquisition period and priority order of the FPGA external interface chip are read from the configuration file through the microcontrol unit (MCU), and the interrupt acquisition period register and the allow interrupt generation switch register of the FPGA are set through the bus address to realize multi-interface shared interrupt processing.
In MCU+FPGA multi-interface communication, only 1 interrupt resource can be consumed to meet the data transmission and reception communication of all FPGA extended interfaces, dynamically match the interface priority, reducing the number of interrupt processing and performance requirements of the MCU.
Smart Images
Figure CN119883534A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic communication technology, and in particular to a multi-interface shared interrupt processing method. Background Art
[0002] At present, as the system function integration is getting higher and higher, the microcontroller unit of the control unit will need more and more external interfaces for communication. Due to the limitation of hardware interface pins, FPGA devices are often used to expand the interface. Thus, the combination of microcontroller unit + FPGA is formed to solve the increasingly frequent application of embedded multi-interface communication control scenarios.
[0003] However, when using a microcontroller unit + FPGA to implement multi-interface communication, the interface chip configuration and data caching are often performed at the FPGA device, which uses more FPGA resources. As a result, the more extended interfaces there are, the higher the FPGA performance requirements are, resulting in higher costs. Summary of the invention
[0004] In view of the above problems, the present invention provides a multi-interface shared interrupt processing method for overcoming the above problems or at least partially solving the above problems.
[0005] The present invention provides the following scheme:
[0006] A multi-interface shared interrupt processing method, comprising:
[0007] The microcontroller unit reads the interruption acquisition cycle of the FPGA external interface chip from the configuration file, and writes the effective interruption acquisition cycle into the FPGA interruption acquisition cycle register through the bus address, so that the FPGA applies the parameter to the interruption acquisition and recording function; the configuration file is stored in the microcontroller unit;
[0008] After receiving the interrupt, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the off state through the bus address, and the FPGA-microcontroller interrupt generation function of the FPGA turns off the interrupt according to the off state; when the interrupt processing is completed, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the on state through the bus address, and the FPGA-microcontroller interrupt generation module generates an interrupt to the microcontroller according to the latest interrupt cycle collection and recording module interrupt state;
[0009] The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, and stores the information into a global variable for real-time reading and use by the interrupt processing function;
[0010] After the parameter configuration is completed, the micro control unit executes a data receiving process or a data sending process according to the configured parameters.
[0011] Preferably: the micro control unit executes the data receiving process including:
[0012] The FPGA external interface chip generates an interrupt, and the FPGA periodically obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register;
[0013] The FPGA-micro control unit interrupt generation module generates an interrupt and sends it to the micro control unit according to the interrupt status and the FPGA-micro control unit allowing the interrupt generation switch;
[0014] After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address;
[0015] The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information;
[0016] The micro control unit accesses the register of the interface chip through the FPGA, reads the received data, and stores the received data in the receiving ring buffer allocated by the micro control unit.
[0017] Preferably: after the received data of the current external interface chip is read and stored, the FPGA-micro control unit interrupt generation switch register is set to an interrupt generation enable state through the bus address;
[0018] When the application interface process calls the data receiving interface function, data is extracted from the receiving ring buffer and returned to the application program.
[0019] Preferably: the interruption period used by the interruption period collection and recording module is period T intSamp The minimum valid value is the default value T intSamp_min ; The default value T intSamp_min Calculated by the following formula:
[0020]
[0021] Where: T intSamp_timeDelMax50 It indicates the maximum time difference among the 50 time differences from the FPGA starting interruption to the FPGA shutting down the microcontroller unit interruption. It represents the time from the FPGA shutdown to the interruption of the microcontroller unit for the i-th time. Indicates the i-th time that the FPGA starts interrupting the unified acquisition time.
[0022] Preferably: the FLASH storage space of the microcontroller unit stores the FPGA external interface chip interrupt collection cycle T to be used by the application program intSamp_app Parameters, after the microcontroller is powered on, T is read from FLASH intSamp_app , through the bus address from the FPGA register to T intSamp_dflt Read back, if T intSamp_app ≥T intSamp_dflt , then determine T intSamp_app Reasonable, T intSamp_app Write to FPGA as the latest cycle T intSamp Parameters, if T intSamp_app <T intSamp_dflt , then determine T intSamp_app Unreasonable, do not modify the current cycle T of FPGA intSamp parameter.
[0023] Preferably: the method for calculating the interrupt processing priority information includes:
[0024] The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, which is 64 bytes of data, and stores it in the PRI
[64] array;
[0025] Clear the interrupt processing priority matching array SEQ
[64] [2] to zero, and set the interrupt status register value Reg
[64] [2] to zero according to the external interface interrupt status register value Reg
[64] [2] of the FPGA. intStatus If the middle bit is equal to 1, it is valid. The value of the array PRI
[64] corresponding to the valid bit is stored in the first column of the interrupt processing priority matching array SEQ
[64] [2], and the array sequence number of PRI
[64] is stored in the second column of SEQ
[64] [2].
[0026] The number of bits that are equal to 1 is m;
[0027] Match the first column of data in the array SEQ
[64] [2] according to the interrupt processing priority order, sort SEQ[0][0] to SEQ[m-1][0], and exchange the second column of data synchronously with the sorting result of the first column of data during sorting;
[0028] The micro control unit processes the external interface interrupts corresponding to the values of SEQ[0][1] to SEQ[m-1][1] in sequence.
[0029] Preferably: the micro control unit executes the data sending process including:
[0030] The application program inputs the data to be sent, and the microcontroller interface driver stores the data into the sending ring buffer, and accesses the register of the external interface chip through the FPGA to control the external interface chip to generate a sending interrupt;
[0031] The FPGA obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register;
[0032] The FPGA-micro control unit interrupt generation module generates a switch according to the interrupt status and the interrupt permission, and sends the interrupt to the micro control unit;
[0033] After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address;
[0034] The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information;
[0035] The micro control unit accesses the register of the external interface chip through the FPGA, controls the external interface chip to close the sending interrupt, and writes the data of the sending ring buffer into the external interface chip.
[0036] Preferably: the interrupt is turned on by enabling the interrupt generation switch register;
[0037] After the data of the sending ring buffer is completely written into the register of the external interface chip, the FPGA-micro control unit interrupt generation switch register is set to the interrupt generation enable state through the bus address.
[0038] Preferably, the communication bus between the micro control unit and the FPGA has one or more interrupts, and the micro control unit can access the register address space of the FPGA through the bus address.
[0039] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0040] The embodiment of the present application provides a multi-interface shared interrupt processing method, in which the MCU implements the configuration and data cache of the interface locally, and only consumes one interrupt resource to meet the data transmission and reception communication of all FPGA expansion interfaces, while realizing dynamic matching of interface priority, and the FPGA does not need to implement communication data cache and interface control logic. It solves the limitation on the number of expansion interfaces when the FPGA performance resources are limited, and under the premise of ensuring the real-time performance of the interface communication, it greatly reduces the number of MCU receiving interrupts and reduces the requirements for the MCU interface and performance.
[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0043] Figure 1 The present invention provides a flowchart of a method for processing a multi-interface shared interruption. DETAILED DESCRIPTION
[0044] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0045] See also Figure 1 , a multi-interface shared interrupt processing method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may include:
[0046] The microcontroller unit reads the interruption acquisition cycle of the FPGA external interface chip from the configuration file, and writes the effective interruption acquisition cycle into the FPGA interruption acquisition cycle register through the bus address, so that the FPGA applies the parameter to the interruption acquisition and recording function; the configuration file is stored in the microcontroller unit;
[0047] After receiving the interrupt, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the off state through the bus address, and the FPGA-microcontroller interrupt generation function of the FPGA turns off the interrupt according to the off state; when the interrupt processing is completed, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the on state through the bus address, and the FPGA-microcontroller interrupt generation module generates an interrupt to the microcontroller according to the latest interrupt cycle collection and recording module interrupt state;
[0048] The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, and stores the information into a global variable for real-time reading and use by the interrupt processing function;
[0049] After the parameter configuration is completed, the micro control unit executes a data receiving process or a data sending process according to the configured parameters.
[0050] The multi-interface shared interrupt processing method provided in the embodiment of the present application realizes that when the MCU+FPGA multi-interfaces communicate, the MCU caches the configuration and data of the interface locally, and only consumes one interrupt resource to meet the data transmission and reception communication of all FPGA expansion interfaces, while realizing dynamic matching of interface priority, and the FPGA does not need to implement communication data caching and interface control logic. It solves the limitation on the number of expansion interfaces when the FPGA performance resources are limited, and under the premise of ensuring the real-time performance of the interface communication, it greatly reduces the number of MCU reception interrupts and reduces the requirements for the MCU interface and performance.
[0051] The micro control unit can perform data reception and data transmission. In a specific implementation, the micro control unit performs a data reception process including:
[0052] The FPGA external interface chip generates an interrupt, and the FPGA periodically obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register;
[0053] The FPGA-micro control unit interrupt generation module generates an interrupt and sends it to the micro control unit according to the interrupt status and the FPGA-micro control unit allowing the interrupt generation switch;
[0054] After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address;
[0055] The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information;
[0056] The micro control unit accesses the register of the interface chip through the FPGA, reads the received data, and stores the received data in the receiving ring buffer allocated by the micro control unit.
[0057] Further, after the received data of the current external interface chip is read and stored, the FPGA-microcontroller unit interrupt generation switch register is set to an interrupt generation enable state through the bus address;
[0058] When the application interface process calls the data receiving interface function, data is extracted from the receiving ring buffer and returned to the application program.
[0059] The interruption period used by the interruption period collection and recording module is period T intSamp The minimum valid value is the default value T intSamp_min ; The default value T intSamp_min Calculated by the following formula:
[0060]
[0061] Where: T intSamp_timeDelMax50 It indicates the maximum time difference among the 50 time differences from the FPGA starting interruption to the FPGA shutting down the microcontroller unit interruption. It represents the time from the FPGA shutdown to the interruption of the microcontroller unit for the i-th time. Indicates the i-th time that the FPGA starts interrupting the unified acquisition time.
[0062] The FLASH storage space of the microcontroller unit stores the FPGA external interface chip interrupt collection cycle T that the application is ready to use. intSamp_app Parameters, after the microcontroller is powered on, T is read from FLASH intSamp_app , through the bus address from the FPGA register to T intSamp_dflt Read back, if T intSamp_app ≥T intSamp_dflt , then determine T intSamp_app Reasonable, T intSamp_app Write to FPGA as the latest cycle T intSamp Parameters, if T intSamp_app <T intSamp_dflt , then determine T intSamp_app Unreasonable, do not modify the current cycle T of FPGA intSamp parameter.
[0063] The method for calculating the interrupt processing priority information includes:
[0064] The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, which is 64 bytes of data, and stores it in the PRI
[64] array;
[0065] Clear the interrupt processing priority matching array SEQ
[64] [2] to zero, and set the interrupt status register value Reg
[64] [2] to zero according to the external interface interrupt status register value Reg
[64] [2] of the FPGA. intStatus If the middle bit is equal to 1, it is valid. The value of the array PRI
[64] corresponding to the valid bit is stored in the first column of the interrupt processing priority matching array SEQ
[64] [2], and the array sequence number of PRI
[64] is stored in the second column of SEQ
[64] [2].
[0066] The number of bits that are equal to 1 is m;
[0067] Match the first column of data in the array SEQ
[64] [2] according to the interrupt processing priority order, sort SEQ[0][0] to SEQ[m-1][0], and exchange the second column of data synchronously with the sorting result of the first column of data during sorting;
[0068] The micro control unit processes the external interface interrupts corresponding to the values of SEQ[0][1] to SEQ[m-1][1] in sequence.
[0069] The microcontroller unit performs a data transmission process including:
[0070] The application program inputs the data to be sent, and the microcontroller interface driver stores the data into the sending ring buffer, and accesses the register of the external interface chip through the FPGA to control the external interface chip to generate a sending interrupt;
[0071] The FPGA obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register;
[0072] The FPGA-micro control unit interrupt generation module generates a switch according to the interrupt status and the interrupt permission, and sends the interrupt to the micro control unit;
[0073] After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address;
[0074] The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information;
[0075] The micro control unit accesses the register of the external interface chip through the FPGA, controls the external interface chip to close the sending interrupt, and writes the data of the sending ring buffer into the external interface chip.
[0076] Furthermore, the interrupt is turned on by enabling the interrupt generation switch register;
[0077] After the data of the sending ring buffer is completely written into the register of the external interface chip, the FPGA-micro control unit interrupt generation switch register is set to the interrupt generation enable state through the bus address.
[0078] Furthermore, the communication bus between the micro control unit and the FPGA has one or more interrupts, and the micro control unit can access the register address space of the FPGA through the bus address.
[0079] The following is a detailed introduction to the multi-interface shared interrupt processing method provided by this application.
[0080] The method provided in the embodiment of the present application aims to solve the problem of insufficient multi-interface concurrent communication capability in an embedded multi-interface real-time communication application scenario when the interface and performance resources of the MCU and FPGA are limited.
[0081] 1. Requirements for communication between MCU and FPGA interface.
[0082] The requirements for the multi-interface shared interrupt processing communication interface are: the communication bus between the MCU (microcontroller unit) and the FPGA has 1 or more interrupts, and the MCU can access the register address space of the FPGA through the bus address.
[0083] 2. Implement functions on the FPGA side.
[0084] a. Parameter configuration.
[0085] FPGA obtains the FPGA external interface chip interrupt collection cycle configured by MCU through the bus address and applies it.
[0086] The FPGA obtains the FPGA-MCU interrupt enable switch set by the MCU through the bus address, thereby enabling the MCU to control whether to allow interrupt input.
[0087] b. Interrupt period collection and recording.
[0088] According to the interrupt collection cycle configured by default or MCU, the FPGA periodically collects the interrupt status of the external interface chip, forms an external interrupt flag by ORing all external interrupt status (enabled or disabled), and stores it in the external interrupt flag register.
[0089] FPGA external interface chip interrupt collection cycle design:
[0090] FPGA collects the interrupt status of all external interface chips in a unified manner. The collection method is periodic triggering with a period of T intSamp , after FPGA is powered on, use T intSamp The minimum valid value is the default value T intSamp_min , this value can be read back and modified by the MCU through the bus address. Set T intSamp_min The time should be greater than the unified acquisition time t from the start of FPGA interruption FPGA_Samp , until MCU responds to interrupt reception time t MCU_ISR , and then the MCU writes the FPGA register through the bus address to realize the time t from closing the FPGA to the MCU interrupt FPGA_closeInt , that is, the time difference from when the FPGA starts interrupting unified collection to when the FPGA shuts down the MCU interrupt is expressed as follows:
[0091] T intSamp_timeDel =t FPGA_closeInt -t FPGA_Samp
[0092] This time can be measured by FPGA. Since the MCU interrupt has strong real-time performance and the FPGA has stronger real-time performance, it is considered that T intSamp_timeDelThe value is stable and reliable. Perform 50 measurements and take the maximum time difference T intSamp_timeDelMax50 , and then 20% redundancy is obtained, which is expressed by the following formula:
[0093]
[0094] The MCU's FLASH storage space stores the FPGA external interface chip interrupt collection cycle T that the application is going to use. intSamp_app Parameters, after the MCU is powered on, read T from FLASH intSamp_app Then, the bus address is used to transfer T from the FPGA register. intSamp_dflt Read back.
[0095] If T intSamp_app ≥T intSamp_dflt , then we think that T intSamp_app Reasonable, then T intSamp_app Write to FPGA as the latest T intSamp parameter.
[0096] If T intSamp_app <T intSamp_dflt , then we think that T intSamp_app Unreasonable, do not modify the current T of FPGA intSamp parameter.
[0097] c. FPGA-MCU interrupt generation.
[0098] Read the external interrupt flag register and the FPGA-MCU interrupt generation switch register. When the external interrupt flag is enabled and the FPGA-MCU interrupt generation switch is on, the FPGA sends an interrupt to the MCU. When the external interrupt flag is disabled or the FPGA-MCU interrupt generation switch is off, the FPGA does not send an interrupt to the MCU.
[0099] d. Access the registers of the external interface chip.
[0100] The registers of the external interface chip are mapped to the MCU for access through the bus address.
[0101] 3. Implement functions on the MCU side.
[0102] a. Parameter configuration.
[0103] The MCU reads the interrupt processing priority of the external interface of the FPGA extension from the configuration file and stores the information in the global variable for priority matching during interrupt processing.
[0104] The MCU reads the FPGA external interface chip interrupt collection cycle from the configuration file and writes the FPGA register through the bus address.
[0105] b. Interrupt processing.
[0106] In the interrupt response function, first write the FPGA register through the bus address to turn off the generation of FPGA to MCU interrupts. Access the FPGA's external interface interrupt status register through the bus address to obtain the interrupt information of all current external interfaces and store the information in the message queue.
[0107] In the interrupt processing task, the external interface interrupt information is obtained from the message queue, and the external interface interrupt events are processed in sequence according to the external interface interrupt processing priority configured by the MCU. The register of the external interface chip is read through the bus address to determine whether it is a send interrupt or a receive interrupt.
[0108] If it is a "send interrupt", the data to be sent is read from the "send ring buffer", written into the corresponding register of the external interface chip through the address, and the register status is read back to confirm whether the sending is successful.
[0109] If it is a "receive interrupt", the received data is read from the external interface chip register through the address, and the register status is read back to confirm whether the data has been read. The data is stored in the data "receive ring buffer" of the corresponding interface.
[0110] After all external interface interrupts are processed in priority order, the FPGA register is written through the bus address to turn on the switch that allows interrupts from FPGA to MCU.
[0111] MCU interrupt processing priority dynamic matching design:
[0112] The MCU reads the external interface interrupt processing priority of the FPGA extension from the configuration file. The content is 64 bytes of data and is stored in the PRI
[64] array. The array number is the same as the FPGA external interface interrupt status register value Reg intStatus PRI[0] indicates the interrupt priority corresponding to bit 0, PRI[1] indicates the interrupt priority corresponding to bit 1, and so on. The value range of PRI
[64] is 0-255, where 0 indicates the highest priority and 255 indicates the lowest priority.
[0113] In the interrupt processing task, the MCU follows PRI
[64] and Reg intStatus Generate interrupt processing priority matching array SEQ
[64] [2] and the number of valid bits of interrupt status register value m. The row numbers of SEQ
[64] [2] array are 0-63, indicating the priority order from front to back. The valid range of the first column value is 0-255, representing the priority, and the valid range of the second column value is 0-63, indicating Reg intStatusThe bit number of the external interface interrupt corresponding to the bit position.
[0114] Calculation method steps:
[0115] First clear SEQ
[64] [2] to zero, then intStatus The bit in the middle is equal to 1 for valid, and the PRI
[64] value (i.e., priority) corresponding to the valid bit is stored in the first column of SEQ
[64] [2], i.e., SEQ[x][0], and the array number of PRI
[64] (i.e., the bit number of the interrupt status register) is stored in the second column of SEQ
[64] [2], i.e., SEQ[x][1].
[0116] The number of bits that are equal to 1 is m.
[0117] According to the first column data of SEQ
[64] [2], that is, the priority value, SEQ[0][0] to SEQ[m-1][0] are sorted, and the second column data is exchanged synchronously with the sorting result of the first column data during sorting.
[0118] Finally, the MCU processes the external interface interrupts corresponding to the values of SEQ[0][1] to SEQ[m-1][1] in turn, thus achieving the purpose of dynamic priority matching.
[0119] c. Application interface processing.
[0120] External interface data transmission: The application program inputs the data to be sent, and the MCU interface driver stores the data in the "send ring buffer", accesses the register of the external interface chip through the address, and controls the external interface chip to generate a "send interrupt" to the FPGA.
[0121] External interface data reception: The application passes the address and length information of the receive buffer. The MCU interface driver extracts the amount of data not greater than the length passed by the application from the "receive ring buffer" of the corresponding interface and stores it in the address space of the receive buffer passed by the application.
[0122] The process of the shared interrupt data transmission method provided in the embodiment of the present application includes:
[0123] a. Parameter configuration process.
[0124] i. MCU reads the interrupt collection cycle of the FPGA external interface chip from the configuration file, writes the valid interrupt collection cycle into the FPGA interrupt collection cycle register through the bus address, and the FPGA applies this parameter to the interrupt collection and recording function.
[0125] ii. After receiving the interrupt, the MCU immediately sets the FPGA-MCU interrupt generation switch register to the off state through the bus address, and the FPGA-MCU interrupt generation function of the FPGA turns off the interrupt according to this state. When the interrupt processing is completed, the MCU sets the FPGA-MCU interrupt generation switch register to the on state through the bus address, and the FPGA-MCU interrupt generation module collects and records the module interrupt status according to the latest interrupt cycle, and generates an interrupt to the MCU.
[0126] iii. MCU reads the interrupt processing priority of the external interface of the FPGA extension from the configuration file and stores the information in the global variable for real-time reading and use by the interrupt processing function.
[0127] b. Data receiving process.
[0128] i. When the external interface chip generates an interrupt, the FPGA obtains the interrupt status through the interrupt cycle acquisition and recording module and records it in the external interrupt identification register.
[0129] ii. The FPGA-MCU interrupt generation module generates an interrupt and sends it to the MCU based on the interrupt status and the FPGA-MCU interrupt generation switch.
[0130] iii. After the MCU receives the interrupt, it sets the FPGA-MCU interrupt generation switch register to the "interrupt generation is not allowed" state through the bus address.
[0131] iv. MCU reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information.
[0132] v. MCU accesses the registers of the interface chip through the FPGA, reads the received data, and then stores it in the "receive ring buffer" allocated by the MCU.
[0133] vi. After reading and storing the received data of the current external interface chip, set the FPGA-MCU interrupt enable switch register to the "interrupt enable" state through the bus address.
[0134] vii. When the application interface process calls the data receiving interface function, it extracts data from the "receive ring buffer" and returns it to the application.
[0135] c. Data sending process:
[0136] i. The application program inputs the data to be sent, and the MCU interface driver stores the data into the "send ring buffer" and accesses the registers of the external interface chip through the FPGA to control the external interface chip to generate a "send interrupt".
[0137] ii. FPGA obtains the interrupt status through the interrupt cycle acquisition and recording module and records it in the external interrupt identification register.
[0138] iii. The FPGA-MCU interrupt generation module generates switches based on the interrupt status and the interrupt enable, and sends the interrupt to the MCU.
[0139] iv. After the MCU receives the interrupt, it sets the FPGA-MCU interrupt generation switch register to the "interrupt generation is not allowed" state through the bus address.
[0140] v. MCU reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information.
[0141] vi.MCU accesses the registers of the external interface chip through FPGA, controls the external interface chip to turn off the "send interrupt", and writes the data of the "send ring buffer" into the external interface chip.
[0142] vii. Then enable the interrupt by enabling the interrupt generation switch register.
[0143] viii. After the data of the "send ring buffer" is completely written into the register of the external interface chip, the FPGA-MCU interrupt enable switch register is set to the "interrupt enable" state through the bus address.
[0144] In summary, the multi-interface shared interrupt processing method provided by the present application solves the problem of insufficient multi-interface concurrent communication capability when the MCU, FPGA interface and performance resources are limited in the embedded multi-interface real-time communication application scenario. Through the multi-interface shared interrupt processing method, the dependence on the MCU, FPGA interface and performance resources can be reduced while satisfying the multi-interface concurrent communication capability. In actual application scenarios, the purpose of reducing costs and power consumption can be achieved.
[0145] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0146] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.
[0147] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.
[0148] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A multi-interface shared interrupt processing method, characterized in that: include: The microcontroller unit reads the interruption acquisition cycle of the FPGA external interface chip from the configuration file, and writes the effective interruption acquisition cycle into the FPGA interruption acquisition cycle register through the bus address, so that the FPGA applies the parameter to the interruption acquisition and recording function; the configuration file is stored in the microcontroller unit; After receiving the interrupt, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the off state through the bus address, and the FPGA-microcontroller interrupt generation function of the FPGA turns off the interrupt according to the off state; when the interrupt processing is completed, the microcontroller sets the interrupt generation switch register of the FPGA-microcontroller to the on state through the bus address, and the FPGA-microcontroller interrupt generation module generates an interrupt to the microcontroller according to the latest interrupt cycle collection and recording module interrupt state; The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, and stores the information into a global variable for real-time reading and use by the interrupt processing function; After the parameter configuration is completed, the micro control unit executes a data receiving process or a data sending process according to the configured parameters.
2. The multi-interface shared interrupt processing method according to claim 1, characterized in that: The microcontroller unit performs a data receiving process including: The FPGA external interface chip generates an interrupt, and the FPGA periodically obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register; The FPGA-micro control unit interrupt generation module generates an interrupt and sends it to the micro control unit according to the interrupt status and the FPGA-micro control unit allowing the interrupt generation switch; After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address; The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information; The micro control unit accesses the register of the interface chip through the FPGA, reads the received data and stores the received data into the receiving ring buffer allocated by the micro control unit.
3. The multi-interface shared interrupt processing method according to claim 2, characterized in that: After the received data of the current external interface chip is read and stored, the FPGA-microcontroller unit interrupt generation switch register is set to an interrupt generation enable state through the bus address; When the application interface process calls the data receiving interface function, data is extracted from the receiving ring buffer and returned to the application program.
4. The multi-interface shared interrupt processing method according to claim 2, characterized in that: The interruption period used by the interruption period collection and recording module is period T intSamp The minimum valid value is the default value T intSamp_min ; The default value T intSamp_min Calculated by the following formula: Where: T intSamp_timeDelMax50 It indicates the maximum time difference among the 50 time differences from the FPGA starting interruption to the FPGA shutting down the microcontroller unit interruption. It represents the time from the FPGA shutdown to the interruption of the microcontroller unit for the i-th time. Indicates the i-th time that the FPGA starts interrupting the unified acquisition time.
5. The multi-interface shared interrupt processing method according to claim 4, characterized in that: The FLASH storage space of the microcontroller unit stores the FPGA external interface chip interrupt collection cycle T that the application is ready to use. intSamp_app Parameters, after the microcontroller is powered on, T is read from FLASH intSamp_app , through the bus address from the FPGA register to T intSamp_dflt Read back, if T intSamp_app ≥T intSamp_dflt , then determine T intSamp_app Reasonable, T intSamp_app Write to FPGA as the latest cycle T intSamp Parameters, if T intSamp_app <T intSamp_dflt , then determine T intSamp_app Unreasonable, do not modify the current cycle T of FPGA intSamp parameter.
6. The multi-interface shared interrupt processing method according to claim 4, characterized in that: The method for calculating the interrupt processing priority information includes: The microcontroller unit reads the external interface interrupt processing priority of the FPGA extension from the configuration file, which is 64 bytes of data, and stores it in the PRI[64] array; Clear the interrupt processing priority matching array SEQ[64][2] to zero, and set the interrupt status register value Reg[64][2] to zero according to the external interface interrupt status register value Reg[64][2] of the FPGA. intStatus If the middle bit is equal to 1, it is valid. The value of the array PRI[64] corresponding to the valid bit is stored in the first column of the interrupt processing priority matching array SEQ[64][2], and the array sequence number of PRI[64] is stored in the second column of SEQ[64][2]. The number of bits that are equal to 1 is m; Match the first column of data in the array SEQ[64][2] according to the interrupt processing priority order, sort SEQ[0][0] to SEQ[m-1][0], and exchange the second column of data synchronously with the sorting result of the first column of data during sorting; The micro control unit processes the external interface interrupts corresponding to the values of SEQ[0][1] to SEQ[m-1][1] in sequence.
7. The multi-interface shared interrupt processing method according to claim 1, characterized in that: The microcontroller unit performs a data transmission process including: The application program inputs the data to be sent, and the microcontroller interface driver stores the data into the sending ring buffer, and accesses the register of the external interface chip through the FPGA to control the external interface chip to generate a sending interrupt; The FPGA obtains the interrupt status through the interrupt cycle acquisition and recording module, and records it in the external interrupt identification register; The FPGA-micro control unit interrupt generation module generates a switch according to the interrupt status and the interrupt permission, and sends an interrupt to the micro control unit; After receiving the interrupt, the microcontroller unit sets the FPGA-microcontroller unit interrupt generation switch register to a state where the interrupt generation is not allowed through the bus address; The microcontroller unit reads the external interrupt identification register to obtain the current external interrupt status, and performs real-time priority processing on the current external interrupt after calculating with the interrupt processing priority information; The micro control unit accesses the register of the external interface chip through the FPGA, controls the external interface chip to close the sending interrupt, and writes the data of the sending ring buffer into the external interface chip.
8. The multi-interface shared interrupt processing method according to claim 7, characterized in that: Enable the interrupt by enabling the interrupt generation switch register; After the data of the sending ring buffer is completely written into the register of the external interface chip, the FPGA-micro control unit interrupt generation switch register is set to the interrupt generation enable state through the bus address.
9. The multi-interface shared interrupt processing method according to claim 1, characterized in that: The communication bus between the micro control unit and the FPGA has one or more interrupts, and the micro control unit can access the register address space of the FPGA through the bus address.