Method and device for optimizing reading performance of flash memory in controller and storage medium

Abstract

The invention discloses an optimization method and device for reading performance of a flash memory in a controller and a storage medium, and belongs to the technical field of flash memories.The method comprises the steps that a preset characteristic quantity, the number of erasing and writing reading times and data retention time are input into a current prediction model to obtain a reading voltage offset interval; the method for predicting the threshold voltage distribution of the flash memory according to the use condition of the flash memory is more real-time; on the basis of reading the voltage offset interval, performing read retry operation; during read retry operation, only one offset value of read voltage is adjusted to change in each page, and other voltage offset values in the same page change along with the change of the offset value of the read voltage; through the correlation of different read voltage deviation values of the same page, the number of times of re-reading is greatly reduced, the re-reading time is shortened, the reading performance is improved, the current prediction model is further updated and stored by utilizing threshold voltage distribution data determined by the read re-try operation, and the updated prediction model is used for the next read operation, so that the prediction accuracy is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of flash memory, and more specifically, relates to a method, device and storage medium for optimizing the reading performance of flash memory in a controller. Background Art

[0002] Flash memory, as a non-volatile storage medium, is widely used in today's electronic devices, from smartphones and tablets to solid-state drives. With the continuous development of technology, the requirements for flash memory read performance are getting higher and higher. Mobile devices such as smartphones and tablets require fast flash memory read performance to quickly start applications and load multimedia content such as photos and videos. SSDs are increasingly used in computer systems, and flash memory read performance directly affects the system startup speed, file transfer speed, and application response time.

[0003] The manufacturing process of flash memory chips is constantly improving, which has led to a continuous increase in storage density and improved reading performance. The design of flash memory controllers is also constantly being optimized to improve the efficiency and reliability of data transmission. The controller can use more advanced algorithms to manage flash memory chips to improve reading speed and life. When reading flash memory, read retry and error correction code are often used in coordination. In actual operation, with repeated erasure and long-term data retention, the optimal read voltage will shift, causing read errors. At this time, the controller will adjust the read reference voltage to repeat the reading until the error rate returns to the error correction capability of the error correction code. This method effectively ensures the reliability of flash memory reading results.

[0004] However, the default initial read voltage offset of the flash memory is often 0, and the number of repeated reads is large, which greatly increases the read time of the flash memory and reduces the read performance of the flash memory. In summary, a new read optimization method is needed to improve the read rate while ensuring read reliability. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention provides a method, device and storage medium for optimizing the flash memory reading performance in a controller, aiming to solve the technical problem in the prior art that the flash memory reading voltage offset causes the read retry step to be too cumbersome, thereby causing the read and write performance to deteriorate.

[0006] To achieve the above object, according to one aspect of the present invention, a method for optimizing the read performance of flash memory in a controller is provided, comprising: S1: When receiving the current read operation, extract the preset feature quantity, erase and write read times and data retention time of the flash memory chip; S2: inputting the preset characteristic quantity, the number of erase / write reads and the data retention time into the current prediction model to predict a threshold voltage distribution; determining a read voltage offset interval from the threshold voltage distribution; S3: Based on the read voltage offset interval, a read retry operation is performed until a target interval is found, and a read is performed in the target interval to obtain an error number and a corresponding page number; Wherein, during the read retry operation, each page only adjusts the offset value change of one read voltage, and other voltage offset values ​​under the same page change following the change of the offset value change of the read voltage; S4: Calculating threshold voltage distribution data using the error number and its corresponding page number; S5: Using the threshold voltage distribution data, the current prediction model is updated and saved for predicting the corresponding threshold voltage distribution during the next read operation.

[0007] Furthermore, the preset characteristic quantity includes: a storage unit number and a storage page number of the flash memory chip.

[0008] Furthermore, the preset characteristic quantity also includes: one or more of programming time, reading time, erasing time, and current of the flash memory chip.

[0009] Furthermore, before S2, it also includes: taking preset feature quantities, erase and write read times, and data retention time in a sample set corresponding to a preset flash memory chip as input, and taking a threshold voltage distribution corresponding to the preset flash memory chip as output, training an initial prediction model to obtain the current prediction model in the first read operation.

[0010] Furthermore, the process of obtaining the sample set includes: Step 1. Erase the flash memory chip under test; Step 2. Writing test data to the flash memory chip under test; Step 3. Wait for a time T0, perform a read operation on the flash memory chip under test, compare the read data with the data written in step 3, count the number of errors generated, and store them in the sample set; Step 4. Determine whether the number of times the flash memory chip under test has been erased, written, and read is less than a first threshold value C1. If so, repeat steps 1 to 3; otherwise, proceed to step 5. Step 5. Power off waiting time T1; Step 6. Perform a read operation, save the read data, collect chip parameters and store them in the sample set; Step 7. Waiting time T2; Step 8. Perform a data reading operation on the flash memory chip under test, compare the read data with the data saved in step 6, count the number of errors generated during the statistical data retention period, and collect chip parameters and store them in the sample set; Step 9. Determine whether the total data retention time exceeds time T3, if it is less, repeat steps 7 and 8, otherwise proceed to step 10 and clear the total data retention time count; Step 10: Determine whether the cumulative number of erase / write / read times executed exceeds the second threshold value C2. If so, repeat steps 1 to 9. Otherwise, complete the test.

[0011] Furthermore, the read retry step length L of the i-th read reference voltage of the same page i and the jth read reference voltage read retry step length L j The relationship conforms to the formula: L i =a×L j ; where a is the proportionality coefficient, which can be expressed by the formula a=△R i / △R j Calculation shows that △R i =(R i -R i ' ), △R j = (R j -R j ' ), R i is the center value of the i-th read reference voltage on the same page, R j is the jth read reference voltage center value, R i ' and R j ' It is the initial read reference voltage center value set when the flash memory chip leaves the factory. Therefore, the read retry interval can be determined according to the read reference voltage center value and the read retry step size.

[0012] According to another aspect of the present invention, there is provided a device for optimizing flash memory read performance, comprising: An extraction module, used for extracting preset characteristic quantities, erase and write read times and data retention time of the flash memory chip when receiving a current read operation; A prediction module, configured to input the preset characteristic quantity, the number of erase / write reads and the data retention time into a current prediction model to predict a threshold voltage distribution; and determine a read voltage offset interval from the threshold voltage distribution; A read retry module, configured to perform a read retry operation on the basis of the read voltage offset interval until a target interval is found, and to read the target interval to obtain an error number and a corresponding page number; wherein, during the read retry operation, only one read voltage offset value is adjusted for each page, and other voltage offset values ​​under the same page change in accordance with the read voltage offset value; A calculation module, used for calculating the threshold voltage distribution data by using the error number and its corresponding page number; An updating module is used to update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

[0013] According to another aspect of the present invention, there is provided a flash memory system, comprising: a flash memory chip and a controller; The controller stores a computer program for implementing the steps of the method for optimizing the flash memory reading performance in the controller when the computer program is executed.

[0014] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for optimizing the flash memory reading performance in the controller are implemented.

[0015] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art: (1) The present invention inputs the preset characteristic quantity, the number of erase and write reads and the data retention time into the current prediction model to obtain a read voltage offset interval; predicts the threshold voltage distribution of the flash memory according to the usage of the flash memory, which is more real-time than using the initial threshold voltage as a reference during a general read retry operation; based on the read voltage offset interval, a read retry operation is performed until a target interval is found and the number of errors and its corresponding page number are obtained; during the read retry operation, only one read voltage offset value is adjusted for each page, and other voltage offset values ​​under the same page change with the read voltage offset value; the correlation between different read voltage offset values ​​of the same page greatly reduces the number of read-retry times, reduces the reread time, and improves the read performance; further, the threshold voltage distribution data is used to update the current prediction model and save it for predicting the corresponding threshold voltage distribution during the next read operation; the updated prediction model is used for the next read operation, which is more in line with the actual situation of each flash memory chip in the actual situation compared with a fixed prediction model, thereby increasing the accuracy of the prediction.

[0016] (2) The preset feature quantities in this solution include: the storage unit number and storage page number of the flash memory chip. This design takes into account the impact of the differences in the specific storage units and storage pages of the flash memory chip on the prediction model, and maintains the stability of the model's performance.

[0017] (3) The preset feature quantities in this solution also include: one or more of the programming time, reading time, erasing time, and current of the flash memory chip. This design takes into account the manifestation of flash memory chip aging in multiple feature quantities during actual use, and enhances the robustness of the prediction model.

[0018] (4) In this scheme, the preset feature quantity, erase and read times, and data retention time in the sample set corresponding to the preset flash memory chip are used as input, and the threshold voltage distribution corresponding to the preset flash memory chip is used as output to train the initial prediction model; the training of the initial prediction model takes into account the wear and aging characteristics of the flash memory, and realizes the prediction of the relationship between the threshold voltage change and the wear and aging of the flash memory.

[0019] (5) This solution simulates the usage of flash memory in actual applications during the sample set acquisition process, and collects parameters during the use process as the sample set, so that the model is more suitable for the application situation and the prediction accuracy is improved.

[0020] (6) This scheme sets the read retry step length L for the i-th read reference voltage of the same page i and the jth read reference voltage read retry step length L j The relationship conforms to the formula: L i =a×L j ; This design takes into account the correlation of changes in different read reference voltages of the same page, reduces the number of read retries, and improves the reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a flowchart of a method for optimizing the reading performance of flash memory in a controller provided by an embodiment of the present invention.

[0022] Figure 2 A schematic diagram of a process for establishing a prediction model provided by an embodiment of the present invention.

[0023] Figure 3 A schematic diagram of a process for obtaining a sample set provided by an embodiment of the present invention.

[0024] Figure 4 A schematic diagram of determining a read reference voltage scanning interval according to a threshold voltage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] like Figure 1 As shown, this embodiment provides a method for optimizing the read performance of flash memory in a controller, including: S1-S5. Wherein, S1: when receiving the current read operation, extract the preset feature quantity, the number of erase and write reads, and the data retention time of the flash memory chip. S2: input the preset feature quantity, the number of erase and write reads, and the data retention time into the current prediction model, predict the threshold voltage distribution; determine the read voltage offset interval from the threshold voltage distribution. S3: on the basis of the read voltage offset interval, perform a read retry operation until the target interval is found, and read the target interval to obtain the number of errors and their corresponding page numbers; wherein, during the read retry operation, each page only adjusts the offset value change of one read voltage, and the other voltage offset values ​​under the same page change with the change of the read voltage offset value. S4: calculate the threshold voltage distribution data using the number of errors and their corresponding page numbers. S5: update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

[0027] It should be noted that most technologies on the market are designed for the flash memory chip itself. After the flash memory is processed and packaged in the device, many parameters cannot be extracted due to the existence of the firmware layer. This solution is based on the controller, so that the flash memory of the packaged device (such as SSD, etc.) can also be predicted, so as to optimize the reading. All algorithm models are fixed in the controller.

[0028] Further, the preset characteristic quantity includes: a storage unit number and a storage page number of the flash memory chip. Further, the preset characteristic quantity also includes: one or more of the programming time, reading time, erasing time, and current of the flash memory chip.

[0029] Furthermore, before S2, it also includes: taking the initial preset feature quantity, initial erase and write read times and corresponding data retention time in the sample set corresponding to the preset flash memory chip as input, and taking the threshold voltage distribution corresponding to the preset flash memory chip as output, training the initial prediction model to obtain the current prediction model in the first read operation.

[0030] Figure 2The flowchart of establishing a prediction model for an embodiment of the present invention is shown in FIG. The model type used in this embodiment is a multi-layer artificial neural network. The artificial neural network comprises: an input layer, a hidden layer, a softmax layer, and an output layer. Among them, the number of hidden layers is 10, the number of units in each layer is 50, and the activation function is sigmoid. The model can be the same as the input and application stages. 70% of the parameter data set obtained by the test is randomly selected as the training set, and the remaining 30% is the test set. The specific steps of the prediction model building are as follows: 1. Initialize the training algorithm; 2. The training set data is input into the artificial neural network, and the training algorithm calculates the error between the output of the artificial neural network and the actual value; 3. The training algorithm adjusts the weights of the artificial neural network; 4. Determine whether the epoch number reaches 100. If it reaches 100, stop training, otherwise return to step 2; 5. The program outputs the prediction model.

[0031] Furthermore, the process of acquiring the sample set is as follows: the storage cells in the flash memory chip are sampled, and the storage cells with the same number of odd block numbers and even block numbers are randomly selected, and the selected storage cells are ensured to be evenly distributed in the entire address range of the chip. For each selected storage cell, the flash memory chip randomly selects a word line storage cell for testing to obtain a sample set. The process is as follows Figure 3 shown.

[0032] At room temperature, place the selected flash memory chip in the test equipment and power on the test equipment. In this embodiment, the test data used in the flash memory test is pseudo-random test data, the number of erase / program cycles is C1, the total number of erase / program cycles is C2, the waiting time is T0, the flash memory chip is powered off and placed for T1, the retention time is T2, and the total data retention time is T3. The amount of data written to each storage unit is determined according to the test requirements. The amount of data must not be less than the minimum write unit size of the storage unit, and must not be higher than the amount of data that can be stored in the storage unit specified in the data manual. The value of the total data retention time T3 is determined according to the test requirements and must be less than the upper limit of the data retention time specified in the data manual of the flash memory chip being tested. The specific test steps are as follows: Step 1. The test equipment performs an erase operation on the flash memory chip under test; Step 2. The test equipment writes test data to the flash memory chip under test; Step 3. After waiting time T0, the test equipment performs a read operation on the flash memory chip under test and collects chip parameters; Step 4. Determine whether the number of erase / program cycles experienced by the flash memory chip under test is less than C1. If the number of erase / program cycles is less than C1, repeat steps 1 to 3; otherwise, proceed to step 5; Step 5. Test the equipment power-off waiting time T1; Step 6. The test equipment performs an erase / program / read operation, saves the read data and collects chip parameters; Step 7. Test the device waiting time T2; Step 8. The test equipment performs a data reading operation on the flash memory chip under test, compares the read data with the data saved in step 6, calculates the number of errors generated during the statistical data retention period, and collects chip parameters; Step 9. Determine whether the total data retention time exceeds time T3, if it is less than, repeat steps 7 and 8, otherwise proceed to step 10 and the total data retention time count is reset; Step 10. Determine whether the cumulative number of erase / program times executed exceeds the threshold C2. If so, repeat steps 1 to 9. Otherwise, complete the test.

[0033] Furthermore, the read retry step length L of the i-th read reference voltage of the same page i and the jth read reference voltage read retry step length L j The relationship conforms to the formula: L i =a×L j ; where a is the proportionality coefficient, which can be expressed by the formula a=△R i / △R j Calculated. △R i =(R i -R i ' ), △R j = (R j -R j ' ), R i is the center value of the i-th read reference voltage on the same page, R j is the jth read reference voltage center value, R i ' and R j ' It is the initial read reference voltage center value set when the flash memory chip leaves the factory. Therefore, the read retry interval can be determined according to the read reference voltage center value and the read retry step length.

[0034] For example, when the read retry operation is performed, the offset value of R5, R6, and R7 is controlled. Since R1 and R5 are used to control the same page, R2, R4, and R6 are used to control the same page, and R3 and R7 are used to control the same page, the offset value of R1 follows the offset value of R5; the offset values ​​of R2 and R4 follow the offset value of R6, and the offset value of R3 follows the offset value of R7. The relationship between the reread interval and the threshold voltage distribution interval is as follows: Figure 4 shown. Figure 4The R1 to R7 marked in the figure are the center values ​​of the read reference interval. The scan interval amplitude and step size of R5 to R7 are the same as the default values. The relationship between the center values ​​of the read reference voltage on the same page conforms to the formula: R i =a×R j + f (C pe ).

[0035] Where R i and R j It is the center value of two read reference voltages controlled by the same page. f (C pe ) is related to the number of erase and write cycles C pe The related linear function, C pe In a single reading, the value is determined. f (C pe ) is also determined and can be regarded as a constant. The specific value is R j When R is 0 i The value of . a is the proportionality coefficient.

[0036] Further, the ratio of the difference between the two read voltage center offset values ​​can be used to obtain a = (R i -R i ’ ) / (R j -R j ’ ), where R i ’ and R j ’ is the initial read reference voltage center value set when the chip leaves the factory. Therefore, after confirming the reread scan step length of R5 to R7, the scan amplitude and step length of R1 to R4 can be calculated accordingly. That is, the reread step length L of the i-th read voltage on the same page is i and the jth read voltage reread step length L j The relationship is: L i =a×L j .

[0037] According to another aspect of the present invention, a flash memory read performance optimization device is provided, comprising: an extraction module, a prediction module, a read retry module, a calculation module and an update module. The extraction module is used to extract the preset feature quantity, the number of erase and write reads and the data retention time of the flash memory chip when receiving the current read operation; the prediction module is used to input the preset feature quantity, the number of erase and write reads and the data retention time into the current prediction model to predict the threshold voltage distribution; the read voltage offset interval is determined from the threshold voltage distribution; the read retry module is used to perform a read retry operation on the basis of the read voltage offset interval until the target interval is found, and read the target interval to obtain the number of errors and the corresponding page number; wherein, during the read retry operation, each page only adjusts the offset value change of one read voltage, and the other voltage offset values ​​under the same page change with the offset value change of the read voltage; the calculation module is used to calculate the threshold voltage distribution data using the number of errors and the corresponding page number; the update module is used to update the current prediction model using the threshold voltage distribution data and save it, and predict the corresponding threshold voltage distribution in the next read operation.

[0038] According to another aspect of the present invention, a flash memory system is provided, comprising: a flash memory chip and a controller; the controller stores a computer program for implementing the steps of a method for optimizing flash memory reading performance in the controller when the computer program is executed.

[0039] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of a method for optimizing the reading performance of flash memory in a controller are implemented.

[0040] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing the read performance of flash memory in a controller, characterized in that: include: S1: When receiving the current read operation, extract the preset feature quantity, erase and write read times and data retention time of the flash memory chip; S2: inputting the preset characteristic quantity, the number of erase / write reads and the data retention time into the current prediction model to predict a threshold voltage distribution; determining a read voltage offset interval from the threshold voltage distribution; S3: Based on the read voltage offset interval, a read retry operation is performed until a target interval is found, and a read is performed in the target interval to obtain an error number and a corresponding page number; Wherein, during the read retry operation, only one read voltage offset value is adjusted for each page, and other voltage offset values ​​under the same page change following the read voltage offset value change; S4: Calculating threshold voltage distribution data using the error number and its corresponding page number; S5: Using the threshold voltage distribution data, the current prediction model is updated and saved for predicting the corresponding threshold voltage distribution during the next read operation.

2. The method for optimizing the read performance of flash memory in a controller according to claim 1, characterized in that: The preset characteristic quantities include: a storage unit number and a storage page number of the flash memory chip.

3. The method for optimizing the read performance of flash memory in a controller according to claim 2, characterized in that: The preset characteristic quantity also includes: one or more of the programming time, reading time, erasing time and current of the flash memory chip.

4. The method for optimizing the read performance of flash memory in a controller according to claim 1, characterized in that: Before the S2, it also includes: Taking the preset feature quantity, erase and write read times and data retention time in the sample set corresponding to the preset flash memory chip as input and the threshold voltage distribution corresponding to the preset flash memory chip as output, the initial prediction model is trained to obtain the current prediction model in the first read operation.

5. The method for optimizing the read performance of flash memory in a controller according to claim 4, characterized in that: The process of obtaining the sample set includes: Step 1. Erase the flash memory chip under test; Step 2. Writing test data to the flash memory chip under test; Step 3. Wait for time T0, perform a read operation on the flash memory chip under test, compare the read data with the written data in step 2, count the number of errors generated, and collect chip parameters and store them in the sample set; Step 4. Determine whether the number of erase / write / read times experienced by the flash memory chip under test is less than a first threshold value C1, if so, repeat steps 1 to 3, otherwise proceed to step 5; Step 5. Power off waiting time T1; Step 6. Perform a read operation, save the read data, collect chip parameters and store them in the sample set; Step 7. Waiting time T2; Step 8. Perform a data reading operation on the flash memory chip under test, compare the read data with the data saved in step 6, count the number of errors generated during the statistical data retention period, and collect chip parameters and store them in the sample set; Step 9. Determine whether the total data retention time exceeds time T3, if it is less, repeat steps 7 and 8, otherwise proceed to step 10 and clear the total data retention time count; Step 10: Determine whether the cumulative number of erase / write / read times executed exceeds the second threshold value C2. If so, repeat steps 1 to 9. Otherwise, complete the test.

6. The method for optimizing the read performance of flash memory in a controller according to claim 1, characterized in that: The i-th read reference voltage read retry step length L of the same page i and the jth read reference voltage read retry step length L j The relationship conforms to the formula: L i =a×L j ; Where a is the proportionality coefficient, which can be expressed by the formula a=△R i / △R j Calculation shows that △R i = (R i -R i ' ), △R j = (R j -R j ' ), R i is the center value of the i-th read reference voltage on the same page, R j is the jth read reference voltage center value, R i ' and R j ' It is the initial read reference voltage center value set when the flash memory chip leaves the factory; The read retry interval is determined according to the read reference voltage center value and the read retry step length.

7. A device for optimizing flash memory read performance, characterized in that: include: An extraction module, used for extracting preset characteristic quantities, erase and write read times and data retention time of the flash memory chip when receiving a current read operation; A prediction module, configured to input the preset characteristic quantity, the number of erase / write reads and the data retention time into a current prediction model to predict a threshold voltage distribution; and determine a read voltage offset interval from the threshold voltage distribution; A read retry module, configured to perform a read retry operation on the basis of the read voltage offset interval until a target interval is found, and to read the target interval to obtain an error number and a corresponding page number; wherein, during the read retry operation, only one read voltage offset value is adjusted for each page, and other voltage offset values ​​under the same page change in accordance with the read voltage offset value; A calculation module, used for calculating the threshold voltage distribution data by using the error number and its corresponding page number; An updating module is used to update the current prediction model using the threshold voltage distribution data and save it for predicting the corresponding threshold voltage distribution during the next read operation.

8. A flash memory system, characterized in that: include: Flash memory chips and controllers; The controller stores a computer program for implementing the steps of the method for optimizing the flash memory read performance according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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