Chip packaging structure and electronic equipment

Abstract

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can meet the requirement of high bandwidth density between chips on the basis of supporting integration of heterogeneous chips (die). The chip packaging structure comprises a first chip, an electronic element and a hybrid adapter plate with a novel structure. The hybrid adapter plate comprises a silicon interposer and a rewiring layer, the front surface of the silicon interposer is provided with a metal wiring layer, and the silicon interposer is provided with a silicon through hole. The first chip is arranged on the front surface of the silicon interposer and is electrically connected with the metal wiring layer. Or the hybrid adapter plate comprises a first rewiring layer, a second rewiring layer, a bridge chip and a metal connecting structure, the bridge chip and the metal connecting structure are located between the two rewiring layers, and the bridge chip achieves interconnection between the first chips through the first rewiring layer. The second redistribution layer is connected with the first redistribution layer through a metal connection structure. The electronic component is located on the back face of the redistribution layer and connected with the redistribution layer or connected with the redistribution layer through the substrate.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] System in a package (SiP) technology is an integrated circuit packaging technology that integrates multiple dies and passive components into a single package. In the post-Moore era, SiP technology can help chip products increase integration, reduce size and power consumption.

[0003] The prior art provides a system-level packaging structure, which cuts out a largest complete continuous square from a wafer as a chip, and the area can reach 46225mm 2 This structure has a low yield rate due to the large wafer area, and cannot support the selection and reintegration of KGD (known good die) on the wafer, nor can it support the integration of heterogeneous chips. In addition, the large chip area requires a large substrate to realize power supply and signal transmission, making the stress risk, power supply and heat dissipation implementation of the entire system more complicated.

[0004] In order to support the selection of KGD and the integration of heterogeneous chips, the existing technology also provides another system-level packaging structure, which realizes the interconnection between multiple dies on the redistribution layer (RDL) by means of re-constribution. However, in this packaging structure, since multiple dies are interconnected through RDL, the bandwidth density between dies cannot be very high, and the bandwidth density can only reach about 0.8Tbps / mm, which cannot support high-density interconnection with larger bandwidth, and thus cannot meet the demand scenario of high bandwidth density between dies. Summary of the invention

[0005] The present application provides a chip packaging structure and an electronic device, which can meet the high bandwidth density requirements between chips on the basis of supporting heterogeneous chip (die) integration.

[0006] The present application provides a chip packaging structure, which includes a silicon interposer (Siinterposer), at least one first chip, at least one electronic component, and a redistribution layer. The front side of the silicon interposer has a metal wiring layer, and a through silicon via TSV (through silicon via) is provided in the silicon interposer. The redistribution layer is located on the back side of the silicon interposer and is electrically connected to the TSV. The first chip is located on the front side of the silicon interposer and is electrically connected to the metal wiring layer on the front side of the silicon interposer. The electronic component is located on a side of the redistribution layer away from the first chip, and is electrically connected to the redistribution layer or connected to the redistribution layer through a substrate.

[0007] In the chip packaging structure, the metal routing layer on the front side of the silicon interposer can be processed by silicon-based technology, so that the line width, line spacing, and line thickness of the metal routing in the metal routing layer can meet the high-bandwidth density interconnection requirements between multiple chips (first chips), such as an interconnection bandwidth density of more than 2Tbps / mm. The rewiring layer on the back side of the silicon interposer can use a thick metal layer and a thick dielectric layer with better current balancing capability, so as to meet the electronic components' high-speed serdes (serializer / deserializer) drive requirements with large current balancing capability, low impedance, and long distance.

[0008] In some possible implementations, the line width, line spacing, and line thickness of the metal routing in the metal routing layer located on the active surface side of the silicon interposer are all less than 5μm; the line width, line spacing, and line thickness of the metal routing in the redistribution layer are all greater than 5μm.

[0009] In some possible implementations, the at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0010] In some possible implementations, the at least one electronic component includes: a power supply module, a control module, a connector, a clock device, a rectifier, and one or more of a resistor, a capacitor, and an inductor.

[0011] In some possible implementations, the chip packaging structure includes: a plurality of first chips and a plurality of electronic components.

[0012] In some possible implementations, the multiple electronic components include multiple power supply modules, which are respectively arranged opposite to the multiple first chips. The power supply modules are electrically connected to the oppositely arranged first chips through the redistribution layer and the silicon interposer, and supply power to the first chips.

[0013] In some possible implementations, the chip packaging structure includes multiple discrete substrates. The substrate is located between the redistribution layer and the electronic components, and the multiple electronic components are electrically connected to the redistribution layer through multiple discrete substrates. In this way, the types of multiple substrates can be flexibly selected according to the electrical requirements of the electronic components to improve the performance of the entire system. In addition, the use of multiple discrete substrates can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought by a large continuous substrate, which is more friendly to system assembly and service reliability.

[0014] In some possible implementations, the multiple substrates are encapsulated in a molding layer to protect the multiple substrates through the molding layer.

[0015] In some possible implementations, the chip packaging structure further includes: a first heat sink and a second heat sink. The first heat sink is disposed on a side of the first chip away from the silicon interposer, and the second heat sink is disposed on a side of the electronic component away from the redistribution layer. The first heat sink and the second heat sink are disposed to meet the heat dissipation of the chip packaging structure.

[0016] In some possible implementations, the chip packaging structure further includes: a fixing structure; the fixing structure penetrates and fixes the first heat sink, the second heat sink, and the hybrid adapter plate; wherein the hybrid adapter plate includes a silicon interposer and a redistribution layer.

[0017] The present application also provides a chip packaging structure, which includes at least one first chip, at least one electronic component, a first redistribution layer, a second redistribution layer, at least one bridge chip and a metal connection structure. The bridge chip and the metal connection structure are connected between the first redistribution layer and the second redistribution layer, and the first redistribution layer is located on the active surface of the bridge chip. The first chip is located on the side of the first redistribution layer away from the bridge chip, and the first chip is electrically connected to the bridge chip through the first redistribution layer. The electronic component is located on the side of the second redistribution layer away from the first redistribution layer, and is connected to the second redistribution layer or connected to the second redistribution layer through a substrate.

[0018] In this chip packaging structure, since the bridge chip can be manufactured by silicon-based technology, the line width, line spacing, and line thickness of the metal routing on the surface of the bridge chip can meet the high-bandwidth density interconnection requirements between chips. On this basis, the first rewiring layer can use a thin metal layer and a thin dielectric layer, and the active surface of the bridge chip can be directly brought out in the area of ​​the bridge chip through the first rewiring layer, thereby achieving the high-bandwidth density interconnection requirements between chips (first chip). The second rewiring layer on the back of the bridge chip can use a thick metal layer and a thick dielectric layer with better current balancing capability, thereby meeting the electronic components' requirements for high-speed serdes driving with large current balancing capability, low impedance, and long distance.

[0019] Illustratively, in some possible implementations, the line width, line spacing, and line thickness of the metal routing in the first redistribution layer are all less than 5 μm; and the line width, line spacing, and line thickness of the metal routing in the second redistribution layer are all greater than 5 μm.

[0020] In some possible implementations, the metal connection structure includes a metal column; the bridge chip and the metal column are encapsulated in a molding layer.

[0021] In some possible implementations, a glass wafer is disposed between the first redistribution layer and the second redistribution layer, a groove is disposed in the glass wafer, and the bridge chip is embedded in the groove; the metal connection structure includes a through glass via (TGV) penetrating the glass wafer.

[0022] In some possible implementations, the at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0023] In some possible implementations, the at least one electronic component includes: a power supply module, a control module, a connector, a clock device, a rectifier, and one or more of a resistor, a capacitor, and an inductor.

[0024] In some possible implementations, the chip packaging structure includes: a plurality of first chips and a plurality of electronic components.

[0025] In some possible implementations, a bridge chip may be included in the chip packaging structure. The bridge chip is located between two adjacent first chips, and the bridge chip connects the two adjacent first chips through a first redistribution layer.

[0026] In some possible implementations, the multiple electronic components include multiple power supply modules, which are respectively arranged opposite to the multiple first chips. The power supply modules are electrically connected to the oppositely arranged first chips through the redistribution layer and the bridge chip, and supply power to the first chips.

[0027] In some possible implementations, the chip packaging structure includes a plurality of discrete substrates. The substrate is located between the second redistribution layer and the electronic components, and the plurality of electronic components are electrically connected to the second redistribution layer through a plurality of discrete substrates. In this way, the types of the plurality of substrates can be flexibly selected according to the electrical requirements of the electronic components to improve the performance of the entire system. In addition, the use of a plurality of discrete substrates can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought about by a large continuous substrate, which is more friendly to system assembly and service reliability.

[0028] In some possible implementations, the multiple substrates are encapsulated in a molding compound to protect the multiple substrates through the molding layer.

[0029] In some possible implementations, the chip packaging structure further includes: a first heat sink and a second heat sink. The first heat sink is disposed on a side of the first chip away from the first redistribution layer, and the second heat sink is disposed on a side of the electronic component away from the second redistribution layer. The first heat sink and the second heat sink are disposed to meet the heat dissipation of the chip packaging structure.

[0030] In some possible implementations, the chip packaging structure further includes: a fixing structure. The fixing structure penetrates and fixes the first heat sink, the second heat sink, and the hybrid adapter; wherein the hybrid adapter includes a first redistribution layer, a second redistribution layer, and an intermediate layer (including a bridge chip and a metal connection structure) connected between the first redistribution layer and the second redistribution layer.

[0031] The present application also provides an electronic device, which includes a circuit board and any possible chip packaging structure as described above, wherein the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of a chip packaging structure provided in Embodiment 1 of the present application;

[0034] Figure 3 A schematic diagram of a chip packaging structure provided in Embodiment 1 of the present application;

[0035] Figure 4 A schematic diagram of a chip packaging structure during the manufacturing process provided in the first embodiment of the present application;

[0036] Figure 5 A schematic diagram of a chip packaging structure during the manufacturing process provided in the first embodiment of the present application;

[0037] Figure 6 A schematic diagram of a chip packaging structure during the manufacturing process provided in the first embodiment of the present application;

[0038] Figure 7 A schematic diagram of a chip packaging structure during the manufacturing process provided in the first embodiment of the present application;

[0039] Figure 8 A schematic diagram of a chip packaging structure during the manufacturing process provided in the first embodiment of the present application;

[0040] Fig. 9 A schematic diagram of a chip packaging structure provided in Embodiment 2 of the present application;

[0041] Fig.10A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0042] Fig.11 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0043] Fig.12 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0044] Fig.13 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0045] Fig.14 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0046] Fig.15 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0047] Fig.16 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0048] Fig.17 A schematic diagram of a chip packaging structure during the manufacturing process provided in the second embodiment of the present application;

[0049] Fig.18 A schematic diagram of a chip packaging structure provided in Embodiment 3 of the present application;

[0050] Fig.19 A schematic diagram of a chip packaging structure during the manufacturing process provided in the third embodiment of the present application;

[0051] Fig. 20 A schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0052] Fig.21 A schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0053] Fig. 22 A schematic diagram of a chip packaging structure during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0056] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.

[0057] Indicatively, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products can be car-mounted navigators, car-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, storage devices, radars, base stations, and other communication equipment.

[0058] The electronic device includes a printed circuit board (PCB) and a chip packaging structure electrically connected to the circuit board. Schematically, the chip packaging structure may be a system-level packaging structure. Figure 1 As shown, a new hybrid adapter board 10 is used in the chip packaging structure. The hybrid adapter board 10 can meet the high bandwidth density requirements between chips on the basis of supporting heterogeneous chip (die) integration.

[0059] Illustratively, in some possible implementations, the hybrid adapter board 10 provided in the embodiment of the present application can achieve an interconnection bandwidth density of more than 2 Tbps / mm.

[0060] This application does not limit the application scenarios of the above chip packaging structure. For example, the chip packaging structure can be applied to large servers, high-bandwidth switches, supercomputers for AI computing, and other scenarios.

[0061] The novel hybrid adapter plate 10 used in the chip packaging structure provided in the present application is described in detail below in conjunction with specific embodiments.

[0062] Embodiment 1

[0063] Indicative, such as Figure 2 As shown, this embodiment 1 provides a chip packaging structure, which includes a hybrid adapter board 10a, at least one chip D (also referred to as a first chip), and at least one electronic component 20; the following description is based on multiple chips D and multiple electronic components 20 as examples.

[0064] The above-mentioned chip D can be a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output chip (I / O), an integrated passive device (IPD), etc., or it can be an integrated functional module that has been packaged, such as HBM (high bandwidth memory), DOI (die on silicon interposer), FOI (fan out RDL interpose), etc. In practice, multiple chips D can be set as needed.

[0065] The electronic components 20 may be power supply modules, control modules, connectors, clock devices, rectifiers, resistors, capacitors, and inductors. The power supply module may be a VRM (voltage regulator module) or other modules related to electrical transmission, voltage transformation, and rectification; the connector may be an electrical connector for transmitting electrical signals, or an optoelectronic conversion connector for transmitting optical signals. In practice, multiple electronic components 20 may be provided as needed.

[0066] refer to Figure 2 As shown, the hybrid transfer board 10a includes a silicon interposer (Siinterposer) and a redistribution layer (RDL).

[0067] refer to Figure 2 As shown, the silicon interposer includes a silicon wafer a1 (wafer) and a metal wiring layer a2 arranged on the surface of the silicon wafer a1 (the surface away from the RDL side). A plurality of through silicon vias TSV (through silicon via) are arranged in the silicon wafer a1. The metal wiring layer a2 is connected to the plurality of through silicon vias TSV. As shown, the aperture of the plurality of through silicon vias TSV can be 1μm to 30μm.

[0068] In the application, the front side of the silicon interposer is the surface of the silicon interposer on the side where the metal wiring layer a2 is provided. The back side of the silicon interposer is the surface of the silicon wafer a1 on the side where the metal wiring layer a2 is not provided, that is, the back side of the silicon wafer a1 (the surface away from the metal wiring layer a2).

[0069] The redistribution layer RDL (redistribution layer) is located on the back side of the silicon wafer a1 (wafer) (ie, the surface away from the metal wiring layer a2), and the redistribution layer RDL is connected to the metal wiring layer a2 through a plurality of through silicon vias TSV in the silicon wafer a1.

[0070] The plurality of chips D are disposed on the front side of a silicon interposer, and connection pads are disposed on the front side of the silicon interposer for electrical connection.

[0071] The plurality of electronic components 20 are disposed below the redistribution layer RDL and are electrically connected to the redistribution layer RDL, thereby achieving electrical connection with the plurality of chips D through the redistribution layer RDL and a silicon interposer (Siinterposer).

[0072] In the first embodiment, the metal wiring layer a2 on the surface of the silicon interposer (Siinterposer) can be processed by a silicon-based process, so that the metal wiring in the metal wiring layer a2 has a smaller line width, line spacing, and line thickness, so as to meet the high bandwidth density interconnection requirements between multiple chips D, such as an interconnection bandwidth density of more than 2Tbps / mm. In some possible implementation methods, the metal wiring layer a2 can be implemented by a Damascus process including deposition, exposure, etching, electroplating, chemical mechanical polishing (CMP) and other processes.

[0073] As shown, the line width, line spacing and line thickness in the metal routing layer a2 can reach 0.4 μm, and the number of layers can be processed to more than 3 layers.

[0074] Illustratively, in some possible implementations, the line width in the metal wiring layer a2 may be less than 5 μm, but is not limited thereto.

[0075] Illustratively, in some possible implementations, the line thickness of the metal wiring layer a2 (ie, the thickness of a single metal layer) may be less than 5 μm, but is not limited thereto.

[0076] Illustratively, in some possible implementations, the line pitch of the metal wiring layer a2 may be less than 5 μm, but is not limited thereto.

[0077] Illustratively, in some possible implementations, the metal routing layer a2 may include 3 to 10 wiring layers (also referred to as metal wiring layers), but is not limited thereto.

[0078] Illustratively, in some possible implementations, the wiring layer in the metal wiring layer a2 may be made of copper (Cu), but is not limited thereto.

[0079] Illustratively, in some possible implementations, the dielectric layer in the metal wiring layer a2 can be made of one or more insulating dielectric materials such as polyimide (PI), polybenzoxazoles (PBO), silicon dioxide SiO2, silicon nitride SiN, and silicon carbon nitride SiCN, but is not limited thereto.

[0080] Illustratively, in some possible implementations, the thickness of the dielectric layer in the metal wiring layer a2 may be in the range of 0.1 μm to 5 μm, but is not limited thereto.

[0081] As shown, in some possible implementation methods, the surface of the metal routing layer a2 can be provided with multiple micro pads (solder points), the spacing between the micro pads can be between 10μm and 200μm, and the metal routing layer a2 is welded to multiple chips D through the multiple micro pads; in some non-welding interconnection connection methods, such as HB (Hybrid bonding), the spacing between the connection points may even be reduced to the order of 1 to 10um.

[0082] In addition, reference Figure 2 As shown, the redistribution layer RDL can adopt thick metal layers and thick dielectric layers with better current balancing capability. For example, the line width, line spacing, and line thickness of the metal routing in the redistribution layer RDL can be above 5μm, thereby being able to meet the electronic component 20's high-speed serdes (serializer / deserializer) driving requirements with large current balancing capability, low impedance, and long distance (such as above 5mm).

[0083] Illustratively, in some possible implementations, the redistribution layer RDL may be implemented by a yellow light process including processes such as glue coating / film lamination, exposure, development, and curing.

[0084] Illustratively, in some possible implementations, the line width in the redistribution layer RDL may be in the range of 5 μm to 30 μm, but is not limited thereto.

[0085] Illustratively, in some possible implementations, the line spacing in the redistribution layer RDL may be in the range of 6 μm to 20 μm, but is not limited thereto.

[0086] Illustratively, in some possible implementations, the line thickness in the redistribution layer RDL may be in the range of 6 μm to 20 μm, but is not limited thereto.

[0087] Illustratively, in some possible implementations, the redistribution layer RDL may include 3 to 6 wiring layers, but is not limited thereto.

[0088] Illustratively, in some possible implementations, the thickness of the dielectric layer in the redistribution layer RDL may be in the range of 10 μm to 40 μm, but is not limited thereto.

[0089] Illustratively, in some possible implementations, the wiring layer in the redistribution layer RDL may be made of copper (Cu), but is not limited thereto.

[0090] Illustratively, in some possible implementations, the dielectric layer in the redistribution layer RDL may be made of one or more dielectric materials such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), etc., but is not limited thereto.

[0091] As shown, in some possible implementations, a plurality of large pads may be provided on the lower surface of the redistribution layer RDL, and the spacing between the large pads may be between 200 μm and 1500 μm, and the redistribution layer RDL forms electrical interconnections with the plurality of electronic components 20 through the plurality of large pads. The electrical interconnections between the redistribution layer RDL and the electronic components 20 may be formed by welding, crimping, plugging, and the like.

[0092] In summary, the new hybrid adapter board 10a provided in the first embodiment includes a silicon interposer (Siinterposer) and a redistribution layer RDL. On the one hand, a metal routing layer a2 with a smaller line width / line spacing / line thickness is formed on the surface of the silicon interposer (Siinterposer) to meet the interconnection requirements of high bandwidth density between chips D. On the other hand, the redistribution layer RDL adopts a thick metal layer and a thick dielectric layer, which can meet the requirements of large current sharing and long routing capabilities of the electronic components 20. In other words, the new hybrid adapter board 10a can integrate the medium that realizes high bandwidth density with the two media that realize large current sharing and long routing capabilities. In this way, the packaging structure of the new hybrid adapter board 10a can support both high bandwidth density between heterogeneous chips and long-distance Serdes driving capabilities, thereby meeting the integration requirements of large systems and improving system energy utilization and computing efficiency.

[0093] The present application does not impose any restrictions on the connection method between the multiple electronic components 20 and the redistribution layer RDL. The multiple electronic components 20 and the redistribution layer RDL can be directly connected or indirectly connected through other devices. In practice, they can be configured as needed.

[0094] Illustratively, in some possible implementations, the electronic component 20 may be directly connected to the lower surface of the redistribution layer RDL.

[0095] Illustratively, in some possible implementations, a plurality of electronic components 20 may be connected to a lower surface of a redistribution layer RDL through a substrate, wherein the substrate may be located between the electronic components 20 and the redistribution layer RDL.

[0096] Among them, the above-mentioned substrate can be manufactured using one or more of the following processes: substrate process, carrier-like process or printed circuit board (PCB) process, and this application does not impose any limitation on this.

[0097] In order to meet the electrical requirements of the plurality of electronic components 20, in some possible implementations, such as Figure 2 As shown, a plurality of discrete substrates 30 may be used, and the number of layers and specifications of the plurality of substrates 30 may not be exactly the same. In this case, a plurality of electronic components 20 may be connected to the redistribution layer RDL through a plurality of discrete substrates 30. Among them, one electronic component 20 may be installed on a single discretely arranged substrate 30, or a plurality of electronic components 20 may be installed. The present application does not impose any restrictions on this, and it may be arranged as needed in practice. In this way, the types of the plurality of substrates 30 may be flexibly selected according to the electrical requirements of the electronic components 20 to improve the performance of the entire system. For example, a multi-layer substrate may be configured only for electronic components 20 that require a complex multi-layer substrate, while a simple substrate may be configured for electronic components 20 that require a simple substrate.

[0098] In addition, the use of multiple discrete substrates 30 can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought by a large continuous substrate, which is more friendly to system assembly and service reliability. This application does not limit the electrical connection method between the substrate 30 and the redistribution layer RDL, and it can be set as needed in practice.

[0099] Illustratively, in some possible implementations, the plurality of substrates 30 and the redistribution layer RDL may be connected to each other by one or a combination of connection methods such as welding, crimping, and plugging.

[0100] In order to protect the plurality of substrates 30, refer to Figure 3 As shown, in some possible implementations, a thermosetting material may be used to fill the bottom of multiple substrates 30 and the gaps between the substrates 30. After filling, the back of the substrate 30 and the connecting structure (such as Cu Stud) may be exposed by grinding to form a molding layer M1 to protect the multiple substrates 30.

[0101] The thermosetting materials involved in the present application may include underfill (UF), molded underfill (MUF), epoxy molding compound, etc., which will be described below and will not be repeated.

[0102] Similarly, in order to protect multiple chips D, in some possible implementations, refer to Figure 2 or Figure 3 As shown, a thermosetting material may be used to first fill and protect the bottom of the multiple chips D by means of underfill, and then the multiple chips D may be encapsulated in a molding layer M2 for protection by means of molding or molding underfill.

[0103] In addition, in some possible implementations, reference Figure 2 or Figure 3 As shown, the chip packaging structure may also be provided with a first heat sink 41 and a second heat sink 42. The first heat sink 41 is provided on a side of the plurality of chips D away from the hybrid adapter 10a, and the second heat sink 42 is provided on a side of the plurality of electronic components 20 away from the hybrid adapter 10a. The heat dissipation of the chip packaging structure is satisfied by providing two heat sinks (41, 42).

[0104] As shown, the gap between the chip D and the first heat sink 41 can be filled with thermal interface materials (TIM). The TIM can be a heat dissipation medium such as thermal gel, thermal grease, graphene, liquid metal, etc., which is not restricted here. Similarly, the gap between the electronic component 20 and the second heat sink 42 can also be filled with TIM.

[0105] The present application does not impose any restrictions on the arrangement of the heat dissipation plates (41, 42), which can be arranged as required in practice.

[0106] For example, in some possible implementations, the heat sink (41, 42) may be a metal cover plate.

[0107] For another example, in some possible implementations, the heat sink (41, 42) may be a hollow structure to support water cooling or liquid cooling.

[0108] For another example, the heat sink (41, 42) may have a hollow structure with a through-hole structure, a grid, etc. In this case, the heat sink can meet the heat dissipation requirements while supporting the external power supply system to be vertically interconnected with the electrical components 20 on the back of the chip through the hollow area.

[0109] In the packaging structure, the thickness, material, and structure of the first heat sink 41 and the second heat sink 42 may be the same or different, and the present application does not impose any limitation on this.

[0110] In addition, refer to Figure 3 As shown, in some possible implementations, in order to ensure that the force inside the chip packaging structure is balanced, a support frame 43 can be provided in the chip packaging structure, and the support frame 43 is located in the gap between the electronic components 20, and the upper end of the support frame 43 can contact the substrate 30, and the lower end can contact the second heat sink 42. On this basis, in order to fix the first heat sink 41, the second heat sink 42, the support frame 43 and the packaging system, as shown in FIG. Figure 2 or Figure 3 As shown, in some possible implementations, a fixing structure 50 can be provided in the chip packaging structure, and the fixing structure 50 passes through the first heat sink 41, the second heat sink 42, the support frame 43 and the hybrid adapter plate 10a, and supports and fixes the first heat sink 41, the second heat sink 42, the support frame 43 and the hybrid adapter plate 10a.

[0111] Indicative, such as Figure 2 or Figure 3 As shown, in some possible implementations, the fixing structure 50 may include bolts and nuts, the bolts penetrate the first heat sink 41, the second heat sink 42 and the hybrid adapter plate 10a, and the nuts are fixed at one end of the bolts, so as to fix the first heat sink 41, the second heat sink 42 and the hybrid adapter plate 10a. In this case, the first heat sink 41 and the second heat sink 42 can not only play a role in heat dissipation, but also play a role in stabilizing the structure.

[0112] Of course, the chip packaging structure may also be provided with other devices or component structures according to actual needs.

[0113] The above chip packaging structure is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0114] Illustratively, this embodiment 1 provides a method for manufacturing a chip packaging structure, and the manufacturing method may include:

[0115] First, refer to Figure 4 As shown in (a), a silicon wafer a1 (wafer) is provided, a plurality of through silicon vias TSV are manufactured on the silicon wafer a1, and a metal wiring layer a2 is manufactured on the surface of the silicon wafer a1 by a Damascus process including deposition, exposure, etching, electroplating, CMP and other processes to form a silicon interposer (Siinterposer).

[0116] After making multiple metal wiring layers in the metal routing layer a2, micro pads will be made on the surface for subsequent welding with the chip D. The spacing between the micro pads can be between 10μm and 200μm. For related instructions, please refer to the previous text and will not be repeated here.

[0117] Next, refer to Figure 4 As shown in (b) and (c), the side of the silicon interposer provided with the metal wiring layer a2 is fixed on the first carrier 01, and a redistribution layer RDL is made on the back of the silicon wafer a1 to form a hybrid adapter board 10a.

[0118] The carrier plate (such as the first carrier plate and the second carrier plate) involved in the present application can be a metal plate, glass or other supporting material, and the present application does not impose any limitation on this, and it can be set as needed in practice.

[0119] In some possible implementations, the process of forming the redistribution layer RDL may include: Figure 4 As shown in (a), a temporary bonding method can be used to fix the side of the silicon interposer (Siinterposer) provided with the metal wiring layer a2 on the glass carrier (01), and the back side of the silicon wafer a1 can be thinned to a desired thickness (e.g., 10 μm to 300 μm) by grinding and chemical mechanical polishing (CMP) processes, and the through silicon vias TSV are exposed; then, a layer of insulating film can be processed by PVD (physical vapor deposition) or CVD (chemical vapor deposition) or suspension coating of liquid glue or film pasting, and the material can be an insulating material such as PI, PBO, SiO2, SiN, etc.; next, refer to Figure 4 As shown in (b), a growth metal layer and a dielectric layer are formed on an insulating film to form a redistribution layer RDL. The specific manufacturing process of the redistribution layer RDL may include: surface pretreatment, organic material coating-exposure-development-curing-seed layer precipitation-organic material coating-exposure-development-electroplating-photoresist removal-seed layer etching, etc.; after the multi-layer metal wiring layer, a large pad will be processed for subsequent welding with the electronic component 20, and the spacing between the centers of adjacent large pads may be between 200μm and 1500μm.

[0120] Next, refer to Figure 5As shown, a temporary bonding method can be used to fix one side of the hybrid transfer board 10a where the redistribution layer RDL is set on the second carrier 02 (such as glass). Then, the first carrier 01 on the other side can be debonded and separated from the hybrid transfer board 10a by laser burning, heat treatment, etc., to expose the micro pad interface on the surface of the silicon interposer.

[0121] Next, refer to Figure 6 As shown, multiple chips D (such as multiple heterogeneous chips D) can be mounted on the surface of a silicon interposer (Siinterposer), and the chips D can be welded to the micro pads on the surface of the silicon interposer (Siinterposer); then a thermosetting material can be used to fill the bottom of the chip and the gap between the chips, and then the backside of the multiple chips D can be ground (backside grinding) to expose the backside of the chip, thereby forming a molding layer M2 to protect the multiple chips D.

[0122] Next, refer to Figure 7 As shown, the second carrier 02 can be removed to expose the pads on the surface of the redistribution layer RDL. In some possible implementations, the second carrier 02 can be debonded and separated from the hybrid transfer board 10a by laser burning, heat treatment, etc., to expose the pad interface on the surface of the redistribution layer RDL.

[0123] Next, refer to Figure 7 As shown, a plurality of substrates 30 are welded to pads exposed on the surface of the redistribution layer RDL, and a plurality of electronic components 20 are welded to the other side of the plurality of substrates 30 respectively.

[0124] Next, refer to Figure 7 As shown, the non-routing area of ​​the hybrid adapter plate 10a is opened to form a via K, and the aperture of the via K can be between 2 mm and 8 mm, so that when the system is finally assembled, the fixing structure 50 (such as a bolt) passes through the via K to penetrate the hybrid adapter plate 10a to form a reliable mechanical support. Of course, in some possible implementations, refer to Figure 8 As shown, after welding the multiple substrates 30 to the pads on the surface of the redistribution layer RDL, a thermosetting material can be used to fill the bottom of the multiple substrates 30 and the gaps between the substrates 30, and the back of the substrates 30 and the connection structure (such as Cu Stud) are exposed by grinding to form a mold layer M1 to protect the multiple substrates 30. After forming the mold layer M1, the non-routing area of ​​the hybrid transfer board 10a is opened to form a via K.

[0125] Of course, in some special scenarios, the electronic component 20 can be directly soldered to the surface of the redistribution layer RDL according to actual needs to form electrical interconnection.

[0126] Next, a support frame 43 having a size matching that of the hybrid adapter board system (i.e., a system including multiple chips D, a hybrid adapter board 10, multiple electronic components 20, and multiple substrates 30) can be used to support the hybrid adapter board system. Of course, the support frame 43 also has holes opened at the locations where the through holes of the hybrid adapter board system are set.

[0127] Next, refer to Figure 3 As shown, under the support of the support frame 43, the first heat sink 41 can be mounted on the side of the hybrid adapter plate system located at the chip D, and the second heat sink 42 can be mounted on the side of the electronic component 20. Of course, the heat sinks (41, 42) are also opened at the positions where the through holes are set in the hybrid adapter plate system. Bolts (50) penetrate the hybrid adapter plate system, the support frame, the first heat sink 41, and the second heat sink 42 at the through hole positions and fix them. In this case, the heat sinks (41, 42) can not only play a role in heat dissipation, but also play a role in stabilizing the structure.

[0128] At this point, the entire packaging system has been constructed. As an independent data processing unit, the required power can be provided to the system through an external power supply module, and the system signal can also be brought out through a cable connector.

[0129] Embodiment 2

[0130] The second embodiment of the present invention provides a chip packaging structure. The main difference between the chip packaging structure and the aforementioned first embodiment is that the structure of the hybrid adapter board is different. The settings of other parts (such as chip D, electronic component 20, etc.) are basically the same. The description of the corresponding reference embodiment can be referred to and will not be repeated here.

[0131] The structure of the new hybrid adapter board provided in the second embodiment is described below.

[0132] Indicative, such as Fig. 9 As shown, a new type of hybrid adapter board 10b is used in the chip packaging structure provided in the second embodiment. The hybrid adapter board 10b includes: a first redistribution layer RDL1, a second redistribution layer RDL2, and at least one bridge chip BG (bridge die) and a plurality of metal pillars P (such as copper pillars, Cu posts) connected between the first redistribution layer RDL1 and the second redistribution layer RDL2. The bridge chip BG and the metal pillars P are plastic-encapsulated in the molding layer to form a molding intermediate layer 11. The first redistribution layer RDL1 is arranged on the active surface of the bridge chip BG and is electrically connected to the active surface of the bridge chip BG. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the metal pillars P.

[0133] In addition, according to actual needs, in some possible implementations, the bridge chip BG may be provided with through silicon vias. In this case, the through silicon vias in the bridge chip BG are electrically connected to the second redistribution layer RDL2 below.

[0134] The structure of the bridge chip BG is similar to that of the Siinterposer in the first embodiment. Since the bridge chip BG can be manufactured by a silicon-based process, the line width, line spacing, and line thickness on the surface of the bridge chip BG can be less than 5 μm, thereby meeting the high-bandwidth density interconnection requirements between multiple chips D.

[0135] refer to Fig. 9 As shown, multiple chips D are arranged on the upper surface of the first redistribution layer RDL1 (i.e., the surface away from the bridge chip BG), and are electrically connected to the first redistribution layer RDL1. The bridge chip BG is located between two adjacent chips D. In this case, the bridge chip realizes the connection between the two adjacent chips D through the first redistribution layer. Any two adjacent chips D can be interconnected through the bridge chip BG.

[0136] A plurality of electronic components 20 are located below the second redistribution layer RDL2 (i.e., away from the side of the bridge chip BG). The electronic components 20 can be directly connected to the lower surface of the second redistribution layer RDL2, or can be connected to the lower surface of the second redistribution layer RDL2 through the substrate 30. For example, a plurality of electronic components 20 can be connected to the second redistribution layer RDL2 through different substrates 30, respectively. For details, please refer to the corresponding description in the first embodiment, which will not be repeated here.

[0137] For the first redistribution layer RDL1 and the second redistribution layer RDL2:

[0138] The first redistribution layer RDL1 may be a thin metal layer and a thin dielectric layer, such as a line width / line spacing / line thickness of less than 5 μm. In this case, the first redistribution layer RDL1 in the area of ​​the bridge chip BG may directly lead out the connection pads on the surface of the bridge chip BG, and the high bandwidth density interconnection requirements between the chips D may be met through the bridge chip BG.

[0139] Illustratively, the first redistribution layer RDL1 may be implemented by a damascene process including deposition, exposure, etching, electroplating, and CMP.

[0140] The second redistribution layer RDL2 can be configured to use a thick metal layer and a thick dielectric layer. For example, the line width / line spacing / line thickness can be above 5 μm, thereby meeting the requirements of large current sharing and long routing capabilities of the electronic component 20 .

[0141] Illustratively, the second redistribution layer RDL2 may be implemented by a yellow light process including coating / filming, exposure, development, and curing.

[0142] Illustratively, the first redistribution layer RDL1 may include 1 to 3 wiring layers, but is not limited thereto.

[0143] Illustratively, the second redistribution layer RDL2 may include 3 to 6 wiring layers, but is not limited thereto.

[0144] Regarding other parts of the chip packaging structure, such as the substrate 30, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., reference may be made to the corresponding parts in the aforementioned embodiment 1, and no further details will be given here.

[0145] The chip packaging structure of the second embodiment is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0146] Illustratively, this second embodiment provides a method for manufacturing a chip packaging structure, and the manufacturing method may include:

[0147] First, refer to Fig.10 As shown in (a), a metal post P, such as a copper post (Cu post), is made on the front side of a first carrier 01 (such as a glass wafer) as a conductive connecting member; then, referring to Fig.10 As shown in (b), at least one bridge chip BG is mounted on the front side of the first carrier 01 (ie, the side where P is provided); next, refer to Fig.10 As shown in (c), a thermosetting material is used to perform plastic encapsulation on the front side of the first carrier 01, the metal pillar P and the whole are plastic encapsulated into the molding layer, and the connection structure (such as Cu Stud) between the metal pillar P and the surface of the bridge chip BG is exposed by grinding, thereby forming a molded interposer 11 (interposer).

[0148] Next, refer to Fig.11 As shown, the first redistribution layer RDL1 is manufactured on the upper surface of the molded interposer 11. The interconnect material in the first redistribution layer RDL1 may be Cu, and the insulating dielectric material may be polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or other materials. Schematically, the manufacturing process of the single-layer routing layer in the first redistribution layer RDL1 includes: surface pretreatment-PI coating-exposure-development-curing-seed layer precipitation-photoresist (PR) coating-exposure-development-electroplating-photoresist removal-seed layer etching.

[0149] Next, refer to Fig.12 As shown in (a), multiple heterogeneous chips D can be mounted on the surface of the first redistribution layer RDL1. Fig.12As shown in (b), a thermosetting material is used to fill the bottom of the multiple chips and the gaps between the chips. Then, the backside of the multiple chips D can be ground (backside grinding) to expose the back of the chips, thereby forming a molding layer M2 to protect the multiple chips D.

[0150] Next, refer to Fig.13 As shown in (a), the back side of the plurality of chips D is temporarily bonded to the second carrier 02 (such as a glass plate, a metal plate, etc.); then, referring to Fig.13 As shown in (b), the first carrier board 01 on the other side can be debonded and separated by laser burning, heat treatment, etc. (such as laser debonding or thermal debonding, etc.), and the metal pillar P and the bridge chip BG can be exposed by grinding. The grinding process can include rough grinding (grinding) - chemical mechanical polishing (CMP) - Si etching (etch) to expose copper - insulating dielectric material deposition - CMP to expose copper, etc.

[0151] Next, refer to Fig.14 As shown, a second redistribution layer RDL2 is fabricated on the back side of the wafer (i.e., the side where the metal pillars P and the bridge chip BG are exposed). The interconnection material in the second redistribution layer RDL2 may be Cu, and the insulating dielectric material may be polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) or other materials. Schematically, the manufacturing process of a single-layer wiring layer in the second redistribution layer RDL2 includes: surface pretreatment-PI coating-exposure-development-curing-seed layer precipitation-photoresist (PR) coating-exposure-development-electroplating-photoresist removal-seed layer etching.

[0152] At this time, the hybrid transfer board 10 b formed by the first redistribution layer RDL1 , the molded interposer 11 embedded with the metal pillars P and the bridge chip BG, and the second redistribution layer RDL2 is completed.

[0153] Next, refer to Fig.15 As shown in (a), multiple substrates 30 can be welded to the pads on the surface of the second redistribution layer RDL2. For example, multiple ABF substrates (ajinomoto build-up film) can be flipped on the surface of the second redistribution layer RDL2. Fig.15As shown in (b), after welding the multiple substrates 30, a thermosetting material can be used to fill the bottom of the multiple substrates 30 and the gaps between the substrates 30 as needed, and the back of the substrate 30 and the connection structure (such as Cu Stud) are exposed by grinding to form a molding layer M1 to protect the multiple substrates 30.

[0154] Next, refer to Fig.16 As shown, multiple electronic components 20 (such as power modules, clocks, passive components and other functional modules) are respectively soldered to the surfaces of multiple substrates 30, thereby realizing vertical power supply interconnection between the electronic components 20 and the substrates 30.

[0155] Next, refer to Fig.17 As shown, the second carrier 02 is debonded and separated by laser burning, heat treatment and the like.

[0156] After that, the non-routing area of ​​the hybrid adapter board 10b is opened, cut, and the first heat sink 41, the second heat sink 42, the support frame 43, the fixed structure 50 and other manufacturing processes are installed. For details, please refer to the relevant instructions in Example 1, which will not be repeated here.

[0157] Embodiment 3

[0158] The third embodiment provides a chip packaging structure. The hybrid adapter board used in the chip packaging structure is similar to the hybrid adapter board 10b in the second embodiment. The only difference is that the material of the intermediate layer on which the bridge chip BG is arranged is different.

[0159] The structure of the new hybrid adapter board provided in the third embodiment is described below.

[0160] Indicative, such as Fig.18 As shown, a new type of hybrid adapter board 10c is used in the chip packaging structure provided in the present embodiment 3, and the hybrid adapter board 10c includes: a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 12 arranged between the first redistribution layer RDL1 and the second redistribution layer RDL2. Among them, a plurality of through glass vias TGV (through glass via) and at least one groove 100 are arranged in the glass interposer 12, and a bridge chip BG (bridge die) is arranged in the groove 100. The bridge chip BG and the through glass via TGV are connected between the first redistribution layer RDL1 and the second redistribution layer RDL2. The first redistribution layer RDL1 is arranged on the active surface of the bridge chip BG and is electrically connected to the active surface of the bridge chip BG. The second redistribution layer RDL2 is electrically connected to the first redistribution layer RDL1 through the through glass via TGV.

[0161] In addition, according to actual needs, in some possible implementations, the bridge chip BG may be provided with through silicon vias. In this case, the through silicon vias in the bridge chip BG are electrically connected to the second redistribution layer RDL2 below.

[0162] That is to say, compared with the second embodiment in which the dielectric layer of the bridge chip BG is formed of a molding material (ie, the molding layer 11 ), the dielectric layer of the bridge chip BG in the third embodiment is formed of a glass wafer.

[0163] In the third embodiment, since the bridge chip BG can be manufactured by a silicon-based process, the line width / line spacing / line thickness can be made smaller than 5 μm, thereby meeting the interconnection requirements of multiple chips D with high bandwidth density.

[0164] The first redistribution layer RDL1 may be a thin metal layer and a thin dielectric layer, such as a line width / line spacing / line thickness of less than 5 μm. In this case, the first redistribution layer RDL1 may lead out the connection pads on the surface of the bridge chip BG in the area of ​​the bridge chip BG, which may meet the high bandwidth density interconnection requirements between the chip D and the bridge chip BG.

[0165] Schematically, the first redistribution layer RDL1 can be implemented by using a damascene process including deposition, exposure, etching, electroplating, CMP and other processes.

[0166] The second redistribution layer RDL2 can be configured to use a thick metal layer and a thick dielectric layer. For example, the line width / line spacing / line thickness can be above 5 μm, thereby meeting the requirements of large current sharing and long routing capabilities of the electronic component 20 .

[0167] Illustratively, the second redistribution layer RDL2 may be implemented by a yellow light process including coating / filming, exposure, development, and curing.

[0168] Regarding other related settings of the bridge chip BG, the first redistribution layer RDL1, and the second redistribution layer RDL2 in the third embodiment, reference may be made to the corresponding parts in the second embodiment, which will not be repeated here.

[0169] Regarding other parts in the chip packaging structure, such as the electronic component 20, the substrate 30, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., corresponding reference may be made to the corresponding parts in the aforementioned embodiment 1 and embodiment 2, and no further details will be given here.

[0170] The chip packaging structure of this embodiment is further described below in conjunction with a method for manufacturing the chip packaging structure.

[0171] refer to Fig.19As shown in (a), a through glass via TGV is made on a glass wafer G, and the glass wafer G with the through glass via TGV is mounted on the surface of a first carrier 01. Then, a groove 100 can be opened on the glass wafer G by using a laser or other method.

[0172] Next, refer to Fig.19 As shown in (b), the bridge chip BG is mounted in the groove body of the groove 100.

[0173] Next, refer to Fig.19 As shown in (c), the groove 100 is filled with a thermal curing material and covers the surface of the glass wafer G. Then, referring to Fig.19 As shown in (d), the through glass via TGV and the connection structure (such as Cu Stud) on the surface of the bridge chip BG are exposed by grinding, so as to form a glass interposer 12.

[0174] The subsequent manufacturing process is basically the same as the steps after the molding of the intermediate layer 11 in the second embodiment. For details, please refer to the corresponding parts in the second embodiment and will not be repeated here.

[0175] The chip packaging structure in the aforementioned embodiments is not limited to being manufactured by the manufacturing method provided in the embodiments, and may also be manufactured by other manufacturing methods.

[0176] For example, in some possible implementations, the chip packaging structure provided in the aforementioned embodiments one, two, and three can first weld multiple substrates 30 on the hybrid adapter board 10 and perform plastic sealing, and finally assemble the chip D and the electronic component 20.

[0177] For example, taking the manufacturing of the chip packaging structure in the first embodiment as an example, the manufacturing method may include:

[0178] First, a hybrid adapter board 10a is manufactured on the first carrier board 01. The specific manufacturing process can be referred to Figure 4 And the corresponding description in embodiment 1.

[0179] Next, refer to Fig. 20 As shown in (a), a plurality of substrates 30 are welded to pads on the surface of the redistribution layer RDL in the hybrid interposer 10a.

[0180] Next, refer to Fig. 20 As shown in (b), a thermosetting material may be used to fill the bottom of the plurality of substrates 30 and the gaps between the substrates 30, and the backside of the substrate 30 and the connection structure (such as Cu Stud) may be exposed by grinding to form a molding layer M1 to protect the plurality of substrates 30.

[0181] Next, refer to Fig. 20As shown in (c), the first carrier 01 and the hybrid adapter plate 10a can be debonded and separated by laser burning, heat treatment, etc., to expose the micro pad interface on the surface of the silicon interposer.

[0182] Next, refer to Fig.21 As shown, multiple heterogeneous chips D can be mounted on the surface of the first redistribution layer RDL1. Then, a thermosetting material can be used to fill the bottom of the multiple chips and the gaps between the chips, and then the backside of the multiple chips D can be ground (backside grinding) to expose the backside of the chips, thereby forming a molding layer M2 to protect the multiple chips D.

[0183] Next, refer to Fig. 22 As shown, multiple electronic components 20 (such as power modules, clocks, passive components and other functional modules) can be respectively soldered to the surfaces of multiple substrates 30, thereby realizing vertical power supply interconnection between the electronic components 20 and the substrates 30.

[0184] After that, the non-routing area of ​​the hybrid adapter board 10b is opened, cut, and the first heat sink 41, the second heat sink 42, the support frame 43, the fixed structure 50 and other manufacturing processes are installed. For details, please refer to the relevant instructions in Example 1, which will not be repeated here.

[0185] It should be understood that the sequence of the production processes in the various embodiments of the present application should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0186] For other relevant contents in the manufacturing method in each embodiment, the corresponding parts in the chip packaging structure can be referred to, and no further details will be given here; for other setting structures in the aforementioned chip packaging structure embodiment, the above-mentioned manufacturing method and related manufacturing methods can be referred to for adjustment, and no further details will be given here one by one.

[0187] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A silicon interposer, wherein the front side of the silicon interposer has a metal wiring layer, and a through silicon via TSV is arranged in the silicon interposer; a redistribution layer formed on the back side of the silicon interposer and electrically connected to the through silicon via; At least one first chip, located on the front side of the silicon interposer and electrically connected to the metal wiring layer; At least one electronic component is located on a side of the redistribution layer away from the first chip and is connected to the redistribution layer or connected to the redistribution layer through a substrate.

2. The chip packaging structure according to claim 1, characterized in that: The at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of the electronic components.

5. The chip packaging structure according to claim 4, characterized in that: The plurality of electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively arranged opposite to the plurality of first chips; The power supply module is electrically connected to the first chip which is arranged opposite to the first chip through the redistribution layer and the silicon interposer, and supplies power to the first chip.

6. The chip packaging structure according to claim 4 or 5, characterized in that: The chip packaging structure comprises: a plurality of substrates; The substrate is located between the redistribution layer and the electronic components, and a plurality of the electronic components are electrically connected to the redistribution layer through a plurality of the substrates.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate; The first heat sink is disposed on a side of the first chip away from the silicon interposer, and the second heat sink is disposed on a side of the plurality of electronic components away from the redistribution layer.

8. A chip packaging structure, characterized in that: include: a first redistribution layer and a second redistribution layer; at least one bridge chip and a metal connection structure connected between the first redistribution layer and the second redistribution layer, and the first redistribution layer is located on the active surface of the bridge chip; at least one first chip, located on a side of the first redistribution layer away from the bridge chip, and the first chip is electrically connected to the bridge chip through the first redistribution layer; At least one electronic component is located on a side of the second redistribution layer away from the first redistribution layer and is connected to the second redistribution layer or connected to the second redistribution layer through a substrate.

9. The chip packaging structure according to claim 8, characterized in that: The line width, line spacing and line thickness of the metal routing in the first redistribution layer are all less than 5 μm; the line width, line spacing and line thickness of the metal routing in the second redistribution layer are all greater than 5 μm.

10. The chip packaging structure according to claim 8 or 9, characterized in that: The metal connection structure includes a metal column; The bridge chip and the metal pillar are encapsulated in a molding layer.

11. The chip packaging structure according to claim 8 or 9, characterized in that: A glass wafer is disposed between the first redistribution layer and the second redistribution layer, and a groove is disposed in the glass wafer; The bridge chip is embedded in the groove, and the metal connection structure includes a through glass via (TGV) penetrating the glass wafer.

12. The chip packaging structure according to any one of claims 8 to 11, characterized in that: The at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

13. The chip packaging structure according to any one of claims 8 to 12, characterized in that: The at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

14. The chip packaging structure according to any one of claims 8 to 13, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of electronic components.

15. The chip packaging structure according to any one of claims 8 to 14, characterized in that: The chip packaging structure includes a plurality of bridge chips; The bridge chip is located between two adjacent first chips, and the bridge chip connects the two adjacent first chips through the first redistribution layer.

16. The chip packaging structure according to claim 14 or 15, characterized in that: The plurality of electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively arranged opposite to the plurality of first chips; The power supply module is electrically connected to the first chip which is arranged opposite to the first chip through the redistribution layer and the bridge chip, and supplies power to the first chip.

17. The chip packaging structure according to any one of claims 14 to 16, characterized in that: The chip packaging structure comprises: a plurality of substrates; The substrate is located between the redistribution layer and the electronic components, and a plurality of the electronic components are electrically connected to the second redistribution layer through a plurality of the substrates.

18. The chip packaging structure according to any one of claims 8 to 17, characterized in that: The chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate; The first heat sink is disposed on a side of the first chip away from the first redistribution layer, and the second heat sink is disposed on a side of the electronic component away from the second redistribution layer.

19. An electronic device, characterized in that: It comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 18, wherein the chip packaging structure is electrically connected to the circuit board.

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