Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region, a first region and a channel layer, the first region is in contact with the channel layer, the first region is of a first conductive type and located on the first surface, and the well region is of a second conductive type and located on the side, away from the first surface, of the first region; a gate trench extending from the first surface into the semiconductor body; the channel layer is arranged to be of a first conduction type and is located between the well region and the side wall of the gate trench; a gate structure; a drain electrode; and a source electrode. According to the technical scheme, the depletion type semiconductor device is formed, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel when the depletion type semiconductor device is in the conducting state and the cut-off state in the normal state, response can be made faster, current circulation can be controlled, the conducting loss is small, and the depletion type semiconductor device is more suitable for a high-frequency circuit and a switching circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) in the prior art is an enhancement-mode device, which is normally non-conductive. If it is conductive, a positive voltage needs to be applied between the gate and the source. However, the enhancement-mode device has a high conduction loss and a slow response speed. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the conduction loss of the semiconductor device and improve the response speed.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first area and a channel layer, the first area and the channel layer are in contact with each other, the first area is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first area away from the first surface; a gate trench is set on the first surface, and the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer is located between the sidewalls of the well region and the gate trench;

[0007] a gate structure disposed within the gate trench;

[0008] a drain electrode, located on the second surface;

[0009] The source is located on the first surface.

[0010] Optionally, the ion concentration of the channel layer is less than the ion concentration of the first region.

[0011] Optionally, the gate structure includes a gate insulating layer and a gate, the gate insulating layer is located on the bottom surface and sidewalls of the gate trench, and the gate is located on a side of the gate insulating layer in the gate trench away from the semiconductor body.

[0012] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0013] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0014] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first region and a channel layer, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is set on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer surrounds the sidewall of the gate trench;

[0015] forming a gate structure in the gate trench;

[0016] forming a drain electrode on the second surface;

[0017] A source electrode is formed on the first surface.

[0018] Optionally, providing a semiconductor body includes:

[0019] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region, the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface;

[0020] A first mask layer is formed on the first surface, the first mask layer covers a first portion of the first region; the first mask layer is provided with a first through hole, the first through hole penetrates the first mask layer;

[0021] forming a second mask layer at the bottom and sidewall of the first through hole, the second mask layer covering the second portion of the first region, the first portion of the first region and the second portion of the first region constituting the first region; the second mask layer and the first mask layer are made of different materials;

[0022] forming a gate trench on the first surface, wherein the gate trench penetrates the second mask layer and extends from the first surface into the semiconductor body;

[0023] forming a third mask layer in the gate trench;

[0024] removing the second mask layer;

[0025] forming a channel layer between the well region and the sidewall of the gate trench, wherein the channel layer is set to be of a first conductivity type;

[0026] removing the third mask layer; the third mask layer and the second mask layer are made of different materials;

[0027] The first mask layer is removed.

[0028] Optionally, forming a third mask layer in the gate trench includes:

[0029] A third mask layer is formed in the gate trench and has a height smaller than that of the first region in a direction perpendicular to the second surface and directed toward the first surface.

[0030] Optionally, forming a second mask layer on the bottom and sidewall of the first through hole includes:

[0031] A second mask layer including silicon nitride is formed on the bottom and sidewalls of the first through hole.

[0032] Optionally, forming a gate structure in the gate trench includes:

[0033] forming a gate insulating layer on the bottom surface and sidewalls of the gate trench;

[0034] A gate is formed on a side of the gate insulating layer in the gate trench away from the semiconductor body.

[0035] Optionally, providing a semiconductor body includes:

[0036] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0037] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used for carrying the semiconductor device.

[0038] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0039] The power conversion circuit comprises a circuit board and at least one of the semiconductor devices mentioned above, and the semiconductor device is electrically connected to the circuit board.

[0040] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0041] The technical solution of the embodiment of the present invention is to set a channel layer of opposite conductivity type to the well region between the sidewalls of the well region and the gate groove. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. It is in the on state under normal conditions, and a negative gate-source voltage needs to be applied to the gate in the off state to cut off the channel. Compared with enhancement-type semiconductor devices, the technical solution provided by the embodiment of the present invention reduces the conduction loss of semiconductor devices, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. Among them, the gate structure is located in the gate groove and extends from the first surface to the semiconductor body. Compared with semiconductor devices including a planar gate structure, there is no need to set a JFET region on one side of the well region, which reduces the on-resistance of the semiconductor device.

[0042] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0045] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0046] Figure 3-Figure 4 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0047] Figure 5 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0048] Figure 6-Figure 18 It is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Figure 1 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103, a first region 104 and a channel layer 105, the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench, and the gate trench extends from the first surface 101 to the semiconductor body 100; the channel layer 105 is set to a first conductivity type, and the channel layer 105 is located between the sidewall of the well region 103 and the gate trench; the gate structure 200 is located in the gate trench; the drain 300 is located on the second surface 102; the source 400 is located on the first surface 101.

[0052] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0053] For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by ion implantation, ion diffusion, or vapor deposition. Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0054] The technical solution of the embodiment of the present invention is to set a channel layer 105 of the opposite conductivity type to the well region 103 between the sidewalls of the well region 103 and the gate groove. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. It is in the on state under normal conditions, and a negative gate-source voltage is required to cut off the channel in the off state. Compared with the enhancement-type semiconductor device, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. Among them, the gate structure 200 is located in the gate groove, extending from the first surface 101 to the semiconductor body 100. Compared with the semiconductor device including the gate structure 200 of the planar structure, there is no need to set the JFET region on one side of the well region 103, which reduces the on-resistance of the semiconductor device.

[0055] For example, Figure 1 In the embodiment, the source 400 is located on the first surface 101 and is a planar source. In other optional embodiments of the present invention, a trench source may be included, that is, a source trench may be provided on the first surface 101, a source insulating layer and a source conductive filling layer may be provided in the source trench, and the source 400 covers the source insulating layer and the source conductive filling layer.

[0056] In other optional embodiments of the present invention, Figure 1 As shown, it also includes a second region 107 , which is set to the second conductivity type and connected to the first region 104 . The doping concentration of the second region 107 is greater than the doping concentration of the well region 103 , and can form a good ohmic contact with the source 400 .

[0057] In other optional embodiments of the present invention, the ion concentration of the channel layer 105 is 10 16 cm -3 -10 17 cm -3 The ion concentration of the channel layer 105 is lower than the ion concentration of the first region 104 , which can reduce the manufacturing cost of the semiconductor device.

[0058] In other optional embodiments of the present invention, the gate structure 200 includes a gate insulating layer 201 and a gate 202 , wherein the gate insulating layer 201 is located on the bottom surface and sidewalls of the gate trench, and the gate 202 is located on a side of the gate insulating layer 201 in the gate trench away from the semiconductor body 100 .

[0059] The gate insulating layer 201 may be a gate oxide layer. The material of the gate 202 may be polysilicon. An interlayer insulating layer 500 is provided between the gate structure 200 and the source 400. The source 400 is formed by metal deposition. The semiconductor device further includes a drain 300 formed by metal deposition on the second surface 102 of the semiconductor body 100.

[0060] In other optional embodiments of the present invention, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0061] The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0062] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0063] Figure 2 The flowchart of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention.

[0064] like Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0065] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first region and a channel layer, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is set on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer surrounds the sidewall of the gate trench.

[0066] refer to Figure 3 The semiconductor body 100 includes a first surface 101 and a second surface 102 that are arranged opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104, and a channel layer 105. The first region 104 is set to the first conductivity type and is located on the first surface 101. The well region 103 is set to the second conductivity type and is located on a side of the first region 104 away from the first surface 101. The first surface 101 is provided with a gate trench 106, and the gate trench 106 extends from the first surface 101 to the semiconductor body 100. The channel layer 105 is set to the first conductivity type, and the channel layer 105 surrounds the sidewall of the gate trench.

[0067] A gate trench 106 is formed on the first surface 101 by photolithography and etching processes.

[0068] For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doped ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the channel layer 105 is an N-type channel layer. The well region 103 is a P-well region, and the P-type doped ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0069] Optional, reference Figure 3 The semiconductor body 100 further includes a second region 107 , which is set to a second conductivity type and connected to the first region 104 . The doping concentration of the second region 107 is greater than the doping concentration of the well region 103 .

[0070] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0071] S120 , forming a gate structure in the gate trench.

[0072] refer to Figure 4, a gate insulating layer 201 is first formed in the gate trench 106 , and then polysilicon is filled in the trench to form a gate 202 . The gate insulating layer 201 and the gate 202 constitute a gate structure 200 .

[0073] S130 , forming a source electrode on the first surface.

[0074] like Figure 1 As shown, a source 400 is formed on the first surface 101. An interlayer insulating layer 500 is disposed between the gate structure 200 and the source 400. The interlayer insulating layer 500 is used to insulate and separate the gate structure 200 and the source 400.

[0075] S140, forming a drain on the second surface.

[0076] refer to Figure 1 , a drain 300 is formed on the second surface 102 of the semiconductor body 100 .

[0077] The technical solution of the embodiment of the present invention forms a channel layer 105 of opposite conductivity type to the well region 103 between the well region 103 and the sidewall of the gate trench. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-type semiconductor device. It is in an on state under normal conditions, and a negative gate-source voltage is required to cut off the channel in the off state. Compared with enhancement-type semiconductor devices, the technical solution provided by the embodiment of the present invention reduces the conduction loss of semiconductor devices, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. Among them, the gate structure 200 is located in the gate trench, extending from the first surface 101 to the semiconductor body 100. Compared with semiconductor devices including a planar gate structure 200, there is no need to set a JFET region on one side of the well region 103, thereby reducing the on-resistance of the semiconductor device.

[0078] Figure 5 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the method for manufacturing the semiconductor device includes:

[0079] S210, providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area, the first area being set to a first conductivity type and located on the first surface, and the well region being set to a second conductivity type and located on a side of the first area away from the first surface.

[0080] refer to Figure 1, a semiconductor body 100 is provided, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101.

[0081] For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doped ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doped ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0082] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0083] The specific process of providing the semiconductor body 100 is as follows:

[0084] refer to Figure 6 The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a substrate 10 and an epitaxial layer 20. A well region 103 is formed on the first surface 101 of the semiconductor body 100 by ion implantation, ion diffusion or vapor deposition.

[0085] refer to Figure 7, a hard mask (HM) process is applied to form a mask layer 60 on the first surface 101 of the semiconductor body 100. The mask layer 60 can also be formed by depositing SiO2 using a plasma enhanced chemical vapor deposition (PECVD) method. The mask layer 60 is patterned by a photolithography process. The photolithography process is an important step in the semiconductor device manufacturing process. This step uses exposure and development to depict a geometric structure on a photoresist layer, and then transfers the pattern of the photoresist layer to the mask layer 60 through an etching process to achieve patterning of the mask layer 60, such as Figure 7 As shown, a through hole 601 is formed by a photolithography process. The through hole 601 penetrates the mask layer 60. The first region 104 is formed by first conductive type ion implantation at the through hole 601. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 by ion implantation, ion diffusion or vapor deposition.

[0086] refer to Figure 8 , a hydrofluoric acid solution may be used to etch away the mask layer 60 of the SiO2 material.

[0087] Optional, reference Fig. 9 , providing the semiconductor body 100 also includes forming a second region 107, the second region 107 is set to a second conductivity type, the second region 107 is connected to the first region 104, the doping concentration of the second region 107 is greater than the doping concentration of the well region 103, and can form a good ohmic contact with the source 400.

[0088] S211, forming a first mask layer on the first surface, wherein the first mask layer covers a first portion of the first region; the first mask layer is provided with a first through hole, wherein the first through hole penetrates the first mask layer.

[0089] refer to Fig.10 , SiO2 is deposited on the first surface 101 of the semiconductor body 100 by HM process or PECVD to form a first mask layer 70, and the first mask layer 70 covers the first region 104. The first mask layer 70 is patterned by photolithography process. A geometric structure is depicted on the photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the first mask layer 70 by etching process, so as to achieve patterning of the first mask layer 70, such as Fig.10 As shown, a first through hole 701 is formed by a photolithography process. The first through hole 701 penetrates the first mask layer 70 , and the first mask layer 70 covers a portion of the first region 104 close to the second region 107 .

[0090] S212, forming a second mask layer at the bottom and sidewall of the first through hole, the second mask layer covers the second part of the first region, the first part of the first region and the second part of the first region constitute the first region; the second mask layer and the first mask layer are made of different materials.

[0091] refer to Fig.11 In an embodiment of the present invention, a second mask layer 80 including silicon nitride is formed at the bottom and sidewall of the first through hole 701. The thickness of the deposited silicon nitride may be between 200A and 500A. The material of the second mask layer 80 is different from that of the first mask layer 70. For example, the material of the first mask layer 70 is silicon dioxide, and the material of the second mask layer 80 is silicon nitride. The material of the second mask layer 80 is distinguished from that of the first mask layer 70 to prevent the influence on the first mask layer 70 when the second mask layer 80 is removed later. The second mask layer 80 covers the second part of the first region to ensure contact with the first region 104 when the groove is formed, thereby improving the manufacturing accuracy of the semiconductor device. Among them, the first part of the first mask layer 70 covering the first region 104 and the second part of the second mask layer 80 covering the first region 104 together constitute the first region 104.

[0092] S213 , forming a gate trench on the first surface, wherein the gate trench penetrates the second mask layer and extends from the first surface into the semiconductor body.

[0093] refer to Fig.12 , a gate trench 106 is formed on the first surface 101 by etching, and the second mask layer 80 on the side wall of the first through hole 701 is retained to facilitate the formation of a channel layer for ion implantation.

[0094] S214, forming a third mask layer in the gate trench.

[0095] refer to Fig.13 , a third mask layer 90 is formed in the gate trench 106 by a deposition process. In the embodiment of the present invention, a third mask layer 90 is formed in the gate trench 106, and its height is smaller than that of the first region 104 in a direction perpendicular to the second surface 102 and pointing to the first surface 101. A portion of the first region 104 is exposed to ensure that the third mask layer 90 on the surface has been etched. The third mask layer 90 may be undoped polysilicon.

[0096] S215, removing the second mask layer.

[0097] refer to Fig.14 Hot phosphoric acid may be applied to remove the second mask layer 80 made of silicon nitride.

[0098] S216 , forming a channel layer between the well region and the sidewall of the gate trench, wherein the channel layer is set to be of the first conductivity type.

[0099] refer to Fig.15 After removing the second mask layer 80, a channel layer 105 is formed between the well region 103 and the sidewall of the gate trench 106 by ion implantation. Exemplarily, the channel layer 105 is formed by implanting N-type doping ions. The ion implantation concentration of the channel layer 105 is less than the ion implantation concentration of the first region 104.

[0100] S217, removing the third mask layer; the third mask layer and the second mask layer are made of different materials.

[0101] refer to Fig.16 , hydrofluoric acid and nitric acid can be used to remove the third mask layer 90. The third mask layer 90 and the second mask layer 80 are made of different materials. The material of the second mask layer 80 is distinguished from the material of the third mask layer 90 to prevent the third mask layer 90 from being affected when the second mask layer 80 is removed. Here, the third mask layer 90 is first formed to fill the gate trench 106, and then the third mask layer 90 is removed to protect the bottom of the gate trench 106 from being injected with ions.

[0102] S218, removing the first mask layer.

[0103] refer to Fig.17 , hydrofluoric acid and nitric acid may be used to remove the first mask layer 70 .

[0104] S219, forming a gate insulating layer on the bottom surface and sidewalls of the gate trench.

[0105] refer to Fig.18 A gate insulating layer 201 is formed on the bottom surface and sidewalls of the gate trench 106. The gate insulating layer 201 may be a gate oxide layer.

[0106] S220 , forming a gate on a side of the gate insulating layer in the gate trench away from the semiconductor body.

[0107] refer to Fig.18 A gate 202 is formed by a deposition process on a side of the gate insulating layer 201 in the gate trench 106 away from the semiconductor body 100, and then the gate 202 on the first surface 101 is etched to form a gate 202 as shown in FIG. Figure 4 The gate insulating layer 201 and the gate 202 together constitute the gate structure 200 .

[0108] S221 , forming a source on the first surface.

[0109] refer to Figure 1 An interlayer insulating layer 500 is disposed between the gate structure 200 and the source 400. The interlayer insulating layer 500 is used to insulate the gate structure 200 and the source 400. The source 400 is formed by metal deposition.

[0110] S222, forming a drain on the second surface.

[0111] refer to Figure 1 , a drain 300 is formed on the second surface 102 of the semiconductor body 100 .

[0112] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0113] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0114] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0115] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0116] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0117] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0118] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is set on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer is located between the sidewalls of the well region and the gate trench; A gate structure, located in the gate trench; a drain electrode, located on the second surface; The source is located on the first surface.

2. The semiconductor device according to claim 1, wherein: The ion concentration of the channel layer is lower than the ion concentration of the first region.

3. The semiconductor device according to claim 1, wherein: The gate structure comprises a gate insulating layer and a gate, wherein the gate insulating layer is located on the bottom surface and sidewall of the gate trench, and the gate is located on a side of the gate insulating layer in the gate trench away from the semiconductor body.

4. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

5. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region and a channel layer, the first region being set to a first conductivity type and located on the first surface, the well region being set to a second conductivity type and located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer surrounds the sidewall of the gate trench; forming a gate structure in the gate trench; forming a drain electrode on the second surface; A source electrode is formed on the first surface.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; forming a first mask layer on the first surface, wherein the first mask layer covers a first portion of the first region; the first mask layer is provided with a first through hole, and the first through hole penetrates the first mask layer; forming a second mask layer at the bottom and sidewall of the first through hole, wherein the second mask layer covers the second portion of the first region, and the first portion of the first region and the second portion of the first region constitute the first region; the second mask layer and the first mask layer are made of different materials; forming a gate trench on the first surface, wherein the gate trench penetrates the second mask layer and extends from the first surface into the semiconductor body; forming a third mask layer in the gate trench; removing the second mask layer; forming a channel layer between the well region and the sidewall of the gate trench, wherein the channel layer is set to a first conductivity type; removing the third mask layer; wherein the third mask layer and the second mask layer are made of different materials; The first mask layer is removed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: Forming a third mask layer in the gate trench comprises: A third mask layer having a height smaller than that of the first region in a direction perpendicular to the second surface and pointing toward the first surface is formed in the gate trench.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: Forming a second mask layer on the bottom and sidewall of the first through hole comprises: A second mask layer including silicon nitride is formed on the bottom and sidewalls of the first through hole.

9. The method for manufacturing a semiconductor device according to claim 5, wherein: Forming a gate structure in the gate trench includes: forming a gate insulating layer on the bottom surface and sidewalls of the gate trench; A gate is formed on a side of the gate insulating layer in the gate trench away from the semiconductor body.

10. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

11. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to carry the semiconductor device.

12. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 12, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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