Method for manufacturing memory device / logic device compatible semi-floating gate transistor

Abstract

The present invention discloses a method for manufacturing a memory device / logic device compatible semi-floating gate transistor. A hard mask is not used to form a U-shaped groove, so that the semi-floating gate polysilicon is prevented from being buried between the hard masks, the etching depth-to-width ratio of the contact window can be reduced, and the first semi-floating gate polysilicon does not need to be etched back. Moreover, since a hard mask is not used to form the U-shaped groove, after depositing the second semi-floating gate polysilicon, there is no thickness difference between the first active area and the semi-floating gate polysilicon on the X-direction shallow trench isolation. The thickness of the semi-floating gate polysilicon in the logic area and the memory area is consistent before and after the floating gate polysilicon is etched back. Therefore, online measurement can be established, and the thickness of the semi-floating gate polysilicon in the memory area can be precisely controlled by using advanced process control to etch to a target thickness, which can reduce process difficulty and facilitate mass production.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, and in particular to a method for manufacturing a memory device / logic device compatible semi-floating gate transistor (SFGT). Background Art

[0002] Capacitors are a bottleneck in the development of traditional DRAM (Dynamic Random Access Memory). Semi-floating gate transistors (SFGTs), as a potential capacitor-free DRAM, are compatible with standard logic processes and are easier to scale down. Data can be erased and written more easily and quickly. Figure 1 As shown, a semi-floating gate transistor (SFGT) combines a tunneling field-effect device (TFET) and a floating gate device to create a novel "semi-floating gate" structure. The TFET is used to charge and discharge the floating gate, completing data write and erase operations. The semi-floating gate polysilicon in the U-shaped trench (U-trench) is used to store charge, enabling data storage and readout. Charging and discharging the semi-floating gate polysilicon via the control gate and the tunneling field-effect device gate (SG) enables the transition between the SFGT's logical 1 and 0 states. The floating gate device's U-trench isolates the semi-floating gate N-well, forming a U-shaped channel at its bottom. Compared to traditional profile channels, this facilitates device miniaturization. Furthermore, the gate polysilicon in the U-trench is used to store charge, utilizing the tunneling effect to accelerate charge writing.

[0003] In the existing memory device / logic device compatible semi-floating gate process, the following steps are included:

[0004] (1) providing a semiconductor silicon substrate 100;

[0005] A semiconductor silicon substrate 100 is separated into a storage area 103 and a logic area 104 by Y-direction shallow trench isolation (STI) 102. In the storage area 103 of the semiconductor silicon substrate 100, multiple X-direction shallow trench isolation (STI) lines 101 are divided into multiple X-direction first active regions 105. The multiple X-direction field oxide lines 101 and the multiple X-direction first active regions 105 are arranged in parallel. The X direction is parallel to the length direction of the first active regions, and the Y direction is perpendicular to the X direction.

[0006] (2) depositing a hard mask 123;

[0007] (3) performing Y-direction etching first and then X-direction etching to expose the upper surface of the first active region 105 and forming U-shaped trenches (U-trench) 109 in the first active region 105 at each Y-direction opening, with a hard mask 123 remaining on the X-direction field oxide 101;

[0008] (4) growing a semi-floating gate dielectric layer 110 on the upper surface of the first active region 105 and the surface of the U-shaped trench 109, such as Figure 2a As shown;

[0009] (5) depositing a first floating gate polysilicon 1201 to fill the U-trench;

[0010] (6) The first floating gate polysilicon 1201 is etched back to thin the first floating gate polysilicon 1201 to reduce the etching depth-to-width ratio of the subsequent contact window etching (C-window ET) 111, such as Figure 2b As shown;

[0011] (VII) Contact window (C-window) etching, removing the first half floating gate polysilicon and gate oxide layer at the contact window 111, exposing the first active area (AA) 105, as shown in FIG. Figure 2c As shown;

[0012] (VIII) Depositing the second floating gate polysilicon 1202 to achieve contact between the half floating gate polysilicon and the active area (AA) Si substrate to form a PN junction, such as Figure 2d As shown;

[0013] (IX) Floating gate polysilicon etching back, etching the half floating gate polysilicon thickness of the storage area 103 to about Thus, the final half-floating gate polysilicon is obtained, such as Figure 2e shown.

[0014] The existing memory device / logic device compatible semi-floating gate process requires etching the semi-floating gate polysilicon of the storage area 103 to about Thus, the X-direction shallow trench isolation (STI) 101 is realized to physically isolate the half-floating gate polysilicon. Figure 3 As can be seen from the cross-sectional view of the storage area 103 shown, the thickness of the half-floating gate polysilicon on the active area (AA) and on the X-direction shallow trench isolation (STI) 101 is different before etching. This is because the presence of the hard mask on the X-direction shallow trench isolation (STI) 101 causes the half-floating gate polysilicon on the active area (AA) to merge, that is, THK1=THK2+THK3; THK1 is the thickness of the half-floating gate polysilicon on the active area (AA) before etching, THK2 is the thickness of the half-floating gate polysilicon on the X-direction shallow trench isolation (STI) 101 before etching, and THK3 is the thickness of the hard mask on the X-direction shallow trench isolation (STI) 101.

[0015] Since the thickness of the semi-floating gate polysilicon on the shallow trench isolation of the logic area 104 and the storage area 103 is the same, it means that when the thickness of the semi-floating gate polysilicon on the active area (AA) of the storage area is in place, there is no semi-floating gate polysilicon left in the logic area 104. This makes it impossible to establish an inline measurement to monitor the thickness of the semi-floating gate polysilicon, and it is also impossible to introduce APC (advanced process control) to accurately control the thickness of the semi-floating gate polysilicon in the storage area 103. The process is difficult and cannot be mass-produced. In addition, the existing memory / logic compatible semi-floating gate process requires two back-etches, the first of which is used to reduce the aspect ratio of the contact window (C-window) 111. However, the additional etching step makes it more difficult to control the uniformity within the wafer surface. Summary of the Invention

[0016] The technical problem to be solved by the present invention is to provide a method for manufacturing a semi-floating gate transistor that is compatible with memory devices / logic devices, which can reduce the etching depth-to-width ratio of the contact window, establish online measurement to accurately control the thickness of the semi-floating gate polysilicon in the storage area and etch it to the target thickness, thereby reducing the process difficulty for mass production.

[0017] To solve the above technical problems, the present invention provides a method for manufacturing a memory device / logic device compatible semi-floating gate transistor, comprising the following steps:

[0018] S1. Providing a semiconductor silicon substrate 100;

[0019] The semiconductor silicon substrate 100 is separated into a storage area 103 and a logic area 104 by a Y-direction shallow trench isolation 102;

[0020] In the storage area 103, the semiconductor silicon substrate 100 is separated into a plurality of X-direction first active regions 105 by a plurality of X-direction shallow trench isolations 101; the X-direction is parallel to the length direction of the first active regions, and the Y-direction is perpendicular to the X-direction;

[0021] S2. A first photoresist is applied to the surface of the first active area 105 and the X-direction shallow trench isolation 101, and a Y-direction opening is photolithographically performed to etch and remove the upper portion of the silicon substrate of the X-direction first active area 105 at the Y-direction opening. A U-shaped trench 109 is formed in each of the first active areas 105 along multiple pairs of Y-direction openings, each pair of Y-direction openings consisting of two adjacent Y-direction openings in the X direction; the first photoresist is then removed;

[0022] S3. A semi-floating gate dielectric layer 110 is generated on the upper surface of the first active region 105 and the surface of the U-shaped trench 109;

[0023] S4. Depositing a first half floating gate polysilicon 1201, the first half floating gate polysilicon 1201 completely fills the U-shaped trench 109;

[0024] S5. A second photoresist is applied to the surface of the first active area 105 and the X-direction shallow trench isolation 101, and then photolithography and etching are performed. The semi-floating gate dielectric layer 110 of a set width is removed on the first active area 105 on the X-direction outer side of each pair of U-shaped trenches corresponding to the Y-direction openings to expose the first active area 105 there, forming a contact window 111; the second photoresist is then removed;

[0025] S6. Depositing a second half floating gate polysilicon 1202, the second half floating gate polysilicon 1202 fills the contact window 111;

[0026] S7. The floating gate polysilicon is etched back to etch the half floating gate polysilicon thickness of the storage area 103 to the target thickness, thereby obtaining the final half floating gate polysilicon;

[0027] S8. Perform subsequent processes.

[0028] Preferably, in step S6, the thickness of the second half floating gate polysilicon 1202 on the first half floating gate polysilicon 1201 is greater than a set thickness;

[0029] The set thickness is greater than the target thickness.

[0030] Preferably, the target thickness is

[0031] Preferably, the set thickness is

[0032] Preferably, the semi-floating gate dielectric layer 110 is formed of a liner oxide layer.

[0033] Preferably, the semi-floating gate dielectric layer 110 is silicon oxide.

[0034] Preferably, in step S1 , the upper portion of the first active region 105 is doped with the first type of doping, and the lower portion is doped with the second type of doping;

[0035] In step S2, the bottom of the U-shaped trench 109 enters the lower portion of the first active region 105;

[0036] In step S4, the first half floating gate polysilicon 1201 is doped with the second type of doping;

[0037] In step S6, the second half floating gate polysilicon 1202 is doped with the second type of doping;

[0038] The first type of doping is N-type doping, and the second type of doping is P-type doping; or,

[0039] The first type of doping is P-type doping, and the second type of doping is N-type doping.

[0040] Preferably, in step S5, the set width is 20 nm to 80 nm.

[0041] Preferably, in step S5 , the aspect ratio of the contact window 111 is less than 1.6.

[0042] The method for manufacturing a memory device / logic device compatible semi-floating gate transistor of the present invention does not use a hard mask (HM) to form a U-trench, thereby preventing the semi-floating gate polysilicon from merging between the hard masks (HM) and reducing the etching aspect ratio of the contact window (C-window) 111. Therefore, the first semi-floating gate polysilicon 1201 does not need to be etched back. Moreover, since a hard mask (HM) is not used to form the U-trench, After depositing the second half-floating gate polysilicon 120, there is no thickness difference between the half-floating gate polysilicon on the first active area 105 and the X-direction shallow trench isolation (STI) 101. The thickness of the half-floating gate polysilicon in the logic area 104 and the storage area 103 is consistent before and after the floating gate polysilicon is etched back. Therefore, inline measurement can be established, and APC (Advanced Process Control) can be used to precisely control the thickness of the half-floating gate polysilicon in the storage area 103 to be etched to the target thickness, which can reduce the process difficulty and facilitate mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a schematic diagram of the typical structure of a semi-floating gate transistor;

[0045] Figures 2a to 2e It is a schematic diagram of the three-dimensional structure of each process step of the manufacturing method of a semi-floating gate transistor compatible with existing memory devices / logic devices;

[0046] Figure 3 is a cross-sectional view of a storage region of a conventional method for manufacturing a semi-floating gate transistor;

[0047] Figures 4a to 4e It is a three-dimensional structural schematic diagram of each process step of the method for manufacturing a memory device / logic device compatible semi-floating gate transistor of the present invention.

[0048] Description of reference numerals in the figures:

[0049] 100. Semiconductor silicon substrate; 101. X-direction shallow trench isolation; 102. Y-direction shallow trench isolation; 103. Storage area; 104. Logic area; 105. First active area; 109. U-shaped trench; 110. Semi-floating gate dielectric layer; 1201. First semi-floating gate polysilicon; 1202. Second semi-floating gate polysilicon; 111. Contact window. DETAILED DESCRIPTION

[0050] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0051] Example 1

[0052] A method for manufacturing a memory device / logic device compatible semi-floating gate transistor comprises the following steps:

[0053] A method for manufacturing a memory device / logic device compatible semi-floating gate transistor, characterized by comprising the following steps:

[0054] S1. Providing a semiconductor silicon substrate 100;

[0055] The semiconductor silicon substrate 100 is separated into a memory area 103 and a logic area 104 by a Y-direction shallow trench isolation (STI) 102;

[0056] In the storage region 103, a semiconductor silicon substrate 100 is separated into a plurality of X-direction first active regions 105 by a plurality of X-direction shallow trench isolations 101. The plurality of X-direction field oxides 101 and the plurality of X-direction first active regions 105 are arranged in parallel. The X direction is parallel to the length direction of the first active regions, and the Y direction is perpendicular to the X direction.

[0057] The storage area (103) is used to form a storage cell array;

[0058] The logic region (104) is used to form a logic device;

[0059] S2. A first photoresist is applied to the surface of the first active area 105 and the X-direction shallow trench isolation 101, and a Y-direction opening is photolithography performed to remove the upper portion of the silicon substrate of the X-direction first active area 105 at the Y-direction opening. U-shaped trenches (U-trench) 109 are formed in each of the first active areas 105 along multiple pairs of Y-direction openings, where each pair of Y-direction openings consists of two adjacent Y-direction openings in the X direction. The first photoresist is then removed.

[0060] S3. A semi-floating gate dielectric layer 110 is formed on the upper surface of the first active region 105 and the surface of the U-shaped trench 109. The semi-floating gate dielectric layer 110 is formed on the inner wall surface of the U-shaped trench 109 and extends to the upper surface of the first active region 105 outside the U-shaped trench 109. Figure 4a As shown;

[0061] S4. Depositing the first half floating gate polysilicon 1201, the first half floating gate polysilicon 1201 completely fills the U-shaped trench 109, completely fills the spacer area at the top of the first active area 105 between the Y-direction shallow trench isolation 102 and extends to the top surface of the Y-direction shallow trench isolation 102, as shown in FIG. Figure 4b As shown;

[0062] S5. A second photoresist is applied to the first active area 105 and the surface of the X-direction shallow trench isolation 101, and then photolithography and etching are performed. The semi-floating gate dielectric layer 110 of a set width is removed on the first active area 105 outside the X-direction of each pair of U-shaped trenches corresponding to the Y-direction openings to expose the first active area 105 there, forming a contact window (C-window) 111; the second photoresist is then removed, as shown in FIG. Figure 4c As shown;

[0063] S6. Depositing the second half floating gate polysilicon 1202, the second half floating gate polysilicon 1202 fills the contact window (C-window) 111, as shown Figure 4d As shown;

[0064] S7. The floating gate polysilicon is etched back to obtain the final half-floating gate polysilicon. The thickness of the half-floating gate polysilicon in the storage area 103 (the thickness from the top surface of the half-floating gate polysilicon gate to the top surface of the half-floating gate dielectric layer 110 outside the U-shaped trench 109 and the contact window (C-window) 111) is etched to the target thickness, thereby obtaining the final half-floating gate polysilicon. Figure 4e As shown;

[0065] S8. Perform subsequent processes.

[0066] Preferably, in step S6, the thickness of the second half floating gate polysilicon 1202 on the first half floating gate polysilicon 1201 is greater than a set thickness; and the set thickness is greater than a target thickness.

[0067] Preferably, the target thickness is

[0068] Preferably, the set thickness is

[0069] The method for manufacturing a memory device / logic device compatible semi-floating gate transistor of the first embodiment does not use a hard mask (HM) to form a U-trench, thereby preventing the semi-floating gate polysilicon from merging between the hard masks (HM) and reducing the etching aspect ratio of the contact window (C-window) 111. Therefore, the first semi-floating gate polysilicon 1201 does not need to be etched back. Moreover, since a hard mask (HM) is not used to form the U-trench, After depositing the second half-floating gate polysilicon 120, there is no thickness difference between the half-floating gate polysilicon on the first active area 105 and the X-direction shallow trench isolation (STI) 101. The thickness of the half-floating gate polysilicon in the logic area 104 and the storage area 102 is consistent before and after the floating gate polysilicon is etched back. Therefore, inline measurement can be established, and APC (Advanced Process Control) can be used to accurately control the thickness of the half-floating gate polysilicon in the storage area 103 to be etched to the target thickness, which can reduce the process difficulty and facilitate mass production.

[0070] Example 2

[0071] Based on the method for manufacturing a memory device / logic device compatible semi-floating gate transistor in the first embodiment, the semi-floating gate dielectric layer 110 uses a liner oxide layer (liner OX), for example, the semi-floating gate dielectric layer 110 is silicon oxide.

[0072] Example 3

[0073] Based on the method for manufacturing a memory device / logic device compatible semi-floating gate transistor of the first embodiment, in step S1, the upper portion of the first active region 105 is doped with the first type of doping, and the lower portion is doped with the second type of doping;

[0074] In step S2, the bottom of the U-shaped trench 109 enters the lower portion of the first active region 105;

[0075] In step S4, the first half floating gate polysilicon 1201 is doped with the second type of doping;

[0076] In step S6, the second half floating gate polysilicon 1202 is doped with the second type of doping;

[0077] The first type of doping is N-type doping, and the second type of doping is P-type doping; or,

[0078] The first type of doping is P-type doping, and the second type of doping is N-type doping.

[0079] Example 4

[0080] Based on the method for manufacturing a memory device / logic device compatible half-floating gate transistor of the first embodiment, in step S5, the set width is 20 nm to 80 nm.

[0081] Preferably, in step S5 , the aspect ratio of the contact window 111 is less than 1.6.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a memory device / logic device compatible semi-floating gate transistor, characterized in that: The following steps are involved: S1. Providing a semiconductor silicon substrate (100); The semiconductor silicon substrate (100) is separated into a storage area (103) and a logic area (104) by a Y-direction shallow trench isolation (102); In the storage area (103), the semiconductor silicon substrate (100) is separated into a plurality of X-direction first active regions (105) by a plurality of X-direction shallow trench isolations (101); the X-direction is parallel to the length direction of the first active region, and the Y-direction is perpendicular to the X-direction; S2. coating a first photoresist on the surface of the first active region (105) and the X-direction shallow trench isolation (101), performing Y-direction opening photolithography, etching and removing the upper portion of the silicon substrate of the X-direction first active region (105) at the Y-direction opening, forming a U-shaped groove (109) in each first active region (105) along multiple pairs of Y-direction openings, each pair of Y-direction openings consisting of two Y-direction openings adjacent to each other in the X-direction; and then removing the first photoresist; S3. Generating a semi-floating gate dielectric layer (110) on the upper surface of the first active region (105) and the surface of the U-shaped trench (109); S4. depositing a first half floating gate polysilicon (1201), wherein the first half floating gate polysilicon (1201) completely fills the U-shaped trench (109); S5. coating a second photoresist on the surface of the first active area (105) and the X-direction shallow trench isolation (101), performing photolithography and etching, and removing a set width of the semi-floating gate dielectric layer (110) on the X-direction outer side of each pair of U-shaped grooves corresponding to the Y-direction openings on the first active area (105) to expose the first active area (105) there, thereby forming a contact window (111); and then removing the second photoresist; S6. depositing a second half floating gate polysilicon (1202), the second half floating gate polysilicon (1202) filling the contact window (111); S7. Etching back the floating gate polysilicon to etch the half floating gate polysilicon thickness of the storage area (103) to the target thickness, thereby obtaining the final half floating gate polysilicon; S8. Perform subsequent processes.

2. The method for manufacturing a memory device / logic device compatible semi-floating gate transistor according to claim 1, wherein: In step S6, the thickness of the second half floating gate polysilicon (1202) on the first half floating gate polysilicon (1201) is greater than a set thickness; The set thickness is greater than the target thickness.

3. The method for manufacturing a memory device / logic device compatible half-floating gate transistor according to claim 2, wherein: The target thickness is 4. The method for manufacturing a memory device / logic device compatible semi-floating gate transistor according to claim 3, wherein: The set thickness is 5. The method for manufacturing a memory device / logic device compatible half-floating gate transistor according to claim 1, wherein: The semi-floating gate dielectric layer (110) adopts an inner liner oxide layer.

6. The method for manufacturing a memory device / logic device compatible half-floating gate transistor according to claim 5, wherein: The semi-floating gate dielectric layer (110) is silicon oxide.

7. The method for manufacturing a memory device / logic device compatible semi-floating gate transistor according to claim 1, wherein: In step S1, the upper portion of the first active region (105) is doped with the first type of doping, and the lower portion is doped with the second type of doping; In step S2, the bottom of the U-shaped trench (109) enters the lower part of the first active area (105); In step S4, the first half floating gate polysilicon (1201) is doped with the second type of doping; In step S6, the second half floating gate polysilicon (1202) is doped with a second type of doping; The first type of doping is N-type doping, and the second type of doping is P-type doping; or, The first type of doping is P-type doping, and the second type of doping is N-type doping.

8. The method for manufacturing a memory device / logic device compatible semi-floating gate transistor according to claim 1, wherein: In step S5, the width is set to be 20 nm to 80 nm.

9. The method for manufacturing a memory device / logic device compatible semi-floating gate transistor according to claim 1, wherein: In step S5, the aspect ratio of the contact window (111) is less than 1.6.

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