A two-dimensional memory junction device and its fabrication, performance acquisition and application methods

Abstract

This application belongs to the field of semiconductor optoelectronic devices and micro / nanoelectronics, specifically disclosing a two-dimensional memory junction device and its fabrication, performance acquisition, and application methods. The two-dimensional memory junction device includes a first contact electrode, a doped n-type Si layer, and AgO. x Charge trapping layer and second contact electrode; AgO x The charge trapping layer and the doped n-type Si layer are combined to form a heterojunction resistive switching region; the heterojunction resistive switching region is used for AgO-based... x The trapping ionization and deionization transitions in the charge trapping layer, driven by voltage, achieve continuously adjustable and mutually coupled memory strength in both photovoltaic responsivity and conductivity dimensions, while exhibiting non-volatility. This application can store information in two different dimensions—photovoltaic and conductivity—and a compact and efficient machine vision system can be built using a single device to construct two-dimensional arrays.

Description

Technical Field

[0001] This application belongs to the field of semiconductor optoelectronic devices and micro / nanoelectronics, and more specifically, relates to a two-dimensional memory junction device and its fabrication, performance acquisition and application methods. Background Technology

[0002] With the rise of artificial intelligence, various types of visual systems that mimic human vision and neuromorphic systems have been proposed to achieve true autonomous driving and replace human intervention. However, the development of this technology is severely constrained by its architecture, hardware, and integration. Traditional machine vision systems often use charge-coupled devices (CCDs) for image sensing and complementary metal-oxide-semiconductor (CMOS)-based computing and storage chips for further storage and computation of the sensed information. This architecture leads to the separation of the sensing, computing, and storage units. Edge computing-based autonomous driving imposes very stringent limitations on overall hardware overhead, thus restricting its development in terms of speed, energy efficiency, and integration due to system architecture and hardware limitations. Therefore, only by achieving the integration of sensing, storage, and computing units at the architectural level and realizing multi-dimensional information processing from light to electricity at the hardware level can the most efficient and compact machine vision system be achieved.

[0003] Building upon this foundation, inductive-memory-computing fusion computing and related devices have been proposed. Currently, the most superior and practically feasible technology is the electrostatically doped split-gate homojunction transistor (SMT), which utilizes the photovoltaic effect for computation, enabling self-powered image processing and handling a wide range of dynamic and static optical information. It is currently recognized as the mainstream technology. However, this approach suffers from two major drawbacks: First, the four-port structure of the electrostatically doped SMT—source, drain, and split gate—leads to an exponential increase in interconnect complexity during integration, making it unsuitable for large-scale integration. Second, it only supports photovoltaic-level computation and cannot further handle subsequent deep neural network processing based on electrical signals. Therefore, developing a low-port, multi-dimensional memory device is crucial for achieving a compact and efficient machine vision system. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application aims to provide a two-dimensional memory junction device and its fabrication, performance acquisition, and application methods. This addresses the issue that the four-port structure of the source, drain, and gate of electrostatically doped cracked-gate homojunction transistors leads to an exponential increase in interconnect complexity during integration, making it unsuitable for large-scale integration. Furthermore, it only provides photovoltaic-level computation and cannot handle deep neural network processing based on electrical signal dimensions.

[0005] To achieve the above objectives, in a first aspect, this application provides a two-dimensional memory junction device, comprising a first contact electrode, a doped n-type Si layer, and an AgO layer stacked sequentially from bottom to top. x Charge trapping layer and second contact electrode; wherein, 0.4 <x<1.2;

[0006] The Fermi level of a doped n-type Si layer is lower than its midband level; AgO x The charge trapping layer and the doped n-type Si layer combine to form a heterojunction resistive switching region; AgO x The area of ​​the charge trapping layer is larger than the area of ​​the second contact electrode;

[0007] The first and second contact electrodes are used to provide ohmic contact and voltage drive;

[0008] Heterojunction resistive switching region for AgO-based x The trapping ionization and deionization transitions in the charge trapping layer, driven by voltage, achieve continuous tunability and mutual coupling of memory intensity in both photovoltaic responsivity and conductivity dimensions, and are non-volatile.

[0009] More preferably, the first contact electrode is Al, Ti, Al silicide, or Ti silicide; the second contact electrode is Au or Pt.

[0010] More preferably, the dopant in the doped n-type Si layer is a combination of one or more materials, and the doped n-type Si layer is P-doped with a doping concentration on the order of 1E¹⁵ cm⁻¹. -3 .

[0011] More preferably, the thickness of the first contact electrode is 3nm-200nm; the thickness of the doped n-type Si layer is 30nm-500um, and the AgO layer... x The charge trapping layer has a thickness of 10nm-100nm, and the second contact electrode has a thickness of 3nm-200nm.

[0012] Secondly, this application provides a corresponding performance acquisition method based on a two-dimensional memory junction device, specifically as follows:

[0013] After applying a negative voltage to the second contact electrode of the dual-dimensional memory junction device, the resistance state of the dual-dimensional memory junction device is read under a light-free environment using a positive voltage, and the resistance state of the dual-dimensional memory junction device decreases. At the same time, based on the 0V short-circuit state, the short-circuit current of the dual-dimensional memory junction device is read under a light-free environment, and the photovoltaic responsivity of the dual-dimensional memory junction device increases.

[0014] After applying a forward voltage to the second contact electrode of the dual-dimensional memory junction device, the resistance state of the dual-dimensional memory junction device is read under no-light conditions using the forward voltage, and the resistance state of the dual-dimensional memory junction device is obtained to rise; at the same time, based on the 0V short-circuit state, the short-circuit current of the dual-dimensional memory junction device is read under light conditions, and the photovoltaic responsivity of the dual-dimensional memory junction device is obtained to decrease.

[0015] More preferably, as the thickness of the AgOx charge trapping layer increases, the forward voltage amplitude used to read the resistive state of the two-dimensional memory junction device increases.

[0016] Furthermore, when the AgOx charge trapping layer thickness is 23nm, the forward voltage used to read the resistive state of the two-dimensional memory junction device is less than or equal to 0.4V.

[0017] Thirdly, this application provides a corresponding neural network application method based on a two-dimensional memory junction device, specifically including the following steps:

[0018] The first and second contact electrodes of the dual-dimensional memory junction device are used as word lines and bit lines, respectively, and cross-array integration is performed.

[0019] One of the cross arrays is used as the photovoltaic response dimension array. All pixels of the input light image are mapped in array form into the photovoltaic response dimension array. The light image and the photovoltaic responsivity matrix corresponding to the photovoltaic response dimension array are subjected to Hadamard product operation to output the current vector.

[0020] Another cross array is used as the conductance dimension array. The output current vector is converted into a voltage vector and input into the conductance dimension array. The matrix-vector multiplication operation is completed by Kirchhoff's current law and Ohm's law, and the classification task of the output light image is completed.

[0021] Fourthly, this application provides a method for fabricating a two-dimensional memory junction device, specifically including the following steps:

[0022] Step 1: Prepare a doped n-type Si layer by using melt doping during the Czochralski or zone melting method of single-crystal Si growth; or grow an intrinsic Si layer using either the Czochralski or zone melting method, and then prepare a doped n-type Si layer by thermal diffusion doping or ion implantation.

[0023] Step 2: Fabricate the first contact electrode on the back side of the doped n-type Si layer using at least one of sputtering, physical vapor deposition, or chemical vapor deposition.

[0024] Step 3: Image-based fabrication of AgO on a doped n-type Si layer x A mask layer for charge trapping and preparation of AgO x Charge trapping layer, mask layer removal;

[0025] Step 4: Prepare a second contact electrode patterning mask layer above the charge trapping layer, prepare the second contact electrode, and remove the mask layer to complete the fabrication of the two-dimensional memory junction device. x x

[0026] Further preferably, the fabrication processes of the second contact electrode, AgO x charge trapping layer, and the first contact electrode are one of sputtering method, physical vapor deposition method, chemical vapor deposition method, molecular beam epitaxy method, atomic layer deposition method, pulsed laser deposition method, or electrochemical method.

[0027] Generally speaking, compared with the prior art by the above technical solutions conceived in this application, the following beneficial effects are achieved:

[0028] This application provides a two-dimensional memory junction device, including a first contact electrode, a doped n-type Si layer, AgO x charge trapping layer, and a second contact electrode stacked in sequence from bottom to top; the charge trapping layer and the doped n-type Si layer form a heterojunction resistive switching region; in AgO x charge trapping layer, 0.4 < x < 1.2; the area of the charge trapping layer should be larger than that of the second contact electrode for light sensing; this application can store information in two different dimensions of photovoltaic and conductivity, different from the existing devices that can only achieve single-dimensional memory function.

[0029] This application provides a two-dimensional memory junction device. Based on the self-rectifying characteristic of the device as a PN junction itself, the integration of the cross array of this device does not require an additional gating device and has theoretically at least two ports, which is beneficial for large-scale integration.

[0030] This application provides an application based on a two-dimensional memory junction device. Using the two dimensions of the device, a photovoltaic dimension array and a conductivity dimension array are constructed. The photovoltaic dimension array performs the Hadamard product of the optical matrix - electrical matrix and outputs an electrical signal in vector form, and then the vector is input into the conductivity dimension matrix to complete the matrix-vector multiplication, realizing the classification task of image information. A compact and efficient machine vision system can be built with two-dimensional arrays constructed by only one device. <​​​​​​​​​​​​Figure 2(b) shows the Ti / n-Si / p-AgO under illumination provided in the embodiment of this application. x DC scan performance of the conductivity of / Pt dual-dimensional memory junction device;

[0034] Figure 3(a) shows the Ti / n-Si / p-AgO provided in the embodiment of this application. x Photovoltaic weighted pulse plasticity performance of / Pt dual-dimensional memory junction device;

[0035] Figure 3(b) shows the Ti / n-Si / p-AgO provided in the embodiment of this application. x Conductivity weighted pulse plasticity performance of / Pt dual-dimensional memory junction device;

[0036] Figure 4(a) shows the Ti / n-Si / p-AgO provided in the embodiment of this application. x 1000s long-term retention plot of the photoresponse state of / Pt dual-dimensional memory junction device;

[0037] Figure 4(b) shows the Ti / n-Si / p-AgO provided in the embodiment of this application. x 1000s long-term retention plot of multiple conductances of / Pt dual-dimensional memory junction device;

[0038] Figure 5(a) shows the circuit connection architecture of two cross arrays provided in an embodiment of this application;

[0039] Figure 5(b) is a network architecture calculation diagram corresponding to the circuit architecture provided in the embodiment of this application;

[0040] Figure 5(c) is a diagram showing the effect of the classification task of the four letters 'H', 'U', 'S' and 'T' provided in the embodiment of this application;

[0041] Figure 5(d) is a graph showing the changing trends of accuracy and loss function in the classification task provided by the embodiments of this application with the number of iterations. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. The symbol " / " in this document indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0044] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, rather than to describe a specific order of objects.

[0045] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0047] The embodiments of this application are described below with reference to the accompanying drawings.

[0048] In one aspect, this application provides a two-dimensional memory junction device, comprising a first contact electrode, a doped n-type Si layer, and an AgO layer stacked sequentially from bottom to top. x Charge trapping layer and second contact electrode; the charge trapping layer and the doped n-type Si layer combine to form a heterojunction resistive switching region; AgO x 0.4 in the charge trapping layer <x<1.2;AgO x The area of ​​the charge trapping layer should be larger than the area of ​​the second contact electrode for photosensing; this application is based on AgO x The trap ionization and deionization transition in the charge trapping layer, this integral effect transition, will bring about intensity changes in both photovoltaic responsivity and conductivity of the memory junction device. Benefiting from the continuous process of trap ionization, the memory intensity of the memory junction device in both photovoltaic responsivity and conductivity is continuously adjustable, mutually coupled, and non-volatile.

[0049] More preferably, the dopant in the Si layer is a combination of one or more materials that form n-type Si, and the Fermi level of the doped n-type Si layer needs to be lower than its mid-bandgap level. The n-type Si layer is p-doped at 1E15cm. -3 The doping concentration can fluctuate within two orders of magnitude. The Fermi level position and the final band structure performance of the device formed by this doping concentration are good, taking into account the transition performance in both dimensions.

[0050] More preferably, the first contact electrode can be made of Al, Ti, Al silicide, or Ti silicide. When the first contact electrode is Al or Ti, annealing after growth forms a metal silicide, resulting in optimal ohmic conductivity. The second contact electrode can be made of Au or Pt, which have high work functions and are inert, making them suitable for use with p-AgO. x An ohmic contact is formed.

[0051] More preferably, the thickness of the first contact electrode is 3nm-200nm; the thickness of the doped n-type Si layer is 30nm-500um, and the AgO layer... x The charge trapping layer has a thickness of 10nm-100nm, and the second contact electrode has a thickness of 3nm-200nm.

[0052] Secondly, based on the aforementioned two-dimensional memory junction device, this application provides a corresponding fabrication method, including the following steps:

[0053] Step 1: Take any smooth substrate and prepare the first contact electrode on the substrate surface;

[0054] Step 2: Grow an intrinsic Si layer on the first contact electrode using sputtering, physical vapor deposition, or chemical vapor deposition. Then, prepare a doped Si layer using thermal diffusion doping or ion implantation. Proceed to Step 3.

[0055] Steps one and two can also be done using the following methods:

[0056] Step 1: Prepare a doped n-type Si layer by using melt doping during the Czochralski or zone melting method of single-crystal Si growth; or grow an intrinsic Si layer using either the Czochralski or zone melting method, and then prepare a doped n-type Si layer by thermal diffusion doping or ion implantation.

[0057] Step 2: Fabricate the first contact electrode on the back side of the doped n-type Si layer using at least one of sputtering, physical vapor deposition, or chemical vapor deposition.

[0058] Step 3: Fabricate a charge trapping mask layer on the doped Si layer using image visualization;

[0059] Step 4: Prepare a charge trapping layer on the mask layer and remove the mask layer;

[0060] Step 5: Fabricate a patterned mask layer for the second contact electrode on the charge trapping layer;

[0061] Step 6: Fabricate the second contact electrode on the mask layer and remove the mask layer to obtain the device.

[0062] More preferably, the fabrication process of the second contact electrode, the charge trapping layer, and the first contact electrode is one of sputtering, physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition, or electrochemical methods.

[0063] Thirdly, this application provides a method for obtaining the transformation performance of a two-dimensional memory junction device, specifically including the following steps:

[0064] A negative voltage is applied to the second contact electrode of the two-dimensional memory junction device:

[0065] The traps in the charge trapping layer are ionized, the thermal equilibrium Fermi level decreases, the hole concentration increases, and the space charge region is enhanced; in the electrical dimension, the device resistance state is read in the dark with a forward voltage less than or equal to 0.4V, and the device resistance state decreases; in the photovoltaic response dimension, the short-circuit current of the device is read in the light environment with a short-circuit state of 0V, and the photovoltaic responsivity of the device increases.

[0066] After applying a positive voltage to the second contact electrode of the two-dimensional memory junction device:

[0067] Traps in the charge-trapping layer undergo deionization, the thermal equilibrium Fermi level rises, the hole concentration decreases, and the space charge region weakens; in the electrical dimension, when AgO... x When the charge trapping layer thickness is 23nm, the device resistance state increases when a forward voltage of less than or equal to 0.4V is used to read the device resistance state in the dark. It should be noted that as the AgOx charge trapping layer thickness increases, the forward voltage amplitude used to read the resistance state of the dual-dimensional memory junction device increases. In the photovoltaic dimension, the short-circuit current of the device is read in the illumination environment with a short-circuit state of 0V, and the photovoltaic responsivity of the device decreases.

[0068] This application provides a method for applying a two-dimensional memory junction device, specifically including the following steps:

[0069] The first and second contact electrodes of the device are used as word lines and bit lines, respectively, and then cross-array integration is performed.

[0070] When the array operates in the photovoltaic dimension, all pixels of the input light image are mapped onto the array in matrix form, with each pixel corresponding to a device, completing the Hadamard product of the light-light responsivity matrix and outputting a current vector;

[0071] When the array operates in the electrical dimension, the input voltage information is input to the array in vector form. Each device on the array constitutes an element in a matrix, and matrix-vector multiplication is performed by Kirchhoff's current law and Ohm's law.

[0072] By combining the two dimensions of the cross array, the voltage vector output from the Hadamard product of the photovoltaic dimension array is input into the electrical dimension array to complete the matrix-vector multiplication. This allows for the ultra-compact construction of a hardware system for a deep neural network from the optical dimension to the electrical dimension, enabling rapid image classification tasks.

[0073] Based on the two-dimensional memory junction device provided above, this application provides a corresponding fabrication method, which specifically includes the following steps:

[0074] Step 1: Select a substrate with a crystal orientation of

[100] and a thickness of 500µm. Dope the melt with phosphorus (P) during the single-crystal Czochralski growth process to obtain a silicon wafer with a resistivity of 5 ohm-cm, which serves as the doped n-type Si layer. Cut it into 1cm pieces. A 1cm sample was soaked in acetone and cleaned with ultrasound for 10 minutes. Then it was soaked in anhydrous ethanol and cleaned with ultrasound for 10 minutes. The ultrasound power was 10W. Finally, it was cleaned with deionized water and dried with a nitrogen gun.

[0075] Step 2: Take the cleaned sample and grow a first contact electrode Ti layer of about 100nm on its back side using magnetron sputtering. The sputtering power is 200W, the Ar atmosphere is 0.5Pa, and the sputtering time is 1000.

[0076] Step 3: Anneal the substrate at 500℃ for 30s to form a Ti-Si alloy, which produces good ohmic conductivity;

[0077] Step 4: A square photolithographic pattern with a size of 125μm×125μm is prepared on the upper surface of the substrate using photolithography. The photolithography process consists of the following steps: spin coating, pre-baking, pre-exposure, post-baking, post-exposure, and development.

[0078] Step 5: Prepare AgO on the sample processed in Step 4 using magnetron sputtering. x For the charge trapping layer, an Ag target is selected, and sputtering is performed using DC. The thickness of the AgO layer is adjusted by controlling the sputtering time during the sputtering process. x Charge trapping layer; in this embodiment, AgO is grown using O2:Ar=20:5. x AgO x The layer thickness is 12nm;

[0079] Step 6: Immerse the thin film sample prepared in step 5 in acetone for 30-50 minutes, then wash with anhydrous ethanol and deionized water to remove the photoresist, and finally dry the sample with nitrogen.

[0080] Step 7: A square photolithographic pattern is prepared on the charge trapping layer by photolithography, and the size of the second contact electrode is 100μm×100μm; wherein the photolithography process consists of the following steps in sequence: spin coating, pre-baking, pre-exposure, post-baking, post-exposure and development.

[0081] Step 8: On the sample processed in step 7, a 100 nm Pt layer is grown by magnetron sputtering with a sputtering power of 100 W, an Ar atmosphere of 0.5 Pa, and a sputtering time of 1000 s to obtain the second contact electrode.

[0082] Step 9: Immerse the thin film sample prepared in step 8 in acetone for 30-50 minutes, then wash with anhydrous ethanol and deionized water to remove the photoresist, and finally dry the sample with nitrogen.

[0083] After completing the above steps, Pt / n-Si / p-AgO was prepared. x / Pt memristor unit, device structure as follows Figure 1 As shown.

[0084] Based on the aforementioned two-dimensional memory junction device, this application provides corresponding electrical characteristic tests, as follows:

[0085] In the embodiments of this application, a semiconductor device analyzer is used to perform DC I / V scanning and pulse switching characteristic testing on the dual-dimensional memory junction device, and a Soleb M530F3 light source is used to apply illumination.

[0086] As shown in Figures 2(a) and 2(b), a voltage was applied to the Pt electrode prepared in the embodiments of this application, and the voltage was measured in both dark and illuminated environments (530 nm illumination, 3.1 mW / cm²). 2 Electrical scanning tests were conducted under various conditions, achieving multiple conductance states (Figure 2(a)) and photovoltaic response states (Figure 2(b)). In the dark environment, during continuous negative voltage scanning (0V to -1.5V and back to 0V), the device current value continuously increased, exhibiting the characteristic of continuous set (SET); while during continuous positive voltage scanning (0V to +5V and back to 0V), the device current value continuously decreased, exhibiting the characteristic of continuous reset (RESET). During the scan under illumination, the short-circuit current biased at 0V was observed. It can be seen that during continuous negative voltage scanning (0V to -1.5V and back to 0V), the short-circuit current continuously increased, exhibiting the characteristic of continuous set (SET) of photoresponsivity; while during continuous positive voltage scanning (0V to +1.5V and back to 0V), the short-circuit current continuously decreased, exhibiting the characteristic of continuous reset (RESET) of photoresponsivity.

[0087] As shown in Figures 3(a) and 3(b), 40 cycles of long-duration (LTP) and long-duration (LTD) pulses were applied to the Pt electrode of the device prepared in the embodiments of this application. Each cycle contained 50 LTP pulses and 50 LTD pulses, resulting in a total of 4000 pulses. The amplitude of the LTP pulse was -1V and the pulse width was 50ms; the amplitude of the LTD pulse was +1V and the pulse width was 50ms. After each pulse, pulses were applied at a wavelength of 530nm and a pulse width of 0.489mW / cm². 2Photoresponse current in the photovoltaic dimension was read and photoresponsivity was calculated in short-circuit mode under illumination with high power (Fig. 3(a)), and current in the electrical dimension was read and conductance was calculated in dark environment using an electrical pulse with amplitude of 0.4V and pulse width of 20ms (Fig. 3(b)).

[0088] As shown in Figure 4, the conductivity and photoresponsivity of the electrical and photovoltaic components were tested for a long duration of 1000 s. The illumination conditions were a wavelength of 530 nm and a wavelength of 0.15 mW / cm². 2 Optical power; it can be seen that 10 distinguishable photoresponse states and 12 distinguishable conductance states are maintained stably for 1000s, demonstrating the non-volatile characteristics of the device.

[0089] Based on the dual-dimensional memory junction device provided above, this embodiment of the application uses the first contact electrode and the second contact electrode on the dual-dimensional memory junction device as word lines and bit lines, respectively, and performs cross-array integration; Figure 5(a) shows the circuit connection architecture of the two cross-arrays, wherein the resistance value of the conductance dimension array can be continuously adjusted to convert the voltage signal into a current signal; the embodiment shown in Figure 5(a) is an input image matrix. P 3×3 With photovoltaic dimensional array R 3×3 The Hadamard product is performed, with each image pixel corresponding to a two-dimensional memory junction device in a photovoltaic dimension array, resulting in the output of three current quantities. These three output current quantities are converted into voltage signals by voltage division under fixed resistors and input to the subsequent conductance dimension array. G 3×4 In the circuit, each device on the conductivity dimension array constitutes an element on a matrix, and matrix-vector multiplication can be performed using Kirchhoff's current law and Ohm's law, ultimately producing four outputs to complete the four-class classification task; Figure 5(b) is the network architecture calculation diagram corresponding to the circuit architecture; This embodiment uses online learning, that is, the weights of the two dimensions are updated in situ through the backpropagation algorithm; It should be noted that the network size in the system can be further expanded to process more complex information images.

[0090] Figures 5(c) and 5(d) specifically illustrate the classification task for the four letters 'H', 'U', 'S', and 'T'; where 'X' represents the intensity of random noise. It can be seen that as the random noise increases, the network's recognition accuracy remains stable, indicating that the system has good robustness.

[0091] In summary, this application has the following advantages compared with the prior art:

[0092] This application provides a two-dimensional memory junction device, comprising a first contact electrode, a doped n-type Si layer, and AgO stacked sequentially from bottom to top.x Charge trapping layer and second contact electrode; the charge trapping layer and the doped n-type Si layer combine to form a heterojunction resistive switching region; AgO x In the charge trapping layer, 0.4 < x < 1.2; the area of the charge trapping layer should be larger than that of the second contact electrode for light sensing; this application can store information in two different dimensions of photovoltaic and conductance, different from existing devices that can only achieve single-dimensional memory functions.

[0093] This application provides a two-dimensional memory junction device. Based on the self-rectifying characteristic of the device as a PN junction itself, the integration of the cross array of this device does not require an additional gating device and has at least two ports in theory, which is beneficial for large-scale integration.

[0094] This application provides an application of a two-dimensional memory junction device. Using the two dimensions of the device, a photovoltaic dimension array and a conductance dimension array are constructed. The photovoltaic dimension array performs the Hadamard product of the optical matrix - electrical matrix and outputs the electrical signal in vector form, and then the vector is input into the conductance dimension matrix to complete the matrix-vector multiplication, realizing the classification task of image information. A compact and efficient machine vision system can be built with two-dimensional arrays constructed by only one type of device. <0000​​​​​​​In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the components can rotate relative to each other after connection. "Sliding connection" refers to a connection where the components can slide relative to each other after connection. The directional terms mentioned in the embodiments of this application, such as "top," "bottom," "inner," "outer," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0098] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A two-dimensional memory junction device, characterized in that, Includes a first contact electrode, a doped n-type Si layer, and AgO stacked sequentially from bottom to top. x Charge trapping layer and second contact electrode; wherein, 0.4 <x<1.2; The Fermi level of a doped n-type Si layer is lower than its midband level; AgO x The charge trapping layer and the doped n-type Si layer combine to form a heterojunction resistive switching region; AgO x The area of ​​the charge trapping layer is larger than the area of ​​the second contact electrode; The first and second contact electrodes are used to provide ohmic contact and voltage drive; Heterojunction resistive switching region for AgO-based x The trapping ionization and deionization transitions in the charge trapping layer, driven by voltage, achieve continuous tunability and mutual coupling of memory intensity in both photovoltaic responsivity and conductivity dimensions, and are non-volatile.

2. The dual-dimensional memory junction device according to claim 1, characterized in that, The first contact electrode is Al, Ti, Al silicide, or Ti silicide; the second contact electrode is Au or Pt.

3. The dual-dimensional memory junction device according to claim 1, characterized in that, The dopant in the doped n-type Si layer is a combination of one or more materials. The doped n-type Si layer is p-doped, and the doping concentration is on the order of 1E¹⁵ cm⁻¹. -3 .

4. The dual-dimensional memory junction device according to claim 1 or 2, characterized in that, The thickness of the first contact electrode is 3nm-200nm; the thickness of the doped n-type Si layer is 30nm-500µm, AgO x The charge trapping layer has a thickness of 10nm-100nm, and the second contact electrode has a thickness of 3nm-200nm.

5. A method for obtaining the performance of a dual-dimensional memory junction device according to any one of claims 1 to 4, characterized in that, Specifically: After applying a negative voltage to the second contact electrode of the dual-dimensional memory junction device, the resistance state of the dual-dimensional memory junction device is read under a light-free environment using a positive voltage, and the resistance state of the dual-dimensional memory junction device decreases. At the same time, based on the 0V short-circuit state, the short-circuit current of the dual-dimensional memory junction device is read under a light-free environment, and the photovoltaic responsivity of the dual-dimensional memory junction device increases. After applying a forward voltage to the second contact electrode of the dual-dimensional memory junction device, the resistance state of the dual-dimensional memory junction device is read under no-light conditions using the forward voltage, and the resistance state of the dual-dimensional memory junction device is obtained to rise; at the same time, based on the 0V short-circuit state, the short-circuit current of the dual-dimensional memory junction device is read under light conditions, and the photovoltaic responsivity of the dual-dimensional memory junction device is obtained to decrease.

6. The method for obtaining the performance of a two-dimensional memory junction device according to claim 5, characterized in that, As the thickness of the AgOx charge trapping layer increases, the forward voltage amplitude required to read the resistive state of a two-dimensional memory junction device increases.

7. A neural network application method based on the dual-dimensional memory junction device according to any one of claims 1 to 4, characterized in that, Includes the following steps: The first and second contact electrodes of the dual-dimensional memory junction device are used as word lines and bit lines, respectively, and cross-array integration is performed. One of the cross arrays is used as the photovoltaic response dimension array. All pixels of the input light image are mapped in array form into the photovoltaic response dimension array. The light image and the photovoltaic responsivity matrix corresponding to the photovoltaic response dimension array are subjected to Hadamard product operation to output the current vector. Another cross array is used as the conductance dimension array. The output current vector is converted into a voltage vector and input into the conductance dimension array. The matrix-vector multiplication operation is completed by Kirchhoff's current law and Ohm's law, and the classification task of the output light image is completed.

8. A method for fabricating a dual-dimensional memory junction device based on any one of claims 1 to 4, characterized in that, Includes the following steps: Step 1: Prepare a doped n-type Si layer by using melt doping during the Czochralski or zone melting method of single-crystal Si growth; or grow an intrinsic Si layer using either the Czochralski or zone melting method, and then prepare a doped n-type Si layer by thermal diffusion doping or ion implantation. Step 2: Fabricate the first contact electrode on the back side of the doped n-type Si layer using at least one of sputtering, physical vapor deposition, or chemical vapor deposition. Step 3: Image-based fabrication of AgO on an n-type doped Si layer x A mask layer for charge trapping was prepared, and AgO was fabricated. x Charge trapping layer, mask layer removal; Step 4: In AgO x A patterned mask layer for the second contact electrode is fabricated above the charge trapping layer, and the second contact electrode is fabricated. The mask layer is then removed to complete the fabrication of the two-dimensional memory junction device.

9. The preparation method according to claim 8, characterized in that, Second contact electrode, AgO x The charge trapping layer and the first contact electrode are prepared by one of the following methods: sputtering, physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition, or electrochemical method.

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