Controllable doping p-type two-dimensional transistor based on vacancy and preparation method thereof

Abstract

The invention discloses a vacancy-based controllable doping p-type two-dimensional transistor and a preparation method thereof, and mainly solves the problem that accurate controllable doping is difficult to realize in the prior art. According to the scheme, the device comprises an insulating substrate, a two-dimensional material channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, wherein the source electrode and the drain electrode are located at the two ends of the two-dimensional material channel layer; the gate dielectric layer is located on the two-dimensional material channel layer and the source and drain electrodes; the method comprises the following steps: depositing a thick mask layer, thinning the mask layer part through photoetching and etching to form a patterned thin layer, bombarding a two-dimensional material and a two-dimensional material under a mask plate thin layer through treated mask layer ions to form a surface vacancy, removing a mask plate, exposing the two-dimensional material in an oxygen flow, and oxidizing to form surface charge transfer doping. According to the invention, under the condition that the two-dimensional material is not damaged and the performance is not influenced, partitioned controllable doping is realized, and the conductivity of the two-dimensional transistor is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and further relates to two-dimensional transistor technology, specifically a vacancy-based controllably doped p-type two-dimensional transistor and a preparation method thereof, which can be used to prepare high-performance two-dimensional field effect transistors. Background Art

[0002] With the development of semiconductor device manufacturing technology, traditional silicon-based transistors have encountered a series of problems when shrinking to the nanoscale, such as short channel effect, increased power consumption, and difficult thermal management. These problems restrict the further miniaturization and performance improvement of transistors. Two-dimensional field-effect transistors use two-dimensional semiconductor materials as channel materials. By utilizing the atomic-level thickness of two-dimensional materials, the device size can be further reduced without losing switching performance, thus breaking through the miniaturization limit of silicon-based transistors. Two-dimensional semiconductor materials, especially transition metal dichalcogenides, such as molybdenum disulfide and tungsten diselenide, have many superior properties as channel materials for field-effect transistors. Their atomic-level thickness and excellent electrical properties can significantly reduce the leakage current and static power consumption in the channel, making them very suitable for low-power devices. At the same time, two-dimensional materials also have good mobility, which can achieve fast switching and efficient signal transmission at low voltage, and are suitable for high-speed circuit applications. In addition, two-dimensional semiconductor materials have excellent mechanical flexibility and transparency, and can be widely used in flexible electronics, wearable devices and other fields, providing more possibilities for the diversity of future electronic products. These characteristics of two-dimensional semiconductor materials make them have broad application prospects in the new generation of electronic devices, especially high-efficiency and low-power nanoelectronic devices.

[0003] As Moore's Law gradually approaches its limit, the outside world is in urgent need of new semiconductor materials with comprehensive and excellent performance. While two-dimensional materials meet many performance requirements for new semiconductor materials, they still have many problems that need to be solved.

[0004] Limited by the characteristics of the two-dimensional materials themselves and the Fermi level pinning effect, the current research on p-type two-dimensional transistors is relatively lagging behind. Existing two-dimensional semiconductor materials, such as transition metal dichalcogenides, mostly exhibit intrinsic n-type conductivity, and two-dimensional materials with excellent p-type properties are relatively scarce. At the same time, the Fermi level pinning effect makes it difficult to control the Schottky barrier when metals contact two-dimensional materials, which also greatly limits the realization of p-type two-dimensional transistors. The ideal CMOS-compatible mass preparation method for p-type two-dimensional transistors is to p-type doping of two-dimensional materials.

[0005] At present, the common p-type doping methods for two-dimensional transistors in academia are mainly to add dopants for substitutional doping during the growth of two-dimensional materials, and to perform surface charge transfer doping on the surface of the grown two-dimensional materials. Substitutional doping can directly increase the carrier concentration and reduce the channel resistance, but this doping method will introduce uncontrollable lattice disorder and seriously reduce the carrier mobility. Unlike substitutional doping, the dopants of surface charge transfer doping are located outside the carrier path and will not introduce any lattice disorder, so they are usually able to retain higher electrical mobility in 2D materials. In surface charge transfer doping, a common strategy is to oxidize the surface of TMDs such as WSe2 with oxygen plasma or UV / ozone to form a self-limiting oxide layer on top of the undamaged layer, such as WO x and WO x Se y These surface oxides produce strong hole doping in the underlying channel material. However, this method of doping the oxidized surface is very uncontrollable, and it is difficult to control the doping concentration and the electrical properties after doping.

[0006] In addition, both the above-mentioned substitutional doping and surface charge transfer doping are difficult to achieve precise partitioned doping. The p-type two-dimensional transistors prepared by uniform doping achieved by these two doping methods have serious gate control problems, making it difficult to turn off the transistor. In silicon-based field-effect transistors, the doping concentration in different regions of the transistor channel can be regulated by partitioned doping to achieve precise control of the electric field distribution, thereby significantly improving carrier mobility, reducing source-drain resistance, and improving short channel effects. However, compared to silicon-based devices, two-dimensional materials have an atomically thin layer structure. The ion implantation partitioned doping method commonly used in silicon-based devices causes high-energy particles to cause serious lattice damage to the two-dimensional material during the process, destroying its inherent structural integrity and electrical properties, resulting in serious degradation of the performance of the two-dimensional transistor. Therefore, conventional ion implantation partitioned doping technology is also difficult to apply to two-dimensional materials.

[0007] At present, the research on two-dimensional transistors still lacks a precise and controllable doping technology that can effectively improve their conductivity while maintaining their gate control performance. This technical bottleneck limits the large-scale preparation of high-performance two-dimensional transistors, especially high-performance p-type devices, and it is difficult to meet the current growing demand for high-performance two-dimensional transistors. Summary of the invention

[0008] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a controllably doped p-type two-dimensional transistor based on vacancies and a method for preparing the same, in order to solve the problem that the prior art is difficult to achieve high-performance p-type two-dimensional transistors. First, a thick mask layer is deposited, and then the mask layer is partially thinned by photolithography and etching to form a patterned partial thin layer. Ions are bombarded on the two-dimensional material through the treated mask layer, and the two-dimensional material under the mask thin layer forms surface vacancies. The mask is then removed, and the two-dimensional material is exposed to an oxygen flow for oxidation to form surface charge transfer doping. The present invention can achieve partitioned controllable doping without damaging the two-dimensional material and affecting its performance, thereby effectively improving the conductivity of the two-dimensional transistor.

[0009] The technical solution to achieve the purpose of the present invention is as follows:

[0010] A controllably doped p-type two-dimensional transistor based on vacancies, comprising an insulating substrate 1, a two-dimensional material channel layer 2, a source electrode 3 and a drain electrode 4 located on both ends of the two-dimensional material channel layer, a gate dielectric layer 5 located on the two-dimensional material channel layer and the source electrode and the drain electrode, and a gate electrode 6 located on the gate dielectric;

[0011] The above-mentioned two-dimensional material channel layer 2 adopts one of the two-dimensional semiconductor materials, which includes at least tungsten diselenide, molybdenum diselenide, and molybdenum disulfide; and is subjected to controllable surface charge transfer doping, that is, partitioned vacancies are manufactured on its surface and then naturally oxidized.

[0012] Furthermore, the two-dimensional material channel layer 2 is a multi-layer structure.

[0013] Furthermore, the insulating substrate 1 is made of any insulating material of SiO2 / Si, sapphire, and diamond; the gate dielectric 7 is made of any insulating dielectric layer of aluminum oxide, aluminum nitride, and silicon nitride; the gate electrode 8 is made of Ni / Au, Pd / Au or Pt / Au metal; the source electrode 5 and the drain electrode 6 are both made of Pd / Au or Pt / Au or a metal that is compatible with the electrical properties of the two-dimensional material.

[0014] A method for preparing a controllably doped p-type two-dimensional transistor based on vacancies comprises the following steps:

[0015] §1: Select a target substrate, use acetone, isopropanol, and deionized water to ultrasonically clean its surface, and then blow dry it with nitrogen to obtain an insulating substrate 1 with a clean surface;

[0016] §2: Using chemical vapor deposition to grow a thin film of the two-dimensional material to be transferred on the substrate surface;

[0017] §3: Using PMMA-assisted transfer method to transfer the grown two-dimensional material film to the insulating substrate 1;

[0018] §4: The two-dimensional material transferred onto the insulating substrate (1) is subjected to coating, pre-baking, photolithography, and development, and then an isolation region is etched to form an array of the two-dimensional material, thereby obtaining a two-dimensional material channel layer to be doped for the transistor;

[0019] §5: Depositing a silicon dioxide layer on the surface of the two-dimensional material obtained in step §4 by plasma enhanced chemical vapor deposition;

[0020] §6: Evenly coat the surface of the silicon dioxide layer with photoresist, and after pre-baking, photolithography, and etching, etch the silicon dioxide layer above the two-dimensional material area to be doped into a thin silicon dioxide layer;

[0021] §7: High-energy hydrogen ions are used to bombard the surface of the two-dimensional material through a silicon dioxide mask layer to create precisely partitioned two-dimensional material surface vacancies, and a controllable number of vacancies is obtained according to different powers and processing times;

[0022] §8: Remove the silicon dioxide mask layer by wet etching;

[0023] §9: The two-dimensional material with surface vacancies is exposed to an oxygen flow for oxidation, thereby achieving precisely controllable surface charge transfer doping and obtaining the two-dimensional material channel layer 2 of the transistor;

[0024] §10: The surface of the two-dimensional material channel layer 2 obtained in step §9 is deposited with source and drain electrode metals by photolithography and electron beam evaporation. After the metal is deposited, a lift-off process is performed to form a source electrode 3 and a drain electrode 4;

[0025] §11: A gate dielectric layer 5 is obtained by magnetron sputtering aluminum oxide, aluminum nitride or silicon nitride on the surfaces of the two-dimensional material channel layer 2, the source electrode 3 and the drain electrode 4;

[0026] §12: A gate electrode 6 is prepared on the surface of the gate dielectric layer 5 by photolithography, electron beam evaporation, deposition of gate metal and lift-off process;

[0027] §13: The area above the source electrode and the drain electrode is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes to complete the device fabrication.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] First, the present invention adopts a surface charge transfer doping method for two-dimensional materials. Compared with traditional substitutional doping, it avoids the introduction of lattice disorder that leads to a decrease in carrier mobility; and the surface charge transfer doping method used in the present invention is achieved by first creating vacancies on the surface of the two-dimensional material and then naturally oxidizing it. This method is a low-temperature and low-energy doping method, which avoids excessive damage to the surface of the two-dimensional material by conventional high-temperature and high-energy doping methods. Compared with conventional low-temperature and low-energy oxidation methods, vacancies are used as binding sites for doping atoms, thereby improving the doping concentration and doping efficiency; at the same time, compared with direct high-power oxygen plasma treatment or UV / ozone oxidation and other two-dimensional material surface oxidation methods, the number of vacancies can be controlled by different powers and processing times during vacancy creation, thereby controlling the doping concentration after natural oxidation to achieve controllable doping of the two-dimensional material.

[0030] Second, the present invention bombards the surface of the two-dimensional material with high-energy hydrogen ions through a silicon dioxide mask layer that has been thinned by patterned etching. In this process, surface vacancies are precisely created on the surface of the two-dimensional material below the thin silicon dioxide layer that has been etched thin, and the thick silicon dioxide layer that has not been etched serves as a protective layer to prevent the two-dimensional material underneath from being bombarded by hydrogen ions. Subsequently, the surface vacancies of the two-dimensional material created by the partitions are subjected to oxidation doping treatment, ultimately achieving precise partitioned doping of the two-dimensional material and improving the electrical performance of the transistor.

[0031] Third, in the present invention, a thin layer of silicon dioxide is used as a mask layer, and high-energy hydrogen ions are used to non-contactly create vacancies on the surface of the two-dimensional material. Compared with the vacancy creation method of directly using high-energy ions to bombard the surface of the two-dimensional material, this method avoids excessive damage to the two-dimensional material, limits the vacancy creation to the surface of the two-dimensional material, and avoids the formation of defects due to lattice disorder inside the two-dimensional material that affects the performance.

[0032] Fourth, grow large-area, uniform two-dimensional material films, and control the number of layers and crystal quality of the two-dimensional material by adjusting parameters such as gas flow, reaction temperature and time, so as to batch prepare two-dimensional material field-effect transistors with different electrical properties.

[0033] Fifth, the present invention uses PMMA wet transfer to achieve the transfer of two-dimensional material thin film layers, which can achieve uniform transfer on a larger area substrate, effectively reduce the mechanical damage to the molybdenum disulfide film during the transfer process, and help obtain a higher quality film. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the device structure of a controllably doped p-type two-dimensional transistor based on vacancies in the present invention;

[0035] Figure 2 This is a schematic diagram of the manufacturing process of the two-dimensional transistor proposed in the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Example 1: Reference Figure 1 The present invention provides a controllably doped p-type two-dimensional transistor based on vacancies, comprising an insulating substrate 1, a two-dimensional material channel layer 2, a source electrode 3 and a drain electrode 4 located on both ends of the two-dimensional material channel layer, a gate dielectric layer 5 located on the two-dimensional material channel layer and the source electrode and the drain electrode, and a gate electrode 6 located on the gate dielectric;

[0038] The above-mentioned two-dimensional material channel layer 2 adopts one of the two-dimensional semiconductor materials, which includes tungsten diselenide, molybdenum diselenide, molybdenum disulfide, etc., and has a multi-layer structure; and it is subjected to controllable surface charge transfer doping, that is, partitioned vacancies are manufactured on its surface and then naturally oxidized.

[0039] The above-mentioned insulating substrate 1 adopts any one of the insulating materials of SiO2 / Si, sapphire, and diamond; the gate dielectric 7 adopts any one of the insulating dielectric layers of aluminum oxide, aluminum nitride, and silicon nitride; the gate electrode 8 adopts Ni / Au, Pd / Au or Pt / Au metal; the source electrode 5 and the drain electrode 6 both adopt Pd / Au or Pt / Au or a metal compatible with the electrical properties of the two-dimensional material.

[0040] Example 2: Reference Figure 2 The present invention provides a method for preparing a controllably doped p-type two-dimensional transistor based on vacancies, comprising the following steps:

[0041] Step §1: Select a target substrate, and ultrasonically clean its surface using acetone, isopropanol, and deionized water, respectively, and then blow dry with nitrogen to obtain an insulating substrate 1 with a clean surface;

[0042] Step §2: Using chemical vapor deposition to grow a two-dimensional material film to be transferred on the substrate surface, the implementation steps include the following:

[0043] 2a) Selecting reaction precursors according to the type of two-dimensional material film to be grown, and placing different types of reaction precursors in the high temperature zone and low temperature zone of the tube furnace respectively according to the reaction requirements;

[0044] 2b) placing a clean substrate for growing a two-dimensional material film in an area about a few centimeters away from the sample in the high temperature zone to facilitate film growth;

[0045] 2c) Setting the working gas, keeping the gas flow constant during the deposition process, raising the temperature at a rate of 15-20°C / min until the set working temperature is reached, and then controlling the reaction time according to the desired thickness of the two-dimensional material film layer to obtain the two-dimensional material film to be transferred.

[0046] Step §3: Using a PMMA-assisted transfer method to transfer the grown two-dimensional material film to the insulating substrate 1, the implementation of which includes the following steps:

[0047] Spin-coat PMMA on the surface of the layer to be transferred and cure it on a hot plate at 90-120°C;

[0048] The sample was placed in a solution required for separating the substrate and immersed for two hours to separate the PMMA-to-be-transferred layer from its substrate;

[0049] The separated floating PMMA-to-be-transferred layer is transferred to the target substrate for curing, and then soaked with acetone to remove PMMA, then cleaned with IPA, and finally blown dry with nitrogen.

[0050] Step §4: The two-dimensional material transferred onto the insulating substrate (1) is subjected to coating, pre-baking, photolithography, and development, and then an isolation region is etched to form an array of the two-dimensional material, thereby obtaining a two-dimensional material channel layer to be doped for the transistor;

[0051] Step §5: Plasma-enhanced chemical vapor deposition of a silicon dioxide layer on the surface of the two-dimensional material obtained in step §4. In this embodiment, the pre-cleaned sample is fixed on a base in a PECVD reaction chamber, Ar gas is introduced to remove residual impurities in the reaction chamber, and the PECVD system is started under set conditions to start SiO2 film deposition; after the deposition is completed, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0052] Step §6: uniformly coating the surface of the silicon dioxide layer with photoresist, and etching the silicon dioxide layer above the two-dimensional material region to be doped into a thin silicon dioxide layer through pre-baking, photolithography, and etching;

[0053] Step §7: Create precisely partitioned two-dimensional material surface vacancies by bombarding the surface of the two-dimensional material with high-energy hydrogen ions through a silicon dioxide mask layer, and obtain a controllable number of vacancies according to different powers and processing times; specifically, place the silicon dioxide mask layer sample that has been thinned by partition etching in a reactive ion etching chamber and expose it to hydrogen plasma, maintain the RF power and hydrogen gas flow rate in the RIE chamber at 100 W and 50 sccm, respectively, and create it by bombarding the surface of the two-dimensional material with high-energy hydrogen ions through the mask layer.

[0054] Step §8: removing the silicon dioxide mask layer by wet etching;

[0055] Step §9: exposing the two-dimensional material with surface vacancies to an oxygen flow for oxidation, thereby achieving precise and controllable surface charge transfer doping, and obtaining a two-dimensional material channel layer 2 of the transistor;

[0056] Step §10: depositing source and drain electrode metals on the surface of the two-dimensional material channel layer 2 obtained in step §9 by photolithography and electron beam evaporation. After the metal is deposited, a lift-off process is performed to form a source electrode 3 and a drain electrode 4;

[0057] Step §11: Aluminum oxide, aluminum nitride or silicon nitride is magnetron sputtered on the surface of the two-dimensional material channel layer 2, the source electrode 3 and the drain electrode 4 to obtain a gate dielectric layer 5. In this step of the present embodiment, the substrate is heated to a set temperature, and a corresponding target material and working gas are used according to the type of the encapsulation protection layer. The magnetron sputtering system is used to control the sputtering time according to the required thickness at the reaction chamber temperature to grow the gate dielectric layer to be etched on the substrate or the two-dimensional material channel layer.

[0058] Step §12: preparing a gate electrode 6 on the surface of the gate dielectric layer 5 by photolithography, electron beam evaporation deposition of gate metal and lift-off process;

[0059] Step §13: Pattern the area above the source electrode and the drain electrode by photolithography, and then etch the gate dielectric layer to expose the source and drain electrodes to complete the device manufacturing.

[0060] Embodiment 3: The overall implementation steps of the transistor preparation method proposed in this embodiment are the same as those in Embodiment 2. Now, a specific example is given in which the substrate is sapphire, the gate dielectric layer is aluminum nitride, the two-dimensional material is molybdenum diselenide, and the source and drain electrode metal is Pt / Au to further describe the preparation process of the present invention in detail:

[0061] Step 1: Pretreatment of transistor substrate 1 .

[0062] Sapphire was selected as the transistor insulating substrate 1, and the substrate 1 was ultrasonically cleaned in acetone solution, isopropanol, and deionized water for 5 minutes each, and then dried with nitrogen.

[0063] Step 2: Chemical vapor deposition of the two-dimensional material to be transferred onto another sapphire substrate.

[0064] 2.1) The sapphire substrate was ultrasonically cleaned with acetone for 20 minutes, the cleaned substrate was rinsed with deionized water for 2 to 3 times, and then immersed in deionized water for ultrasonic cleaning for 15 minutes, and finally the treated substrate was blown dry with nitrogen;

[0065] 2.2) MoO3 is used as the molybdenum source, and high-purity selenium powder is used as the selenium source. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the exit. The cleaned sapphire substrates a and b are placed with the surface facing up in an area about a few centimeters away from the MoO3 powder to facilitate the growth of MoSe2;

[0066] 2.3) setting an argon-hydrogen mixed gas, with the gas flow rates of argon and hydrogen being 100 sccm and 10 sccm respectively, keeping the gas flow constant during the deposition process, turning on the tubular furnace, setting the heating rate to 15°C / min, heating the MoO3 powder area to 800°C, and the temperature of the selenium powder area to 300°C. When the temperature reaches the set value, keeping the constant temperature for about 5 minutes, at which time the selenium vapor reacts with MoO3 on the substrate to generate molybdenum diselenide, and growing the molybdenum diselenide film to be transferred;

[0067] 2.4) After the reaction is completed, turn off the heating and keep the argon gas flowing until the system cools naturally to room temperature to prevent the molybdenum diselenide from being oxidized at high temperature;

[0068] Step 3: Transfer the two-dimensional material grown on the sapphire substrate to the insulating substrate 1.

[0069] 3.1) Evenly drop a small amount of PMMA solution on the surface of the MoSe2 / sapphire substrate, use a spin coating device, spin coat at 4000 rpm for 1 minute, and then dry on a hot plate at 100°C for 10 minutes to solidify the PMMA layer;

[0070] 3.2) Dissolve 55g of KOH solute in 300ml of deionized water, and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then, soak the sample in the prepared KOH solution for two hours to gradually separate the PMMA-MoSe2 layer from the substrate.

[0071] 3.3) Rinse the PMMA-MoSe2 layer in deionized water, use tweezers or other auxiliary tools to gently pick up the PMMA / MoSe2 film floating on the water surface and slowly place it on the target substrate, press gently with a glass rod or scraper to remove the bubbles between the PMMA / MoSe2 film and the substrate to ensure full contact and adhesion, and let it stand for several hours to allow the film to fully adhere to the substrate;

[0072] 3.4) Soak the sample in acetone to remove PMMA, then clean it with IPA, and finally blow dry it with nitrogen.

[0073] Step 4: Array the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0074] The surface of the two-dimensional material transferred onto the substrate 1 is coated with glue, photolithographed, and developed to pattern the area to be etched; the process conditions of gas flow, reaction pressure, and RF power are set to 10 sccm, 30 mTorr, and 50 W respectively, and the etching time is about 3 minutes. Oxygen plasma is used to etch the molybdenum diselenide to obtain an isolation area to array the molybdenum diselenide, forming a two-dimensional material channel layer 2 to be doped for the transistor.

[0075] Step 5: Depositing a silicon dioxide layer on the surface of the two-dimensional material channel layer 2 by plasma enhanced chemical vapor deposition.

[0076] 5.1) Ultrasonic cleaning of the sample with deionized water and isopropanol for 3 minutes each, followed by drying with nitrogen;

[0077] 5.2) Set the process parameters as operating temperature of 200°C, operating pressure of 800mTorr, RF power of 40W, SiH4 gas flow rate of 2sccm, O2 and Ar gas flow rates of 50sccm and 10sccm respectively, and deposition time of about 8 minutes;

[0078] 5.3) Fix the sample on the base in the PECVD reaction chamber, start the PECVD system under the set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0079] 5.4) After the deposition is completed, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0080] Step 6: After photolithography, the silicon dioxide above the area to be doped with the two-dimensional material is etched into a thin layer.

[0081] Photoresist is coated on the surface of the sample, and the area to be etched is exposed and developed; CF4 plasma is used under the process conditions of CF4 gas flow rate of 30sccm, auxiliary gas Ar and O2 gas flow rates of 10sccm and 2sccm respectively, reaction pressure and RF power of 10mTorr and 100W respectively, and etching time of about 3min, to etch the silicon dioxide above the area to be doped with the two-dimensional material into a thin layer of about 10nm.

[0082] Step 7: Create vacancies on the surface of two-dimensional materials.

[0083] A sample covered with a patterned etched silicon dioxide mask layer was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and the flow rate of hydrogen gas in the RIE chamber were maintained at 100 W and 50 sccm, respectively. The hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0084] Step 8: Remove the silicon dioxide mask layer by wet etching.

[0085] Use a 1:6 diluted buffered oxide etching solution, gently immerse the sample in the solution, keep the liquid completely covering the sample surface, let it stand in the solution, or gently stir to promote uniform etching; remove the sample immediately after etching, quickly rinse with a large amount of deionized water to remove residual etching solution components, and finally rinse the sample with IPA and blow dry with nitrogen.

[0086] Step 9: Oxidative doping of vacancies.

[0087] The sample with the silicon dioxide layer removed is exposed to an oxygen flow to perform natural oxidation doping on the surface vacancies of the manufactured two-dimensional material, thereby obtaining a two-dimensional material channel layer 2 with partitioned doping of the transistor.

[0088] Step 10: Make source and drain electrodes 3 and 4.

[0089] 10.1) Coating photoresist on the sample surface, exposing, and developing to form source and drain regions of the metal to be deposited;

[0090] 10.2) Mount the sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0091] 10.3) Select Pt as the target and set the evaporation rate to To ensure the uniformity and adhesion of the platinum layer, the vacuum pump was turned on to evacuate to a high vacuum and then the electron beam current was gradually increased to start evaporating the Pt layer. After evaporation to a thickness of 5 nm in the source and drain contact area, the electron beam was turned off to stop evaporation, the target material was replaced with Au and the evaporation rate was set to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0092] 10.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure, and then the sample is taken out and placed in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0093] Step 11: Aluminum nitride is formed as the gate dielectric layer 5 on the surface of the two-dimensional material channel layer and the source and drain electrodes by magnetron sputtering.

[0094] 11.1) In a magnetron sputtering system, aluminum nitride is used as a target material, argon and nitrogen are set as working gases, the gas flow rates are 20 sccm and 5 sccm respectively, and the working gas pressure, sputtering power, and sputtering temperature are 3 mTorr, 100 W, and 300° C. respectively. An aluminum nitride film is sputtered on a substrate 1 as a bottom layer 2 of a packaging protective layer;

[0095] 11.2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment and start the vacuum pump until the chamber reaches 10 - 6 After the vacuum degree reaches below 100 Torr, nitrogen and argon are introduced, and the flow rate is adjusted to the target working pressure and sputtering is started after it is kept stable. The sputtering time is about 10 minutes, and a 50nm thick aluminum nitride film is deposited on the surface of the two-dimensional material channel layer and the source and drain electrodes as the gate dielectric layer 5;

[0096] 11.3) After the sample is cooled to room temperature in the vacuum chamber, nitrogen is introduced to return the chamber to atmospheric pressure, the chamber is opened and the sample is taken out.

[0097] Step 12: Making the gate electrode 6.

[0098] 12.1) Coating photoresist on the surface of the gate dielectric layer 5, exposing and developing to form a gate region where metal is to be deposited;

[0099] 12.2) Mount the sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0100] 12.3) Select Pd as the target and set the evaporation rate to To ensure the uniformity and adhesion of the Pd layer, turn on the vacuum pump to evacuate to a high vacuum and gradually increase the electron beam current to start evaporating the Pd layer. After evaporating to a thickness of 5nm in the source and drain contact area, turn off the electron beam to stop evaporation, replace the target material with Au and set the evaporation rate to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0101] 12.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure, and then the sample is taken out and placed in acetone for stripping, and the excess metal layer is removed to form a gate electrode 6.

[0102] Step 13: Etch the gate dielectric layer to expose the source and drain electrodes

[0103] 13.1) Coating photoresist on the sample surface, exposing and developing the area to be etched;

[0104] 13.2) Using CF4 plasma, under the process conditions of CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min, aluminum nitride is etched to expose source and drain electrodes after etching;

[0105] 13.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure that there is no residue on the surface.

[0106] Embodiment 4: The overall implementation steps of the transistor preparation method proposed in this embodiment are the same as those in Embodiment 2. Now, a specific example in which the substrate is made of diamond, the gate dielectric layer is made of aluminum nitride, the two-dimensional material is tungsten diselenide, and the source and drain electrode metal is Pd / Au is given to further describe the preparation process of the present invention in detail:

[0107] Step a: Pretreatment of transistor substrate 1 .

[0108] Diamond was selected as the insulating substrate 1 of the transistor. The substrate 1 was ultrasonically cleaned in acetone solution, isopropanol and deionized water for 5 minutes each, and then dried with nitrogen.

[0109] Step b: chemically vapor depositing the two-dimensional material to be transferred on a sapphire substrate.

[0110] b.1) The sapphire substrate was ultrasonically cleaned with acetone for 20 minutes, the cleaned substrate was rinsed with deionized water for 2 to 3 times, and then immersed in deionized water for ultrasonic cleaning for 15 minutes, and finally the treated substrate was blown dry with nitrogen;

[0111] b.2) WO3 is used as the molybdenum source, and high-purity selenium powder is used as the selenium source. The WO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the exit. The cleaned sapphire substrates a and b are placed with the surface facing up in an area about a few centimeters away from the WO3 powder to facilitate the growth of WSe2;

[0112] b.3) Set an argon-hydrogen mixed gas, with the gas flow rates of argon and hydrogen being 100 sccm and 10 sccm respectively. Keep the gas flow constant during the deposition process, start the tube furnace, set the heating rate to 15°C / min, heat the WO3 powder area to 800°C, and the temperature of the selenium powder area to 300°C. When the temperature reaches the set value, keep the constant temperature for about 5 minutes. At this time, selenium vapor reacts with MoO3 on the substrate to generate tungsten diselenide, and grows the tungsten diselenide film to be transferred;

[0113] b.4) After the reaction is completed, turn off the heating and keep the argon gas flowing until the system cools naturally to room temperature to prevent tungsten diselenide from being oxidized at high temperature;

[0114] Step c: transferring the two-dimensional material grown on the sapphire substrate to the insulating substrate 1 .

[0115] c.1) evenly drop a small amount of PMMA solution on the surface of WSe2 / sapphire substrate, use spin coating equipment, spin coating at 4000 rpm for 1 minute, and then dry on a hot plate at 100°C for 10 minutes to solidify the PMMA layer;

[0116] c.2) Dissolve 55g of KOH solute in 300ml of deionized water, and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then, soak the sample in the prepared KOH solution for two hours to gradually separate the PMMA-WSe2 layer from the substrate;

[0117] c.3) Rinse the PMMA-WSe2 layer in deionized water, use tweezers or other auxiliary tools to gently pick up the PMMA / WSe2 film floating on the water surface and slowly place it on the target substrate, press gently with a glass rod or scraper to remove the bubbles between the PMMA / WSe2 film and the substrate to ensure full contact and adhesion, and let it stand for several hours to allow the film to fully adhere to the substrate;

[0118] c.4) Soak the sample in acetone to remove PMMA, then clean it with IPA, and finally blow dry it with nitrogen.

[0119] Step d: Arraying the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0120] The surface of the two-dimensional material transferred onto the substrate 1 is coated with glue, photolithographed, and developed to pattern the area to be etched; the process conditions of gas flow, reaction pressure, and RF power are set to 10 sccm, 30 mTorr, and 50 W respectively, and the etching time is about 3 minutes. The tungsten diselenide is etched using oxygen plasma to obtain an isolation area to array the tungsten diselenide, forming a two-dimensional material channel layer 2 to be doped for the transistor.

[0121] Step e: depositing a silicon dioxide layer on the surface of the two-dimensional material channel layer 2 by plasma enhanced chemical vapor deposition.

[0122] e.1) ultrasonically clean the sample with deionized water and isopropanol for 3 minutes each, and then blow dry with nitrogen;

[0123] e.2) setting the process parameters to an operating temperature of 200°C, an operating pressure of 800mTorr, an RF power of 40W, a SiH4 gas flow rate of 2sccm, an O2 gas flow rate of 50sccm and an Ar gas flow rate of 10sccm, and a deposition time of about 8 minutes;

[0124] e.3) Fix the sample on the base in the PECVD reaction chamber, start the PECVD system under set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0125] e.4) After the deposition is completed, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0126] Step f: After photolithography, the silicon dioxide above the area to be doped with the two-dimensional material is etched into a thin layer.

[0127] Photoresist is coated on the surface of the sample, and the area to be etched is exposed and developed; CF4 plasma is used under the process conditions of CF4 gas flow rate of 30sccm, auxiliary gas Ar and O2 gas flow rates of 10sccm and 2sccm respectively, reaction pressure and RF power of 10mTorr and 100W respectively, and etching time of about 3min, to etch the silicon dioxide above the area to be doped with the two-dimensional material into a thin layer of about 10nm.

[0128] Step g: Create vacancies on the surface of two-dimensional materials.

[0129] A sample covered with a patterned etched silicon dioxide mask layer was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and the flow rate of hydrogen gas in the RIE chamber were maintained at 100 W and 50 sccm, respectively. The hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0130] Step h: Wet etching to remove the silicon dioxide mask layer

[0131] Use a 1:6 diluted buffered oxide etching solution, gently immerse the sample in the solution, keep the liquid completely covering the sample surface, let it stand in the solution, or gently stir to promote uniform etching; remove the sample immediately after etching, quickly rinse with a large amount of deionized water to remove residual etching solution components, and finally rinse the sample with IPA and blow dry with nitrogen.

[0132] Step i: Oxidative doping of vacancies.

[0133] The sample with the silicon dioxide layer removed is exposed to an oxygen flow to perform natural oxidation doping on the surface vacancies of the manufactured two-dimensional material, thereby obtaining a two-dimensional material channel layer 2 with partitioned doping of the transistor.

[0134] Step j: Make source and drain electrodes 3 and 4.

[0135] j.1) coating a photoresist on the sample surface, exposing, and developing to form a source and drain region of the metal to be deposited;

[0136] j.2) Mount the partition-doped sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0137] j.3) Select Pd as the target material and set the evaporation rate to To ensure the uniformity and adhesion of the Pd layer, turn on the vacuum pump to evacuate to a high vacuum and gradually increase the electron beam current to start evaporating the Pd layer. After evaporating to a thickness of 5nm in the source and drain contact area, turn off the electron beam to stop evaporation, replace the target material with Au and set the evaporation rate to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0138] j.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure. The sample is taken out and placed in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0139] Step k: Aluminum nitride is formed as the gate dielectric layer 5 on the surface of the two-dimensional material channel layer and the source and drain electrodes by magnetron sputtering.

[0140] k.1) using aluminum nitride as a target material in a magnetron sputtering system, setting argon and nitrogen as working gases, with gas flow rates of 20 sccm and 5 sccm respectively, and setting the working gas pressure, sputtering power, and sputtering temperature to process conditions of 3 mTorr, 100 W, and 300° C., sputtering an aluminum nitride film on a substrate 1 as a bottom layer 2 of a packaging protective layer;

[0141] k.2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment and start the vacuum pump until the chamber reaches 10 - 6 After the vacuum degree reaches below 100 Torr, nitrogen and argon are introduced, and the flow rate is adjusted to the target working pressure and sputtering is started after it is kept stable. The sputtering time is about 10 minutes, and a 50nm thick aluminum nitride film is deposited on the surface of the two-dimensional material channel layer and the source and drain electrodes as the gate dielectric layer 5;

[0142] k.3) After the sample is cooled to room temperature in the vacuum chamber, nitrogen is introduced to return the chamber to atmospheric pressure, the chamber is opened and the sample is taken out.

[0143] Step 1: Making a gate electrode 6.

[0144] 1.1) coating a photoresist on the surface of the gate dielectric layer 5, exposing and developing the layer to form a gate region where metal is to be deposited;

[0145] 1.2) Mount the sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0146] l.3) Select Pd as the target material and set the evaporation rate to To ensure the uniformity and adhesion of the Pd layer, turn on the vacuum pump to evacuate to a high vacuum and gradually increase the electron beam current to start evaporating the Pd layer. After evaporating to a thickness of 5nm in the source and drain contact area, turn off the electron beam to stop evaporation, replace the target material with Au and set the evaporation rate to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0147] l.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure, and then the sample is taken out and placed in acetone for stripping, and the excess metal layer is removed to form a gate electrode 6.

[0148] Step m: Etching the gate dielectric layer to expose the source and drain electrodes

[0149] m.1) coating a photoresist on the sample surface, exposing and developing the area to be etched;

[0150] m.2) using CF4 plasma, under the process conditions of CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min, to etch aluminum nitride, exposing source and drain electrodes after etching;

[0151] m.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure that there is no residue on the surface.

[0152] Embodiment 5: The overall implementation steps of the transistor preparation method proposed in this embodiment are the same as those in Embodiment 2. Now, a specific example in which the substrate is made of diamond, the gate dielectric layer is made of silicon nitride, the two-dimensional material is molybdenum diselenide, and the source and drain electrode metal is Pd / Au is given to further describe the preparation process of the present invention in detail:

[0153] Step A: Pretreatment of transistor substrate 1 .

[0154] Sapphire was selected as the transistor insulating substrate 1, and the substrate 1 was ultrasonically cleaned in acetone solution, isopropanol, and deionized water for 5 minutes each, and then dried with nitrogen.

[0155] Step B: chemically vapor depositing the two-dimensional material to be transferred on another sapphire substrate.

[0156] B.1) The sapphire substrate was ultrasonically cleaned with acetone for 20 minutes, the cleaned substrate was rinsed with deionized water for 2 to 3 times, and then immersed in deionized water for ultrasonic cleaning for 15 minutes, and finally the treated substrate was blown dry with nitrogen;

[0157] B.2) MoO3 is used as the molybdenum source, and high-purity sulfur powder is used as the sulfur source. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity sulfur powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrate is placed with the substrate surface facing upward in an area about several centimeters away from the MoO3 powder to facilitate the growth of MoS3;

[0158] B.3) setting an argon-hydrogen mixed gas, with the gas flow rates of argon and hydrogen being 100 sccm and 10 sccm respectively, keeping the gas flow constant during the deposition process, turning on the tubular furnace, setting the heating rate to 15°C / min, heating the MoO3 powder area to 750°C, and the temperature of the sulfur powder area to 200°C. When the temperature reaches the set value, keeping the constant temperature for about 5 minutes, at which time the sulfur vapor reacts with MoO3 on the substrate to generate molybdenum disulfide, and growing a 10 nm molybdenum disulfide film to be transferred;

[0159] B.4) After the reaction is completed, turn off the heating and keep argon flowing until the system cools naturally to room temperature to prevent molybdenum disulfide from being oxidized at high temperature.

[0160] Step C: Transferring the two-dimensional material grown on the sapphire substrate to the insulating substrate 1 .

[0161] C.1) evenly drop a small amount of PMMA solution on the surface of the MoS2 / sapphire substrate, use a spin coating device, spin coat at 4000 rpm for 1 minute, and then dry on a hot plate at 100°C for 10 minutes to solidify the PMMA layer;

[0162] C.2) Dissolve 55 g of KOH solute in 300 ml of deionized water, and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then, soak the sample in the prepared KOH solution for two hours to gradually separate the PMMA-MoS2 layer from the substrate;

[0163] C.3) Rinse the PMMA-MoS2 layer in deionized water, use tweezers or other auxiliary tools to gently pick up the PMMA / MoS2 film floating on the water surface and slowly place it on the target substrate, use a glass rod or scraper to gently press to remove the bubbles between the PMMA / MoS2 film and the substrate to ensure full contact and adhesion, and let it stand for several hours to allow the film to fully adhere to the substrate;

[0164] 3.4) Soak the sample in acetone to remove PMMA, then clean it with IPA, and finally blow dry it with nitrogen.

[0165] Step D: Arraying the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0166] The surface of the two-dimensional material transferred to the substrate 1 is coated with glue, photolithographed, and developed to pattern the area to be etched; the process conditions of gas flow, reaction pressure, and RF power are set to 10sccm, 30mTorr, and 50W respectively, and the etching time is about 3min. Oxygen plasma is used to etch molybdenum disulfide to obtain an isolation area to array molybdenum disulfide, forming a two-dimensional material channel layer 2 to be doped for the transistor.

[0167] Step E: depositing a silicon dioxide layer on the surface of the two-dimensional material channel layer 2 by plasma enhanced chemical vapor deposition.

[0168] E.1) ultrasonically clean the sample with deionized water and isopropanol for 3 minutes each, and then blow dry with nitrogen;

[0169] E.2) setting the process parameters to an operating temperature of 200°C, an operating pressure of 800 mTorr, an RF power of 40 W, a SiH2 gas flow rate of 2 sccm, an O2 gas flow rate of 50 sccm and an Ar gas flow rate of 10 sccm, and a deposition time of about 8 minutes;

[0170] E.3) Fix the sample on the base in the PECVD reaction chamber, start the PECVD system under the set conditions, and deposit a 40nm silicon dioxide layer on the surface of the two-dimensional material.

[0171] E.4) After the deposition is completed, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

[0172] Step F: After photolithography, the silicon dioxide above the area to be doped with the two-dimensional material is etched into a thin layer.

[0173] Photoresist is coated on the surface of the sample, and the area to be etched is exposed and developed; CF4 plasma is used under the process conditions of CF4 gas flow rate of 30sccm, auxiliary gas Ar and O2 gas flow rates of 10sccm and 2sccm respectively, reaction pressure and RF power of 10mTorr and 100W respectively, and etching time of about 3min, to etch the silicon dioxide above the area to be doped with the two-dimensional material into a thin layer of about 10nm.

[0174] Step G: Creating vacancies on the surface of two-dimensional materials.

[0175] A sample covered with a patterned etched silicon dioxide mask layer was placed in a reactive ion etching chamber and exposed to hydrogen plasma. The RF power and the flow rate of hydrogen gas in the RIE chamber were maintained at 100 W and 50 sccm, respectively. The hydrogen ions partially penetrated the silicon dioxide thin layer and precisely created vacancies on the surface of the two-dimensional material below.

[0176] Step H: Wet etching to remove the silicon dioxide mask layer

[0177] Use a 1:6 diluted buffered oxide etching solution, gently immerse the sample in the solution, keep the liquid completely covering the sample surface, let it stand in the solution, or gently stir to promote uniform etching; remove the sample immediately after etching, quickly rinse with a large amount of deionized water to remove residual etching solution components, and finally rinse the sample with IPA and blow dry with nitrogen.

[0178] Step I: Oxidative doping of vacancies.

[0179] The sample with the silicon dioxide layer removed is exposed to an oxygen flow to perform natural oxidation doping on the surface vacancies of the manufactured two-dimensional material, thereby obtaining a two-dimensional material channel layer 2 with partitioned doping of the transistor.

[0180] Step J: Making source and drain electrodes 3 and 4.

[0181] J.1) coating a photoresist on the sample surface, exposing, and developing to form a source and drain region where metal is to be deposited;

[0182] J.2) Mount the partition-doped sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0183] J.3) Select Pd as the target material and set the evaporation rate to To ensure the uniformity and adhesion of the Pd layer, turn on the vacuum pump to evacuate to a high vacuum and gradually increase the electron beam current to start evaporating the Pd layer. After evaporating to a thickness of 5nm in the source and drain contact area, turn off the electron beam to stop evaporation, replace the target material with Au and set the evaporation rate to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0184] J.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure. The sample is taken out and placed in acetone for stripping. After removing the excess metal layer, the source electrode 3 and the drain electrode 4 are formed.

[0185] Step K: Silicon nitride is used as the gate dielectric layer 5 on the surface of the two-dimensional material channel layer and the source and drain electrodes by magnetron sputtering.

[0186] K.1) performing low-power oxygen plasma pretreatment on the substrate surface under process conditions of a power of 20 W, a gas flow rate of 5 sccm, and a time of about 10 minutes to further improve the adhesion of the silicon nitride film;

[0187] K.2) Install the high-purity silicon target on the cathode and ensure that it is in good contact with the magnetron sputtering system. Start the vacuum pump until the chamber reaches 10 -6 After reaching a high vacuum degree below Torr, argon and nitrogen are introduced as working gases, with the gas flow rates of argon and nitrogen being 15 sccm, and the working pressure maintained at 3 mTorr;

[0188] K.3) After heating the sapphire substrate 1 to 300 degrees Celsius, a 50 nm thick silicon nitride film is deposited as the gate dielectric layer 7 under process conditions of a sputtering power of 150 W and a sputtering time of 10 min;

[0189] K.4) After the deposition is completed, the sample is cooled to room temperature in the vacuum chamber, nitrogen is introduced to return the chamber to atmospheric pressure, the chamber is opened and the sample is taken out.

[0190] Step L: Making the gate electrode 6.

[0191] L.1) coating a photoresist on the surface of the gate dielectric layer 5, exposing and developing the layer to form a gate region where metal is to be deposited;

[0192] L.2) Mount the sample on the sample stage in the evaporation system and ensure that the sample surface is aligned with the target placement area;

[0193] L.3) Select Pd as the target and set the evaporation rate to To ensure the uniformity and adhesion of the Pd layer, turn on the vacuum pump to evacuate to a high vacuum and gradually increase the electron beam current to start evaporating the Pd layer. After evaporating to a thickness of 5nm in the source and drain contact area, turn off the electron beam to stop evaporation, replace the target material with Au and set the evaporation rate to Then, an Au layer is evaporated on the source and drain contact areas to a thickness of 25 nm;

[0194] L.4) After the evaporation is completed, the sample is allowed to cool in the chamber for a few minutes, and then the air is slowly released to return to normal pressure, and then the sample is taken out and placed in acetone for stripping, and the excess metal layer is removed to form a gate electrode 6.

[0195] Step M: Etching the gate dielectric layer to expose the source and drain electrodes

[0196] M.1) Coating photoresist on the sample surface, exposing and developing the area to be etched;

[0197] M.2) using CF4 plasma, under the process conditions of CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min, to etch silicon nitride, exposing the source and drain electrodes after etching;

[0198] M.3) After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure that there is no residue on the surface.

[0199] The preparation methods used in the above specific embodiments are conventional methods unless otherwise specified; the reagents and materials used are commercially available unless otherwise specified. The parts not described in detail in the present invention belong to the common knowledge of those skilled in the art.

[0200] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Obviously, after understanding the content and principle of the present invention, professionals in the field may make various modifications and changes in form and details without deviating from the principle and result of the present invention. For example, in addition to SiO2, sapphire and diamond, other insulating substrate materials may be used for the insulating substrate; in addition to tungsten diselenide and molybdenum diselenide, other two-dimensional semiconductor materials such as tungsten disulfide that can be oxidized to achieve p-type doping may be used for the two-dimensional material; in addition to chemical vapor deposition and transfer, the two-dimensional material thin film layer may also be obtained by mechanical stripping and transfer; in addition to aluminum oxide, aluminum nitride and silicon nitride, the gate dielectric layer may also be made of other insulating dielectric materials such as hafnium oxide and boron nitride; in addition to magnetron sputtering, the method for preparing the gate dielectric may also be chemical vapor deposition, atomic layer deposition and other methods; in addition to Pt / Au or Pd / Au, the source and drain metal electrodes may also be made of other metals that are compatible with the p-type electrical properties of the two-dimensional material. However, these modifications and changes based on the idea of ​​the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A controllably doped p-type two-dimensional transistor based on vacancies, characterized in that: include: An insulating substrate (1), a two-dimensional material channel layer (2), a source electrode (3) and a drain electrode (4) located on both ends of the two-dimensional material channel layer, a gate dielectric layer (5) located on the two-dimensional material channel layer and the source electrode and the drain electrode, and a gate electrode (6) located on the gate dielectric; The two-dimensional material channel layer (2) is made of one of two-dimensional semiconductor materials, and the two-dimensional semiconductor material at least includes tungsten diselenide, molybdenum diselenide, and molybdenum disulfide; And controllable surface charge transfer doping is performed on it, that is, partitioned vacancies are manufactured on its surface and then naturally oxidized.

2. The transistor according to claim 1, characterized in that: The two-dimensional material channel layer (2) is a multi-layer structure.

3. The transistor according to claim 1, characterized in that The insulating substrate (1) is made of any insulating material selected from the group consisting of SiO2 / Si, sapphire and diamond; the gate dielectric (7) is made of any insulating dielectric layer selected from the group consisting of aluminum oxide, aluminum nitride and silicon nitride; the gate electrode (8) is made of Ni / Au, Pd / Au or Pt / Au metal; and the source electrode (5) and the drain electrode (6) are both made of Pd / Au or Pt / Au or a metal having electrical properties compatible with the two-dimensional material.

4. A method for preparing a controllably doped p-type two-dimensional transistor based on vacancies, characterized in that: The steps include: §1: Select a target substrate, and use acetone, isopropanol, and deionized water to ultrasonically clean its surface, and then blow dry it with nitrogen to obtain an insulating substrate with a clean surface (1); §2: Using chemical vapor deposition to grow a thin film of the two-dimensional material to be transferred on the substrate surface; §3: Using PMMA-assisted transfer method to transfer the grown two-dimensional material film to the insulating substrate (1); §4: The two-dimensional material transferred onto the insulating substrate (1) is subjected to coating, pre-baking, photolithography, and development, and then an isolation region is etched to form an array of the two-dimensional material, thereby obtaining a two-dimensional material channel layer to be doped for the transistor; §5: Depositing a silicon dioxide layer on the surface of the two-dimensional material obtained in step §4 by plasma enhanced chemical vapor deposition; §6: Evenly coat the surface of the silicon dioxide layer with photoresist, and after pre-baking, photolithography, and etching, etch the silicon dioxide layer above the two-dimensional material area to be doped into a thin silicon dioxide layer; §7: High-energy hydrogen ions are used to bombard the surface of the two-dimensional material through a silicon dioxide mask layer to create precisely partitioned two-dimensional material surface vacancies, and a controllable number of vacancies is obtained according to different powers and processing times; §8: Remove the silicon dioxide mask layer by wet etching; §9: The two-dimensional material with surface vacancies is exposed to an oxygen flow for oxidation, thereby achieving precisely controllable surface charge transfer doping and obtaining a two-dimensional material channel layer of the transistor (2); §10: Depositing source and drain electrode metals on the surface of the two-dimensional material channel layer (2) obtained in step §9 by photolithography and electron beam evaporation. After the metal is deposited, a stripping process is performed to form a source electrode (3) and a drain electrode (4); §11: A gate dielectric layer (5) is obtained by magnetron sputtering aluminum oxide, aluminum nitride or silicon nitride on the surfaces of the two-dimensional material channel layer (2), the source electrode (3) and the drain electrode (4); §12: preparing a gate electrode (6) on the surface of the gate dielectric layer (5) by photolithography, electron beam evaporation, and gate metal deposition and lift-off process; §13: The area above the source electrode and the drain electrode is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes to complete the device fabrication.

5. The method according to claim 4, characterized in that: In step §2, a two-dimensional material film to be transferred is grown on the surface of the substrate using chemical vapor deposition, and the implementation steps include the following: 2a) Selecting reaction precursors according to the type of two-dimensional material film to be grown, and placing different types of reaction precursors in the high temperature zone and low temperature zone of the tube furnace respectively according to the reaction requirements; 2b) placing a clean substrate for growing a two-dimensional material film in an area about a few centimeters away from the sample in the high temperature zone to facilitate film growth; 2c) Setting the working gas, keeping the gas flow constant during the deposition process, raising the temperature at a rate of 15-20°C / min until the set working temperature is reached, and then controlling the reaction time according to the desired thickness of the two-dimensional material film layer to obtain the two-dimensional material film to be transferred.

6. The method according to claim 4, characterized in that: The PMMA-assisted transfer method in step §3 is implemented as follows: Spin-coat PMMA on the surface of the layer to be transferred and cure it on a hot plate at 90-120°C; The sample was immersed in a solution required for separating the substrate for two hours to separate the PMMA-to-be-transferred layer from its substrate; The separated floating PMMA-to-be-transferred layer is transferred to the target substrate for curing, and then soaked with acetone to remove PMMA, then cleaned with IPA, and finally blown dry with nitrogen.

7. The method according to claim 4, characterized in that: The plasma enhanced chemical vapor deposition described in step §5 is to fix the pre-cleaned sample on a base in a PECVD reaction chamber, introduce Ar gas to remove residual impurities in the reaction chamber, start the PECVD system under set conditions, and start SiO2 film deposition; After the deposition is completed, pure Ar gas is introduced to clean the chamber for 1 minute to prevent contamination.

8. The method according to claim 4, characterized in that: The surface vacancies of the two-dimensional material in step §7 are specifically produced by placing the silicon dioxide mask layer sample that has been thinned by partition etching in a reactive ion etching chamber and exposing it to hydrogen plasma, maintaining the RF power and the flow rate of hydrogen gas in the RIE chamber at 100 W and 50 sccm respectively, and bombarding it with high-energy hydrogen ions through the mask layer.

9. The method according to claim 4, characterized in that: The magnetron sputtering described in step §11 is to heat the substrate to a set temperature, use the corresponding target material and working gas according to the type of packaging protective layer, and use the magnetron sputtering system to control the sputtering time according to the required thickness at the reaction chamber temperature to grow the gate dielectric layer to be etched on the substrate or the two-dimensional material channel layer.

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