System and method for testing and analyzing single event effect of high-capacity nonvolatile memory

Abstract

The invention discloses a system and a method for testing and analyzing the single event effect of a high-capacity nonvolatile memory. The system comprises an upper computer module, an FPGA (Field Programmable Gate Array) control module and a programmable power supply module. The system is used for testing and analyzing various single event effects of a high-capacity nonvolatile memory chip in a dynamic working mode. And according to the error data read from the memory in the dynamic working mode, presetting error bitmap rules of various single-particle function interruptions in an FPGA test program, carrying out real-time analysis and identification on the various single-particle function interruptions, and discriminating single-particle upset of the memory unit. According to the system, testing and real-time analysis of various complex single event effects of the high-capacity nonvolatile memory can be achieved, then radiation hardening and evaluation can be conducted on the sensitive position of a memory chip, and high pertinence is achieved.

Description

Technical Field

[0001] The present invention relates to the field of radiation testing technology, and in particular to a large-capacity non-volatile memory single particle effect testing and analysis system and method. Background Art

[0002] There is a harsh high-energy particle radiation environment in space. Spacecraft will be exposed to radiation from solar cosmic rays, galactic cosmic rays and radiation belts. These radiations can easily cause varying degrees of damage to electronic components in satellites or spacecraft, affecting their normal operation on spacecraft. The large-capacity non-volatile memory inside the aerospace electronic system has the ability to save data after power failure, and is widely used in the long-term storage of system source programs, important configuration data and important scientific research data. In each working mode of the non-volatile memory chip, the key circuit modules of the chip, such as the charge pump, main state machine, sense amplifier, row and column decoder or storage cell array, may be affected by single-particle radiation in the aerospace environment, causing complex single-particle functional interrupts, single-particle latches or single-particle flips, resulting in a large number of data errors and whole system failures. Therefore, before the memory chip is used in the space system, it is necessary to conduct a full and accurate irradiation test evaluation on it, and reinforce the irradiation-sensitive units based on the evaluation results, so as to provide data basis for model device selection and design.

[0003] At present, the single-particle effect test of the dynamic working mode of large-capacity non-volatile memory is often accompanied by megabit-level error data caused by single-particle functional interruption, which causes two shortcomings of the traditional single-particle test method: 1) If all the megabit-level error data read out in the dynamic working mode are uploaded to the host computer, the speed is slow and the time is long, which interferes with the effect of high-energy particles on the dynamic operation of the memory itself. If only part of the error data is uploaded, it is impossible to establish a complete full-chip error bitmap, and it is difficult to analyze and locate the single-particle functional interruption; 2) A large amount of error data will interfere with the statistics of single-particle flips caused by charge leakage of storage units. This makes the current single-particle effect evaluation of large-capacity non-volatile memory incomplete and insufficient, and it is difficult to carry out targeted anti-single-particle reinforcement. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to provide a single particle effect test and analysis system for a large-capacity non-volatile memory, to solve the problem that the single particle effect is difficult to accurately analyze due to the long time spent uploading megabit-level erroneous data, and to achieve real-time, comprehensive and accurate evaluation of the single particle effect of the large-capacity non-volatile memory.

[0005] The technical solution of the present invention is: a single-particle effect test and analysis system for a large-capacity non-volatile memory, comprising: a host computer module, an FPGA control module, and a program-controlled power supply module;

[0006] The FPGA control module solidifies the memory chip test program and the error data analysis upload program into the FPGA board; wherein the memory chip test program controls the FPGA board to send operation instructions to the memory chip, so that the memory chip performs read and reset operations in the dynamic cycle read-only mode and erase, program, read and reset operations in the dynamic cycle erase-read-write mode; the error data analysis upload program controls the FPGA board to compare the original data code stream of the entire memory chip with the actual data code stream read out, and performs identification analysis of single-particle functional interruption of the logic circuit and single-particle flip of the storage unit; the FPGA control module outputs data information to the serial port of the host computer module after each read operation;

[0007] The program-controlled power supply module starts the program-controlled power supply to provide current to the FPGA board and memory chip of the system after receiving the start signal sent by the host computer module;

[0008] The host computer module sends instructions to the FPGA board through the communication interface, and receives and prints the data information output by the FPGA board in real time.

[0009] The identification and analysis of single-particle functional interruptions and single-particle upsets of various logic circuits includes: analyzing the megabit-level data code stream read out of the memory chip according to the preset error bitmap rules of various single-particle functional errors, identifying various single-particle functional interruptions in real time, and identifying and uploading single-particle upset events of storage units with random address distribution.

[0010] The data information includes: storage unit single particle upset error data and its address, logic circuit single particle function interruption event, memory chip instruction execution status, the number of all "0" words and all "1" words, and operation execution timeout status.

[0011] A method for performing single event effect test and analysis of a large-capacity non-volatile memory using the system comprises:

[0012] The FPGA control module is connected to the chip under test and placed together in the irradiation experimental environment to ensure that the chip under test can be irradiated by the specified ions under the irradiation source during the test;

[0013] Turn on the program-controlled power supply to power on the single-particle effect test and analysis system of the large-capacity non-volatile memory and the memory chip;

[0014] The host computer sends programming instructions to the FPGA control module and selects the initial data pattern to write into each address unit of the chip to be tested;

[0015] Turn on the irradiation, send the corresponding working mode selection instructions, execute the corresponding chip operations in different working modes, and perform single-particle effect test and analysis of large-capacity non-volatile memory.

[0016] The working modes include a static power-on mode, a dynamic cycle read-only mode and a dynamic cycle erase-read-write-read mode.

[0017] The static power-on mode includes:

[0018] The chip is placed in an irradiation environment and irradiation is started. No dynamic operation is performed during the irradiation process. After the irradiation is completed, the full chip data of the memory chip is read out and compared with the initial data pattern, and the single particle flip situation of the memory unit is recorded.

[0019] The dynamic loop read-only mode includes:

[0020] The chip is placed in an irradiation environment and irradiated. During the irradiation process, the chip function execution status output by the host computer is monitored; the FPGA control module reads out the data stored in each address bit of the memory chip to be tested, and compares it with the initial data pattern to obtain the unit address of the data error;

[0021] According to the address location of the acquired error data distribution and the built-in single-particle functional interrupt event identification rules, the characteristic description of the single-particle functional interrupt is sorted out in the FPGA hard core and uploaded to the host computer for printing; for a large number of read data errors of memory chips with known capacity and bank, block, section, page, row and column structure, except for column-level errors, the judgment of other levels of single-particle functional interrupts is performed in a hierarchical manner in ascending order of capacity;

[0022] In addition to the above-mentioned single-particle function interruption events, the (72,64) Hamming code error correction algorithm is executed for each consecutive 64-bit data starting from the starting bit address of the memory chip. The "0 to 1" type bit error that can be corrected is defined as a single-particle flip caused by the charge leakage of the storage unit. The single-particle flip data is uploaded to the host computer for printing;

[0023] Taking the n-bit-wide word output from the chip I / O terminal as the unit, count the number of all-0 words and all-1 words in the error data read from the FPGA module, and output and print them in the host computer;

[0024] Define the time tREAD for normal reading of the whole chip when there is no irradiation, and set the timing judgment condition in the FPGA module. If the read operation time exceeds 2×tREAD during the irradiation process, "Read operation execution timeout" will be printed in the host computer, and the dynamic cycle read-only operation will continue after the reset operation; if the read operation execution timeout phenomenon still occurs during the read operation again, the dynamic cycle read-only operation and irradiation will be stopped, and the host computer will control the program-controlled power supply to cut off the power to the memory chip and FPGA board and end the test, otherwise the irradiation test will continue to the end of the injection amount;

[0025] During the irradiation process, the host computer module prints the data information uploaded in real time by the FPGA board through the communication interface;

[0026] After reaching the end point of the irradiation injection, the dynamic cycle read-only operation and irradiation are stopped, the test data is saved, and the upper computer controls the program-controlled power supply to cut off the power to the memory chip and the FPGA board and end the test.

[0027] The specific rules for determining the interruption of the single-particle function at each level are as follows:

[0028] Local continuous address error: If the local continuous address data is wrong and the data is all turned to 1 or all turned to 0, it is judged as a local continuous address error, and the statement "local continuous address error: address A to address B are all turned to 0 / 1" is output to the upper computer;

[0029] Column-level error: If the entire column of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a column-level error and the statement "column-level error: column X is all turned to 0 / 1" is output to the upper computer;

[0030] Row-level error: If the entire row of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a row-level error and the statement "row-level error: row X is all turned to 0 / 1" is output to the upper computer;

[0031] Page-level error: If the entire page of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a page-level error, and the statement "Page-level error: Page X is all turned to 0 / 1" is output to the host computer;

[0032] Section-level error: If the entire section of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a section-level error, and the statement "Section-level error: Section X is all turned to 0 / 1" is output to the upper computer;

[0033] Block-level error: If the entire block of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a block-level error, and the statement "block-level error: block X is all turned to 0 / 1" is output to the upper computer;

[0034] Bank-level error: If the entire bank of data is wrong and manifested as all turned to 1 or all turned to 0, it is determined to be a Bank-level error and the statement "Bank-level error: BankX all turned to 0 / 1" is output to the host computer.

[0035] The dynamic cycle erase-read-write mode includes: identifying various single particle effects according to the read error data in the read operation, and identifying the single particle function interruption occurring in the erase operation and the programming operation through the operation execution timeout phenomenon, including:

[0036] During the erase operation, according to the normal erase time tERASE of the whole chip when there is no irradiation, the timing judgment condition is set in the FPGA module. If the erase operation time exceeds 2×tERASE during the irradiation process, the host computer will output "erase operation execution timeout", and the erase operation and subsequent dynamic cycle operations will continue after the reset operation. If the erase operation execution timeout phenomenon still occurs during the second erase operation, the dynamic cycle erase, read, write and read operation and irradiation will be stopped, and the host computer will control the program-controlled power supply to cut off the power to the memory chip and FPGA board and end the test, otherwise the irradiation test will continue to the end of the injection amount;

[0037] During the programming operation, select the data pattern to write into each address unit of the chip to be tested. According to the normal programming time tPROG of the whole chip when there is no irradiation, set the timing judgment condition in the FPGA module. If the programming operation time exceeds 2×tPROG during the irradiation process, the FPGA module will output "Programming operation execution timeout" to the upper computer, and continue to execute the programming operation and subsequent dynamic cycle operations after the reset operation. If the programming operation execution timeout phenomenon still occurs during the second execution of the programming operation, stop the dynamic cycle erase, read, write, read and irradiation, and the upper computer controls the program-controlled power supply to power off the memory chip and FPGA board and end the test. Otherwise, continue the irradiation test to the end of the injection amount;

[0038] After reaching the end point of the irradiation injection, the dynamic cycle erase, read, write and read operations and irradiation are stopped, the test data is saved, and the upper computer controls the program-controlled power supply to cut off the power to the memory chip and FPGA board and end the test.

[0039] The advantages of the present invention compared with the prior art are:

[0040] (1) The test system of the present invention can sort out a large number of data errors of a large-capacity memory chip into characteristic descriptions of single-particle functional interruptions and upload them to a host computer, thereby avoiding the time-consuming process of uploading erroneous data one by one through a serial port and causing interference to the irradiation test.

[0041] (2) The test system of the present invention can set the working mode of the memory chip to a static power-on mode, a dynamic cycle read-only mode, and a dynamic erase-read-write-read mode, thereby enriching the test method of the memory chip and making the detection function more comprehensive.

[0042] (3) The test system of the present invention establishes a set of single-particle functional interrupt judgment rules for large-capacity non-volatile memory chips, and the random single-particle upsets of storage units can be distinguished and counted, thereby guiding chip designers to perform reinforcement design. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a flow chart of the single-particle effect test and analysis method of the large-capacity non-volatile memory of the present invention;

[0044] Figure 2 It is a structural diagram of a single-particle effect test and analysis system for a large-capacity non-volatile memory of the present invention;

[0045] Figure 3 It is a schematic diagram of a flow chart for distinguishing various types of single-particle functional interruptions in a single-particle effect test and analysis system for a large-capacity non-volatile memory of the present invention. DETAILED DESCRIPTION

[0046] The test and analysis system of the present invention includes a host computer configuration module, an FPGA control module, and a program-controlled power supply module. Figure 2 A single-particle effect test and analysis system for a large-capacity non-volatile memory includes: a host computer module, an FPGA control module, and a programmable power supply module;

[0047] The FPGA control module solidifies the memory chip test program and the error data analysis upload program into the FPGA board; wherein the memory chip test program controls the FPGA board to send operation instructions to the memory chip, so that the memory chip performs read and reset operations in the dynamic cycle read-only mode and erase, program, read and reset operations in the dynamic cycle erase-read-write mode; the error data analysis upload program controls the FPGA board to compare the original data code stream of the entire memory chip with the actual data code stream read out, and performs identification analysis of single-particle functional interruption of the logic circuit and single-particle flip of the storage unit; the FPGA control module outputs data information to the serial port of the host computer module after each read operation;

[0048] The program-controlled power supply module starts the program-controlled power supply to provide current to the FPGA board and memory chip of the system after receiving the start signal sent by the host computer module;

[0049] The host computer module sends instructions to the FPGA board through the communication interface, and receives and prints the data information output by the FPGA board in real time.

[0050] The identification and analysis of single-particle functional interruptions and single-particle upsets of various logic circuits includes: analyzing the megabit-level data code stream read out of the memory chip according to the preset error bitmap rules of various single-particle functional errors, identifying various single-particle functional interruptions in real time, and identifying and uploading single-particle upset events of storage units with random address distribution.

[0051] The data information includes: storage unit single particle upset error data and its address, logic circuit single particle function interruption event, memory chip instruction execution status, the number of all "0" words and all "1" words, and operation execution timeout status.

[0052] like Figure 1The figure shows a basic method flow chart of the single event effect test and analysis system of the large capacity non-volatile memory of the present invention. The specific working process is as follows:

[0053] The FPGA control module is connected to the chip under test and placed together in the irradiation experimental environment to ensure that the chip under test can be irradiated by the specified ions under the irradiation source during the test;

[0054] Turn on the program-controlled power supply to power on the single-particle effect test and analysis system of the large-capacity non-volatile memory and the memory chip;

[0055] The host computer sends programming instructions to the FPGA control module and selects the initial data pattern to write into each address unit of the chip to be tested;

[0056] Turn on the irradiation, send the corresponding working mode selection instruction, perform the corresponding chip operation in different working modes, and perform single particle effect test and analysis of large-capacity non-volatile memory. The working modes include static power-on mode, dynamic cycle read-only mode and dynamic cycle erase-read-write mode.

[0057] (1) Static power-on mode

[0058] The memory chip in static power-on mode is only used as a control group and does not perform any dynamic operations during the irradiation process. After the irradiation is completed, the full chip data is read out and compared with the initial data pattern to record the single-particle upset of the storage unit.

[0059] (2) Dynamic loop read-only mode

[0060] The memory chip in the dynamic cycle read-only mode is used to observe the chip function execution status output by the host computer serial port during the irradiation process. The FPGA control module compares the actual data code stream read out of the memory chip with the initial data, counts the error data and its address, and then performs the logic circuit single particle function interrupt identification according to the preset single particle function error error bitmap rule.

[0061] According to the address position of the error bit distribution, establish local continuous address error, column level error, row level error, bank level error, section level error, page level error and block level error identification rules, such as Figure 3 As shown in the figure, except for column-level errors, the determination of single-particle functional interrupts at other levels is performed in ascending order of capacity to avoid overlap. For memory chips with known capacity and bank, block, section, page, row and column structures, the specific identification rules are as follows:

[0062] Local continuous address error: If the local continuous address data is wrong and the characteristics are that all are turned to 1 or all are turned to 0, it is judged as a local continuous address error, and the statement "Local continuous address error: address A to address B are all turned to 0 / 1" is output to the host computer.

[0063] Column-level error: If the entire column of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a column-level error and the statement "column-level error: column X is all turned to 0 / 1" is output to the host computer.

[0064] Row-level error: If the entire row of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a row-level error and the statement "Row-level error: Row X is all turned to 0 / 1" is output to the host computer.

[0065] Page-level error: If the entire page of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a page-level error, and the statement "Page-level error: Page X is all turned to 0 / 1" is output to the host computer.

[0066] Section-level error: If the entire section of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a section-level error and the statement "Section-level error: Section X is all turned to 0 / 1" is output to the host computer.

[0067] Block-level error: If the entire block of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a block-level error and the statement "Block-level error: Block X is all turned to 0 / 1" is output to the host computer.

[0068] Bank-level error: If the entire bank of data is wrong and manifested as all turned to 1 or all turned to 0, it is determined to be a Bank-level error and the statement "Bank-level error: BankX all turned to 0 / 1" is output to the host computer.

[0069] According to the normal read time tREAD of the whole chip when there is no irradiation, the timing judgment condition is set in the FPGA module. If the read operation time exceeds 2×tREAD during the irradiation process, "Read operation execution timeout" is printed in the host computer, and the dynamic cycle read-only operation is continued after the reset operation. If the read operation execution timeout phenomenon still occurs during the read operation again, the dynamic cycle read-only operation and irradiation are stopped, and the host computer controls the program-controlled power supply to power off the memory chip and FPGA board and end the test, otherwise the irradiation test continues to the end of the injection amount.

[0070] According to the (72,64) Hamming code error correction algorithm, single-particle upsets of storage cells with random address distribution are identified, and the number of typical error words of all "0" words and all "1" words in the statistical bit stream is counted.

[0071] After each read operation, five types of information are output to the host computer serial port: 1) storage unit single particle upset error data and its address, 2) logic circuit single particle function interrupt event, 3) memory chip instruction execution status, 4) all "0" and all "1" word number, 5) operation execution timeout.

[0072] After reaching the end point of the irradiation injection, the chip operation and irradiation are stopped, the test data is saved, and the host computer controls the program-controlled power supply to cut off the power to the memory chip and the FPGA board and end the test.

[0073] (3) Dynamic cycle erase read write read mode

[0074] The memory chip in the dynamic cycle erase-read-write mode performs the same single-particle functional interrupt and single-particle upset identification as the dynamic cycle read-only mode in the read operation during the irradiation process. In the erase and programming operations, the FPGA module sets the timing judgment conditions according to the normal erase and programming time of the whole chip when there is no irradiation, and records the timeout of the erase and programming operations.

[0075] During the erase operation, according to the normal erase time tERASE of the whole chip without irradiation, the timing judgment condition is set in the FPGA module. If the erase operation time exceeds 2×tERASE during the irradiation process, the host computer outputs "erase operation execution timeout", and the erase operation and subsequent dynamic cycle operations are continued after the reset operation. If the erase operation execution timeout phenomenon still occurs during the second erase operation, the dynamic cycle erase, read, write, and read operation and irradiation are stopped, and the host computer controls the program-controlled power supply to power off the memory chip and FPGA board and end the test, otherwise the irradiation test continues to the end of the injection amount.

[0076] During the programming operation, select the data pattern to write into each address unit of the chip to be tested. According to the normal programming time tPROG of the whole chip without irradiation, set the timing judgment condition in the FPGA module. If the programming operation time exceeds 2×tPROG during the irradiation process, the FPGA module will output "Programming operation execution timeout" to the upper computer, and continue to execute the programming operation and subsequent dynamic cycle operation after the reset operation. If the programming operation execution timeout phenomenon still occurs during the re-execution of the programming operation, the dynamic cycle erase, read, write, and read operation and irradiation are stopped, and the upper computer controls the program-controlled power supply to power off the memory chip and FPGA board and end the test, otherwise continue the irradiation test to the end of the injection amount.

[0077] After reaching the end point of the irradiation injection, the chip operation and irradiation are stopped, the test data is saved, and the host computer controls the program-controlled power supply to cut off the power to the memory chip and the FPGA board and end the test.

[0078] The above description is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A single event effect test and analysis system for large-capacity non-volatile memory, characterized in that: include: Host computer module, FPGA control module, programmable power supply module; The FPGA control module solidifies the memory chip test program and the error data analysis upload program into the FPGA board; wherein the memory chip test program controls the FPGA board to send operation instructions to the memory chip, so that the memory chip performs read and reset operations in the dynamic cycle read-only mode and erase, program, read and reset operations in the dynamic cycle erase-read-write mode; the error data analysis upload program controls the FPGA board to compare the original data code stream of the entire memory chip with the actual data code stream read out, and performs identification analysis of single-particle functional interruption of the logic circuit and single-particle flip of the storage unit; the FPGA control module outputs data information to the serial port of the host computer module after each read operation; The program-controlled power supply module starts the program-controlled power supply to provide current to the FPGA board and memory chip of the system after receiving the start signal sent by the host computer module; The host computer module sends instructions to the FPGA board through the communication interface, and receives and prints the data information output by the FPGA board in real time.

2. The single event effect test and analysis system for large capacity non-volatile memory according to claim 1, characterized in that: The identification and analysis of single-particle functional interruptions and single-particle upsets of various logic circuits includes: analyzing the megabit-level data code stream read out of the memory chip according to the preset error bitmap rules of various single-particle functional errors, identifying various single-particle functional interruptions in real time, and identifying and uploading single-particle upset events of storage units with random address distribution.

3. The single event effect test and analysis system for large capacity non-volatile memory according to claim 2, characterized in that: The data information includes: storage unit single particle upset error data and its address, logic circuit single particle function interruption event, memory chip instruction execution status, the number of all "0" words and all "1" words, and operation execution timeout status.

4. A method for performing single event effect test and analysis of a large capacity non-volatile memory using the system of claim 3, characterized in that: include: The FPGA control module is connected to the chip under test and placed together in the irradiation experimental environment to ensure that the chip under test can be irradiated by the specified ions under the irradiation source during the test; Turn on the program-controlled power supply to power on the single-particle effect test and analysis system of the large-capacity non-volatile memory and the memory chip; The host computer sends programming instructions to the FPGA control module and selects the initial data pattern to write into each address unit of the chip to be tested; Turn on the irradiation, send the corresponding working mode selection instructions, execute the corresponding chip operations in different working modes, and perform single-particle effect test and analysis of large-capacity non-volatile memory.

5. The method according to claim 4, characterized in that: The working modes include a static power-on mode, a dynamic cycle read-only mode and a dynamic cycle erase-read-write-read mode.

6. The method according to claim 5, characterized in that: The static power-on mode includes: The chip is placed in an irradiation environment and irradiation is started. No dynamic operation is performed during the irradiation process. After the irradiation is completed, the full chip data of the memory chip is read out and compared with the initial data pattern, and the single particle flip situation of the memory unit is recorded.

7. The method according to claim 5, characterized in that: The dynamic loop read-only mode includes: The chip is placed in an irradiation environment and irradiated. During the irradiation process, the chip function execution status output by the host computer is monitored; the FPGA control module reads out the data stored in each address bit of the memory chip to be tested, and compares it with the initial data pattern to obtain the unit address of the data error; According to the address location of the acquired error data distribution and the built-in single-particle functional interrupt event identification rules, the characteristic description of the single-particle functional interrupt is sorted out in the FPGA hard core and uploaded to the host computer for printing; for a large number of read data errors of memory chips with known capacity and bank, block, section, page, row and column structure, except for column-level errors, the judgment of other levels of single-particle functional interrupts is performed in a hierarchical manner in ascending order of capacity; In addition to the above-mentioned single-particle function interruption events, the (72,64) Hamming code error correction algorithm is executed for each consecutive 64-bit data starting from the starting bit address of the memory chip. The "0 to 1" type bit error that can be corrected is defined as a single-particle upset caused by charge leakage of the storage unit. The single-particle upset data is uploaded to the host computer for printing; Taking the n-bit-wide word output from the chip I / O terminal as the unit, count the number of all-0 words and all-1 words in the error data read from the FPGA module, and output and print them in the host computer; Define the time tREAD for normal readout of the whole chip when there is no irradiation, and set the timing judgment condition in the FPGA module. If the read operation time exceeds 2×tREAD during the irradiation process, "read operation execution timeout" will be printed in the host computer, and the dynamic cycle read-only operation will continue after the reset operation; if the read operation execution timeout phenomenon still occurs during the read operation again, the dynamic cycle read-only operation and irradiation will be stopped, and the host computer will control the program-controlled power supply to cut off the power to the memory chip and FPGA board and end the test, otherwise the irradiation test will continue to the end of the injection amount; During the irradiation process, the host computer module prints the data information uploaded in real time by the FPGA board through the communication interface; After reaching the end point of the irradiation injection, the dynamic cycle read-only operation and irradiation are stopped, the test data is saved, and the upper computer controls the program-controlled power supply to cut off the power to the memory chip and the FPGA board and end the test.

8. The method according to claim 7, characterized in that: The specific rules for determining the interruption of the single-particle function at each level are as follows: Local continuous address error: If the local continuous address data is wrong and the data is all turned to 1 or all turned to 0, it is judged as a local continuous address error and the statement "local continuous address error: address A to address B are all turned to 0 / 1" is output to the upper computer; Column-level error: If the entire column of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a column-level error and the statement "column-level error: column X is all turned to 0 / 1" is output to the upper computer; Row-level error: If the entire row of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is judged as a row-level error and the statement "row-level error: row X is all turned to 0 / 1" is output to the upper computer; Page-level error: If the entire page of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a page-level error, and the statement "Page-level error: Page X is all turned to 0 / 1" is output to the upper computer; Section-level error: If the entire section of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a section-level error, and the statement "Section-level error: Section X is all turned to 0 / 1" is output to the upper computer; Block-level error: If the entire block of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a block-level error, and the statement "block-level error: block X is all turned to 0 / 1" is output to the upper computer; Bank-level error: If the entire bank of data is wrong and has the characteristics of all turning to 1 or all turning to 0, it is determined to be a Bank-level error and the statement "Bank-level error: BankX all turned to 0 / 1" is output to the host computer.

9. The method according to claim 5, characterized in that: The dynamic cycle erase-read-write mode includes: identifying various single particle effects according to the read error data in the read operation, and identifying the single particle function interruption occurring in the erase operation and the programming operation through the operation execution timeout phenomenon, including: During the erase operation, according to the normal erase time tERASE of the whole chip when there is no irradiation, the timing judgment condition is set in the FPGA module. If the erase operation time exceeds 2×tERASE during the irradiation process, the host computer will output "erase operation execution timeout", and the erase operation and subsequent dynamic cycle operations will continue after the reset operation. If the erase operation execution timeout phenomenon still occurs during the second erase operation, the dynamic cycle erase, read, write, and read operation and irradiation will be stopped, and the host computer will control the program-controlled power supply to power off the memory chip and FPGA board and end the test, otherwise the irradiation test will continue to the end of the injection amount; During the programming operation, select the data pattern to write into each address unit of the chip to be tested. According to the normal programming time tPROG of the whole chip when there is no irradiation, set the timing judgment condition in the FPGA module. If the programming operation time exceeds 2×tPROG during the irradiation process, the FPGA module will output "Programming operation execution timeout" to the upper computer, and continue to execute the programming operation and subsequent dynamic cycle operations after the reset operation. If the programming operation execution timeout phenomenon still occurs during the second execution of the programming operation, stop the dynamic cycle erase, read, write, read and irradiation, and the upper computer controls the program-controlled power supply to power off the memory chip and FPGA board and end the test, otherwise continue the irradiation test to the end of the injection amount; After reaching the end point of the irradiation injection, the dynamic cycle erase, read, write and read operations and irradiation are stopped, the test data is saved, and the upper computer controls the program-controlled power supply to cut off the power to the memory chip and FPGA board and end the test.

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