Memory chip, logic chip, chip stacking structure and memory

Abstract

The embodiment of the invention provides a memory chip, a logic chip, a chip stacking structure and a memory. The central point of the active surface of the memory chip and the adjacent region of the central point are defined as a global signal region; the global signal area is penetrated by n conductive through hole groups, and all conductive through holes in the same conductive through hole group are used for transmitting the same global signal; and the i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive through hole group through the i-th first OR logic circuit and send the i-th global signal to an internal circuit of the memory chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory chip, a logic chip, a chip stacking structure and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked using bonding processes (e.g., hybrid bonding, bump bonding, wire bonding) to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affects the quality of signal transmission. Summary of the invention

[0003] Embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory chip, wherein the center point of an active surface of the memory chip and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer;

[0005] The memory chip further includes n first OR logic circuits and n first driving circuits; the input end of the i-th first OR logic circuit is respectively coupled to all the conductive vias in the i-th conductive via group, and the output end of the i-th first OR logic circuit is coupled to the i-th first driving circuit; i is a positive integer less than or equal to n;

[0006] The i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th first OR logic circuit, and send the i-th global signal to the internal circuit of the memory chip;

[0007] Wherein, each of the conductive through-hole groups includes a first conductive through-hole, a second conductive through-hole, a third conductive through-hole and a fourth conductive through-hole, the first conductive through-hole and the second conductive through-hole are symmetrical about a first axis, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the first axis, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

[0008] In some embodiments, the first OR logic circuit includes a first OR gate, a second OR gate, and a third OR gate;

[0009] For the i-th first OR logic circuit, the first input terminal of the first OR gate is connected to the first conductive through hole in the i-th conductive through hole group, the second input terminal of the first OR gate is connected to the fourth conductive through hole in the i-th conductive through hole group, and the output terminal of the first OR gate is connected to the first input terminal of the third OR gate; the first input terminal of the second OR gate is connected to the second conductive through hole in the i-th conductive through hole group, the second input terminal of the second OR gate is connected to the third conductive through hole in the i-th conductive through hole group, and the output terminal of the second OR gate is connected to the second input terminal of the third OR gate; the output terminal of the third OR gate is used to output the global signal.

[0010] In some embodiments, each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0011] Among them, if the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be a low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

[0012] In some embodiments, the memory chip further includes n second driving circuits; the i-th second driving circuit is coupled to all the conductive vias in the i-th conductive via group;

[0013] The i-th second driving circuit is configured to send the i-th global signal generated inside the memory chip to all the conductive through holes coupled thereto.

[0014] In some embodiments, the conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same memory chip are electrically isolated from each other.

[0015] In a second aspect, an embodiment of the present disclosure provides a logic chip, wherein the center point of an active surface of the logic chip and an adjacent area thereof are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by n conductive via groups, and all conductive vias in the same conductive via group are used to transmit the same global signal; n is a positive integer;

[0016] Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis;

[0017] The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

[0018] In some embodiments, the logic chip further includes n third driving circuits;

[0019] The i-th third driving circuit is coupled to all the conductive vias in the i-th conductive via group; i is a positive integer less than or equal to n;

[0020] The i-th third driving circuit is configured to send the i-th global signal generated inside the logic chip to all the conductive through-holes coupled thereto.

[0021] In some embodiments, the logic chip further includes n second OR logic circuits and n fourth driving circuits; the input end of the i-th second OR logic circuit is respectively coupled to all the conductive vias in the i-th conductive via group, and the output end of the i-th second OR logic circuit is coupled to the i-th fourth driving circuit;

[0022] The i-th fourth driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th second OR logic circuit, and send the i-th global signal to the internal circuit of the logic chip.

[0023] In some embodiments, the second OR logic circuit includes a fourth OR gate, a fifth OR gate, and a sixth OR gate;

[0024] For the i-th second OR logic circuit, the first input terminal of the fourth OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the fourth OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the fourth OR gate is connected to the first input terminal of the sixth OR gate; the first input terminal of the fifth OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the fifth OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the fifth OR gate is connected to the second input terminal of the sixth OR gate; the output terminal of the sixth OR gate is used to output the global signal.

[0025] In some embodiments, each of the conductive vias is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0026] Among them, if the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be a low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

[0027] In some embodiments, the conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same logic chip are electrically isolated from each other.

[0028] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising a logic chip as described in any one of the second aspects and at least one stacking unit, wherein the logic chip and the at least one stacking unit are sequentially stacked along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked along the third direction, wherein the third direction is perpendicular to a top surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all memory chips as described in any one of the first aspects;

[0029] The first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner;

[0030] The first memory chip and the logic chip in the first stacking unit are stacked back to back, or the first memory chip and the logic chip in the first stacking unit are stacked back to back; the n conductive through-hole groups in the logic chip correspond one-to-one with the n conductive through-hole groups in each of the first memory chips, the n conductive through-hole groups in each of the second memory chips, the n conductive through-hole groups in each of the third memory chips, and the n conductive through-hole groups in each of the fourth memory chips, and are aligned along the third direction, and n is a positive integer.

[0031] In some embodiments, the global signal area in each chip is penetrated by n conductive via groups, each conductive via group includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about the second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip;

[0032] The first axes of the logic chip and each of the memory chips are aligned along the third direction, and the second axes of the logic chip and each of the memory chips are aligned along the third direction.

[0033] In some embodiments, when the logic chip and the first memory chip are stacked back to back,

[0034] The fourth conductive through hole in the i-th conductive through hole group in the logic chip, the first conductive through hole in the i-th conductive through hole group in each of the first memory chips, the second conductive through hole in the i-th conductive through hole group in each of the second memory chips, the third conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the fourth conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0035] The third conductive through hole in the i-th conductive through hole group in the logic chip, the second conductive through hole in the i-th conductive through hole group in each of the first memory chips, the first conductive through hole in the i-th conductive through hole group in each of the second memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the third conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0036] The second conductive through hole in the i-th conductive through hole group in the logic chip, the third conductive through hole in the i-th conductive through hole group in each of the first memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the second memory chips, the first conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the second conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0037] The first conductive through hole in the i-th conductive through hole group in the logic chip, the fourth conductive through hole in the i-th conductive through hole group in each of the first memory chips, the third conductive through hole in the i-th conductive through hole group in each of the second memory chips, the second conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the first conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0038] Here, i is a positive integer less than or equal to n.

[0039] In some embodiments, when the logic chip and the first memory chip are stacked back to back,

[0040] The second conductive through hole in the i-th conductive through hole group in the logic chip, the first conductive through hole in the i-th conductive through hole group in each of the first memory chips, the second conductive through hole in the i-th conductive through hole group in each of the second memory chips, the third conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the fourth conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0041] The first conductive through hole in the i-th conductive through hole group in the logic chip, the second conductive through hole in the i-th conductive through hole group in each of the first memory chips, the first conductive through hole in the i-th conductive through hole group in each of the second memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the third conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0042] The fourth conductive through hole in the i-th conductive through hole group in the logic chip, the third conductive through hole in the i-th conductive through hole group in each of the first memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the second memory chips, the first conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the second conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel;

[0043] The third conductive through hole in the i-th conductive through hole group in the logic chip, the fourth conductive through hole in the i-th conductive through hole group in each of the first storage chips, the third conductive through hole in the i-th conductive through hole group in each of the second storage chips, the second conductive through hole in the i-th conductive through hole group in each of the third storage chips, and the first conductive through hole in the i-th conductive through hole group in each of the fourth storage chips are aligned along the third direction and constitute a signal transmission channel.

[0044] In some embodiments, for two chips connected face to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias in the two chips aligned along the third direction are electrically connected by a conductive bump bonding process; or,

[0045] For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected by the hybrid bonding process; or,

[0046] For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected through the conductive bump bonding process.

[0047] In a fourth aspect, an embodiment of the present disclosure provides a memory, comprising a chip stacking structure as described in any one of the third aspects.

[0048] The embodiments of the present disclosure provide a memory chip, a logic chip, a chip stacking structure and a memory, which utilize conductive through holes with special symmetry to not only reduce the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip and the logic chip realizes a signal rotation transmission effect through the direct connection configuration of the conductive through holes, and also reduces parasitic resistance; further, all conductive through holes in the same conductive through hole group are utilized to transmit the same global signal, thereby achieving a repair effect; and the conductive through hole setting can achieve multi-point connection of the global signal with the least number of conductive through holes, thereby reducing the occupied area of ​​the global signal area and further reducing the area of ​​the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of the structure of a chip;

[0050] Figure 2A Schematic diagram of signal transmission in a chip stacking structure Figure 1 ;

[0051] Figure 2B A second schematic diagram of signal transmission of a chip stacking structure;

[0052] Figure 3 A schematic diagram of an active surface in a memory chip provided by an embodiment of the present disclosure;

[0053] Figure 4 A schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure Figure 1 ;

[0054] Figure 5 A second schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure;

[0055] Figure 6 A schematic diagram of the composition structure of a memory chip provided in an embodiment of the present disclosure Figure 3 ;

[0056] Figure 7 A schematic diagram of an active surface in a logic chip provided by an embodiment of the present disclosure;

[0057] Figure 8 A schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure Figure 1 ;

[0058] Fig. 9 A second schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure;

[0059] Fig.10 A schematic diagram of the structure of a logic chip provided in an embodiment of the present disclosure Figure 3 ;

[0060] Fig.11 A schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0061] Fig.12 A schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0062] Fig.13A / Fig. 13B A specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure Figure 1 ;

[0063] Fig.14A / Fig. 14B A second specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure;

[0064] Fig.15A / Fig. 15B A specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure Figure 3 ;

[0065] Fig.16A / Fig. 16B A specific schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure Figure 4 ;

[0066] Fig.17 A second schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure;

[0067] Fig.18 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0070] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0071] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0072] Before introducing the embodiments of the present disclosure, three directions that may be used to describe the three-dimensional structure of the plane involved in the following embodiments are defined first. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0073] See also Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, a direction intersecting (e.g., perpendicular) the top surface and the bottom surface of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two directions perpendicular to each other are defined, namely, a first direction and a second direction, and the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0074] See also Figure 1 The semiconductor chip includes a substrate, one side of which is used to make devices (such as transistors, capacitors, etc.) and forms an active surface (the side of the substrate opposite to the active surface is a non-active surface, i.e. Figure 1 There are multiple metal layers between the substrate and the top surface, such as M1, M2, M3... Figure 1 Also shown are two types of conductive vias (eg, through silicon vias), both used to achieve signal connections between different stacked chips.

[0075] like Figure 1 As shown, for the type 1 conductive via, it penetrates the bottom surface and the top surface along the third direction, and the conductive via is connected to the internal circuit of the chip through the metal layer.

[0076] like Figure 1 As shown, for the conductive via of type 2, it only penetrates the substrate along the third direction (through the active surface and the bottom surface), and needs to cooperate with the contact structure that penetrates the top surface along the third direction to realize signal transmission; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1 The contact structure in is connected to M4, M4 is connected to M1 via M3 and M2 in sequence, and M1 is connected to the conductive through hole; or, Figure 1 The conductive vias in the chip are connected to the internal circuits via M1-M4 ( Figure 1The output signal processed by the chip internal circuit is then output to the corresponding contact structure through the metal layers M1-M4. Figure 1 The contact structure in can also be connected to the internal circuit of the chip via M1-M4 ( Figure 1 The output signal processed by the chip internal circuit is then output to the corresponding conductive via via M1-M4. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0077] Meanwhile, the types of conductive vias are not limited to the above two types, which are only examples. In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the drawings are not necessarily drawn to scale.

[0078] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0079] In one embodiment, a memory chip and a logic chip are provided, each of which includes a plurality of conductive vias penetrating the chip along a third direction, the conductive vias being used to achieve signal transmission between different chips, and all the conductive vias can be located at any position. In particular, every four conductive vias can be functionally regarded as a conductive via group, but the positions of the four conductive vias are not limited.

[0080] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device, and the conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Figure 2A , which shows a schematic diagram of signal transmission of a chip stacking structure Figure 1 .like Figure 2A As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2A Only four conductive through holes D0 to D3 are shown for each memory chip, and these four conductive through holes D0 to D3 belong to the same conductive through hole group. At this time, the conductive through holes D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive through holes D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... and the remaining conductive through holes are similar.

[0081] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits ( Figure 2A Only one of the driving circuits is shown in a dotted box, and the rest of the driving circuits are not framed), and each conductive through hole is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 2A Each conductive via group corresponds to a data selector, that is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective driving circuits. In other words, the data selector can select which conductive via transmits the signal to be output to the inside of the memory chip or which conductive via transmits the signal output by the memory chip to be input to.

[0082] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management, and the signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive through hole D0 in the logic chip, conductive through hole D0 in memory chip 0 - conductive through hole D0 in memory chip 1 - conductive through hole D0 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D0 in memory chip 4 - conductive through hole D0 in memory chip 5 - conductive through hole D0 in memory chip 6 - conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 via the aforementioned electrical path; the output process of the signal can be understood similarly.

[0083] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1... That is, each memory chip only needs to obtain signals from one of the conductive vias in a conductive via group. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using Figure 2A In the chip stacking structure shown, each conductive through hole corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel, and the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases the power consumption, and also restricts the number of chip stacks in the three-dimensional device.

[0084] In another embodiment, see Figure 2B , which shows a second schematic diagram of signal transmission of a chip stacking structure. In particular, Figure 2B Only some conductive vias are marked (D0 to D3), and the others are omitted. Figure 2BFor example, the conductive vias aligned along the third direction have the same identifier. Figure 2B As shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through hole in each memory chip is rotationally connected to another conductive through hole at a different position in another memory chip, and a spiral ascending connection is realized as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through hole D0 in the logic chip - conductive through hole D1 in memory chip 0 - conductive through hole D2 in memory chip 1 - conductive through hole D3 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D1 in memory chip 4 - conductive through hole D2 in memory chip 5 - conductive through hole D3 in memory chip 6 - conductive through hole D0 in memory chip 7", and the other signals are similar.

[0085] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of conductive via D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of conductive via D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of conductive via D0 in memory chip 1, memory chip 3 can obtain signal Signal_CH5 through the input end of conductive via D0 in memory chip 2... For each memory chip, only one conductive via in each conductive via group is required to connect to the drive circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2A The conductive through-hole direct connection configuration, Figure 2B The process of rotating the conductive through hole is more complicated. Specifically, Figure 2B A horizontal interconnection structure ( Figure 2B Only one of them is marked with a five-pointed star), the signal interconnection structure can be a metal interconnection line, a conductive through hole, etc. In order to realize the rotation connection of the conductive through hole, the input signal signal_CH0 must first be transmitted upward from the conductive through hole D0 of the logic chip to the interconnection structure below the conductive through hole D0 of the memory chip 0 (not connected to the conductive through hole D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive through hole D0 of the memory chip 0 to the conductive through hole D1 of the memory chip 0. That is: Figure 2B The structure shown in the figure also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0086] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are actively facing upward, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0087] In summary, on the one hand, Figure 2A The chip stacking structure requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 2A and Figure 2B There are certain problems with the stacking structure, and it cannot be directly applied to the face-to-face stacking structure. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as the active side up and the active side down. This method has high process complexity and uncontrollable cost; another way is to make an extra set of conductive vias and connect the two sets of conductive vias to the same drive circuit in the memory chip, but this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity, but also increase power consumption.

[0088] Therefore, the embodiments of the present disclosure propose a storage chip, a logic chip, a chip stacking structure and a memory. The chip stacking structure not only has smaller parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method. In particular, the embodiments of the present disclosure also provide a related mechanism for global signal redundancy repair under this structure.

[0089] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0090] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of an active surface in a memory chip provided by an embodiment of the present disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. Figure 3 As shown, the memory chip 10 includes m channels (m is a positive integer, Figure 3 Taking m=4 as an example for illustration), m channels are arranged in sequence along the first direction, each channel includes a first storage array area, a channel signal area, and a second storage array area distributed in sequence along the second direction, and the center of each channel signal area coincides with the center of the channel to which it belongs.

[0091] It should be noted that during the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made in the reference channel (for example, the first channel) of the storage chip 10, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and other channels can be identified in combination with the active surface orientation of the chip.

[0092] Figure 3 The illustration is made by taking m=4 as an example, and the following description is also made by taking m=4 as an example, but m can be any positive integer.

[0093] like Figure 3 As shown, the center point of the active surface of the memory chip 10 and its adjacent area are defined as a global signal area 11 , and the center point of the global signal area 11 coincides with the center point of the active surface; the m channels are symmetrical about the global signal area 11 .

[0094] It should be noted that both the global signal area 11 and the channel signal area are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface. Here, the conductive via can be a through silicon via (TSV), which is specifically a vertical interconnection structure that penetrates a silicon wafer / chip, or, in other embodiments, it can also be other conductive vias with conductive functions, which are not specifically limited. In addition, the conductive via can be in the form of the aforementioned type 1, or in the form of the aforementioned type 2.

[0095] For the global signal area 11, each conductive through-hole is used to transmit a global signal, and the global signal is shared by all areas of the corresponding memory chip 10. Global signals include, but are not limited to, command signals Command and address signals Address. In some cases, the global signal area 11 may also refer to a pad area. The global signal may be a test signal of the Design For Test (DFT), through which the working status of the internal circuit of the chip and the transmission status of related signals can be known. In addition, because the pin pads (PADs) of the DFT in the memory chip 10 are generally located in the middle of the chip, the conductive through-holes of global signals such as the DFT are preferably located in a narrower area in the middle of the chip, such as Figure 3 The location of the global signal area 11 is shown.

[0096] For the channel signal area, each conductive via is used to transmit the channel signal, and the signal transmitted by each channel signal area is only used by the corresponding channel. The conductive vias in each channel signal area are for their own channel signal area, and only the local memory chip 10 (corresponding channel) will use the conductive vias; while the conductive vias in the global signal area 11 located in the middle of the memory chip 10 are used to test the entire memory chip 10, and the signals transmitted by the global signal area 11 are used by the m channels of the memory chip 10.

[0097] See also Figure 3For the active surface of the memory chip 10, there are a first axis AA' and a second axis BB', the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface, the first axis AA' is parallel to the first side of the memory chip 10, and the second axis BB' is parallel to the second side of the memory chip 10. Figure 3 In the embodiment, the first axis AA' may extend along the first direction, and the second axis BB' may extend along the second direction. In other embodiments, the first axis AA' may extend along the second direction, and the second axis BB' may extend along the first direction. This is not specifically limited.

[0098] Further, see Figure 4 , which shows a schematic diagram of the composition structure of a memory chip provided by an embodiment of the present disclosure Figure 1 .like Figure 4 As shown, in the memory chip 10, the global signal area is divided into n conductive via groups 20 ( Figure 4 Only one conductive via group 20 is shown, and the rest are omitted), and all conductive vias in the same conductive via group 20 are used to transmit the same global signal; n is a positive integer; each conductive via group 20 includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3.

[0099] In particular, Figure 4 It can be regarded as a cross-section diagram of the memory chip 10 along the active surface. Figure 4 For the same conductive via group 20 , the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA′, the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA′, and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB′.

[0100] like Figure 4 As shown, in one possibility, the memory chip 10 further includes n first OR logic circuits 30 and n first drive circuits 40 ( Figure 4 Only one first OR logic circuit 30 and one first driving circuit 40 are shown, and the rest are omitted); the input end of the i-th first OR logic circuit 30 is coupled to all the conductive through holes in the i-th conductive through hole group 20, and the output end of the i-th first OR logic circuit 30 is coupled to the i-th first driving circuit 40; i is a positive integer less than or equal to n;

[0101] The i-th first driving circuit 40 is configured to receive the i-th global signal from the i-th conductive via group 20 via the i-th first OR logic circuit 30 , and send the i-th global signal to the internal circuit of the memory chip 10 .

[0102] It should be noted that the n first OR logic circuits 30 and the n first driving circuits 40 correspond one-to-one to the n conductive through-hole groups 20 .

[0103] It should also be noted that the positions of the conductive via groups 20 in the global signal area are different. Specifically, the number and position of the conductive via groups 20 can be adjusted according to actual conditions, and there is no limitation on this. However, the number of conductive vias in each conductive via group 20 must be the same, and the above-mentioned symmetrical distribution rule must be followed. The following description is based on an example in which the global signal area is penetrated by one conductive via group 20, and the number of conductive vias in the conductive via group 20 is 4.

[0104] It can be understood that the numbering sequence of the conductive vias in each conductive via group 20 does not constitute any limitation.

[0105] Specifically, the first OR logic circuit 30 can be coupled to the active surface portion of all the conductive vias in the same conductive via group 20. That is, for each memory chip 10, all the conductive vias in each conductive via group 20 are coupled to the corresponding first OR logic circuit 30, and the first OR logic circuit 30 is coupled to the corresponding first driving circuit 40, and the global signal transmitted by the conductive via group 20 will enter the memory chip 10 through the first OR logic circuit 30 and the first driving circuit 40 coupled to the corresponding first OR logic circuit 30.

[0106] It should be noted that the driving circuit may include an input driving branch (Receive, RX) and / or an output driving branch (Transmit, TX). Figure 4 As shown, the first driving circuit 40 includes an input driving branch, which sends the global signal output by the corresponding coupled conductive via group 20 to the internal circuit of the memory chip 10 .

[0107] It should also be noted that the conductive vias mentioned above can at least be embodied as through silicon vias, which are specifically a vertical interconnect structure penetrating a silicon wafer / memory chip, for example Figure 1 Type 1 in the diagram; of course, conductive vias can also be Figure 1 Type 2 in the embodiment, which realizes signal transmission together with the contact structure. In other embodiments, other electrical connection structures can also be selected as the conductive through hole.

[0108] In this embodiment, for the same conductive via group 20 of the memory chip 10, each conductive via transmits exactly the same signal, that is, a signal of the same transmission type and signal value, and further transmits it to the internal circuit of the memory chip 10. Therefore, in this case, each conductive via group 20 only needs one first driving circuit 40 to drive the signal. In addition, a driving circuit may also be included between the first OR logic circuit 30 and all the conductive vias in the conductive via group 20 to drive the global signal, which is not specifically limited.

[0109] For the first OR logic circuit 30, see Figure 5 , which shows a second schematic diagram of the composition structure of a memory chip provided by an embodiment of the present disclosure. Figure 5 As shown, in some embodiments, the first OR logic circuit 30 may include a first OR gate 301, a second OR gate 302, and a third OR gate 303;

[0110] For the i-th first OR logic circuit 30, the first input terminal of the first OR gate 301 is connected to the first conductive through hole D0 in the i-th conductive through hole group 20, the second input terminal of the first OR gate 301 is connected to the fourth conductive through hole D3 in the i-th conductive through hole group 20, and the output terminal of the first OR gate 301 is connected to the first input terminal of the third OR gate 303; the first input terminal of the second OR gate 302 is connected to the second conductive through hole D1 in the i-th conductive through hole group 20, the second input terminal of the second OR gate 302 is connected to the third conductive through hole D2 in the i-th conductive through hole group 20, and the output terminal of the second OR gate 302 is connected to the second input terminal of the third OR gate 303; the output terminal of the third OR gate 303 is used to output a global signal.

[0111] In addition, see, for example, Figure 5 In some embodiments, a DFT pin pad (DFT PAD, PAD for short) is placed on the second axis BB', so conductive vias cannot be placed, and each conductive via can only be placed symmetrically on both sides of the DFT PAD.

[0112] Furthermore, if Figure 5 As shown, in some embodiments, each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0113] If the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

[0114] It should be noted that the resistance of the resistor in the weak ground terminal is relatively large, and the specific value of the resistance is not specifically limited. In addition, the weak ground terminal can be represented by weak pull "0".

[0115] exist Figure 4 Based on Figure 6 , which shows a schematic diagram of the composition structure of a memory chip provided by an embodiment of the present disclosure Figure 3 .like Figure 6 As shown, in another possibility, the memory chip 10 further includes n second driving circuits 41; the i-th second driving circuit 41 is coupled to all the conductive vias in the i-th conductive via group 20 ( Figure 6 Only one conductive through hole group 20 and one second driving circuit 41 are shown, and the rest are omitted);

[0116] The i-th second driving circuit 41 is configured to send the i-th global signal generated inside the memory chip 10 to all conductive vias coupled thereto.

[0117] Specifically, the second driving circuit 41 can be coupled to the active surface portion of each conductive via in the corresponding conductive via group 20. That is, for the memory chip 10, each conductive via in its conductive via group 20 is connected to the same second driving circuit 41, and the global signal is output from the inside of the memory chip 10 and sent to all the conductive vias coupled thereto.

[0118] For example, Figure 6 As shown, the second driving circuit 41 includes an output driving branch, which outputs the global signal generated by the internal circuit of the memory chip 10 to the corresponding coupled conductive via group 20. In particular, the input driving branch and the output driving branch in the remaining figures will not be marked. Figure 6 Develop adaptive understanding.

[0119] In some embodiments, each conductive via in the memory chip 10 can be prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same memory chip 10 are electrically isolated from each other.

[0120] Among them, the through-hole-first process refers to a through-hole process method that manufactures a through-hole structure before manufacturing a device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET or MOS tube for short). The intermediate through-hole process is a through-hole structure formed during the manufacturing process of the process flow, and is often a through-hole process manufactured after the device is formed and before the stack is manufactured. The through-hole-last process is a manufacturing process that forms a through-hole from the front side of the wafer after the back-end of line (BEOL) process is completed. The back through-hole process is a manufacturing process that forms a through-hole structure from the back side of the wafer after the BEOL process is completed. In other words, the through-hole-first process can refer to making a through-hole first and then making a circuit, for example Figure 1 Conductive vias of type 1; the intermediate via process can refer to making the circuit and part of the metal layer first, then making the vias, and finally making the remaining vias, for example Figure 1 Conductive vias of type 2; via-last process and via-behind process can refer to making the circuit and metal layers first and then making the vias, for example Figure 1 Type 2 conductive via.

[0121] The present disclosure provides a memory chip, wherein the conductive through hole has a special symmetry, and can be directly applied to a stacked structure formed in any manner such as face-to-face / back-to-back / face-to-back, without the need for two sets of masks or two sets of conductive through holes; in addition, there is no need to set a data selector for conductive through hole selection, which can reduce the number of devices, thereby reducing the number of devices compared to the conventional memory chip. Figure 1 The memory chip reduces parasitic capacitance, which not only saves circuit area but also reduces chip manufacturing cost; the subsequent memory chip 10 can also be compared to Figure 2A and Figure 2B The parasitic resistance of the memory chip is reduced (for specific reasons, please refer to the subsequent description). Furthermore, the structure of transmitting global signals through a conductive through-hole group with 4-quadrant symmetry (that is, the conductive through-hole group is symmetrical about the first axis and also about the second axis) can ensure that the memory chips flipped to different positions can receive the same global signal output by the logic chip. At the same time, the 4 transmission paths formed by the 4 conductive through-holes in the conductive through-hole group can be used to form a 4-dummy structure, which ensures the accuracy of signal transmission and saves the relevant circuit area for redundant repair and the test time of the conductive through-hole transmission path.

[0122] In another embodiment of the present disclosure, see Figure 7 , which shows a schematic diagram of an active surface in a logic chip provided by an embodiment of the present disclosure. Figure 7As shown, the center point of the active surface of the logic chip 50 and its adjacent signal area are defined as a global signal area 11 . The center point of the global signal area 11 coincides with the center point of the active surface. Channel signal areas are distributed on both sides of the global signal area 11 .

[0123] The global signal area 11 and the channel signal area are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface. In addition, because the PAD in the logic chip 50 is generally located in the middle of the chip, the conductive vias of global signals such as DFT are preferably located in a narrow area in the middle of the chip, that is, Figure 7 The location of the global signal area 11 is shown.

[0124] In addition, the areas of the logic chip 50 and the memory chip 10 may be the same or different, which is not specifically limited, but the global signal regions in both are located in the middle of their respective chips, and the areas of the two global signal regions are the same.

[0125] See also Figure 7 For the active surface of the logic chip 50, there are a first axis AA' and a second axis BB', the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface, the first axis AA' is parallel to the first side of the logic chip 50, and the second axis BB' is parallel to the second side of the logic chip 50. Figure 7 In the embodiment, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation.

[0126] See also Figure 8 , which shows a schematic diagram of the composition structure of a logic chip provided by an embodiment of the present disclosure Figure 1 .like Figure 8 As shown, in the logic chip 50, the global signal area is divided by n conductive via groups 60 ( Figure 8 Only one conductive via group 60 is shown, and the rest are omitted), and all conductive vias in the same conductive via group 60 are used to transmit the same global signal; n is a positive integer; each conductive via group 60 includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3.

[0127] In particular, Figure 8 It can be regarded as a schematic cross-section of the logic chip 50 along the active surface. Figure 8 For the same conductive via group 60 , the first conductive via D0 and the second conductive via D1 are symmetrical about the first axis AA′, the third conductive via D2 and the fourth conductive via D3 are symmetrical about the first axis AA′, and the first conductive via D0 and the fourth conductive via D3 are symmetrical about the second axis BB′.

[0128] It should be noted that the positions of the conductive via groups 60 in the global signal area are different. Specifically, the number and position of the conductive via groups 60 can be adjusted according to actual conditions, and there is no limitation on this. However, the number of conductive vias in each conductive via group 60 must be the same, and the above-mentioned symmetrical distribution rule must be followed. The following is an example in which the global signal area is penetrated by one conductive via group 60, and the number of conductive vias in the conductive via group 60 is 4.

[0129] It can be understood that the numbering sequence of the conductive vias in each conductive via group 60 does not constitute any limitation.

[0130] like Figure 8 As shown, in one possibility, the logic chip 50 further includes n third driving circuits 70 ( Figure 8 Only one third driving circuit 70 is shown, and the rest are omitted);

[0131] The i-th third driving circuit 70 is coupled to all the conductive vias in the i-th conductive via group 60; i is a positive integer less than or equal to n;

[0132] The i-th third driving circuit 70 is configured to send the i-th global signal generated inside the logic chip 50 to all conductive vias coupled thereto.

[0133] It can be understood that the i-th third driving circuit 70 is configured to send the i-th global signal generated inside the logic chip 50 to all the conductive vias in the i-th conductive via group.

[0134] Here, the n third driving circuits 70 correspond one-to-one to the n conductive via groups 60 .

[0135] Specifically, the third driving circuit 70 can be coupled to the active surface portion of each conductive via in the corresponding conductive via group 60. That is, for the logic chip 50, each conductive via in its conductive via group 60 is connected to the same third driving circuit 70, and the global signal is output from the inside of the logic chip 50 and sent to all the conductive vias coupled thereto.

[0136] like Figure 8 As shown, the third driving circuit 70 includes an output driving branch, which outputs the global signal generated by the internal circuit of the logic chip 50 to the corresponding coupled conductive via group 60 .

[0137] It should be noted that, in this embodiment, for the same conductive via group 60 of the logic chip 50, each conductive via transmits exactly the same signal, that is, a signal with the same transmission type and signal value, and further transmits it to different memory chips 10. Therefore, in this case, each conductive via group 60 only needs one third driving circuit 70 to drive the signal.

[0138] exist Figure 8 Based on Fig. 9 , which shows a schematic diagram of the second structure of a logic chip provided by an embodiment of the present disclosure. Fig. 9 As shown, in another possibility, the logic chip 50 may also include n second OR logic circuits 71 and n fourth drive circuits 72 ( Fig. 9 Only one second OR logic circuit 71 and one fourth drive circuit 72 are shown, and the rest are omitted); the input end of the i-th second OR logic circuit 71 is respectively coupled to all the conductive through holes in the i-th conductive through hole group 60, and the output end of the i-th second OR logic circuit 71 is coupled to the i-th fourth drive circuit 72;

[0139] The i-th fourth driving circuit 72 is configured to receive the i-th global signal from the i-th conductive via group 60 via the i-th second OR logic circuit 71 , and send the i-th global signal to the internal circuit of the logic chip 50 .

[0140] It should be noted that the n second OR logic circuits 71 and the n fourth driving circuits 72 correspond to the n conductive through-hole groups 60 one by one.

[0141] Specifically, the second OR logic circuit 71 can be coupled to the active surface portion of all the conductive vias in the same conductive via group 60. That is, for the logic chip 50, all the conductive vias in each conductive via group 60 are coupled to the corresponding second OR logic circuit 71, and the second OR logic circuit 71 is coupled to the corresponding fourth driving circuit 72, and the global signal transmitted by the conductive via group 60 will enter the logic chip 50 via the second OR logic circuit 71 and the fourth driving circuit 72 coupled to the corresponding second OR logic circuit 71.

[0142] like Fig. 9 As shown, the fourth driving circuit 72 includes an input driving branch, which sends the global signal output by the corresponding coupled conductive via group 60 to the internal circuit of the logic chip 50. In addition, a driving circuit may also be included between the second OR logic circuit 71 and all the conductive vias in the conductive via group 60 to drive the global signal, which is not specifically limited.

[0143] For the second OR logic circuit 71, see Fig.10, which shows a schematic diagram of the composition structure of a logic chip provided by an embodiment of the present disclosure Figure 3 .like Fig.10 As shown, in some embodiments, the second OR logic circuit 71 may include a fourth OR gate 711, a fifth OR gate 712, and a sixth OR gate 713;

[0144] For the i-th second OR logic circuit 71, the first input terminal of the fourth OR gate 711 is connected to the first conductive through hole D0 in the i-th conductive through hole group 60, the second input terminal of the fourth OR gate 711 is connected to the fourth conductive through hole D3 in the i-th conductive through hole group 60, and the output terminal of the fourth OR gate 711 is connected to the first input terminal of the sixth OR gate 713; the first input terminal of the fifth OR gate 712 is connected to the second conductive through hole D1 in the i-th conductive through hole group 60, the second input terminal of the fifth OR gate 712 is connected to the third conductive through hole D2 in the i-th conductive through hole group 60, and the output terminal of the fifth OR gate 712 is connected to the second input terminal of the sixth OR gate 713; the output terminal of the sixth OR gate 713 is used to output a global signal.

[0145] Furthermore, if Fig.10 As shown, in some embodiments, each conductive via is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal;

[0146] If the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

[0147] In the embodiment of the present disclosure, when the global signal is transmitted from the memory chip 10 to the logic chip 50, because each conductive via in the logic chip 50 is connected to the weak ground terminal, that is, the default level value of each conductive via is 0, as long as one of the signal transmission channels formed by the four conductive vias can transmit signal data normally, even if some of the conductive vias are disconnected (Open), it will not affect the final signal reception, that is, a 4-dummy signal transmission architecture is formed.

[0148] It should be noted that when multiple memory chips send global signals to the logic chip 50, it is possible that memory chip 0 (i.e., the first memory chip 11 in the chip stacking structure 80 described below) and memory chip 3 (i.e., the fourth memory chip 14 in the chip stacking structure 80 described below) will pass through the same conductive via. At this time, in order to distinguish from which conductive via the global signal is sent, the logic chip 50 can use the following mechanism to make a judgment: if the logic chip 50 needs to receive a global signal from a certain memory chip, the logic chip 50 will first send an enable signal, for example, send an enable signal to the first memory chip 11, and then the global signal received from the first conductive via D0 or the fourth conductive via D3 will be known to be sent by the first memory chip 11; send an enable signal to the fourth memory chip 14, and then the global signal received from the first conductive via D0 or the fourth conductive via D3 will be known to be sent by the fourth memory chip 14, but this is not specifically limited. In addition, when multiple memory chips transmit global signals to the logic chip 50 , only one output driving branch included in the first driving circuit 40 in all memory chips is enabled at the same time, that is, only one memory chip transmits a global signal to the logic chip 50 at the same time.

[0149] It should be noted that, in some embodiments, global signals can be transmitted bidirectionally, that is, they can be transmitted from the logic chip 50 to the memory chip 10, and can also be transmitted from the memory chip 10 to the logic chip 50, such as the CP_DQ signal, which is a signal representing the success (pass) or failure (fail) of the chip test result, but this is not specifically limited.

[0150] In some embodiments, each conductive via in the logic chip 50 can be prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same logic chip 50 are electrically isolated from each other.

[0151] The embodiment of the present disclosure provides a logic chip, and the arrangement position of the conductive through holes in the logic chip and the aforementioned memory chip is the same. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0152] In another embodiment of the present disclosure, see Fig.11 , which shows a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure. Fig.11 As shown, the chip stacking structure 80 includes a logic chip 50 and at least one stacking unit ( Fig.11Only two stacking units are shown, and the rest are omitted), and the logic chip 50 and at least one stacking unit are stacked in sequence along the third direction; each stacking unit includes a first memory chip 11, a second memory chip 12, a third memory chip 13 and a fourth memory chip 14 stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each memory chip; the structures of the first memory chip 11, the second memory chip 12, the third memory chip 13 and the fourth memory chip 14 are all the aforementioned memory chips 10, and the structure of the logic chip 50 is the aforementioned logic chip 50. In particular, in Fig.11 In the figure, the portion shown is only the global signal area 11 of each chip, rather than the entire active surface.

[0153] For each stacking unit, the first memory chip 11 and the second memory chip 12 are stacked face to face, the second memory chip 12 and the third memory chip 13 are stacked back to back, and the third memory chip 13 and the fourth memory chip 14 are stacked face to face; the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to back, or the first memory chip 11 and the logic chip 50 in the first stacking unit are stacked back to back.

[0154] In the disclosed embodiments, face-to-face stacking means that the top surfaces of the two chips are approximately aligned along the third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surfaces are all aligned along the third direction; back-to-back stacking means that the bottom surfaces of the two chips are approximately aligned along the third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. When the logic chip or memory chip is not specified, "chip" can refer to both the logic chip and the memory chip.

[0155] n conductive via groups in the logic chip 50 ( Fig.11 Only one conductive through-hole group is shown, and the rest are omitted), which corresponds one by one to the n conductive through-hole groups in each first memory chip 11, the n conductive through-hole groups in each second memory chip 12, the n conductive through-hole groups in each third memory chip 13, and the n conductive through-hole groups in each fourth memory chip 14, and are aligned along the third direction, and n is a positive integer.

[0156] It should also be noted that due to process errors, the "alignment" in this article is not an absolute alignment, and any deviation within a reasonable range can be considered as alignment.

[0157] In the embodiment of the present disclosure, the chip stacking structure 80 may be a high bandwidth memory (HBM) stacking product, and particularly relates to the design of a repair pattern of multiple (Multidrop) conductive vias in the global signal area of ​​each chip under the condition of 4-quadrant symmetry in each chip (i.e., the conductive via group is symmetrical about the first axis and also about the second axis), and utilizes the face-to-face and back-to-back symmetry between multiple conductive vias and each chip, and is applied to signal transmission through multiple conductive vias, such as command signal Command, address signal Address, etc., and is not specifically limited to this. Here, the memory chip can be represented by Core die, and the logic chip can be represented by Base die.

[0158] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding (Hyperbonding, also known as bonding column) process; for two chips connected back to back or back to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a conductive bump (UBump, also known as micro-bump) bonding process.

[0159] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding process.

[0160] In another possibility, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are electrically connected through a conductive bump bonding process.

[0161] Here, the above chip may refer to a logic chip 50 or a memory chip 10 .

[0162] It should be noted that, compared with the conductive bump bonding process, the face-to-face connection using the hybrid bonding process can make the adjacent memory chips fit more closely, with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, the two memory chips connected back to back can also be electrically connected through the hybrid bonding process, but its connection performance is weaker than that of the case where the electrical connection is achieved through the conductive bump process. In this way, in the embodiment of the present disclosure, the chip stacking structure supports face-to-face stacking and has better performance.

[0163] exist Fig.11Based on Fig.12 , which shows a signal transmission schematic diagram of a chip stacking structure provided by an embodiment of the present disclosure Figure 1 . Fig.12 Only the signal transmission path of one conductive through hole group and two stacking units (i.e., eight memory chips) is shown as an example. However, in fact, the chip stacking structure can have three, four, etc., multiple stacking units, and each stacking unit has similar signal transmission characteristics. The signal transmission conditions of the remaining stacking units are no longer shown. Please refer to the following text and Fig.12 Develop adaptive understanding.

[0164] Specifically, Fig.12 . . , which shows how a global signal is transmitted from the logic chip 50 to each memory chip.

[0165] It should be noted that Fig.12 The "OR" in represents each OR gate in the first OR logic circuit. In addition, Fig.12 It is used to emphasize the alignment relationship between signal areas and conductive vias along the third direction, but it does not represent its real structure, that is, the oblique striped column may not correspond to any physical structure; or, in some working scenarios, Fig.12 The oblique striped columns between the chips can be understood as conductive bumps, hybrid bonding structures, etc., which realize the connection of conductive through holes between different memory chips.

[0166] It should also be noted that, because each conductive via in each memory chip is connected to the weak ground terminal, that is, the default level value of each conductive via is 0, as long as one of the signal transmission channels formed by the four conductive vias can transmit signal data normally, even if some of the conductive vias are disconnected (Open), it will not affect the final signal reception, that is, a 4-dummy signal transmission architecture is formed.

[0167] In some embodiments, the global signal area in each chip is penetrated by n conductive through-hole groups, each conductive through-hole group includes a first conductive through-hole D0, a second conductive through-hole D1, a third conductive through-hole D2 and a fourth conductive through-hole D3, the first conductive through-hole D0 and the second conductive through-hole D1 are symmetrical about the first axis AA', the third conductive through-hole D2 and the fourth conductive through-hole D3 are symmetrical about the first axis AA', and the first conductive through-hole D0 and the fourth conductive through-hole D3 are symmetrical about the second axis BB'; the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface, the first axis AA' is parallel to the first side of the memory chip, and the second axis BB' is parallel to the second side of the memory chip;

[0168] The first axes AA′ of the logic chip 50 and each memory chip are aligned along the third direction, and the second axes BB′ of the logic chip 50 and each memory chip are aligned along the third direction.

[0169] It should be understood that the logic chip 50 or each memory chip can be divided into a high-order transmission area and a low-order transmission area. Figures 13A to 16B The arrows are uniformly located in the high-order transmission area of ​​the chip. In particular, the high-order transmission area and the low-order transmission area in the embodiment of the present disclosure are only two areas to distinguish the logic chip 50 or each memory chip, and do not have any additional restrictions, and may not be directly related to the high-order data and low-order data commonly mentioned in data transmission. In addition, Figures 11 to 17 Only one conductive via group in the global signal area is shown as an example, but in fact there are multiple conductive via groups in the global signal area, and different conductive via groups have similar alignment characteristics. The alignment of the remaining conductive vias is no longer shown. Please refer to the following text description, Figures 11 to 17 Develop adaptive understanding.

[0170] It should be noted that the top surface of the logic chip 50 or each memory chip is divided into 2×2 signal areas, namely the first signal area, the second signal area, the third signal area and the fourth signal area, which are represented by C, D, E and F. Among them, the first signal area (C) and the second signal area (D) are symmetrical along their first axis AA', the first signal area (C) and the fourth signal area (F) are symmetrical along their second axis BB', and the third signal area (E) and the fourth signal area (F) are symmetrical along their first axis AA'; the first axis AA' of the logic chip 50 and each memory chip is aligned along the third direction, and the second axis BB' of the logic chip 50 and each memory chip is aligned along the third direction.

[0171] It should be noted that the first conductive through hole D0 in each conductive through hole group is located in the first signal area (C), the second conductive through hole D1 in each conductive through hole group is located in the second signal area (D), the third conductive through hole D2 in each conductive through hole group is located in the third signal area (E), and the fourth conductive through hole D3 in each conductive through hole group is located in the fourth signal area (F).

[0172] When the logic chip 50 and the first memory chip 11 are stacked back to back and the logic chip 50 is placed in the same manner as the fourth memory chip 14, a first specific implementation method and a second specific implementation method are provided; when the logic chip 50 and the first memory chip 11 are stacked back to back and the logic chip 50 is placed in the same manner as the second memory chip 12, a third specific implementation method and a fourth specific implementation method are provided, and the specific descriptions are as follows.

[0173] In the first specific embodiment, Fig.13A As shown, assuming that the first axis AA' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the first axis AA' extends along the first direction), the high-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0174] In the second specific embodiment, Fig.14A As shown, assuming that the second axis BB' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the second axis BB' extends along the first direction), the high-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the low-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0175] See also Fig.13A or Fig.14A For the first and second specific embodiments, each signal region has the following alignment relationship:

[0176] (1) the fourth signal area (F) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0177] (2) the third signal area (E) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction;

[0178] (3) the second signal area (D) of the logic chip 50, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction;

[0179] (4) The first signal area (C) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0180] It should also be noted that each conductive via group of the logic chip 50 and each memory chip includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 distributed in a 2×2 array.

[0181] See also Fig. 13B or Fig. 14B For the first and second specific embodiments, only for the multiple signal areas aligned along the third direction, each conductive through hole has the following alignment relationship:

[0182] (1) the fourth conductive through hole D3 in the i-th conductive through hole group in the logic chip 50, the first conductive through hole D0 in the i-th conductive through hole group in each first memory chip 11, the second conductive through hole D1 in the i-th conductive through hole group in each second memory chip 12, the third conductive through hole D2 in the i-th conductive through hole group in each third memory chip 13, and the fourth conductive through hole D3 in the i-th conductive through hole group in each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0183] (2) the third conductive through hole D2 in the i-th conductive through hole group in the logic chip 50, the second conductive through hole D1 in the i-th conductive through hole group in each first memory chip 11, the first conductive through hole D0 in the i-th conductive through hole group in each second memory chip 12, the fourth conductive through hole D3 in the i-th conductive through hole group in each third memory chip 13, and the third conductive through hole D2 in the i-th conductive through hole group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0184] (3) the second conductive through hole D1 in the i-th conductive through hole group in the logic chip 50, the third conductive through hole D2 in the i-th conductive through hole group in each first memory chip 11, the fourth conductive through hole D3 in the i-th conductive through hole group in each second memory chip 12, the first conductive through hole D0 in the i-th conductive through hole group in each third memory chip 13, and the second conductive through hole D1 in the i-th conductive through hole group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0185] (4) The first conductive through hole D0 in the i-th conductive through hole group in the logic chip 50, the fourth conductive through hole D3 in the i-th conductive through hole group in each first storage chip 11, the third conductive through hole D2 in the i-th conductive through hole group in each second storage chip 12, the second conductive through hole D1 in the i-th conductive through hole group in each third storage chip 13, and the first conductive through hole D0 in the i-th conductive through hole group in each fourth storage chip 14 are aligned along the third direction and constitute a signal transmission channel.

[0186] It should be noted that i is a positive integer less than or equal to n.

[0187] In the third specific embodiment, Fig.15A As shown, assuming that the first axis AA' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the first axis AA' extends along the first direction), the low-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the high-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0188] In a fourth specific embodiment, Fig.16A As shown, assuming that the second axis BB' of the logic chip 50 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (i.e., the second axis BB' extends along the first direction), the low-order transmission area of ​​the logic chip 50, the low-order transmission area of ​​the first memory chip 11, the low-order transmission area of ​​the second memory chip 12, the high-order transmission area of ​​the third memory chip 13, and the high-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction; the high-order transmission area of ​​the logic chip 50, the high-order transmission area of ​​the first memory chip 11, the high-order transmission area of ​​the second memory chip 12, the low-order transmission area of ​​the third memory chip 13, and the low-order transmission area of ​​the fourth memory chip 14 are aligned along the third direction.

[0189] See also Fig.15A or Fig.16A For the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0190] (1) the second signal area (D) of the logic chip 50, the first signal area (C) of the first memory chip 11, the second signal area (D) of the second memory chip 12, the third signal area (E) of the third memory chip 13, and the fourth signal area (F) of the fourth memory chip 14 are aligned along the third direction;

[0191] (2) the first signal area (C) of the logic chip 50, the second signal area (D) of the first memory chip 11, the first signal area (C) of the second memory chip 12, the fourth signal area (F) of the third memory chip 13, and the third signal area (E) of the fourth memory chip 14 are aligned along the third direction;

[0192] (3) the fourth signal area (F) of the logic chip 50, the third signal area (E) of the first memory chip 11, the fourth signal area (F) of the second memory chip 12, the first signal area (C) of the third memory chip 13, and the second signal area (D) of the fourth memory chip 14 are aligned along the third direction;

[0193] (4) The third signal area (E) of the logic chip 50, the fourth signal area (F) of the first memory chip 11, the third signal area (E) of the second memory chip 12, the second signal area (D) of the third memory chip 13, and the first signal area (C) of the fourth memory chip 14 are aligned along the third direction.

[0194] See also Fig. 15B or Fig. 16B For the third and fourth specific embodiments, only for the multiple signal areas aligned along the third direction, each conductive through hole has the following alignment relationship:

[0195] (1) The second conductive via D1 in the i-th conductive via group in the logic chip 50, the first conductive via D0 in the i-th conductive via group in each first memory chip 11, the second conductive via D1 in the i-th conductive via group in each second memory chip 12, the third conductive via D2 in the i-th conductive via group in each third memory chip 13, and the fourth conductive via D3 in the i-th conductive via group in each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0196] (2) the first conductive through hole D0 in the i-th conductive through hole group in the logic chip 50, the second conductive through hole D1 in the i-th conductive through hole group in each first memory chip 11, the first conductive through hole D0 in the i-th conductive through hole group in each second memory chip 12, the fourth conductive through hole D3 in the i-th conductive through hole group in each third memory chip 13, and the third conductive through hole D2 in the i-th conductive through hole group in each fourth memory chip 14 are aligned along the third direction and constitute a signal transmission channel;

[0197] (3) the fourth conductive through hole D3 in the i-th conductive through hole group in the logic chip 50, the third conductive through hole D2 in the i-th conductive through hole group in each first memory chip 11, the fourth conductive through hole D3 in the i-th conductive through hole group in each second memory chip 12, the first conductive through hole D0 in the i-th conductive through hole group in each third memory chip 13, and the second conductive through hole D1 in the i-th conductive through hole group in each fourth memory chip 14 are aligned along the third direction and form a signal transmission channel;

[0198] (4) The third conductive through hole D2 in the i-th conductive through hole group in the logic chip 50, the fourth conductive through hole D3 in the i-th conductive through hole group in each first storage chip 11, the third conductive through hole D2 in the i-th conductive through hole group in each second storage chip 12, the second conductive through hole D1 in the i-th conductive through hole group in each third storage chip 13, and the first conductive through hole D0 in the i-th conductive through hole group in each fourth storage chip 14 are aligned along the third direction and constitute a signal transmission channel.

[0199] In some embodiments, see Fig.17 , which shows a second schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure. In particular, Fig.17 It is for FIG. 13A to FIG. 14B The chip stacking structure shown is shown. In addition, Fig.17 It is only an abstract circuit schematic diagram, in which the first OR logic circuit 30 and the third drive circuit 70 are coupled to all the conductive through holes in their corresponding conductive through hole groups, and the first OR logic circuit 30 is coupled to its corresponding first drive circuit 40. Please combine the text description for adaptive understanding.

[0200] So, please refer to Fig.17For the chip stacking structure 80, the signal transmission path from bottom to top will be similar to the following form: the fourth conductive through hole D3 in the logic chip 50 - the first conductive through hole D0 in the first memory chip 11 - the second conductive through hole D1 in the second memory chip 12 - the third conductive through hole D2 in the third memory chip 13 - the fourth conductive through hole D3 in the fourth memory chip 14..." for transmission, and the rest of the signals are similar. That is to say, for the chip stacking structure 80, from a physical point of view, the conductive through holes therein are still a direct connection configuration, but from the absolute position of the conductive through holes on the active surface, the conductive through holes therein can be regarded as a functional rotation configuration, that is, a similar direct connection configuration is realized through the physical direct connection configuration. Figure 2B The signal transmission effect (i.e. the rotation transmission effect of conductive via D0-conductive via D1-conductive via D2-conductive via D3...). In simple terms, Figure 2B The chip stacking structure in the embodiment requires a physical spiral structure, in which a horizontal interconnection structure must exist, while the chip stacking structure 80 in the embodiment of the present disclosure is a physically direct connection structure, which does not require a horizontal interconnection structure, greatly reduces the parasitic resistance, and greatly improves the transmission speed and transmission performance.

[0201] From the above, it can be seen that the memory chip provided by the embodiment of the present disclosure not only reduces the number of drive circuits and data selectors, thereby reducing parasitic capacitance; in addition, the chip stacking structure formed by the memory chip realizes the signal rotation transmission effect through the direct connection configuration of the conductive through hole, and also reduces the parasitic resistance. Further, although a connection point on the logic chip corresponds to 4 different connection points of the first memory chip, the second memory chip, the third memory chip and the fourth memory chip, all the conductive through holes in the same conductive through hole group transmit the same global signal, so that the memory chips flipped to different positions can receive the same global signal output by the logic chip through 4 signal transmission channels, that is, all the conductive through holes in the same conductive through hole group transmit the same global signal, that is, the multiple signal transmission channels formed are redundant with each other, and when some of the conductive through holes have defects and cause some signal transmission channels to fail to transmit global signals normally, other redundant signal transmission channels can still ensure that all memory chips can receive the correct global signal, achieving the repair effect; and the conductive through hole setting can achieve multi-point connection of global signals with as few conductive through holes as possible, reduce the occupied area of ​​the global signal area, and further reduce the area of ​​the memory chip.

[0202] In another embodiment of the present disclosure, see Fig.18 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig.18 As shown, the memory 90 includes the chip stacking structure 80 described in the above embodiment.

[0203] In some embodiments, the chip stacking structure 80 can be applied to a memory 90. The memory 90 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0204] In the embodiment of the present disclosure, for the memory 90, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0205] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0206] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0207] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0208] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0209] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0210] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0211] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0212] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory chip, characterized in that: The center point of the active surface of the memory chip and its adjacent area are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by n conductive through-hole groups, and all conductive through-holes in the same conductive through-hole group are used to transmit the same global signal; n is a positive integer; The memory chip further includes n first OR logic circuits and n first driving circuits; the input end of the i-th first OR logic circuit is respectively coupled to all the conductive vias in the i-th conductive via group, and the output end of the i-th first OR logic circuit is coupled to the i-th first driving circuit; i is a positive integer less than or equal to n; The i-th first driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th first OR logic circuit, and send the i-th global signal to the internal circuit of the memory chip; Wherein, each of the conductive through-hole groups includes a first conductive through-hole, a second conductive through-hole, a third conductive through-hole and a fourth conductive through-hole, the first conductive through-hole and the second conductive through-hole are symmetrical about a first axis, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the first axis, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip.

2. The memory chip according to claim 1, characterized in that: The first OR logic circuit includes a first OR gate, a second OR gate and a third OR gate; For the i-th first OR logic circuit, the first input terminal of the first OR gate is connected to the first conductive through hole in the i-th conductive through hole group, the second input terminal of the first OR gate is connected to the fourth conductive through hole in the i-th conductive through hole group, and the output terminal of the first OR gate is connected to the first input terminal of the third OR gate; the first input terminal of the second OR gate is connected to the second conductive through hole in the i-th conductive through hole group, the second input terminal of the second OR gate is connected to the third conductive through hole in the i-th conductive through hole group, and the output terminal of the second OR gate is connected to the second input terminal of the third OR gate; the output terminal of the third OR gate is used to output the global signal.

3. The memory chip according to claim 1, characterized in that: Each of the conductive through holes is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal; Among them, if the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be a low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

4. The memory chip according to claim 1, characterized in that: The memory chip further includes n second driving circuits; the i-th second driving circuit is coupled to all the conductive through holes in the i-th conductive through hole group; The i-th second driving circuit is configured to send the i-th global signal generated inside the memory chip to all the conductive through holes coupled thereto.

5. The memory chip according to claim 1, characterized in that: The conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same memory chip are electrically isolated from each other.

6. A logic chip, characterized in that: The center point of the active surface of the logic chip and its adjacent area are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by n conductive through-hole groups, and all conductive through-holes in the same conductive through-hole group are used to transmit the same global signal; n is a positive integer; Each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via and a fourth conductive via, the first conductive via and the second conductive via are symmetrical about a first axis, the third conductive via and the fourth conductive via are symmetrical about the first axis, and the first conductive via and the fourth conductive via are symmetrical about a second axis; The first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the logic chip, and the second axis is parallel to the second side of the logic chip.

7. The logic chip according to claim 6, characterized in that: The logic chip further includes n third driving circuits; The i-th third driving circuit is coupled to all the conductive vias in the i-th conductive via group; i is a positive integer less than or equal to n; The i-th third driving circuit is configured to send the i-th global signal generated inside the logic chip to all the conductive through-holes coupled thereto.

8. The logic chip according to claim 6, characterized in that: The logic chip further includes n second OR logic circuits and n fourth drive circuits; the input end of the i-th second OR logic circuit is respectively coupled to all the conductive vias in the i-th conductive via group, and the output end of the i-th second OR logic circuit is coupled to the i-th fourth drive circuit; The i-th fourth driving circuit is configured to receive the i-th global signal from the i-th conductive via group via the i-th second OR logic circuit, and send the i-th global signal to the internal circuit of the logic chip.

9. The logic chip according to claim 8, characterized in that: The second OR logic circuit includes a fourth OR gate, a fifth OR gate and a sixth OR gate; For the i-th second OR logic circuit, the first input terminal of the fourth OR gate is connected to the first conductive via in the i-th conductive via group, the second input terminal of the fourth OR gate is connected to the fourth conductive via in the i-th conductive via group, and the output terminal of the fourth OR gate is connected to the first input terminal of the sixth OR gate; the first input terminal of the fifth OR gate is connected to the second conductive via in the i-th conductive via group, the second input terminal of the fifth OR gate is connected to the third conductive via in the i-th conductive via group, and the output terminal of the fifth OR gate is connected to the second input terminal of the sixth OR gate; the output terminal of the sixth OR gate is used to output the global signal.

10. The logic chip according to claim 6, characterized in that: Each of the conductive through holes is connected to a weak ground terminal; the weak ground terminal includes a resistor and a ground terminal; Among them, if the conductive via does not transmit a signal or is not connected normally, the weak ground terminal controls the level state of the conductive via to be a low level; if the conductive via is connected normally and transmits a signal, the level state of the conductive via depends on the transmitted signal.

11. The logic chip according to claim 6, characterized in that: The conductive via is prepared by any one or more of a via-first process, a via-middle process, a via-last process, and a back side via-last process, and different conductive vias in the same logic chip are electrically isolated from each other.

12. A chip stacking structure, characterized in that: The chip stacking structure comprises a logic chip according to any one of claims 6 to 11 and at least one stacking unit, and the logic chip and the at least one stacking unit are sequentially stacked along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip sequentially stacked along the third direction, and the third direction is perpendicular to a top surface of each of the memory chips; The first storage chip, the second storage chip, the third storage chip, and the fourth storage chip are all storage chips according to any one of claims 1 to 5; The first memory chip and the second memory chip are stacked in a face-to-face manner, the second memory chip and the third memory chip are stacked in a back-to-back manner, and the third memory chip and the fourth memory chip are stacked in a face-to-face manner; The first memory chip and the logic chip in the first stacking unit are stacked in a back-to-face manner, or the first memory chip and the logic chip in the first stacking unit are stacked in a back-to-back manner; The n conductive through-hole groups in the logic chip correspond one-to-one with the n conductive through-hole groups in each of the first storage chips, the n conductive through-hole groups in each of the second storage chips, the n conductive through-hole groups in each of the third storage chips, and the n conductive through-hole groups in each of the fourth storage chips, and are aligned along the third direction, and n is a positive integer.

13. The chip stacking structure according to claim 12, characterized in that: The global signal area in each chip is penetrated by n conductive through-hole groups, each conductive through-hole group includes a first conductive through-hole, a second conductive through-hole, a third conductive through-hole and a fourth conductive through-hole, the first conductive through-hole and the second conductive through-hole are symmetrical about a first axis, the third conductive through-hole and the fourth conductive through-hole are symmetrical about the first axis, and the first conductive through-hole and the fourth conductive through-hole are symmetrical about the second axis; the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface, the first axis is parallel to the first side of the memory chip, and the second axis is parallel to the second side of the memory chip; The first axes of the logic chip and each of the memory chips are aligned along the third direction, and the second axes of the logic chip and each of the memory chips are aligned along the third direction.

14. The chip stacking structure according to claim 12, characterized in that: When the logic chip and the first memory chip are stacked back to back, The fourth conductive through hole in the i-th conductive through hole group in the logic chip, the first conductive through hole in the i-th conductive through hole group in each of the first memory chips, the second conductive through hole in the i-th conductive through hole group in each of the second memory chips, the third conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the fourth conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The third conductive through hole in the i-th conductive through hole group in the logic chip, the second conductive through hole in the i-th conductive through hole group in each of the first memory chips, the first conductive through hole in the i-th conductive through hole group in each of the second memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the third conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The second conductive through hole in the i-th conductive through hole group in the logic chip, the third conductive through hole in the i-th conductive through hole group in each of the first memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the second memory chips, the first conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the second conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The first conductive through hole in the i-th conductive through hole group in the logic chip, the fourth conductive through hole in the i-th conductive through hole group in each of the first memory chips, the third conductive through hole in the i-th conductive through hole group in each of the second memory chips, the second conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the first conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; Here, i is a positive integer less than or equal to n.

15. The chip stacking structure according to claim 12, characterized in that: When the logic chip and the first memory chip are stacked back to back, The second conductive through hole in the i-th conductive through hole group in the logic chip, the first conductive through hole in the i-th conductive through hole group in each of the first memory chips, the second conductive through hole in the i-th conductive through hole group in each of the second memory chips, the third conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the fourth conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The first conductive through hole in the i-th conductive through hole group in the logic chip, the second conductive through hole in the i-th conductive through hole group in each of the first memory chips, the first conductive through hole in the i-th conductive through hole group in each of the second memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the third conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The fourth conductive through hole in the i-th conductive through hole group in the logic chip, the third conductive through hole in the i-th conductive through hole group in each of the first memory chips, the fourth conductive through hole in the i-th conductive through hole group in each of the second memory chips, the first conductive through hole in the i-th conductive through hole group in each of the third memory chips, and the second conductive through hole in the i-th conductive through hole group in each of the fourth memory chips are aligned along the third direction and constitute a signal transmission channel; The third conductive through hole in the i-th conductive through hole group in the logic chip, the fourth conductive through hole in the i-th conductive through hole group in each of the first storage chips, the third conductive through hole in the i-th conductive through hole group in each of the second storage chips, the second conductive through hole in the i-th conductive through hole group in each of the third storage chips, and the first conductive through hole in the i-th conductive through hole group in each of the fourth storage chips are aligned along the third direction and constitute a signal transmission channel.

16. The chip stacking structure according to any one of claims 12 to 15, characterized in that: For two chips connected face to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a hybrid bonding process; for two chips connected back to back or two chips connected back to face, the positions where the conductive vias are aligned along the third direction are electrically connected by a conductive bump bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected by the hybrid bonding process; or, For two chips connected face to face or two chips connected back to back or two chips connected back to face, the positions of the conductive through holes aligned along the third direction in both chips are electrically connected through the conductive bump bonding process.

17. A memory, characterized in that: The memory comprises a chip stacking structure as claimed in any one of claims 12 to 16.

Images