Primary impedance qualified design method for PCB (Printed Circuit Board) process

Abstract

The invention discloses a primary impedance qualification design method for a PCB (Printed Circuit Board) process, which comprises the following steps of: measuring a medium thickness gradient, slicing a sample on a laminated PCB, measuring the thickness of a medium layer at each point by adopting a metallographic microscope, recording a board edge region, importing measured data into CAM (Computer Aided Manufacturing) software to generate a medium thickness distribution cloud picture, and dividing a compensation region; surface copper is measured, a thickness gauge is used for measuring the thickness of copper on the plate edge and in the plate after the ceramic plate is ground, and a comparison table of the copper thickness difference value and the line width deviation is established; compensation area division: dividing a board edge area, a transition area and an in-board area on the surface of the PCB by laser engraving; length compensation is carried out, 0.1 mi and 0.3 mi of medium thickness compensation and copper thickness compensation are carried out on the plate edge area, 0.05 mi and 0.15 mi of medium thickness compensation and copper thickness compensation are carried out on the transition area, and the total compensation amount of the plate edge area and the total compensation amount of the transition area are kept to be 0.4 mi and 0.2 mi respectively. The problems that in the prior art, a traditional PCB uniformization compensation design cannot adapt to regional process differences in actual production and multi-impedance-line cooperative regulation and control cannot be achieved are solved.

Description

Technical Field

[0001] The invention relates to the field of PCB technology, and in particular to a primary impedance qualified design method for PCB technology. Background Art

[0002] In traditional PCB design, impedance control usually adopts the "homogenization compensation" method, that is, uniform process adjustment parameters are applied to all areas. This design concept is based on idealized assumptions, assuming that the process parameters (such as dielectric thickness, copper thickness, line width and line spacing) of each process (such as pressing, copper plating, etching, etc.) in the production process can maintain a high degree of uniformity. However, there are complex process fluctuations and regional differences in actual production, which makes it difficult for the homogenization compensation method to meet the requirements of the impedance first-time pass rate. The core problem lies in the separation of the design stage and the production process, and the lack of adaptability of the homogenization compensation to complex variables and regional differences. This disconnect makes it difficult for the impedance design to meet the high-precision and multi-scenario requirements, which ultimately affects the first-time pass rate, especially in high-density, multi-impedance complex PCB boards.

[0003] In view of this, the present technical solution proposes a primary impedance qualified design method for PCB process, which designs impedance "according to local conditions" to achieve qualified impedance. Summary of the invention

[0004] The technical solution of the present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the main purpose of the present invention is to provide a primary impedance qualified design method for PCB process, which solves the problem that the traditional PCB uniform compensation design cannot adapt to the regional process differences in actual production (such as uneven dielectric thickness and copper thickness at the edge and inside the board) and the coordinated regulation of multiple impedance lines, and improves the primary qualified rate and yield rate of the impedance of complex PCB boards by optimizing the compensation parameters of the Gerber file (circuit design file) in a targeted manner (such as differentiated reduction of line width compensation and dynamic adjustment of spacing).

[0005] To achieve the above object, the present invention provides a primary impedance qualified design method for PCB process, comprising the following steps:

[0006] Dielectric thickness gradient measurement,

[0007] Slice the sample on the pressed PCB board, then use a metallographic microscope to measure the thickness of the dielectric layer at each point, record the board edge area, and import the measurement data into the CAM software to generate a dielectric thickness distribution cloud map and divide the compensation area;

[0008] Surface copper measurement,

[0009] Use a thickness gauge to measure the copper thickness at the edge and inside of the board after the ceramic plate is ground, and establish a comparison table between the copper thickness difference and the line width deviation;

[0010] Compensation area division,

[0011] Use laser engraving to divide the PCB board into edge area, transition area and inner area;

[0012] Length compensation,

[0013] The dielectric thickness compensation and copper thickness compensation of the board edge area are 0.1mil and 0.3mil respectively, and the dielectric thickness compensation and copper thickness compensation of the transition zone are 0.05mil and 0.15mil respectively, and the total compensation amount of the board edge area and transition zone is maintained at 0.4mil and 0.2mil respectively.

[0014] As a further solution of the present invention, in the dielectric thickness gradient measurement step, the sample slices are 9 samples cut out in a nine-square grid distribution on the pressed PCB board using a precision slicer, including the four corners, the midpoints of the four sides and the center of the PCB.

[0015] As a further solution of the present invention, in the surface copper measurement step, after measuring the copper thickness at the edge and inside the board, an etching experiment is also performed. The etching experiment includes designing the same line width at the edge and inside the board, and using an optical measuring instrument to compare the actual line width after etching.

[0016] As a further solution of the present invention, after the etching experiment, the etching effect verification is also carried out, including extending the etching time of the board edge area by 10%, and increasing the spray pressure by 15%, and then using an automatic line width measuring machine to scan each test point.

[0017] As a further solution of the present invention, after the length compensation step, compensation verification is also performed, including implanting comparison impedance strips in the board edge area and the board inner area, and measuring the impedance value using a TDR tester.

[0018] As a further solution of the present invention, after the compensation verification, an impedance consistency test is also carried out. The test method is to deploy impedance test points in the compensation area. If the impedance at the edge of the board is still too high, the compensation amount is increased by 0.05 mi l / time. If the impedance inside the board exceeds the standard, the compensation gradient in the transition zone is reduced.

[0019] The beneficial effects of the present invention are as follows:

[0020] The primary impedance qualified design method for PCB process proposed in the present invention combines the actual process capability to realize the directional control of impedance, has the ability to maintain a high degree of consistency with actual production, and ensures effectiveness. For multi-impedance design, it can alleviate the defect of low yield of multi-impedance design in design and production. It is not only limited to impedance design, but also has indicative significance for the control of other key influencing factors. For example, BGA and IC can use this method to specifically consider the influence of variation factors and perform single control to achieve improved qualified rate, or even pn l 100% yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the technical solutions of the present invention or the technical solutions of the present invention in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the technical solutions of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0022] Figure 1 It is a schematic diagram of the implementation process of the present invention. DETAILED DESCRIPTION

[0023] as follows:

[0024] Please refer to the attached Figure 1 ,

[0025] The main implementation steps of the plan are as follows:

[0026] For dielectric thickness gradient measurement, sample slices are made on the pressed PCB board, and then the thickness of the dielectric layer at each point is measured using a metallographic microscope, the board edge area is recorded, and the measurement data is imported into the CAM software to generate a dielectric thickness distribution cloud map and divide the compensation area; for surface copper measurement, a thickness gauge is used to measure the copper thickness at the board edge and inside the board after the ceramic plate is ground, and a comparison table of copper thickness difference and line width deviation is established; for compensation area division, the PCB board surface is divided into board edge area, transition area and board inner area by laser engraving; for length compensation, the board edge area is compensated for 0.1mil and 0.3mil of dielectric thickness and copper thickness respectively, and the transition area is compensated for 0.05mil and 0.15mil of dielectric thickness and copper thickness respectively, and the total compensation amount of the board edge area and transition area is kept at 0.4mil and 0.2mil respectively.

[0027] In the PCB impedance design process, the core purpose of slice sampling is to accurately quantify the difference in dielectric thickness (dielectric thickness) in different areas of the PCB board, and provide a physical basis for dynamic compensation. By cutting cross-sectional samples at specific locations of the PCB board (board edge, inside the board, transition zone), the dielectric layer structure is exposed, and the resin flow unevenness caused by the lamination process can be directly observed (more resin loss at the board edge, and the dielectric thickness is 10-15μm thinner than the inside of the board). When the board edge dielectric thickness difference is ≥10μm (equivalent to an impedance increase of 5-8Ω), the partition compensation mechanism is triggered forcibly. In addition, it also has the role of guiding the formulation of compensation strategies, including every 10μm reduction in dielectric thickness → impedance increase of about 1.2Ω → need to increase line width by 0.1-0.15mil compensation, and divide the compensation gradient area according to the slice data (such as 0.4mil compensation within 15mm from the board edge, 0.2mil compensation within 15-30mm).

[0028] In addition, sample slices can be used to analyze the thickness fluctuation range of mass-produced board sampling slices. For example, if the board edge thickness fluctuation is greater than ±5μm, it triggers the adjustment of the lamination process parameters (such as adjusting the steel plate window design or lamination pressure). The metallographic microscope is used to accurately measure the thickness of the dielectric layer, aiming to physically verify the difference in dielectric thickness between the board edge and the inside of the board caused by the lamination process (such as the board edge is 10-15μm thinner), locate the area to be compensated by quantifying actual data (not theoretical assumptions), and provide an objective basis for dynamically adjusting the line width to ensure that the impedance design compensation amount (such as 0.1-0.4mi l) matches the actual dielectric thickness loss, avoiding the problem of impedance exceeding the standard due to uneven dielectric thickness. Then, the thickness gauge is used to accurately quantify the difference in copper thickness between the board edge and the inside of the board after the ceramic grinding plate is ground (such as the copper loss at the board edge reaches 1.5-2μm), and the physical correlation between the copper thickness difference and the line width deviation is established in combination with the etching experiment (such as every 1μm reduction in copper thickness → the line width is reduced by 0.08mi l). This comparison table converts the abstract copper thickness parameter into an executable line width compensation amount (e.g., the board edge needs an additional compensation of 0.2-0.3mil), solves the problem of uneven etching caused by the copper thickness gradient, and avoids the low impedance caused by the small line width at the board edge (e.g., the deviation reaches 5-8Ω). Through data mapping, the compensation rules are matched with the actual process to improve the impedance control accuracy. Through laser engraving and other equipment to divide the area (board edge, transition, and board interior), the aim is to convert the dielectric thickness and copper thickness measurement data into an executable space compensation strategy. Based on the measured dielectric thickness gradient (10-15μm thin board edge) and copper thickness difference (1.5-2μm copper loss board edge), the compensation requirements of different areas are clarified, such as board edge area (within 15mm from the edge): dielectric thickness compensation (+0.1-0.2mil) and copper thickness compensation (+0.2-0.3mil) need to be superimposed, transition area (15-30mm): reduce the compensation amount according to the gradient (such as total compensation 0.15-0.25mil), and board inner area: only basic compensation is required. Through physical marking, exposure, etching and other equipment can load differentiated parameters in different areas (such as board edge area line width design value +0.4mil), avoiding over / under compensation problems caused by unified compensation for the whole board, and providing regional judgment benchmarks for AOI detection to ensure that the impedance control accuracy matches the actual process.

[0029] A preferred embodiment of the present invention: in the dielectric thickness gradient measurement step, the sample slices are 9 samples cut out in a nine-square grid distribution on the pressed PCB board using a precision slicer, including the four corners, the midpoints of the four sides and the center of the PCB.

[0030] The purpose of the nine-square grid sampling is to fully cover all areas of the PCB board, especially the edges and the center, to capture the gradient changes in dielectric thickness. The nine-square grid can cover key areas such as the board edge, four corners, and the center to ensure comprehensive data. If there are too few sampling points, such as only taking the center and the edge, changes in the transition zone may be missed, resulting in inaccurate compensation strategies. For example, the dielectric thickness at different locations on the board edge may vary due to the production process, and the four corners may be thinner than the middle of the edge.

[0031] A preferred embodiment of the present invention is as follows: in the copper surface measurement step, after measuring the copper thickness at the edge and inside the board, an etching experiment is performed. The etching experiment includes designing the same line width at the edge and inside the board, and using an optical measuring instrument to compare the actual line width after etching.

[0032] As the preferred solution of this technology, the etching experiment aims to physically verify the influence of copper thickness difference on the actual line width and clarify the quantitative relationship between process fluctuation and design compensation. By making a test board containing a comparison group of board edge / board interior, the etching effect of copper thickness difference is observed under the same etching conditions (time, solution concentration). For example, the board edge has a thinner copper thickness and a faster etching rate, resulting in a line width that is 0.2-0.3mil (measured value) smaller than the board interior, and the compensation amount is calibrated. According to the measured line width deviation (such as a board edge reduction of 0.25mil), the line width increment that needs to be pre-compensated at the design end (such as +0.3mil) is reversely deduced. It also has the function of determining the critical value of copper thickness (such as additional compensation needs to be started when it is less than 10μm) to avoid impedance loss due to insufficient copper thickness.

[0033] A preferred embodiment of the present invention is as follows: after the etching experiment, the etching effect verification is also carried out, including extending the etching time of the board edge area by 10%, increasing the spray pressure by 15%, and then using an automatic line width measuring machine to scan each test point.

[0034] As a preferred solution of this technology, by adjusting the etching parameters (time +10%, pressure +15%), the etching uniformity of the board edge can be improved in a targeted manner, the etching rate difference caused by the thin copper thickness at the board edge can be compensated, the line width can be avoided to be too large due to insufficient etching, and the spray pressure can be increased to enhance the fluidity of the etching solution at the board edge, reduce the line spacing abnormality caused by the residual liquid, and also have the function of automatic line width measurement, quantify the actual effect after parameter adjustment (such as the line width deviation of the board edge is reduced from ±0.2mi l to ±0.05mi l), verify the effectiveness of the compensation strategy, and provide data support for mass production parameter solidification, and finally achieve board edge / board impedance consistency control.

[0035] A preferred embodiment of the present invention is as follows: after the length compensation step, compensation verification is also performed, including implanting contrast impedance strips in the board edge area and the board inner area, and using a TDR tester to measure the impedance value.

[0036] As a preferred solution, the actual effect of the compensation strategy can be directly verified by implanting a comparison impedance bar and measuring it. By comparing the board edge / board impedance values ​​on the same board through regional comparison (e.g., the board edge impedance drops from 55Ω to 50±1Ω after compensation), it is confirmed whether the compensation amount accurately offsets the difference in dielectric thickness and copper thickness, or by using deviation detection to locate the residual deviation with high precision (±0.5Ω) of TDR (e.g., the board edge is still 2Ω higher) to guide the secondary compensation adjustment. Verify the matching of the compensation design and etching parameters to avoid compensation failure due to process fluctuations and ensure that the impedance consistency meets the standards during mass production (e.g., regional differences ≤3Ω).

[0037] A preferred embodiment of the present invention is as follows: after compensation verification, an impedance consistency test is also performed. The test method is to deploy impedance test points in the compensation area. If the impedance at the edge of the board is still too high, the compensation amount is increased by 0.05 mi l / time. If the impedance inside the board exceeds the standard, the compensation gradient in the transition area is reduced.

[0038] As a preferred solution, the compensation amount is dynamically adjusted to achieve precise matching of process parameters and design goals. For the high impedance of the board edge exposed in the verification (such as still exceeding the tolerance by +2Ω), the compensation is increased by 0.05mil / time, gradually approaching the target value. In addition, when the impedance inside the board exceeds the standard (excessive compensation leads to excessive line width), the compensation gradient of the transition zone is reduced (such as from 0.2mil to 0.15mil) to avoid yield loss. Through iterative adjustment, the impedance difference of the board edge / transition zone / board is ≤3Ω, ensuring that the impedance consistency of the entire board meets the standard (such as 50Ω±5Ω), and ultimately the overall yield is increased to more than 85%.

[0039] The above description is only a preferred embodiment of the technical solution of the present invention, and does not limit the patent scope of the technical solution of the present invention. All equivalent structural changes made by using the contents of the technical solution description and drawings of the present invention under the conception of the technical solution of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the technical solution of the present invention.

Claims

1. A qualified primary impedance design method for PCB technology, characterized in that: The following steps are involved: S1. Dielectric thickness gradient measurement, Slice the sample on the pressed PCB board, then use a metallographic microscope to measure the thickness of the dielectric layer at each point, record the board edge area, and import the measurement data into the CAM software to generate a dielectric thickness distribution cloud map and divide the compensation area; S2, surface copper measurement, Use a thickness gauge to measure the copper thickness at the edge and inside of the board after the ceramic plate is ground, and establish a comparison table between the copper thickness difference and the line width deviation; S3. Compensation area division, Use laser engraving to divide the PCB board into edge area, transition area and inner area; S4, length compensation, The dielectric thickness compensation and copper thickness compensation of the board edge area are 0.1mil and 0.3mil respectively, and the dielectric thickness compensation and copper thickness compensation of the transition area are 0.05mil and 0.15mil respectively, and the total compensation amount of the board edge area and transition area is maintained at 0.4mil and 0.2mil respectively.

2. The primary impedance qualified design method for PCB process according to claim 1 is characterized in that: In the dielectric thickness gradient measurement step, the sample slices are 9 samples cut out in a nine-square grid distribution on the pressed PCB board using a precision slicer, including the four corners, the midpoints of the four sides and the center of the PCB.

3. The primary impedance qualified design method for PCB process according to claim 1, characterized in that: In the surface copper measurement step, after measuring the copper thickness at the edge and inside the board, an etching experiment is also performed. The etching experiment includes designing the same line width at the edge and inside the board, and using an optical measuring instrument to compare the actual line width after etching.

4. The primary impedance qualified design method for PCB process according to claim 3 is characterized in that: After the etching experiment, the etching effect verification was also carried out, including extending the etching time of the board edge area by 10% and increasing the spray pressure by 15%, and then using an automatic line width measurement machine to scan each test point.

5. The primary impedance qualified design method for PCB process according to claim 1, characterized in that: After the length compensation step, compensation verification is also performed, including implanting contrast impedance strips in the board edge area and the board interior area, and measuring the impedance value using a TDR tester.

6. The method for designing a qualified primary impedance for a PCB process according to claim 5, characterized in that: After the compensation verification, an impedance consistency test is also performed. The test method is to deploy impedance test points in the compensation area. If the impedance at the edge of the board is still too high, the compensation amount is increased by 0.05mil / time. If the impedance inside the board exceeds the standard, the compensation gradient in the transition area is reduced.

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